./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2b04c290f1a7102f69086810812946480d0557325a865f39f1fc1d9d1f1627d8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:00:03,015 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:00:03,017 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:00:03,051 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:00:03,053 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:00:03,058 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:00:03,060 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:00:03,063 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:00:03,065 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:00:03,066 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:00:03,067 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:00:03,068 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:00:03,069 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:00:03,070 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:00:03,071 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:00:03,072 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:00:03,072 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:00:03,073 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:00:03,075 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:00:03,076 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:00:03,078 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:00:03,080 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:00:03,081 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:00:03,082 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:00:03,085 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:00:03,085 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:00:03,086 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:00:03,087 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:00:03,087 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:00:03,088 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:00:03,088 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:00:03,089 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:00:03,090 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:00:03,090 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:00:03,091 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:00:03,091 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:00:03,092 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:00:03,092 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:00:03,093 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:00:03,094 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:00:03,094 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:00:03,095 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:00:03,129 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:00:03,130 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:00:03,130 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:00:03,130 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:00:03,131 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:00:03,131 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:00:03,131 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:00:03,132 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:00:03,132 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:00:03,132 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:00:03,132 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:00:03,133 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:00:03,136 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:00:03,136 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:00:03,137 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:00:03,137 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:00:03,137 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:00:03,137 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:00:03,138 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:00:03,138 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:00:03,138 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:00:03,138 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:00:03,139 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:00:03,139 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:00:03,139 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:00:03,139 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:00:03,140 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:00:03,140 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:00:03,140 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:00:03,141 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:00:03,141 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:00:03,141 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:00:03,141 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:00:03,142 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:00:03,142 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:00:03,142 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:00:03,143 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:00:03,143 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:00:03,143 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b04c290f1a7102f69086810812946480d0557325a865f39f1fc1d9d1f1627d8 [2022-11-03 02:00:03,425 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:00:03,459 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:00:03,462 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:00:03,463 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:00:03,464 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:00:03,465 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:03,542 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/d29d19117/7052db0410874eebaa2606c598c282c3/FLAG5a9077199 [2022-11-03 02:00:04,012 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:00:04,013 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:04,026 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/d29d19117/7052db0410874eebaa2606c598c282c3/FLAG5a9077199 [2022-11-03 02:00:04,395 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/d29d19117/7052db0410874eebaa2606c598c282c3 [2022-11-03 02:00:04,401 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:00:04,403 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:00:04,405 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:00:04,405 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:00:04,408 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:00:04,409 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,411 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24b9da2d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04, skipping insertion in model container [2022-11-03 02:00:04,411 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,418 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:00:04,450 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:00:04,658 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c[1107,1120] [2022-11-03 02:00:04,726 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:00:04,729 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:00:04,742 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c[1107,1120] [2022-11-03 02:00:04,783 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:00:04,794 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:00:04,794 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04 WrapperNode [2022-11-03 02:00:04,795 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:00:04,796 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:00:04,796 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:00:04,796 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:00:04,803 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,820 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,860 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 104 [2022-11-03 02:00:04,861 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:00:04,861 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:00:04,862 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:00:04,862 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:00:04,871 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,871 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,876 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,876 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,891 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,894 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,895 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,896 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,898 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:00:04,899 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:00:04,899 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:00:04,899 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:00:04,912 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (1/1) ... [2022-11-03 02:00:04,918 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:00:04,929 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:04,948 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:00:04,975 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:00:04,994 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:00:04,995 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:00:05,099 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:00:05,108 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:00:05,329 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:00:05,427 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:00:05,427 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:00:05,430 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:05 BoogieIcfgContainer [2022-11-03 02:00:05,430 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:00:05,432 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:00:05,432 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:00:05,447 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:00:05,447 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:00:04" (1/3) ... [2022-11-03 02:00:05,448 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27b3cf22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:00:05, skipping insertion in model container [2022-11-03 02:00:05,448 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:04" (2/3) ... [2022-11-03 02:00:05,449 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@27b3cf22 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:00:05, skipping insertion in model container [2022-11-03 02:00:05,449 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:05" (3/3) ... [2022-11-03 02:00:05,450 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:05,473 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:00:05,473 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:00:05,524 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:00:05,530 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6df11285, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:00:05,530 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:00:05,537 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:05,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:00:05,543 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:05,544 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:00:05,546 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:05,554 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:05,554 INFO L85 PathProgramCache]: Analyzing trace with hash 2214562, now seen corresponding path program 1 times [2022-11-03 02:00:05,564 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:00:05,566 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761118452] [2022-11-03 02:00:05,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:05,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:00:05,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:00:05,879 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:00:05,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:00:05,956 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:00:05,958 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:00:05,960 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:00:05,962 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:00:05,966 INFO L444 BasicCegarLoop]: Path program histogram: [1] [2022-11-03 02:00:05,970 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:00:05,987 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:00:05,995 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:00:05 BoogieIcfgContainer [2022-11-03 02:00:05,995 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:00:05,997 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:00:05,998 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:00:05,998 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:00:05,999 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:05" (3/4) ... [2022-11-03 02:00:06,002 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:00:06,002 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:00:06,004 INFO L158 Benchmark]: Toolchain (without parser) took 1600.89ms. Allocated memory is still 104.9MB. Free memory was 67.7MB in the beginning and 72.9MB in the end (delta: -5.2MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:00:06,005 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 104.9MB. Free memory is still 84.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:00:06,006 INFO L158 Benchmark]: CACSL2BoogieTranslator took 390.49ms. Allocated memory is still 104.9MB. Free memory was 67.5MB in the beginning and 80.0MB in the end (delta: -12.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-03 02:00:06,007 INFO L158 Benchmark]: Boogie Procedure Inliner took 65.30ms. Allocated memory is still 104.9MB. Free memory was 80.0MB in the beginning and 77.5MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:00:06,008 INFO L158 Benchmark]: Boogie Preprocessor took 36.94ms. Allocated memory is still 104.9MB. Free memory was 77.5MB in the beginning and 76.3MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:00:06,014 INFO L158 Benchmark]: RCFGBuilder took 531.14ms. Allocated memory is still 104.9MB. Free memory was 76.3MB in the beginning and 54.0MB in the end (delta: 22.2MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-11-03 02:00:06,014 INFO L158 Benchmark]: TraceAbstraction took 563.41ms. Allocated memory is still 104.9MB. Free memory was 53.6MB in the beginning and 73.4MB in the end (delta: -19.8MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:00:06,016 INFO L158 Benchmark]: Witness Printer took 5.52ms. Allocated memory is still 104.9MB. Free memory was 73.4MB in the beginning and 72.9MB in the end (delta: 527.8kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:00:06,023 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 104.9MB. Free memory is still 84.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 390.49ms. Allocated memory is still 104.9MB. Free memory was 67.5MB in the beginning and 80.0MB in the end (delta: -12.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 65.30ms. Allocated memory is still 104.9MB. Free memory was 80.0MB in the beginning and 77.5MB in the end (delta: 2.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 36.94ms. Allocated memory is still 104.9MB. Free memory was 77.5MB in the beginning and 76.3MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 531.14ms. Allocated memory is still 104.9MB. Free memory was 76.3MB in the beginning and 54.0MB in the end (delta: 22.2MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * TraceAbstraction took 563.41ms. Allocated memory is still 104.9MB. Free memory was 53.6MB in the beginning and 73.4MB in the end (delta: -19.8MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 5.52ms. Allocated memory is still 104.9MB. Free memory was 73.4MB in the beginning and 72.9MB in the end (delta: 527.8kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 65, overapproximation of bitwiseAnd at line 68. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 3); [L29] const SORT_4 msb_SORT_4 = (SORT_4)1 << (3 - 1); [L31] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 32); [L32] const SORT_23 msb_SORT_23 = (SORT_23)1 << (32 - 1); [L34] const SORT_4 var_5 = 0; [L35] const SORT_1 var_13 = 1; [L36] const SORT_1 var_17 = 0; [L37] const SORT_23 var_25 = 1; [L39] SORT_1 input_2; [L40] SORT_1 input_3; [L42] SORT_4 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_4; [L43] SORT_4 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_4; [L44] SORT_1 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L45] SORT_1 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L47] SORT_4 init_7_arg_1 = var_5; [L48] state_6 = init_7_arg_1 [L49] SORT_4 init_9_arg_1 = var_5; [L50] state_8 = init_9_arg_1 [L51] SORT_1 init_19_arg_1 = var_17; [L52] state_18 = init_19_arg_1 [L53] SORT_1 init_21_arg_1 = var_17; [L54] state_20 = init_21_arg_1 VAL [init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, state_18=0, state_20=0, state_6=0, state_8=0, var_13=1, var_17=0, var_25=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 0.5s, OverallIterations: 1, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=7occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 0.0s InterpolantComputationTime, 4 NumberOfCodeBlocks, 4 NumberOfCodeBlocksAsserted, 1 NumberOfCheckSat, 0 ConstructedInterpolants, 0 QuantifiedInterpolants, 0 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 0 InterpolantComputations, 0 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:00:06,082 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2b04c290f1a7102f69086810812946480d0557325a865f39f1fc1d9d1f1627d8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:00:08,423 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:00:08,426 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:00:08,471 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:00:08,472 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:00:08,476 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:00:08,478 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:00:08,482 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:00:08,488 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:00:08,495 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:00:08,496 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:00:08,499 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:00:08,499 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:00:08,500 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:00:08,501 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:00:08,504 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:00:08,505 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:00:08,506 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:00:08,508 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:00:08,516 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:00:08,518 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:00:08,519 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:00:08,521 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:00:08,524 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:00:08,532 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:00:08,532 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:00:08,532 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:00:08,534 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:00:08,535 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:00:08,536 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:00:08,536 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:00:08,537 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:00:08,539 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:00:08,540 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:00:08,541 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:00:08,541 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:00:08,542 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:00:08,542 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:00:08,543 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:00:08,544 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:00:08,545 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:00:08,546 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:00:08,585 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:00:08,586 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:00:08,587 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:00:08,587 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:00:08,588 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:00:08,589 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:00:08,589 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:00:08,589 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:00:08,589 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:00:08,589 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:00:08,590 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:00:08,591 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:00:08,592 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:00:08,592 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:00:08,592 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:00:08,592 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:00:08,593 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:00:08,594 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:00:08,594 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:00:08,594 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:00:08,594 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:00:08,594 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:00:08,595 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:00:08,595 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:00:08,595 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:00:08,595 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:00:08,595 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:08,596 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:00:08,596 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:00:08,596 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:00:08,596 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2b04c290f1a7102f69086810812946480d0557325a865f39f1fc1d9d1f1627d8 [2022-11-03 02:00:09,021 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:00:09,052 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:00:09,056 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:00:09,058 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:00:09,058 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:00:09,060 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:09,141 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/2fc8f2de2/0c69a9794b0c41bb9dad553c1857c978/FLAGc3fc6334b [2022-11-03 02:00:09,666 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:00:09,667 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:09,674 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/2fc8f2de2/0c69a9794b0c41bb9dad553c1857c978/FLAGc3fc6334b [2022-11-03 02:00:10,033 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/data/2fc8f2de2/0c69a9794b0c41bb9dad553c1857c978 [2022-11-03 02:00:10,035 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:00:10,036 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:00:10,037 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:00:10,038 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:00:10,045 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:00:10,046 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,047 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6aee54eb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10, skipping insertion in model container [2022-11-03 02:00:10,047 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,056 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:00:10,083 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:00:10,196 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c[1107,1120] [2022-11-03 02:00:10,249 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:00:10,253 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:00:10,282 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.dyn_partition.c[1107,1120] [2022-11-03 02:00:10,319 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:00:10,331 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:00:10,332 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10 WrapperNode [2022-11-03 02:00:10,332 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:00:10,333 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:00:10,333 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:00:10,334 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:00:10,340 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,348 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,369 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 104 [2022-11-03 02:00:10,369 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:00:10,370 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:00:10,370 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:00:10,370 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:00:10,377 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,377 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,379 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,379 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,384 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,388 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,392 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,393 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,396 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:00:10,396 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:00:10,397 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:00:10,397 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:00:10,398 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (1/1) ... [2022-11-03 02:00:10,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:00:10,429 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:10,443 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:00:10,464 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:00:10,485 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:00:10,486 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:00:10,564 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:00:10,566 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:00:10,741 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:00:10,748 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:00:10,748 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:00:10,750 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:10 BoogieIcfgContainer [2022-11-03 02:00:10,750 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:00:10,753 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:00:10,753 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:00:10,756 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:00:10,756 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:00:10" (1/3) ... [2022-11-03 02:00:10,757 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e8ec75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:00:10, skipping insertion in model container [2022-11-03 02:00:10,757 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:00:10" (2/3) ... [2022-11-03 02:00:10,758 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e8ec75 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:00:10, skipping insertion in model container [2022-11-03 02:00:10,758 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:10" (3/3) ... [2022-11-03 02:00:10,759 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.dyn_partition.c [2022-11-03 02:00:10,774 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:00:10,774 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:00:10,834 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:00:10,840 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@122167fc, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:00:10,840 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:00:10,851 INFO L276 IsEmpty]: Start isEmpty. Operand has 15 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:10,856 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 02:00:10,856 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:10,856 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 02:00:10,857 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:10,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:10,862 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 02:00:10,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:10,873 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [369772429] [2022-11-03 02:00:10,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:10,874 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:10,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:10,875 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:10,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:00:10,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:10,978 INFO L263 TraceCheckSpWp]: Trace formula consists of 36 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:00:10,984 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:11,361 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:11,361 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:00:11,362 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:11,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [369772429] [2022-11-03 02:00:11,363 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [369772429] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:00:11,364 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:00:11,364 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:00:11,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901617998] [2022-11-03 02:00:11,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:00:11,371 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:00:11,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:11,407 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:00:11,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:00:11,410 INFO L87 Difference]: Start difference. First operand has 15 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:11,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:11,487 INFO L93 Difference]: Finished difference Result 32 states and 48 transitions. [2022-11-03 02:00:11,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:00:11,490 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 02:00:11,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:11,501 INFO L225 Difference]: With dead ends: 32 [2022-11-03 02:00:11,502 INFO L226 Difference]: Without dead ends: 19 [2022-11-03 02:00:11,504 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:00:11,507 INFO L413 NwaCegarLoop]: 10 mSDtfsCounter, 15 mSDsluCounter, 19 mSDsCounter, 0 mSdLazyCounter, 10 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 10 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:11,508 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 29 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 10 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:00:11,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2022-11-03 02:00:11,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 13. [2022-11-03 02:00:11,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 12 states have (on average 1.25) internal successors, (15), 12 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:11,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 15 transitions. [2022-11-03 02:00:11,535 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 15 transitions. Word has length 5 [2022-11-03 02:00:11,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:11,536 INFO L495 AbstractCegarLoop]: Abstraction has 13 states and 15 transitions. [2022-11-03 02:00:11,536 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:11,536 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 15 transitions. [2022-11-03 02:00:11,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-11-03 02:00:11,537 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:11,537 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:11,557 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:11,748 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:00:11,749 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:11,750 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:11,750 INFO L85 PathProgramCache]: Analyzing trace with hash 505863741, now seen corresponding path program 1 times [2022-11-03 02:00:11,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:11,751 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1013140312] [2022-11-03 02:00:11,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:11,752 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:11,752 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:11,758 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:11,764 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:00:11,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:11,840 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 02:00:11,842 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:11,931 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:11,931 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:00:11,932 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:11,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1013140312] [2022-11-03 02:00:11,932 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1013140312] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:00:11,932 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:00:11,933 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:00:11,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010372718] [2022-11-03 02:00:11,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:00:11,934 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:00:11,934 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:11,935 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:00:11,935 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:00:11,935 INFO L87 Difference]: Start difference. First operand 13 states and 15 transitions. Second operand has 5 states, 5 states have (on average 2.4) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:12,015 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:12,016 INFO L93 Difference]: Finished difference Result 34 states and 41 transitions. [2022-11-03 02:00:12,016 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:00:12,016 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.4) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-11-03 02:00:12,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:12,018 INFO L225 Difference]: With dead ends: 34 [2022-11-03 02:00:12,018 INFO L226 Difference]: Without dead ends: 25 [2022-11-03 02:00:12,019 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:00:12,021 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 20 mSDsluCounter, 28 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 43 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:12,025 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 43 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:00:12,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-11-03 02:00:12,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 17. [2022-11-03 02:00:12,034 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 16 states have (on average 1.25) internal successors, (20), 16 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:12,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 20 transitions. [2022-11-03 02:00:12,036 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 20 transitions. Word has length 12 [2022-11-03 02:00:12,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:12,037 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 20 transitions. [2022-11-03 02:00:12,037 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.4) internal successors, (12), 5 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:12,041 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 20 transitions. [2022-11-03 02:00:12,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-11-03 02:00:12,042 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:12,042 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:12,059 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:12,242 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:00:12,243 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:12,243 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:12,244 INFO L85 PathProgramCache]: Analyzing trace with hash 504016699, now seen corresponding path program 1 times [2022-11-03 02:00:12,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:12,244 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1974272404] [2022-11-03 02:00:12,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:12,245 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:12,245 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:12,248 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:12,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:00:12,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:12,341 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-03 02:00:12,347 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:12,582 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:12,583 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:13,103 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:13,104 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:13,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1974272404] [2022-11-03 02:00:13,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1974272404] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:13,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [883992276] [2022-11-03 02:00:13,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:13,105 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:13,105 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:13,109 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:13,118 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (5)] Waiting until timeout for monitored process [2022-11-03 02:00:13,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:13,224 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-03 02:00:13,227 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:13,552 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:13,552 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:14,343 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:14,346 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [883992276] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:14,346 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [148943385] [2022-11-03 02:00:14,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:14,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:00:14,347 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:14,353 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:00:14,373 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-03 02:00:14,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:14,417 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:00:14,419 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:14,575 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:14,576 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:14,837 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:14,838 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [148943385] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:14,838 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:00:14,838 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 9, 9, 9, 9] total 28 [2022-11-03 02:00:14,838 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [983789185] [2022-11-03 02:00:14,839 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:00:14,839 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-11-03 02:00:14,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:14,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-03 02:00:14,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=640, Unknown=0, NotChecked=0, Total=756 [2022-11-03 02:00:14,841 INFO L87 Difference]: Start difference. First operand 17 states and 20 transitions. Second operand has 28 states, 28 states have (on average 1.5714285714285714) internal successors, (44), 28 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:15,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:15,989 INFO L93 Difference]: Finished difference Result 45 states and 55 transitions. [2022-11-03 02:00:15,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-03 02:00:15,990 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 1.5714285714285714) internal successors, (44), 28 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-11-03 02:00:15,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:15,990 INFO L225 Difference]: With dead ends: 45 [2022-11-03 02:00:15,990 INFO L226 Difference]: Without dead ends: 43 [2022-11-03 02:00:15,991 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 447 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=323, Invalid=1569, Unknown=0, NotChecked=0, Total=1892 [2022-11-03 02:00:15,992 INFO L413 NwaCegarLoop]: 10 mSDtfsCounter, 90 mSDsluCounter, 111 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 90 SdHoareTripleChecker+Valid, 121 SdHoareTripleChecker+Invalid, 160 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 130 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:15,993 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [90 Valid, 121 Invalid, 160 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 22 Invalid, 0 Unknown, 130 Unchecked, 0.0s Time] [2022-11-03 02:00:15,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2022-11-03 02:00:15,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 26. [2022-11-03 02:00:15,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 25 states have (on average 1.24) internal successors, (31), 25 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:15,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 31 transitions. [2022-11-03 02:00:15,999 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 31 transitions. Word has length 12 [2022-11-03 02:00:15,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:16,000 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 31 transitions. [2022-11-03 02:00:16,000 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 1.5714285714285714) internal successors, (44), 28 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:16,000 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 31 transitions. [2022-11-03 02:00:16,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-11-03 02:00:16,001 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:16,001 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:16,017 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:16,242 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:16,418 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:16,612 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:16,613 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:16,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:16,614 INFO L85 PathProgramCache]: Analyzing trace with hash -2015943235, now seen corresponding path program 1 times [2022-11-03 02:00:16,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:16,614 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1544706175] [2022-11-03 02:00:16,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:16,615 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:16,615 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:16,616 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:16,619 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 02:00:16,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:16,690 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 02:00:16,694 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:16,725 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:16,725 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:00:16,725 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:16,725 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1544706175] [2022-11-03 02:00:16,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1544706175] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:00:16,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:00:16,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:00:16,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473755619] [2022-11-03 02:00:16,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:00:16,727 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:00:16,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:16,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:00:16,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:00:16,728 INFO L87 Difference]: Start difference. First operand 26 states and 31 transitions. Second operand has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:16,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:16,754 INFO L93 Difference]: Finished difference Result 39 states and 46 transitions. [2022-11-03 02:00:16,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:00:16,755 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 12 [2022-11-03 02:00:16,756 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:16,756 INFO L225 Difference]: With dead ends: 39 [2022-11-03 02:00:16,756 INFO L226 Difference]: Without dead ends: 28 [2022-11-03 02:00:16,757 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:00:16,758 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 9 mSDsluCounter, 19 mSDsCounter, 0 mSdLazyCounter, 9 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 10 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 9 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:16,758 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [9 Valid, 32 Invalid, 10 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 9 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:00:16,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-11-03 02:00:16,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 24. [2022-11-03 02:00:16,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 23 states have (on average 1.2173913043478262) internal successors, (28), 23 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:16,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 28 transitions. [2022-11-03 02:00:16,763 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 28 transitions. Word has length 12 [2022-11-03 02:00:16,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:16,764 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 28 transitions. [2022-11-03 02:00:16,764 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 3.0) internal successors, (12), 4 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:16,764 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2022-11-03 02:00:16,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-11-03 02:00:16,765 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:16,765 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:16,786 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:16,976 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:00:16,977 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:16,977 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:16,977 INFO L85 PathProgramCache]: Analyzing trace with hash 140837325, now seen corresponding path program 1 times [2022-11-03 02:00:16,978 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:16,978 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [932002456] [2022-11-03 02:00:16,978 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:16,978 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:16,978 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:16,979 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:16,980 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 02:00:17,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:17,061 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-03 02:00:17,064 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:17,524 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:17,524 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:19,015 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:19,015 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:19,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [932002456] [2022-11-03 02:00:19,018 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [932002456] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:19,018 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [663003137] [2022-11-03 02:00:19,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:19,018 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:19,018 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:19,019 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:19,021 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (9)] Waiting until timeout for monitored process [2022-11-03 02:00:19,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:19,145 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 53 conjunts are in the unsatisfiable core [2022-11-03 02:00:19,153 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:19,339 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:19,339 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:19,600 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:19,601 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [663003137] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:19,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [580874377] [2022-11-03 02:00:19,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:19,601 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:00:19,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:19,605 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:00:19,625 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-03 02:00:19,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:19,684 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 56 conjunts are in the unsatisfiable core [2022-11-03 02:00:19,687 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:19,965 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:19,966 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:20,355 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:20,355 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [580874377] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:20,355 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:00:20,355 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 15, 15] total 28 [2022-11-03 02:00:20,355 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926453122] [2022-11-03 02:00:20,356 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:00:20,356 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-11-03 02:00:20,356 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:20,357 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-03 02:00:20,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=673, Unknown=0, NotChecked=0, Total=756 [2022-11-03 02:00:20,357 INFO L87 Difference]: Start difference. First operand 24 states and 28 transitions. Second operand has 28 states, 28 states have (on average 1.4285714285714286) internal successors, (40), 28 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:23,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:23,739 INFO L93 Difference]: Finished difference Result 77 states and 93 transitions. [2022-11-03 02:00:23,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2022-11-03 02:00:23,740 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 1.4285714285714286) internal successors, (40), 28 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-11-03 02:00:23,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:23,741 INFO L225 Difference]: With dead ends: 77 [2022-11-03 02:00:23,741 INFO L226 Difference]: Without dead ends: 75 [2022-11-03 02:00:23,743 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 143 GetRequests, 83 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 631 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=418, Invalid=3122, Unknown=0, NotChecked=0, Total=3540 [2022-11-03 02:00:23,744 INFO L413 NwaCegarLoop]: 8 mSDtfsCounter, 90 mSDsluCounter, 120 mSDsCounter, 0 mSdLazyCounter, 173 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 90 SdHoareTripleChecker+Valid, 128 SdHoareTripleChecker+Invalid, 436 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 173 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 239 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:23,744 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [90 Valid, 128 Invalid, 436 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 173 Invalid, 0 Unknown, 239 Unchecked, 0.3s Time] [2022-11-03 02:00:23,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2022-11-03 02:00:23,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 55. [2022-11-03 02:00:23,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 54 states have (on average 1.2592592592592593) internal successors, (68), 54 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:23,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 68 transitions. [2022-11-03 02:00:23,755 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 68 transitions. Word has length 19 [2022-11-03 02:00:23,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:23,756 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 68 transitions. [2022-11-03 02:00:23,756 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 1.4285714285714286) internal successors, (40), 28 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:23,756 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 68 transitions. [2022-11-03 02:00:23,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-11-03 02:00:23,757 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:23,757 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:23,761 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (9)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:23,967 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:24,180 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:24,359 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:00:24,360 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:24,361 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:24,361 INFO L85 PathProgramCache]: Analyzing trace with hash 138990283, now seen corresponding path program 1 times [2022-11-03 02:00:24,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:24,361 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [698043569] [2022-11-03 02:00:24,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:24,361 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:24,362 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:24,363 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:24,367 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-03 02:00:24,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:24,438 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 02:00:24,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:24,522 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:24,522 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:24,578 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 5 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:24,578 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:24,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [698043569] [2022-11-03 02:00:24,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [698043569] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:24,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [221219889] [2022-11-03 02:00:24,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:00:24,579 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:24,579 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:24,581 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:24,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (12)] Waiting until timeout for monitored process [2022-11-03 02:00:24,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:00:24,691 INFO L263 TraceCheckSpWp]: Trace formula consists of 142 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:00:24,693 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:24,708 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:00:24,708 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:00:24,709 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [221219889] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:00:24,709 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:00:24,709 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [6, 6] total 9 [2022-11-03 02:00:24,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [839759919] [2022-11-03 02:00:24,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:00:24,710 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:00:24,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:24,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:00:24,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:00:24,711 INFO L87 Difference]: Start difference. First operand 55 states and 68 transitions. Second operand has 5 states, 5 states have (on average 3.4) internal successors, (17), 5 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:24,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:24,795 INFO L93 Difference]: Finished difference Result 97 states and 118 transitions. [2022-11-03 02:00:24,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:00:24,796 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 3.4) internal successors, (17), 5 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 19 [2022-11-03 02:00:24,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:24,802 INFO L225 Difference]: With dead ends: 97 [2022-11-03 02:00:24,802 INFO L226 Difference]: Without dead ends: 78 [2022-11-03 02:00:24,802 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:00:24,806 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 31 mSDsluCounter, 26 mSDsCounter, 0 mSdLazyCounter, 25 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 25 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:24,807 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [31 Valid, 47 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 25 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:00:24,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2022-11-03 02:00:24,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 57. [2022-11-03 02:00:24,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 56 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:24,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 68 transitions. [2022-11-03 02:00:24,833 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 68 transitions. Word has length 19 [2022-11-03 02:00:24,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:24,833 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 68 transitions. [2022-11-03 02:00:24,834 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 3.4) internal successors, (17), 5 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:24,834 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 68 transitions. [2022-11-03 02:00:24,834 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-11-03 02:00:24,836 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:24,836 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:24,854 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:25,049 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (12)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:25,248 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:25,248 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:25,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:25,249 INFO L85 PathProgramCache]: Analyzing trace with hash 1071281085, now seen corresponding path program 2 times [2022-11-03 02:00:25,249 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:25,249 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [398685294] [2022-11-03 02:00:25,249 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:00:25,249 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:25,249 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:25,250 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:25,251 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 02:00:25,346 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:00:25,346 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:25,352 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 02:00:25,354 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:25,448 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 18 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:00:25,449 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:25,495 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 18 proven. 4 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:00:25,495 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:25,495 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [398685294] [2022-11-03 02:00:25,495 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [398685294] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:25,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1298463354] [2022-11-03 02:00:25,496 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:00:25,496 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:25,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:25,497 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:25,503 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (14)] Waiting until timeout for monitored process [2022-11-03 02:00:25,636 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:00:25,636 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:25,638 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:00:25,640 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:25,673 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-03 02:00:25,673 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:00:25,674 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1298463354] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:00:25,674 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:00:25,674 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5, 5] total 10 [2022-11-03 02:00:25,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708733420] [2022-11-03 02:00:25,674 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:00:25,675 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:00:25,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:25,675 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:00:25,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:00:25,676 INFO L87 Difference]: Start difference. First operand 57 states and 68 transitions. Second operand has 5 states, 5 states have (on average 4.4) internal successors, (22), 5 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:25,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:25,752 INFO L93 Difference]: Finished difference Result 84 states and 100 transitions. [2022-11-03 02:00:25,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:00:25,752 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 4.4) internal successors, (22), 5 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-11-03 02:00:25,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:25,754 INFO L225 Difference]: With dead ends: 84 [2022-11-03 02:00:25,754 INFO L226 Difference]: Without dead ends: 66 [2022-11-03 02:00:25,754 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2022-11-03 02:00:25,755 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 33 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:25,761 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [33 Valid, 34 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 17 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:00:25,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2022-11-03 02:00:25,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 57. [2022-11-03 02:00:25,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 56 states have (on average 1.1428571428571428) internal successors, (64), 56 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:25,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 64 transitions. [2022-11-03 02:00:25,772 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 64 transitions. Word has length 26 [2022-11-03 02:00:25,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:25,773 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 64 transitions. [2022-11-03 02:00:25,773 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 4.4) internal successors, (22), 5 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:25,773 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 64 transitions. [2022-11-03 02:00:25,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-11-03 02:00:25,774 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:25,774 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:25,783 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:25,977 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (14)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:26,175 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:26,175 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:26,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:26,176 INFO L85 PathProgramCache]: Analyzing trace with hash -1716690569, now seen corresponding path program 3 times [2022-11-03 02:00:26,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:26,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [984238060] [2022-11-03 02:00:26,177 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:00:26,177 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:26,177 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:26,178 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:26,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 02:00:26,264 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-11-03 02:00:26,264 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:26,270 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 70 conjunts are in the unsatisfiable core [2022-11-03 02:00:26,274 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:26,977 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:00:26,977 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:29,379 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:00:29,379 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:29,379 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [984238060] [2022-11-03 02:00:29,380 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [984238060] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:29,380 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [590277228] [2022-11-03 02:00:29,380 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:00:29,380 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:29,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:29,381 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:29,388 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (16)] Waiting until timeout for monitored process [2022-11-03 02:00:29,543 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-11-03 02:00:29,543 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:29,546 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 70 conjunts are in the unsatisfiable core [2022-11-03 02:00:29,548 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:29,871 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:00:29,871 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:30,336 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:00:30,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [590277228] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:30,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [49084943] [2022-11-03 02:00:30,337 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:00:30,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:00:30,338 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:30,355 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:00:30,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-03 02:00:30,445 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-11-03 02:00:30,445 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:30,448 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 64 conjunts are in the unsatisfiable core [2022-11-03 02:00:30,451 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:31,856 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:00:31,856 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:34,617 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 1 proven. 25 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:00:34,618 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [49084943] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:34,618 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:00:34,618 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 15, 16] total 53 [2022-11-03 02:00:34,618 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1562120988] [2022-11-03 02:00:34,619 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:00:34,619 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 53 states [2022-11-03 02:00:34,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:34,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-11-03 02:00:34,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=2580, Unknown=0, NotChecked=0, Total=2756 [2022-11-03 02:00:34,622 INFO L87 Difference]: Start difference. First operand 57 states and 64 transitions. Second operand has 53 states, 53 states have (on average 1.679245283018868) internal successors, (89), 53 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:57,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:57,547 INFO L93 Difference]: Finished difference Result 128 states and 142 transitions. [2022-11-03 02:00:57,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2022-11-03 02:00:57,548 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 53 states have (on average 1.679245283018868) internal successors, (89), 53 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-11-03 02:00:57,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:57,549 INFO L225 Difference]: With dead ends: 128 [2022-11-03 02:00:57,549 INFO L226 Difference]: Without dead ends: 126 [2022-11-03 02:00:57,553 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 209 GetRequests, 92 SyntacticMatches, 9 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2579 ImplicationChecksByTransitivity, 28.4s TimeCoverageRelationStatistics Valid=1264, Invalid=10726, Unknown=0, NotChecked=0, Total=11990 [2022-11-03 02:00:57,554 INFO L413 NwaCegarLoop]: 6 mSDtfsCounter, 192 mSDsluCounter, 246 mSDsCounter, 0 mSdLazyCounter, 278 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 252 SdHoareTripleChecker+Invalid, 1313 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 278 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1020 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:57,554 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 252 Invalid, 1313 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 278 Invalid, 0 Unknown, 1020 Unchecked, 0.3s Time] [2022-11-03 02:00:57,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2022-11-03 02:00:57,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 78. [2022-11-03 02:00:57,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 77 states have (on average 1.1428571428571428) internal successors, (88), 77 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:57,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 88 transitions. [2022-11-03 02:00:57,568 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 88 transitions. Word has length 26 [2022-11-03 02:00:57,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:57,568 INFO L495 AbstractCegarLoop]: Abstraction has 78 states and 88 transitions. [2022-11-03 02:00:57,569 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 53 states, 53 states have (on average 1.679245283018868) internal successors, (89), 53 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:57,569 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 88 transitions. [2022-11-03 02:00:57,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2022-11-03 02:00:57,570 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:57,570 INFO L195 NwaCegarLoop]: trace histogram [4, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:57,601 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2022-11-03 02:00:57,803 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:57,991 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (16)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:58,189 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:58,190 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:00:58,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:00:58,190 INFO L85 PathProgramCache]: Analyzing trace with hash 60163835, now seen corresponding path program 4 times [2022-11-03 02:00:58,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:00:58,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1061052342] [2022-11-03 02:00:58,191 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-03 02:00:58,191 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:00:58,191 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:00:58,191 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:00:58,197 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Waiting until timeout for monitored process [2022-11-03 02:00:58,282 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-03 02:00:58,282 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:58,287 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:00:58,289 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:58,425 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 12 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:58,425 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:58,513 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 15 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:58,513 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:00:58,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1061052342] [2022-11-03 02:00:58,513 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1061052342] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:58,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1792224001] [2022-11-03 02:00:58,514 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-03 02:00:58,514 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:00:58,514 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:00:58,517 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:00:58,541 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (19)] Waiting until timeout for monitored process [2022-11-03 02:00:58,686 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-03 02:00:58,687 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:58,690 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-03 02:00:58,692 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:58,821 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 12 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:58,821 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:58,868 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 15 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:58,868 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1792224001] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:58,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [501954058] [2022-11-03 02:00:58,869 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-03 02:00:58,869 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:00:58,869 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:00:58,870 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:00:58,877 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-03 02:00:58,949 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-03 02:00:58,949 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:00:58,951 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 31 conjunts are in the unsatisfiable core [2022-11-03 02:00:58,953 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:00:59,112 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 12 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:59,113 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:00:59,209 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 19 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:00:59,210 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [501954058] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:00:59,210 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:00:59,210 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 8, 8] total 14 [2022-11-03 02:00:59,213 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239761886] [2022-11-03 02:00:59,213 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:00:59,214 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-03 02:00:59,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:00:59,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-03 02:00:59,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=132, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:00:59,215 INFO L87 Difference]: Start difference. First operand 78 states and 88 transitions. Second operand has 14 states, 14 states have (on average 4.0) internal successors, (56), 14 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:59,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:00:59,492 INFO L93 Difference]: Finished difference Result 130 states and 144 transitions. [2022-11-03 02:00:59,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-03 02:00:59,493 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 4.0) internal successors, (56), 14 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 26 [2022-11-03 02:00:59,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:00:59,493 INFO L225 Difference]: With dead ends: 130 [2022-11-03 02:00:59,493 INFO L226 Difference]: Without dead ends: 79 [2022-11-03 02:00:59,494 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=129, Invalid=377, Unknown=0, NotChecked=0, Total=506 [2022-11-03 02:00:59,494 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 127 mSDsluCounter, 67 mSDsCounter, 0 mSdLazyCounter, 85 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 127 SdHoareTripleChecker+Valid, 87 SdHoareTripleChecker+Invalid, 111 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 85 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:00:59,495 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [127 Valid, 87 Invalid, 111 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 85 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:00:59,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2022-11-03 02:00:59,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 67. [2022-11-03 02:00:59,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 66 states have (on average 1.0757575757575757) internal successors, (71), 66 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:59,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 71 transitions. [2022-11-03 02:00:59,517 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 71 transitions. Word has length 26 [2022-11-03 02:00:59,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:00:59,517 INFO L495 AbstractCegarLoop]: Abstraction has 67 states and 71 transitions. [2022-11-03 02:00:59,517 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 4.0) internal successors, (56), 14 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:00:59,518 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 71 transitions. [2022-11-03 02:00:59,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2022-11-03 02:00:59,518 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:00:59,519 INFO L195 NwaCegarLoop]: trace histogram [6, 5, 5, 5, 5, 4, 4, 1, 1, 1, 1, 1, 1] [2022-11-03 02:00:59,542 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:59,725 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (19)] Forceful destruction successful, exit code 0 [2022-11-03 02:00:59,929 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Forceful destruction successful, exit code 0 [2022-11-03 02:01:00,121 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:01:00,121 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:01:00,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:01:00,122 INFO L85 PathProgramCache]: Analyzing trace with hash -570516297, now seen corresponding path program 5 times [2022-11-03 02:01:00,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:01:00,122 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [797580023] [2022-11-03 02:01:00,122 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-03 02:01:00,122 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:01:00,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:01:00,125 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:01:00,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Waiting until timeout for monitored process [2022-11-03 02:01:00,275 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-03 02:01:00,275 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:00,281 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 02:01:00,282 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:00,415 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 50 proven. 12 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2022-11-03 02:01:00,416 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:00,630 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 43 proven. 19 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2022-11-03 02:01:00,630 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:01:00,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [797580023] [2022-11-03 02:01:00,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [797580023] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:00,631 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1532102114] [2022-11-03 02:01:00,631 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-03 02:01:00,631 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:01:00,631 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:01:00,632 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:01:00,657 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (22)] Waiting until timeout for monitored process [2022-11-03 02:01:00,863 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-03 02:01:00,863 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:00,867 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 02:01:00,869 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:01,127 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:01:01,127 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:01,252 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:01:01,252 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1532102114] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:01,253 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [48284790] [2022-11-03 02:01:01,253 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-11-03 02:01:01,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:01:01,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:01:01,255 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:01:01,257 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-03 02:01:01,406 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2022-11-03 02:01:01,406 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:01,410 INFO L263 TraceCheckSpWp]: Trace formula consists of 301 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-03 02:01:01,412 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:01,555 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:01:01,555 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:01,628 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2022-11-03 02:01:01,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [48284790] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:01,629 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:01:01,629 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 8, 8, 7, 7] total 20 [2022-11-03 02:01:01,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81495052] [2022-11-03 02:01:01,629 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:01:01,630 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-11-03 02:01:01,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:01:01,630 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-11-03 02:01:01,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=296, Unknown=0, NotChecked=0, Total=380 [2022-11-03 02:01:01,631 INFO L87 Difference]: Start difference. First operand 67 states and 71 transitions. Second operand has 20 states, 20 states have (on average 4.85) internal successors, (97), 20 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:01,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:01:01,946 INFO L93 Difference]: Finished difference Result 89 states and 92 transitions. [2022-11-03 02:01:01,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:01:01,947 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 4.85) internal successors, (97), 20 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 40 [2022-11-03 02:01:01,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:01:01,947 INFO L225 Difference]: With dead ends: 89 [2022-11-03 02:01:01,948 INFO L226 Difference]: Without dead ends: 75 [2022-11-03 02:01:01,948 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 244 GetRequests, 217 SyntacticMatches, 2 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 178 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=165, Invalid=537, Unknown=0, NotChecked=0, Total=702 [2022-11-03 02:01:01,949 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 87 mSDsluCounter, 110 mSDsCounter, 0 mSdLazyCounter, 97 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 87 SdHoareTripleChecker+Valid, 131 SdHoareTripleChecker+Invalid, 120 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 97 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 12 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:01:01,949 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [87 Valid, 131 Invalid, 120 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 97 Invalid, 0 Unknown, 12 Unchecked, 0.1s Time] [2022-11-03 02:01:01,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2022-11-03 02:01:01,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 55. [2022-11-03 02:01:01,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 54 states have (on average 1.037037037037037) internal successors, (56), 54 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:01,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 56 transitions. [2022-11-03 02:01:01,959 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 56 transitions. Word has length 40 [2022-11-03 02:01:01,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:01:01,959 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 56 transitions. [2022-11-03 02:01:01,959 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 4.85) internal successors, (97), 20 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:01,959 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 56 transitions. [2022-11-03 02:01:01,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2022-11-03 02:01:01,960 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:01:01,960 INFO L195 NwaCegarLoop]: trace histogram [7, 6, 6, 6, 6, 3, 3, 3, 3, 1, 1, 1, 1] [2022-11-03 02:01:01,982 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-11-03 02:01:02,173 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Ended with exit code 0 [2022-11-03 02:01:02,368 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (22)] Ended with exit code 0 [2022-11-03 02:01:02,565 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:01:02,565 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:01:02,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:01:02,566 INFO L85 PathProgramCache]: Analyzing trace with hash 2100617045, now seen corresponding path program 6 times [2022-11-03 02:01:02,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:01:02,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1911121455] [2022-11-03 02:01:02,567 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-03 02:01:02,567 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:01:02,567 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:01:02,568 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:01:02,570 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Waiting until timeout for monitored process [2022-11-03 02:01:02,720 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-03 02:01:02,720 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:02,728 INFO L263 TraceCheckSpWp]: Trace formula consists of 354 conjuncts, 134 conjunts are in the unsatisfiable core [2022-11-03 02:01:02,730 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:05,284 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:05,285 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:16,729 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:16,730 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:01:16,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1911121455] [2022-11-03 02:01:16,730 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1911121455] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:16,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1979667384] [2022-11-03 02:01:16,730 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-03 02:01:16,730 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:01:16,730 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:01:16,731 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:01:16,737 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Waiting until timeout for monitored process [2022-11-03 02:01:16,984 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-03 02:01:16,984 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:16,990 INFO L263 TraceCheckSpWp]: Trace formula consists of 354 conjuncts, 121 conjunts are in the unsatisfiable core [2022-11-03 02:01:16,992 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:21,457 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:21,457 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:32,693 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:32,693 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1979667384] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:32,693 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1101404320] [2022-11-03 02:01:32,693 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-11-03 02:01:32,693 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:01:32,694 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:01:32,694 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:01:32,696 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-03 02:01:32,834 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2022-11-03 02:01:32,835 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:01:32,840 INFO L263 TraceCheckSpWp]: Trace formula consists of 354 conjuncts, 134 conjunts are in the unsatisfiable core [2022-11-03 02:01:32,844 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:33,674 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:33,675 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:01:35,846 INFO L134 CoverageAnalysis]: Checked inductivity of 117 backedges. 0 proven. 115 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 02:01:35,847 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1101404320] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:01:35,847 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:01:35,847 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 32, 32, 34, 34] total 112 [2022-11-03 02:01:35,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060247351] [2022-11-03 02:01:35,847 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:01:35,848 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 112 states [2022-11-03 02:01:35,848 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:01:35,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 112 interpolants. [2022-11-03 02:01:35,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=689, Invalid=11743, Unknown=0, NotChecked=0, Total=12432 [2022-11-03 02:01:35,852 INFO L87 Difference]: Start difference. First operand 55 states and 56 transitions. Second operand has 112 states, 112 states have (on average 1.5) internal successors, (168), 112 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:56,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:01:56,513 INFO L93 Difference]: Finished difference Result 118 states and 122 transitions. [2022-11-03 02:01:56,514 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2022-11-03 02:01:56,514 INFO L78 Accepts]: Start accepts. Automaton has has 112 states, 112 states have (on average 1.5) internal successors, (168), 112 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 47 [2022-11-03 02:01:56,514 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:01:56,515 INFO L225 Difference]: With dead ends: 118 [2022-11-03 02:01:56,515 INFO L226 Difference]: Without dead ends: 116 [2022-11-03 02:01:56,522 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 347 GetRequests, 161 SyntacticMatches, 15 SemanticMatches, 171 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8997 ImplicationChecksByTransitivity, 47.3s TimeCoverageRelationStatistics Valid=2312, Invalid=27444, Unknown=0, NotChecked=0, Total=29756 [2022-11-03 02:01:56,522 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 274 mSDsluCounter, 326 mSDsCounter, 0 mSdLazyCounter, 626 mSolverCounterSat, 36 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 274 SdHoareTripleChecker+Valid, 330 SdHoareTripleChecker+Invalid, 1787 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 36 IncrementalHoareTripleChecker+Valid, 626 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1125 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-03 02:01:56,523 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [274 Valid, 330 Invalid, 1787 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [36 Valid, 626 Invalid, 0 Unknown, 1125 Unchecked, 0.6s Time] [2022-11-03 02:01:56,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states. [2022-11-03 02:01:56,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 104. [2022-11-03 02:01:56,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 103 states have (on average 1.0485436893203883) internal successors, (108), 103 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:56,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 108 transitions. [2022-11-03 02:01:56,542 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 108 transitions. Word has length 47 [2022-11-03 02:01:56,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:01:56,542 INFO L495 AbstractCegarLoop]: Abstraction has 104 states and 108 transitions. [2022-11-03 02:01:56,543 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 112 states, 112 states have (on average 1.5) internal successors, (168), 112 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:01:56,543 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 108 transitions. [2022-11-03 02:01:56,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 02:01:56,544 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:01:56,544 INFO L195 NwaCegarLoop]: trace histogram [8, 7, 7, 7, 7, 4, 4, 3, 3, 1, 1, 1, 1] [2022-11-03 02:01:56,548 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Forceful destruction successful, exit code 0 [2022-11-03 02:01:56,769 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-11-03 02:01:56,957 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Forceful destruction successful, exit code 0 [2022-11-03 02:01:57,148 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:01:57,148 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:01:57,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:01:57,149 INFO L85 PathProgramCache]: Analyzing trace with hash -2124760337, now seen corresponding path program 7 times [2022-11-03 02:01:57,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:01:57,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [797411929] [2022-11-03 02:01:57,149 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-03 02:01:57,150 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:01:57,150 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:01:57,151 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:01:57,152 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-03 02:01:57,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:01:57,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 407 conjuncts, 138 conjunts are in the unsatisfiable core [2022-11-03 02:01:57,317 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:01:59,994 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:01:59,995 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:02:12,569 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:02:12,569 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:02:12,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [797411929] [2022-11-03 02:02:12,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [797411929] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:02:12,569 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [919418747] [2022-11-03 02:02:12,570 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-03 02:02:12,570 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:02:12,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:02:12,571 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:02:12,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Waiting until timeout for monitored process [2022-11-03 02:02:12,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:02:12,828 INFO L263 TraceCheckSpWp]: Trace formula consists of 407 conjuncts, 138 conjunts are in the unsatisfiable core [2022-11-03 02:02:12,833 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:02:13,752 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:02:13,752 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:02:15,500 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:02:15,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [919418747] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:02:15,501 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1938919957] [2022-11-03 02:02:15,501 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-03 02:02:15,501 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:02:15,502 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:02:15,505 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:02:15,529 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-03 02:02:15,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:02:15,649 INFO L263 TraceCheckSpWp]: Trace formula consists of 407 conjuncts, 141 conjunts are in the unsatisfiable core [2022-11-03 02:02:15,653 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:02:16,666 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:02:16,667 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:02:18,842 INFO L134 CoverageAnalysis]: Checked inductivity of 161 backedges. 0 proven. 158 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 02:02:18,842 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1938919957] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:02:18,843 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:02:18,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 37, 37] total 72 [2022-11-03 02:02:18,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1683874512] [2022-11-03 02:02:18,843 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:02:18,844 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2022-11-03 02:02:18,844 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:02:18,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2022-11-03 02:02:18,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=342, Invalid=4770, Unknown=0, NotChecked=0, Total=5112 [2022-11-03 02:02:18,846 INFO L87 Difference]: Start difference. First operand 104 states and 108 transitions. Second operand has 72 states, 72 states have (on average 1.5277777777777777) internal successors, (110), 72 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:02:43,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:02:43,645 INFO L93 Difference]: Finished difference Result 113 states and 117 transitions. [2022-11-03 02:02:43,646 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2022-11-03 02:02:43,646 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 1.5277777777777777) internal successors, (110), 72 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 02:02:43,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:02:43,647 INFO L225 Difference]: With dead ends: 113 [2022-11-03 02:02:43,647 INFO L226 Difference]: Without dead ends: 111 [2022-11-03 02:02:43,649 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 240 SyntacticMatches, 22 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3380 ImplicationChecksByTransitivity, 40.8s TimeCoverageRelationStatistics Valid=1743, Invalid=16617, Unknown=0, NotChecked=0, Total=18360 [2022-11-03 02:02:43,650 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 299 mSDsluCounter, 156 mSDsCounter, 0 mSdLazyCounter, 659 mSolverCounterSat, 62 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 299 SdHoareTripleChecker+Valid, 160 SdHoareTripleChecker+Invalid, 1457 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 62 IncrementalHoareTripleChecker+Valid, 659 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 736 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 02:02:43,650 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [299 Valid, 160 Invalid, 1457 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [62 Valid, 659 Invalid, 0 Unknown, 736 Unchecked, 0.7s Time] [2022-11-03 02:02:43,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2022-11-03 02:02:43,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2022-11-03 02:02:43,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 110 states have (on average 1.018181818181818) internal successors, (112), 110 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:02:43,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2022-11-03 02:02:43,676 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 112 transitions. Word has length 54 [2022-11-03 02:02:43,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:02:43,677 INFO L495 AbstractCegarLoop]: Abstraction has 111 states and 112 transitions. [2022-11-03 02:02:43,677 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 1.5277777777777777) internal successors, (110), 72 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:02:43,677 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 112 transitions. [2022-11-03 02:02:43,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2022-11-03 02:02:43,679 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:02:43,679 INFO L195 NwaCegarLoop]: trace histogram [15, 14, 14, 14, 14, 7, 7, 7, 7, 1, 1, 1, 1] [2022-11-03 02:02:43,725 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2022-11-03 02:02:43,908 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Ended with exit code 0 [2022-11-03 02:02:44,114 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-03 02:02:44,305 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:02:44,305 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:02:44,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:02:44,306 INFO L85 PathProgramCache]: Analyzing trace with hash 510805605, now seen corresponding path program 8 times [2022-11-03 02:02:44,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:02:44,306 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1593821558] [2022-11-03 02:02:44,306 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:02:44,307 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:02:44,307 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:02:44,307 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:02:44,308 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Waiting until timeout for monitored process [2022-11-03 02:02:44,561 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:02:44,562 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:02:44,586 INFO L263 TraceCheckSpWp]: Trace formula consists of 778 conjuncts, 257 conjunts are in the unsatisfiable core [2022-11-03 02:02:44,592 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:02:55,949 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 659 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-03 02:02:55,949 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:03:58,359 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 659 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-03 02:03:58,359 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:03:58,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1593821558] [2022-11-03 02:03:58,359 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1593821558] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:03:58,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [21469460] [2022-11-03 02:03:58,360 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:03:58,360 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:03:58,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:03:58,361 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:03:58,362 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Waiting until timeout for monitored process [2022-11-03 02:03:58,863 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:03:58,863 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:03:58,874 INFO L263 TraceCheckSpWp]: Trace formula consists of 778 conjuncts, 139 conjunts are in the unsatisfiable core [2022-11-03 02:03:58,877 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:04:16,324 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 1 proven. 628 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2022-11-03 02:04:16,324 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:04:57,504 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 629 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2022-11-03 02:04:57,505 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [21469460] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:04:57,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [525860365] [2022-11-03 02:04:57,505 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:04:57,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:04:57,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:04:57,511 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:04:57,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-03 02:04:57,709 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:04:57,709 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:04:57,718 INFO L263 TraceCheckSpWp]: Trace formula consists of 778 conjuncts, 139 conjunts are in the unsatisfiable core [2022-11-03 02:04:57,722 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:05:02,146 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 1 proven. 628 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2022-11-03 02:05:02,146 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:05:10,540 INFO L134 CoverageAnalysis]: Checked inductivity of 665 backedges. 0 proven. 629 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2022-11-03 02:05:10,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [525860365] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:05:10,540 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:05:10,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 34, 34, 34, 34] total 193 [2022-11-03 02:05:10,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277462619] [2022-11-03 02:05:10,541 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:05:10,542 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 193 states [2022-11-03 02:05:10,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:05:10,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 193 interpolants. [2022-11-03 02:05:10,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1427, Invalid=35629, Unknown=0, NotChecked=0, Total=37056 [2022-11-03 02:05:10,547 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. Second operand has 193 states, 193 states have (on average 1.8290155440414508) internal successors, (353), 193 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:07:43,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:07:43,495 INFO L93 Difference]: Finished difference Result 232 states and 240 transitions. [2022-11-03 02:07:43,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 148 states. [2022-11-03 02:07:43,496 INFO L78 Accepts]: Start accepts. Automaton has has 193 states, 193 states have (on average 1.8290155440414508) internal successors, (353), 193 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 103 [2022-11-03 02:07:43,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:07:43,498 INFO L225 Difference]: With dead ends: 232 [2022-11-03 02:07:43,498 INFO L226 Difference]: Without dead ends: 230 [2022-11-03 02:07:43,508 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 778 GetRequests, 409 SyntacticMatches, 39 SemanticMatches, 330 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30533 ImplicationChecksByTransitivity, 286.3s TimeCoverageRelationStatistics Valid=6585, Invalid=103307, Unknown=0, NotChecked=0, Total=109892 [2022-11-03 02:07:43,509 INFO L413 NwaCegarLoop]: 4 mSDtfsCounter, 816 mSDsluCounter, 381 mSDsCounter, 0 mSdLazyCounter, 2822 mSolverCounterSat, 71 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 816 SdHoareTripleChecker+Valid, 385 SdHoareTripleChecker+Invalid, 8569 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 71 IncrementalHoareTripleChecker+Valid, 2822 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 5676 IncrementalHoareTripleChecker+Unchecked, 3.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:07:43,510 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [816 Valid, 385 Invalid, 8569 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [71 Valid, 2822 Invalid, 0 Unknown, 5676 Unchecked, 3.0s Time] [2022-11-03 02:07:43,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 230 states. [2022-11-03 02:07:43,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 230 to 216. [2022-11-03 02:07:43,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 216 states, 215 states have (on average 1.041860465116279) internal successors, (224), 215 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:07:43,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 224 transitions. [2022-11-03 02:07:43,559 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 224 transitions. Word has length 103 [2022-11-03 02:07:43,559 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:07:43,559 INFO L495 AbstractCegarLoop]: Abstraction has 216 states and 224 transitions. [2022-11-03 02:07:43,560 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 193 states, 193 states have (on average 1.8290155440414508) internal successors, (353), 193 states have internal predecessors, (353), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:07:43,560 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 224 transitions. [2022-11-03 02:07:43,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2022-11-03 02:07:43,562 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:07:43,562 INFO L195 NwaCegarLoop]: trace histogram [16, 15, 15, 15, 15, 8, 8, 7, 7, 1, 1, 1, 1] [2022-11-03 02:07:43,576 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Forceful destruction successful, exit code 0 [2022-11-03 02:07:43,790 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2022-11-03 02:07:43,969 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Forceful destruction successful, exit code 0 [2022-11-03 02:07:44,165 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:07:44,165 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:07:44,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:07:44,166 INFO L85 PathProgramCache]: Analyzing trace with hash -2002894369, now seen corresponding path program 9 times [2022-11-03 02:07:44,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:07:44,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1505894530] [2022-11-03 02:07:44,167 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:07:44,167 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:07:44,167 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:07:44,167 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:07:44,169 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Waiting until timeout for monitored process [2022-11-03 02:07:44,553 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2022-11-03 02:07:44,554 INFO L229 tOrderPrioritization]: Conjunction of SSA is sat [2022-11-03 02:07:44,554 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:07:44,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:07:44,977 INFO L130 FreeRefinementEngine]: Strategy WALRUS found a feasible trace [2022-11-03 02:07:44,978 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:07:44,979 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:07:45,009 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Forceful destruction successful, exit code 0 [2022-11-03 02:07:45,203 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:07:45,206 INFO L444 BasicCegarLoop]: Path program histogram: [9, 1, 1, 1, 1, 1] [2022-11-03 02:07:45,209 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:07:45,343 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,346 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,346 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,346 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,346 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,347 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,348 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,348 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,348 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,348 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,396 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:07:45 BoogieIcfgContainer [2022-11-03 02:07:45,396 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:07:45,397 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:07:45,397 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:07:45,397 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:07:45,397 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:00:10" (3/4) ... [2022-11-03 02:07:45,399 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-03 02:07:45,458 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,459 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,460 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:07:45,627 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/witness.graphml [2022-11-03 02:07:45,627 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:07:45,628 INFO L158 Benchmark]: Toolchain (without parser) took 455591.43ms. Allocated memory was 69.2MB in the beginning and 308.3MB in the end (delta: 239.1MB). Free memory was 49.5MB in the beginning and 140.8MB in the end (delta: -91.3MB). Peak memory consumption was 146.2MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,628 INFO L158 Benchmark]: CDTParser took 0.26ms. Allocated memory is still 69.2MB. Free memory is still 49.3MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:07:45,628 INFO L158 Benchmark]: CACSL2BoogieTranslator took 295.02ms. Allocated memory is still 69.2MB. Free memory was 49.2MB in the beginning and 51.1MB in the end (delta: -1.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,629 INFO L158 Benchmark]: Boogie Procedure Inliner took 35.97ms. Allocated memory is still 69.2MB. Free memory was 51.1MB in the beginning and 49.3MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:07:45,630 INFO L158 Benchmark]: Boogie Preprocessor took 26.23ms. Allocated memory is still 69.2MB. Free memory was 49.3MB in the beginning and 47.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,630 INFO L158 Benchmark]: RCFGBuilder took 353.81ms. Allocated memory is still 69.2MB. Free memory was 47.9MB in the beginning and 35.3MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,630 INFO L158 Benchmark]: TraceAbstraction took 454643.26ms. Allocated memory was 69.2MB in the beginning and 308.3MB in the end (delta: 239.1MB). Free memory was 34.5MB in the beginning and 169.1MB in the end (delta: -134.5MB). Peak memory consumption was 107.4MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,631 INFO L158 Benchmark]: Witness Printer took 230.75ms. Allocated memory is still 308.3MB. Free memory was 169.1MB in the beginning and 140.8MB in the end (delta: 28.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2022-11-03 02:07:45,635 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26ms. Allocated memory is still 69.2MB. Free memory is still 49.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 295.02ms. Allocated memory is still 69.2MB. Free memory was 49.2MB in the beginning and 51.1MB in the end (delta: -1.9MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 35.97ms. Allocated memory is still 69.2MB. Free memory was 51.1MB in the beginning and 49.3MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 26.23ms. Allocated memory is still 69.2MB. Free memory was 49.3MB in the beginning and 47.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 353.81ms. Allocated memory is still 69.2MB. Free memory was 47.9MB in the beginning and 35.3MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * TraceAbstraction took 454643.26ms. Allocated memory was 69.2MB in the beginning and 308.3MB in the end (delta: 239.1MB). Free memory was 34.5MB in the beginning and 169.1MB in the end (delta: -134.5MB). Peak memory consumption was 107.4MB. Max. memory is 16.1GB. * Witness Printer took 230.75ms. Allocated memory is still 308.3MB. Free memory was 169.1MB in the beginning and 140.8MB in the end (delta: 28.3MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 20]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 3); [L29] const SORT_4 msb_SORT_4 = (SORT_4)1 << (3 - 1); [L31] const SORT_23 mask_SORT_23 = (SORT_23)-1 >> (sizeof(SORT_23) * 8 - 32); [L32] const SORT_23 msb_SORT_23 = (SORT_23)1 << (32 - 1); [L34] const SORT_4 var_5 = 0; [L35] const SORT_1 var_13 = 1; [L36] const SORT_1 var_17 = 0; [L37] const SORT_23 var_25 = 1; [L39] SORT_1 input_2; [L40] SORT_1 input_3; [L42] SORT_4 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_4; [L43] SORT_4 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_4; [L44] SORT_1 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L45] SORT_1 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L47] SORT_4 init_7_arg_1 = var_5; [L48] state_6 = init_7_arg_1 [L49] SORT_4 init_9_arg_1 = var_5; [L50] state_8 = init_9_arg_1 [L51] SORT_1 init_19_arg_1 = var_17; [L52] state_18 = init_19_arg_1 [L53] SORT_1 init_21_arg_1 = var_17; [L54] state_20 = init_21_arg_1 VAL [init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, state_18=0, state_20=0, state_6=0, state_8=0, var_13=1, var_17=0, var_25=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=9, input_3=10, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, state_18=0, state_20=0, state_6=0, state_8=0, var_10=1, var_10_arg_0=0, var_10_arg_1=0, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29_arg_0=1, var_29_arg_1=0, var_29_arg_2=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=9, input_3=10, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, state_18=0, state_20=0, state_6=0, state_8=0, var_10=1, var_10_arg_0=0, var_10_arg_1=0, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=0, var_29_arg_1=0, var_29_arg_2=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=9, input_3=10, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=0, state_18=0, state_20=0, state_6=0, state_8=0, var_10=1, var_10_arg_0=0, var_10_arg_1=0, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=0, var_29_arg_0=1, var_29_arg_1=0, var_29_arg_2=1, var_31=0, var_31_arg_0=0, var_32=1, var_32_arg_0=0, var_32_arg_1=1, var_33=1, var_33_arg_0=1, var_34_arg_0=1, var_34_arg_1=1, var_34_arg_2=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=9, input_3=10, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=0, state_18=0, state_20=0, state_6=0, state_8=0, var_10=1, var_10_arg_0=0, var_10_arg_1=0, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=0, var_29_arg_0=1, var_29_arg_1=0, var_29_arg_2=1, var_31=0, var_31_arg_0=0, var_32=1, var_32_arg_0=0, var_32_arg_1=1, var_33=1, var_33_arg_0=1, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=1, var_34_arg_1=1, var_34_arg_2=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=9, input_3=10, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=0, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=0, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=0, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=0, var_29_arg_0=1, var_29_arg_1=0, var_29_arg_2=1, var_31=0, var_31_arg_0=0, var_32=1, var_32_arg_0=0, var_32_arg_1=1, var_33=1, var_33_arg_0=1, var_34=1, var_34_arg_0=1, var_34_arg_1=1, var_34_arg_2=0, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=11, input_3=12, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=0, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=0, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=0, var_29_arg_0=0, var_29_arg_1=0, var_29_arg_2=1, var_31=0, var_31_arg_0=0, var_32=1, var_32_arg_0=0, var_32_arg_1=1, var_33=1, var_33_arg_0=1, var_34=1, var_34_arg_0=1, var_34_arg_1=1, var_34_arg_2=0, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=11, input_3=12, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=0, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=0, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=0, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=1, var_29_arg_1=0, var_29_arg_2=1, var_31=0, var_31_arg_0=0, var_32=1, var_32_arg_0=0, var_32_arg_1=1, var_33=1, var_33_arg_0=1, var_34=1, var_34_arg_0=1, var_34_arg_1=1, var_34_arg_2=0, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=11, input_3=12, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=0, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=1, var_29_arg_0=0, var_29_arg_1=0, var_29_arg_2=1, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=11, input_3=12, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=0, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=1, var_29_arg_0=0, var_29_arg_1=0, var_29_arg_2=1, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=1, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=11, input_3=12, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=1, state_8=1, var_10=1, var_10_arg_0=0, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=0, var_24_arg_0=0, var_25=1, var_26=1, var_26_arg_0=0, var_26_arg_1=1, var_27=1, var_27_arg_0=1, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=1, var_29_arg_0=0, var_29_arg_1=0, var_29_arg_2=1, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=13, input_3=14, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=1, state_8=1, var_10=1, var_10_arg_0=1, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=1, var_29_arg_0=1, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=13, input_3=14, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=1, state_8=1, var_10=1, var_10_arg_0=1, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=1, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=1, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=0, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=13, input_3=14, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=1, state_8=1, var_10=1, var_10_arg_0=1, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=1, var_29_arg_0=1, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=1, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=13, input_3=14, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=1, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=1, state_8=1, var_10=1, var_10_arg_0=1, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=1, var_29_arg_0=1, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=1, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=2, var_34_arg_1=2, var_34_arg_2=1, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=13, input_3=14, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=1, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=1, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=1, var_29_arg_0=1, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=2, var_34_arg_0=1, var_34_arg_1=2, var_34_arg_2=1, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=15, input_3=16, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=1, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=1, var_29_arg_0=0, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=2, var_34_arg_0=1, var_34_arg_1=2, var_34_arg_2=1, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=15, input_3=16, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=1, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=1, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=1, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=2, var_29_arg_1=1, var_29_arg_2=2, var_31=1, var_31_arg_0=1, var_32=2, var_32_arg_0=1, var_32_arg_1=1, var_33=2, var_33_arg_0=2, var_34=2, var_34_arg_0=1, var_34_arg_1=2, var_34_arg_2=1, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=15, input_3=16, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=1, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=2, var_29_arg_0=0, var_29_arg_1=1, var_29_arg_2=2, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=15, input_3=16, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=1, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=2, var_29_arg_0=0, var_29_arg_1=1, var_29_arg_2=2, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=2, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=15, input_3=16, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=2, state_8=2, var_10=1, var_10_arg_0=1, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=1, var_24_arg_0=1, var_25=1, var_26=2, var_26_arg_0=1, var_26_arg_1=1, var_27=2, var_27_arg_0=2, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=2, var_29_arg_0=0, var_29_arg_1=1, var_29_arg_2=2, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=17, input_3=18, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=2, state_8=2, var_10=1, var_10_arg_0=2, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=2, var_29_arg_0=1, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=17, input_3=18, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=2, state_8=2, var_10=1, var_10_arg_0=2, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=2, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=2, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=0, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=17, input_3=18, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=2, state_8=2, var_10=1, var_10_arg_0=2, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=2, var_29_arg_0=1, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=1, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=17, input_3=18, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=2, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=2, state_8=2, var_10=1, var_10_arg_0=2, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=2, var_29_arg_0=1, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=2, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=3, var_34_arg_1=3, var_34_arg_2=2, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=17, input_3=18, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=2, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=2, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=2, var_29_arg_0=1, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=3, var_34_arg_0=1, var_34_arg_1=3, var_34_arg_2=2, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=19, input_3=20, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=2, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=2, var_29_arg_0=0, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=3, var_34_arg_0=1, var_34_arg_1=3, var_34_arg_2=2, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=19, input_3=20, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=2, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=2, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=2, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=3, var_29_arg_1=2, var_29_arg_2=3, var_31=2, var_31_arg_0=2, var_32=3, var_32_arg_0=2, var_32_arg_1=1, var_33=3, var_33_arg_0=3, var_34=3, var_34_arg_0=1, var_34_arg_1=3, var_34_arg_2=2, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=19, input_3=20, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=2, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=3, var_29_arg_0=0, var_29_arg_1=2, var_29_arg_2=3, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=19, input_3=20, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=2, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=3, var_29_arg_0=0, var_29_arg_1=2, var_29_arg_2=3, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=3, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=19, input_3=20, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=3, state_8=3, var_10=1, var_10_arg_0=2, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=2, var_24_arg_0=2, var_25=1, var_26=3, var_26_arg_0=2, var_26_arg_1=1, var_27=3, var_27_arg_0=3, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=3, var_29_arg_0=0, var_29_arg_1=2, var_29_arg_2=3, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=21, input_3=22, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=3, state_8=3, var_10=1, var_10_arg_0=3, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=3, var_29_arg_0=1, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=21, input_3=22, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=3, state_8=3, var_10=1, var_10_arg_0=3, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=3, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=3, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=0, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=21, input_3=22, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=3, state_8=3, var_10=1, var_10_arg_0=3, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=3, var_29_arg_0=1, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=1, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=21, input_3=22, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=3, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=3, state_8=3, var_10=1, var_10_arg_0=3, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=3, var_29_arg_0=1, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=3, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=4, var_34_arg_1=4, var_34_arg_2=3, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=21, input_3=22, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=3, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=3, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=3, var_29_arg_0=1, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=4, var_34_arg_0=1, var_34_arg_1=4, var_34_arg_2=3, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=23, input_3=24, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=3, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=3, var_29_arg_0=0, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=4, var_34_arg_0=1, var_34_arg_1=4, var_34_arg_2=3, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=23, input_3=24, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=3, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=3, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=3, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=4, var_29_arg_1=3, var_29_arg_2=4, var_31=3, var_31_arg_0=3, var_32=4, var_32_arg_0=3, var_32_arg_1=1, var_33=4, var_33_arg_0=4, var_34=4, var_34_arg_0=1, var_34_arg_1=4, var_34_arg_2=3, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=23, input_3=24, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=3, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=4, var_29_arg_0=0, var_29_arg_1=3, var_29_arg_2=4, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=23, input_3=24, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=3, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=4, var_29_arg_0=0, var_29_arg_1=3, var_29_arg_2=4, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=4, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=23, input_3=24, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=4, state_8=4, var_10=1, var_10_arg_0=3, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=3, var_24_arg_0=3, var_25=1, var_26=4, var_26_arg_0=3, var_26_arg_1=1, var_27=4, var_27_arg_0=4, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=4, var_29_arg_0=0, var_29_arg_1=3, var_29_arg_2=4, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=25, input_3=26, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=4, state_8=4, var_10=1, var_10_arg_0=4, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=4, var_29_arg_0=1, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=25, input_3=26, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=4, state_8=4, var_10=1, var_10_arg_0=4, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=4, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=4, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=0, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=25, input_3=26, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=4, state_8=4, var_10=1, var_10_arg_0=4, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=4, var_29_arg_0=1, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=1, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=25, input_3=26, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=4, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=4, state_8=4, var_10=1, var_10_arg_0=4, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=4, var_29_arg_0=1, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=4, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=5, var_34_arg_1=5, var_34_arg_2=4, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=25, input_3=26, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=4, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=4, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=4, var_29_arg_0=1, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=5, var_34_arg_0=1, var_34_arg_1=5, var_34_arg_2=4, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=27, input_3=28, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=4, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=4, var_29_arg_0=0, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=5, var_34_arg_0=1, var_34_arg_1=5, var_34_arg_2=4, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=27, input_3=28, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=4, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=4, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=4, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=5, var_29_arg_1=4, var_29_arg_2=5, var_31=4, var_31_arg_0=4, var_32=5, var_32_arg_0=4, var_32_arg_1=1, var_33=5, var_33_arg_0=5, var_34=5, var_34_arg_0=1, var_34_arg_1=5, var_34_arg_2=4, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=27, input_3=28, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=4, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=5, var_29_arg_0=0, var_29_arg_1=4, var_29_arg_2=5, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=27, input_3=28, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=4, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=5, var_29_arg_0=0, var_29_arg_1=4, var_29_arg_2=5, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=5, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=27, input_3=28, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=5, state_8=5, var_10=1, var_10_arg_0=4, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=4, var_24_arg_0=4, var_25=1, var_26=5, var_26_arg_0=4, var_26_arg_1=1, var_27=5, var_27_arg_0=5, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=5, var_29_arg_0=0, var_29_arg_1=4, var_29_arg_2=5, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=29, input_3=30, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=5, state_8=5, var_10=1, var_10_arg_0=5, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=5, var_29_arg_0=1, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=29, input_3=30, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=5, state_8=5, var_10=1, var_10_arg_0=5, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=5, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=5, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=0, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=29, input_3=30, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=5, state_8=5, var_10=1, var_10_arg_0=5, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=5, var_29_arg_0=1, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=1, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=29, input_3=30, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=5, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=5, state_8=5, var_10=1, var_10_arg_0=5, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=5, var_29_arg_0=1, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=5, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=6, var_34_arg_1=6, var_34_arg_2=5, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=29, input_3=30, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=5, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=5, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=5, var_29_arg_0=1, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=6, var_34_arg_0=1, var_34_arg_1=6, var_34_arg_2=5, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=31, input_3=32, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=5, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=5, var_29_arg_0=0, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=6, var_34_arg_0=1, var_34_arg_1=6, var_34_arg_2=5, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=31, input_3=32, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=5, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=5, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=5, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=6, var_29_arg_1=5, var_29_arg_2=6, var_31=5, var_31_arg_0=5, var_32=6, var_32_arg_0=5, var_32_arg_1=1, var_33=6, var_33_arg_0=6, var_34=6, var_34_arg_0=1, var_34_arg_1=6, var_34_arg_2=5, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=31, input_3=32, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=5, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=6, var_29_arg_0=0, var_29_arg_1=5, var_29_arg_2=6, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=31, input_3=32, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=5, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=6, var_29_arg_0=0, var_29_arg_1=5, var_29_arg_2=6, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=6, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=31, input_3=32, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=6, state_8=6, var_10=1, var_10_arg_0=5, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=5, var_24_arg_0=5, var_25=1, var_26=6, var_26_arg_0=5, var_26_arg_1=1, var_27=6, var_27_arg_0=6, var_28=0, var_28_arg_0=0, var_28_arg_1=1, var_29=6, var_29_arg_0=0, var_29_arg_1=5, var_29_arg_2=6, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=33, input_3=34, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=6, state_8=6, var_10=1, var_10_arg_0=6, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=6, var_29_arg_0=1, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=33, input_3=34, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=6, state_8=6, var_10=1, var_10_arg_0=6, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=6, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=6, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=0, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=33, input_3=34, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=6, state_8=6, var_10=1, var_10_arg_0=6, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=6, var_29_arg_0=1, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=1, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=33, input_3=34, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=6, next_37_arg_1=0, next_38_arg_1=0, state_18=0, state_20=0, state_6=6, state_8=6, var_10=1, var_10_arg_0=6, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=6, var_29_arg_0=1, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=6, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=7, var_34_arg_1=7, var_34_arg_2=6, var_36=0, var_36_arg_0=1, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=33, input_3=34, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=6, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=6, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_29=6, var_29_arg_0=1, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=7, var_34_arg_0=1, var_34_arg_1=7, var_34_arg_2=6, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=35, input_3=36, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=6, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=6, var_29_arg_0=0, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=7, var_34_arg_0=1, var_34_arg_1=7, var_34_arg_2=6, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=35, input_3=36, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=6, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=6, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=6, var_29_arg_0=0, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=7, var_29_arg_1=6, var_29_arg_2=7, var_31=6, var_31_arg_0=6, var_32=7, var_32_arg_0=6, var_32_arg_1=1, var_33=7, var_33_arg_0=7, var_34=7, var_34_arg_0=1, var_34_arg_1=7, var_34_arg_2=6, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=35, input_3=36, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=6, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=7, var_29_arg_0=0, var_29_arg_1=6, var_29_arg_2=7, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=35, input_3=36, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=0, state_18=1, state_20=0, state_6=6, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=7, var_29_arg_0=0, var_29_arg_1=6, var_29_arg_2=7, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=0, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=7, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=35, input_3=36, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=7, state_8=7, var_10=1, var_10_arg_0=6, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=6, var_24_arg_0=6, var_25=1, var_26=7, var_26_arg_0=6, var_26_arg_1=1, var_27=7, var_27_arg_0=7, var_28=0, var_28_arg_0=1, var_28_arg_1=0, var_29=7, var_29_arg_0=0, var_29_arg_1=6, var_29_arg_2=7, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L71] RET __VERIFIER_assert(!(bad_16_arg_0)) [L73] SORT_1 var_28_arg_0 = state_18; [L74] SORT_1 var_28_arg_1 = state_20; [L75] SORT_1 var_28 = var_28_arg_0 == var_28_arg_1; [L76] SORT_4 var_24_arg_0 = state_6; [L77] var_24_arg_0 = var_24_arg_0 & mask_SORT_4 [L78] SORT_23 var_24 = var_24_arg_0; [L79] SORT_23 var_26_arg_0 = var_24; [L80] SORT_23 var_26_arg_1 = var_25; [L81] SORT_23 var_26 = var_26_arg_0 + var_26_arg_1; [L82] SORT_23 var_27_arg_0 = var_26; [L83] SORT_4 var_27 = var_27_arg_0 >> 0; [L84] SORT_1 var_29_arg_0 = var_28; [L85] SORT_4 var_29_arg_1 = state_6; [L86] SORT_4 var_29_arg_2 = var_27; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=37, input_3=38, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=7, state_8=7, var_10=1, var_10_arg_0=7, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=7, var_24_arg_0=7, var_25=1, var_26=8, var_26_arg_0=7, var_26_arg_1=1, var_27=8, var_27_arg_0=8, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=7, var_29_arg_0=1, var_29_arg_1=7, var_29_arg_2=8, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L87] EXPR var_29_arg_0 ? var_29_arg_1 : var_29_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=37, input_3=38, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=7, state_8=7, var_10=1, var_10_arg_0=7, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=7, var_24_arg_0=7, var_25=1, var_26=8, var_26_arg_0=7, var_26_arg_1=1, var_27=8, var_27_arg_0=8, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=7, var_29_arg_0=1, var_29_arg_0 ? var_29_arg_1 : var_29_arg_2=7, var_29_arg_1=7, var_29_arg_2=8, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=0, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L87] SORT_4 var_29 = var_29_arg_0 ? var_29_arg_1 : var_29_arg_2; [L88] var_29 = var_29 & mask_SORT_4 [L89] SORT_4 next_30_arg_1 = var_29; [L90] SORT_4 var_31_arg_0 = state_8; [L91] var_31_arg_0 = var_31_arg_0 & mask_SORT_4 [L92] SORT_23 var_31 = var_31_arg_0; [L93] SORT_23 var_32_arg_0 = var_31; [L94] SORT_23 var_32_arg_1 = var_25; [L95] SORT_23 var_32 = var_32_arg_0 + var_32_arg_1; [L96] SORT_23 var_33_arg_0 = var_32; [L97] SORT_4 var_33 = var_33_arg_0 >> 0; [L98] SORT_1 var_34_arg_0 = var_28; [L99] SORT_4 var_34_arg_1 = var_33; [L100] SORT_4 var_34_arg_2 = state_8; VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=37, input_3=38, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=7, state_8=7, var_10=1, var_10_arg_0=7, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=7, var_24_arg_0=7, var_25=1, var_26=8, var_26_arg_0=7, var_26_arg_1=1, var_27=8, var_27_arg_0=8, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=7, var_29_arg_0=1, var_29_arg_1=7, var_29_arg_2=8, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=1, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L101] EXPR var_34_arg_0 ? var_34_arg_1 : var_34_arg_2 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=37, input_3=38, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=7, next_37_arg_1=1, next_38_arg_1=1, state_18=1, state_20=1, state_6=7, state_8=7, var_10=1, var_10_arg_0=7, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=7, var_24_arg_0=7, var_25=1, var_26=8, var_26_arg_0=7, var_26_arg_1=1, var_27=8, var_27_arg_0=8, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=7, var_29_arg_0=1, var_29_arg_1=7, var_29_arg_2=8, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=7, var_34_arg_0=1, var_34_arg_0 ? var_34_arg_1 : var_34_arg_2=8, var_34_arg_1=8, var_34_arg_2=7, var_36=1, var_36_arg_0=0, var_5=0] [L101] SORT_4 var_34 = var_34_arg_0 ? var_34_arg_1 : var_34_arg_2; [L102] var_34 = var_34 & mask_SORT_4 [L103] SORT_4 next_35_arg_1 = var_34; [L104] SORT_1 var_36_arg_0 = state_20; [L105] SORT_1 var_36 = ~var_36_arg_0; [L106] var_36 = var_36 & mask_SORT_1 [L107] SORT_1 next_37_arg_1 = var_36; [L108] SORT_1 next_38_arg_1 = state_18; [L110] state_6 = next_30_arg_1 [L111] state_8 = next_35_arg_1 [L112] state_18 = next_37_arg_1 [L113] state_20 = next_38_arg_1 VAL [bad_16_arg_0=0, init_19_arg_1=0, init_21_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_2=37, input_3=38, mask_SORT_1=1, mask_SORT_23=4294967295, mask_SORT_4=7, msb_SORT_1=1, msb_SORT_23=2147483648, msb_SORT_4=4, next_30_arg_1=7, next_35_arg_1=0, next_37_arg_1=0, next_38_arg_1=1, state_18=0, state_20=1, state_6=7, state_8=0, var_10=1, var_10_arg_0=7, var_10_arg_1=7, var_13=1, var_14=254, var_14_arg_0=1, var_15=0, var_15_arg_0=1, var_15_arg_1=254, var_17=0, var_24=7, var_24_arg_0=7, var_25=1, var_26=8, var_26_arg_0=7, var_26_arg_1=1, var_27=8, var_27_arg_0=8, var_28=1, var_28_arg_0=1, var_28_arg_1=1, var_29=7, var_29_arg_0=1, var_29_arg_1=7, var_29_arg_2=8, var_31=7, var_31_arg_0=7, var_32=8, var_32_arg_0=7, var_32_arg_1=1, var_33=8, var_33_arg_0=8, var_34=0, var_34_arg_0=1, var_34_arg_1=8, var_34_arg_2=7, var_36=0, var_36_arg_0=1, var_5=0] [L57] input_2 = __VERIFIER_nondet_uchar() [L58] input_3 = __VERIFIER_nondet_uchar() [L61] SORT_4 var_10_arg_0 = state_6; [L62] SORT_4 var_10_arg_1 = state_8; [L63] SORT_1 var_10 = var_10_arg_0 <= var_10_arg_1; [L64] SORT_1 var_14_arg_0 = var_10; [L65] SORT_1 var_14 = ~var_14_arg_0; [L66] SORT_1 var_15_arg_0 = var_13; [L67] SORT_1 var_15_arg_1 = var_14; [L68] SORT_1 var_15 = var_15_arg_0 & var_15_arg_1; [L69] var_15 = var_15 & mask_SORT_1 [L70] SORT_1 bad_16_arg_0 = var_15; [L71] CALL __VERIFIER_assert(!(bad_16_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 15 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 454.4s, OverallIterations: 14, TraceHistogramMax: 16, PathProgramHistogramMax: 9, EmptinessCheckTime: 0.0s, AutomataDifference: 227.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2083 SdHoareTripleChecker+Valid, 5.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2083 mSDsluCounter, 1779 SdHoareTripleChecker+Invalid, 4.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 8938 IncrementalHoareTripleChecker+Unchecked, 1631 mSDsCounter, 259 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 4837 IncrementalHoareTripleChecker+Invalid, 14034 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 259 mSolverCounterUnsat, 148 mSDtfsCounter, 4837 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 2533 GetRequests, 1521 SyntacticMatches, 90 SemanticMatches, 922 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46836 ImplicationChecksByTransitivity, 411.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=216occurred in iteration=13, InterpolantAutomatonStates: 468, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 13 MinimizatonAttempts, 191 StatesRemovedByMinimization, 12 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.9s SsaConstructionTime, 2.8s SatisfiabilityAnalysisTime, 215.1s InterpolantComputationTime, 1210 NumberOfCodeBlocks, 1210 NumberOfCodeBlocksAsserted, 94 NumberOfCheckSat, 2069 ConstructedInterpolants, 741 QuantifiedInterpolants, 122141 SizeOfPredicates, 1786 NumberOfNonLiveVariables, 8271 ConjunctsInSsa, 2018 ConjunctsInUnsatCore, 57 InterpolantComputations, 5 PerfectInterpolantSequences, 698/6658 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-03 02:07:45,725 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_48116cf3-04e2-406d-9079-fc970602931b/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE