./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash a057f8e84c57630b688ef84d43f8a057c3ac3f8873065d131b16909986852b1e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:20:31,199 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:20:31,201 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:20:31,245 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:20:31,245 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:20:31,246 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:20:31,247 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:20:31,249 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:20:31,251 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:20:31,252 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:20:31,253 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:20:31,254 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:20:31,255 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:20:31,256 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:20:31,257 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:20:31,258 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:20:31,259 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:20:31,260 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:20:31,262 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:20:31,265 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:20:31,267 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:20:31,268 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:20:31,270 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:20:31,271 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:20:31,274 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:20:31,275 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:20:31,275 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:20:31,276 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:20:31,277 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:20:31,278 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:20:31,278 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:20:31,279 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:20:31,280 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:20:31,281 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:20:31,282 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:20:31,282 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:20:31,283 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:20:31,284 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:20:31,284 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:20:31,285 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:20:31,286 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:20:31,287 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:20:31,310 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:20:31,310 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:20:31,311 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:20:31,311 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:20:31,312 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:20:31,312 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:20:31,312 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:20:31,312 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:20:31,313 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:20:31,313 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:20:31,313 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:20:31,313 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:20:31,314 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:20:31,314 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:20:31,314 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:20:31,315 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:20:31,315 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:20:31,315 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:20:31,316 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:20:31,316 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:20:31,317 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:20:31,317 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:20:31,317 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:20:31,317 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:20:31,318 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:20:31,318 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:20:31,318 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:20:31,318 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:20:31,319 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:20:31,319 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:20:31,319 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:20:31,320 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:20:31,320 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:20:31,320 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:20:31,320 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:20:31,320 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:20:31,321 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:20:31,321 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:20:31,321 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a057f8e84c57630b688ef84d43f8a057c3ac3f8873065d131b16909986852b1e [2022-11-03 02:20:31,547 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:20:31,573 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:20:31,576 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:20:31,577 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:20:31,578 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:20:31,580 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:20:31,668 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/122246b09/019680e999bd4e5bb401d1a13f3a74bc/FLAGde206e8f1 [2022-11-03 02:20:32,281 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:20:32,281 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:20:32,309 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/122246b09/019680e999bd4e5bb401d1a13f3a74bc/FLAGde206e8f1 [2022-11-03 02:20:32,516 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/122246b09/019680e999bd4e5bb401d1a13f3a74bc [2022-11-03 02:20:32,520 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:20:32,523 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:20:32,529 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:20:32,529 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:20:32,533 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:20:32,534 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:20:32" (1/1) ... [2022-11-03 02:20:32,537 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@56eb7d57 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:32, skipping insertion in model container [2022-11-03 02:20:32,537 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:20:32" (1/1) ... [2022-11-03 02:20:32,545 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:20:32,623 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:20:32,859 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c[1014,1027] [2022-11-03 02:20:33,292 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:20:33,296 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:20:33,307 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c[1014,1027] [2022-11-03 02:20:33,498 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:20:33,524 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:20:33,525 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33 WrapperNode [2022-11-03 02:20:33,525 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:20:33,526 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:20:33,526 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:20:33,526 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:20:33,549 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:33,612 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:33,861 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2212 [2022-11-03 02:20:33,861 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:20:33,862 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:20:33,863 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:20:33,863 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:20:33,872 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:33,873 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:33,892 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:33,892 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,013 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,034 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,063 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,076 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,126 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:20:34,128 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:20:34,128 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:20:34,128 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:20:34,129 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (1/1) ... [2022-11-03 02:20:34,148 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:20:34,160 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:20:34,174 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:20:34,204 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:20:34,223 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:20:34,224 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:20:34,855 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:20:34,857 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:22:03,888 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:22:22,976 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:22:22,977 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:22:22,979 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:22:22 BoogieIcfgContainer [2022-11-03 02:22:22,980 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:22:22,983 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:22:22,983 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:22:22,988 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:22:22,988 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:20:32" (1/3) ... [2022-11-03 02:22:22,989 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@eacc57e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:22:22, skipping insertion in model container [2022-11-03 02:22:22,989 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:20:33" (2/3) ... [2022-11-03 02:22:22,990 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@eacc57e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:22:22, skipping insertion in model container [2022-11-03 02:22:22,990 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:22:22" (3/3) ... [2022-11-03 02:22:22,991 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:22:23,011 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:22:23,011 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:22:23,060 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:22:23,067 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@37eba692, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:22:23,068 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:22:23,072 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:22:23,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:22:23,078 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:22:23,079 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:22:23,080 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:22:23,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:22:23,085 INFO L85 PathProgramCache]: Analyzing trace with hash 17884628, now seen corresponding path program 1 times [2022-11-03 02:22:23,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:22:23,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [973059129] [2022-11-03 02:22:23,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:22:23,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:22:23,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:22:24,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:22:24,658 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 02:22:24,658 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [973059129] [2022-11-03 02:22:24,659 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [973059129] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:22:24,659 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:22:24,660 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 02:22:24,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519774782] [2022-11-03 02:22:24,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:22:24,667 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:22:24,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 02:22:24,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:22:24,705 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:22:24,707 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:22:27,057 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.25s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:22:27,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:22:27,145 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 02:22:27,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:22:27,148 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 02:22:27,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:22:27,156 INFO L225 Difference]: With dead ends: 15 [2022-11-03 02:22:27,156 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 02:22:27,159 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:22:27,162 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:22:27,163 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 1 Unknown, 0 Unchecked, 2.4s Time] [2022-11-03 02:22:27,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 02:22:27,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 02:22:27,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:22:27,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 02:22:27,194 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 02:22:27,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:22:27,195 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 02:22:27,195 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:22:27,196 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 02:22:27,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 02:22:27,196 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:22:27,196 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 02:22:27,197 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:22:27,197 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:22:27,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:22:27,198 INFO L85 PathProgramCache]: Analyzing trace with hash 253110985, now seen corresponding path program 1 times [2022-11-03 02:22:27,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:22:27,199 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2122382796] [2022-11-03 02:22:27,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:22:27,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:25:26,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:25:26,415 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:28:06,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:28:06,657 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:28:06,657 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:28:06,659 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:28:06,661 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 02:28:06,665 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 02:28:06,669 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:28:06,792 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:28:06,793 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:28:06,876 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:28:06 BoogieIcfgContainer [2022-11-03 02:28:06,876 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:28:06,879 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:28:06,879 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:28:06,880 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:28:06,881 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:22:22" (3/4) ... [2022-11-03 02:28:06,884 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:28:06,884 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:28:06,886 INFO L158 Benchmark]: Toolchain (without parser) took 454361.95ms. Allocated memory was 109.1MB in the beginning and 5.7GB in the end (delta: 5.5GB). Free memory was 72.9MB in the beginning and 3.7GB in the end (delta: -3.7GB). Peak memory consumption was 1.9GB. Max. memory is 16.1GB. [2022-11-03 02:28:06,887 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 86.0MB. Free memory is still 44.6MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:28:06,890 INFO L158 Benchmark]: CACSL2BoogieTranslator took 996.22ms. Allocated memory is still 109.1MB. Free memory was 72.7MB in the beginning and 70.1MB in the end (delta: 2.6MB). Peak memory consumption was 45.0MB. Max. memory is 16.1GB. [2022-11-03 02:28:06,891 INFO L158 Benchmark]: Boogie Procedure Inliner took 335.65ms. Allocated memory is still 109.1MB. Free memory was 70.1MB in the beginning and 49.2MB in the end (delta: 20.9MB). Peak memory consumption was 41.8MB. Max. memory is 16.1GB. [2022-11-03 02:28:06,894 INFO L158 Benchmark]: Boogie Preprocessor took 264.80ms. Allocated memory was 109.1MB in the beginning and 178.3MB in the end (delta: 69.2MB). Free memory was 49.2MB in the beginning and 109.9MB in the end (delta: -60.7MB). Peak memory consumption was 23.6MB. Max. memory is 16.1GB. [2022-11-03 02:28:06,895 INFO L158 Benchmark]: RCFGBuilder took 108851.93ms. Allocated memory was 178.3MB in the beginning and 4.3GB in the end (delta: 4.1GB). Free memory was 109.9MB in the beginning and 2.7GB in the end (delta: -2.6GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. [2022-11-03 02:28:06,896 INFO L158 Benchmark]: TraceAbstraction took 343894.30ms. Allocated memory was 4.3GB in the beginning and 5.7GB in the end (delta: 1.4GB). Free memory was 2.7GB in the beginning and 3.7GB in the end (delta: -1.0GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. [2022-11-03 02:28:06,896 INFO L158 Benchmark]: Witness Printer took 5.07ms. Allocated memory is still 5.7GB. Free memory is still 3.7GB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:28:06,900 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 86.0MB. Free memory is still 44.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 996.22ms. Allocated memory is still 109.1MB. Free memory was 72.7MB in the beginning and 70.1MB in the end (delta: 2.6MB). Peak memory consumption was 45.0MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 335.65ms. Allocated memory is still 109.1MB. Free memory was 70.1MB in the beginning and 49.2MB in the end (delta: 20.9MB). Peak memory consumption was 41.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 264.80ms. Allocated memory was 109.1MB in the beginning and 178.3MB in the end (delta: 69.2MB). Free memory was 49.2MB in the beginning and 109.9MB in the end (delta: -60.7MB). Peak memory consumption was 23.6MB. Max. memory is 16.1GB. * RCFGBuilder took 108851.93ms. Allocated memory was 178.3MB in the beginning and 4.3GB in the end (delta: 4.1GB). Free memory was 109.9MB in the beginning and 2.7GB in the end (delta: -2.6GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. * TraceAbstraction took 343894.30ms. Allocated memory was 4.3GB in the beginning and 5.7GB in the end (delta: 1.4GB). Free memory was 2.7GB in the beginning and 3.7GB in the end (delta: -1.0GB). Peak memory consumption was 1.2GB. Max. memory is 16.1GB. * Witness Printer took 5.07ms. Allocated memory is still 5.7GB. Free memory is still 3.7GB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 452, overapproximation of bitwiseAnd at line 191, overapproximation of bitwiseComplement at line 236, overapproximation of bitwiseXOr at line 255. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 8); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (8 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 24); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (24 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_2 var_5 = 0; [L38] const SORT_1 var_74 = 0; [L39] const SORT_2 var_85 = 255; [L40] const SORT_2 var_89 = 1; [L41] const SORT_2 var_97 = 2; [L42] const SORT_2 var_105 = 3; [L43] const SORT_2 var_113 = 4; [L44] const SORT_2 var_171 = 6; [L45] const SORT_2 var_173 = 5; [L46] const SORT_2 var_179 = 0; [L47] const SORT_3 var_188 = 0; [L48] const SORT_4 var_292 = 1; [L49] const SORT_4 var_385 = 3; [L50] const SORT_4 var_397 = 0; [L51] const SORT_4 var_489 = 2; [L53] SORT_1 input_83; [L54] SORT_1 input_84; [L55] SORT_1 input_90; [L56] SORT_1 input_91; [L57] SORT_1 input_98; [L58] SORT_1 input_99; [L59] SORT_1 input_106; [L60] SORT_1 input_107; [L61] SORT_1 input_114; [L62] SORT_1 input_115; [L63] SORT_1 input_121; [L64] SORT_1 input_122; [L65] SORT_1 input_126; [L66] SORT_1 input_127; [L67] SORT_1 input_170; [L68] SORT_1 input_172; [L69] SORT_1 input_174; [L70] SORT_1 input_175; [L71] SORT_1 input_176; [L72] SORT_1 input_177; [L73] SORT_1 input_178; [L74] SORT_1 input_364; [L76] SORT_2 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L77] SORT_2 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L78] SORT_2 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L79] SORT_2 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L80] SORT_2 state_14 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L81] SORT_2 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L82] SORT_2 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L83] SORT_2 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L84] SORT_2 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L85] SORT_2 state_24 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L86] SORT_2 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L87] SORT_2 state_28 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L88] SORT_2 state_30 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L89] SORT_2 state_32 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L90] SORT_2 state_34 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L91] SORT_2 state_36 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L92] SORT_2 state_38 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L93] SORT_2 state_40 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L94] SORT_2 state_42 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L95] SORT_2 state_44 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L96] SORT_2 state_46 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L97] SORT_2 state_48 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L98] SORT_2 state_50 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L99] SORT_2 state_52 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L100] SORT_2 state_54 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L101] SORT_2 state_56 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L102] SORT_2 state_58 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L103] SORT_2 state_60 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L104] SORT_2 state_62 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L105] SORT_2 state_64 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L106] SORT_2 state_66 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L107] SORT_2 state_68 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L108] SORT_2 state_70 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L109] SORT_2 state_72 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L110] SORT_1 state_75 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] SORT_1 state_77 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L112] SORT_1 state_79 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L114] SORT_2 init_7_arg_1 = var_5; [L115] state_6 = init_7_arg_1 [L116] SORT_2 init_9_arg_1 = var_5; [L117] state_8 = init_9_arg_1 [L118] SORT_2 init_11_arg_1 = var_5; [L119] state_10 = init_11_arg_1 [L120] SORT_2 init_13_arg_1 = var_5; [L121] state_12 = init_13_arg_1 [L122] SORT_2 init_15_arg_1 = var_5; [L123] state_14 = init_15_arg_1 [L124] SORT_2 init_17_arg_1 = var_5; [L125] state_16 = init_17_arg_1 [L126] SORT_2 init_19_arg_1 = var_5; [L127] state_18 = init_19_arg_1 [L128] SORT_2 init_21_arg_1 = var_5; [L129] state_20 = init_21_arg_1 [L130] SORT_2 init_23_arg_1 = var_5; [L131] state_22 = init_23_arg_1 [L132] SORT_2 init_25_arg_1 = var_5; [L133] state_24 = init_25_arg_1 [L134] SORT_2 init_27_arg_1 = var_5; [L135] state_26 = init_27_arg_1 [L136] SORT_2 init_29_arg_1 = var_5; [L137] state_28 = init_29_arg_1 [L138] SORT_2 init_31_arg_1 = var_5; [L139] state_30 = init_31_arg_1 [L140] SORT_2 init_33_arg_1 = var_5; [L141] state_32 = init_33_arg_1 [L142] SORT_2 init_35_arg_1 = var_5; [L143] state_34 = init_35_arg_1 [L144] SORT_2 init_37_arg_1 = var_5; [L145] state_36 = init_37_arg_1 [L146] SORT_2 init_39_arg_1 = var_5; [L147] state_38 = init_39_arg_1 [L148] SORT_2 init_41_arg_1 = var_5; [L149] state_40 = init_41_arg_1 [L150] SORT_2 init_43_arg_1 = var_5; [L151] state_42 = init_43_arg_1 [L152] SORT_2 init_45_arg_1 = var_5; [L153] state_44 = init_45_arg_1 [L154] SORT_2 init_47_arg_1 = var_5; [L155] state_46 = init_47_arg_1 [L156] SORT_2 init_49_arg_1 = var_5; [L157] state_48 = init_49_arg_1 [L158] SORT_2 init_51_arg_1 = var_5; [L159] state_50 = init_51_arg_1 [L160] SORT_2 init_53_arg_1 = var_5; [L161] state_52 = init_53_arg_1 [L162] SORT_2 init_55_arg_1 = var_5; [L163] state_54 = init_55_arg_1 [L164] SORT_2 init_57_arg_1 = var_5; [L165] state_56 = init_57_arg_1 [L166] SORT_2 init_59_arg_1 = var_5; [L167] state_58 = init_59_arg_1 [L168] SORT_2 init_61_arg_1 = var_5; [L169] state_60 = init_61_arg_1 [L170] SORT_2 init_63_arg_1 = var_5; [L171] state_62 = init_63_arg_1 [L172] SORT_2 init_65_arg_1 = var_5; [L173] state_64 = init_65_arg_1 [L174] SORT_2 init_67_arg_1 = var_5; [L175] state_66 = init_67_arg_1 [L176] SORT_2 init_69_arg_1 = var_5; [L177] state_68 = init_69_arg_1 [L178] SORT_2 init_71_arg_1 = var_5; [L179] state_70 = init_71_arg_1 [L180] SORT_2 init_73_arg_1 = var_5; [L181] state_72 = init_73_arg_1 [L182] SORT_1 init_76_arg_1 = var_74; [L183] state_75 = init_76_arg_1 [L184] SORT_1 init_78_arg_1 = var_74; [L185] state_77 = init_78_arg_1 [L186] SORT_1 init_80_arg_1 = var_74; [L187] state_79 = init_80_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_31_arg_1=0, init_33_arg_1=0, init_35_arg_1=0, init_37_arg_1=0, init_39_arg_1=0, init_41_arg_1=0, init_43_arg_1=0, init_45_arg_1=0, init_47_arg_1=0, init_49_arg_1=0, init_51_arg_1=0, init_53_arg_1=0, init_55_arg_1=0, init_57_arg_1=0, init_59_arg_1=0, init_61_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, init_76_arg_1=0, init_78_arg_1=0, init_7_arg_1=0, init_80_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_30=0, state_32=0, state_34=0, state_36=0, state_38=0, state_40=0, state_42=0, state_44=0, state_46=0, state_48=0, state_50=0, state_52=0, state_54=0, state_56=0, state_58=0, state_6=0, state_60=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, state_75=0, state_77=0, state_79=0, state_8=0, var_105=3, var_113=4, var_171=6, var_173=5, var_179=0, var_188=0, var_292=1, var_385=3, var_397=0, var_489=2, var_5=0, var_74=0, var_85=255, var_89=1, var_97=2] [L190] input_83 = __VERIFIER_nondet_uchar() [L191] input_83 = input_83 & mask_SORT_1 [L192] input_84 = __VERIFIER_nondet_uchar() [L193] input_84 = input_84 & mask_SORT_1 [L194] input_90 = __VERIFIER_nondet_uchar() [L195] input_90 = input_90 & mask_SORT_1 [L196] input_91 = __VERIFIER_nondet_uchar() [L197] input_91 = input_91 & mask_SORT_1 [L198] input_98 = __VERIFIER_nondet_uchar() [L199] input_98 = input_98 & mask_SORT_1 [L200] input_99 = __VERIFIER_nondet_uchar() [L201] input_99 = input_99 & mask_SORT_1 [L202] input_106 = __VERIFIER_nondet_uchar() [L203] input_106 = input_106 & mask_SORT_1 [L204] input_107 = __VERIFIER_nondet_uchar() [L205] input_107 = input_107 & mask_SORT_1 [L206] input_114 = __VERIFIER_nondet_uchar() [L207] input_114 = input_114 & mask_SORT_1 [L208] input_115 = __VERIFIER_nondet_uchar() [L209] input_115 = input_115 & mask_SORT_1 [L210] input_121 = __VERIFIER_nondet_uchar() [L211] input_121 = input_121 & mask_SORT_1 [L212] input_122 = __VERIFIER_nondet_uchar() [L213] input_122 = input_122 & mask_SORT_1 [L214] input_126 = __VERIFIER_nondet_uchar() [L215] input_126 = input_126 & mask_SORT_1 [L216] input_127 = __VERIFIER_nondet_uchar() [L217] input_127 = input_127 & mask_SORT_1 [L218] input_170 = __VERIFIER_nondet_uchar() [L219] input_170 = input_170 & mask_SORT_1 [L220] input_172 = __VERIFIER_nondet_uchar() [L221] input_172 = input_172 & mask_SORT_1 [L222] input_174 = __VERIFIER_nondet_uchar() [L223] input_174 = input_174 & mask_SORT_1 [L224] input_175 = __VERIFIER_nondet_uchar() [L225] input_175 = input_175 & mask_SORT_1 [L226] input_176 = __VERIFIER_nondet_uchar() [L227] input_176 = input_176 & mask_SORT_1 [L228] input_177 = __VERIFIER_nondet_uchar() [L229] input_177 = input_177 & mask_SORT_1 [L230] input_178 = __VERIFIER_nondet_uchar() [L231] input_178 = input_178 & mask_SORT_1 [L232] input_364 = __VERIFIER_nondet_uchar() [L235] SORT_1 var_81_arg_0 = state_77; [L236] SORT_1 var_81_arg_1 = ~state_79; [L237] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L238] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L239] var_81 = var_81 & mask_SORT_1 [L240] SORT_1 bad_82_arg_0 = var_81; [L241] CALL __VERIFIER_assert(!(bad_82_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L241] RET __VERIFIER_assert(!(bad_82_arg_0)) [L243] SORT_1 var_86_arg_0 = input_84; [L244] SORT_2 var_86_arg_1 = var_85; [L245] SORT_2 var_86_arg_2 = state_6; [L246] EXPR var_86_arg_0 ? var_86_arg_1 : var_86_arg_2 [L246] SORT_2 var_86 = var_86_arg_0 ? var_86_arg_1 : var_86_arg_2; [L247] SORT_1 var_87_arg_0 = input_83; [L248] SORT_2 var_87_arg_1 = state_62; [L249] SORT_2 var_87_arg_2 = var_86; [L250] EXPR var_87_arg_0 ? var_87_arg_1 : var_87_arg_2 [L250] SORT_2 var_87 = var_87_arg_0 ? var_87_arg_1 : var_87_arg_2; [L251] var_87 = var_87 & mask_SORT_2 [L252] SORT_2 next_88_arg_1 = var_87; [L253] SORT_2 var_92_arg_0 = var_89; [L254] SORT_2 var_92_arg_1 = state_8; [L255] SORT_2 var_92 = var_92_arg_0 ^ var_92_arg_1; [L256] var_92 = var_92 & mask_SORT_2 [L257] SORT_1 var_93_arg_0 = input_91; [L258] SORT_2 var_93_arg_1 = var_85; [L259] SORT_2 var_93_arg_2 = var_92; [L260] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 [L260] SORT_2 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L261] SORT_1 var_94_arg_0 = input_90; [L262] SORT_2 var_94_arg_1 = state_62; [L263] SORT_2 var_94_arg_2 = var_93; [L264] EXPR var_94_arg_0 ? var_94_arg_1 : var_94_arg_2 [L264] SORT_2 var_94 = var_94_arg_0 ? var_94_arg_1 : var_94_arg_2; [L265] SORT_2 var_95_arg_0 = var_89; [L266] SORT_2 var_95_arg_1 = var_94; [L267] SORT_2 var_95 = var_95_arg_0 ^ var_95_arg_1; [L268] SORT_2 next_96_arg_1 = var_95; [L269] SORT_2 var_100_arg_0 = var_97; [L270] SORT_2 var_100_arg_1 = state_10; [L271] SORT_2 var_100 = var_100_arg_0 ^ var_100_arg_1; [L272] var_100 = var_100 & mask_SORT_2 [L273] SORT_1 var_101_arg_0 = input_99; [L274] SORT_2 var_101_arg_1 = var_85; [L275] SORT_2 var_101_arg_2 = var_100; [L276] EXPR var_101_arg_0 ? var_101_arg_1 : var_101_arg_2 [L276] SORT_2 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L277] SORT_1 var_102_arg_0 = input_98; [L278] SORT_2 var_102_arg_1 = state_62; [L279] SORT_2 var_102_arg_2 = var_101; [L280] EXPR var_102_arg_0 ? var_102_arg_1 : var_102_arg_2 [L280] SORT_2 var_102 = var_102_arg_0 ? var_102_arg_1 : var_102_arg_2; [L281] SORT_2 var_103_arg_0 = var_97; [L282] SORT_2 var_103_arg_1 = var_102; [L283] SORT_2 var_103 = var_103_arg_0 ^ var_103_arg_1; [L284] SORT_2 next_104_arg_1 = var_103; [L285] SORT_2 var_108_arg_0 = var_105; [L286] SORT_2 var_108_arg_1 = state_12; [L287] SORT_2 var_108 = var_108_arg_0 ^ var_108_arg_1; [L288] var_108 = var_108 & mask_SORT_2 [L289] SORT_1 var_109_arg_0 = input_107; [L290] SORT_2 var_109_arg_1 = var_85; [L291] SORT_2 var_109_arg_2 = var_108; [L292] EXPR var_109_arg_0 ? var_109_arg_1 : var_109_arg_2 [L292] SORT_2 var_109 = var_109_arg_0 ? var_109_arg_1 : var_109_arg_2; [L293] SORT_1 var_110_arg_0 = input_106; [L294] SORT_2 var_110_arg_1 = state_62; [L295] SORT_2 var_110_arg_2 = var_109; [L296] EXPR var_110_arg_0 ? var_110_arg_1 : var_110_arg_2 [L296] SORT_2 var_110 = var_110_arg_0 ? var_110_arg_1 : var_110_arg_2; [L297] SORT_2 var_111_arg_0 = var_105; [L298] SORT_2 var_111_arg_1 = var_110; [L299] SORT_2 var_111 = var_111_arg_0 ^ var_111_arg_1; [L300] SORT_2 next_112_arg_1 = var_111; [L301] SORT_2 var_116_arg_0 = var_113; [L302] SORT_2 var_116_arg_1 = state_14; [L303] SORT_2 var_116 = var_116_arg_0 ^ var_116_arg_1; [L304] var_116 = var_116 & mask_SORT_2 [L305] SORT_1 var_117_arg_0 = input_115; [L306] SORT_2 var_117_arg_1 = var_85; [L307] SORT_2 var_117_arg_2 = var_116; [L308] EXPR var_117_arg_0 ? var_117_arg_1 : var_117_arg_2 [L308] SORT_2 var_117 = var_117_arg_0 ? var_117_arg_1 : var_117_arg_2; [L309] SORT_1 var_118_arg_0 = input_114; [L310] SORT_2 var_118_arg_1 = state_62; [L311] SORT_2 var_118_arg_2 = var_117; [L312] EXPR var_118_arg_0 ? var_118_arg_1 : var_118_arg_2 [L312] SORT_2 var_118 = var_118_arg_0 ? var_118_arg_1 : var_118_arg_2; [L313] SORT_2 var_119_arg_0 = var_113; [L314] SORT_2 var_119_arg_1 = var_118; [L315] SORT_2 var_119 = var_119_arg_0 ^ var_119_arg_1; [L316] SORT_2 next_120_arg_1 = var_119; [L317] SORT_1 var_123_arg_0 = input_122; [L318] SORT_2 var_123_arg_1 = var_85; [L319] SORT_2 var_123_arg_2 = state_16; [L320] EXPR var_123_arg_0 ? var_123_arg_1 : var_123_arg_2 [L320] SORT_2 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L321] SORT_1 var_124_arg_0 = input_121; [L322] SORT_2 var_124_arg_1 = state_62; [L323] SORT_2 var_124_arg_2 = var_123; [L324] EXPR var_124_arg_0 ? var_124_arg_1 : var_124_arg_2 [L324] SORT_2 var_124 = var_124_arg_0 ? var_124_arg_1 : var_124_arg_2; [L325] var_124 = var_124 & mask_SORT_2 [L326] SORT_2 next_125_arg_1 = var_124; [L327] SORT_2 var_128_arg_0 = var_105; [L328] SORT_2 var_128_arg_1 = state_18; [L329] SORT_2 var_128 = var_128_arg_0 ^ var_128_arg_1; [L330] var_128 = var_128 & mask_SORT_2 [L331] SORT_1 var_129_arg_0 = input_127; [L332] SORT_2 var_129_arg_1 = var_85; [L333] SORT_2 var_129_arg_2 = var_128; [L334] EXPR var_129_arg_0 ? var_129_arg_1 : var_129_arg_2 [L334] SORT_2 var_129 = var_129_arg_0 ? var_129_arg_1 : var_129_arg_2; [L335] SORT_1 var_130_arg_0 = input_126; [L336] SORT_2 var_130_arg_1 = state_62; [L337] SORT_2 var_130_arg_2 = var_129; [L338] EXPR var_130_arg_0 ? var_130_arg_1 : var_130_arg_2 [L338] SORT_2 var_130 = var_130_arg_0 ? var_130_arg_1 : var_130_arg_2; [L339] SORT_2 var_131_arg_0 = var_105; [L340] SORT_2 var_131_arg_1 = var_130; [L341] SORT_2 var_131 = var_131_arg_0 ^ var_131_arg_1; [L342] SORT_2 next_132_arg_1 = var_131; [L343] SORT_2 var_133_arg_0 = var_89; [L344] SORT_2 var_133_arg_1 = state_20; [L345] SORT_2 var_133 = var_133_arg_0 ^ var_133_arg_1; [L346] var_133 = var_133 & mask_SORT_2 [L347] SORT_2 var_134_arg_0 = var_89; [L348] SORT_2 var_134_arg_1 = var_133; [L349] SORT_2 var_134 = var_134_arg_0 ^ var_134_arg_1; [L350] SORT_2 next_135_arg_1 = var_134; [L351] SORT_2 next_136_arg_1 = state_22; [L352] SORT_2 next_137_arg_1 = state_24; [L353] SORT_2 var_138_arg_0 = var_89; [L354] SORT_2 var_138_arg_1 = state_26; [L355] SORT_2 var_138 = var_138_arg_0 ^ var_138_arg_1; [L356] var_138 = var_138 & mask_SORT_2 [L357] SORT_2 var_139_arg_0 = var_89; [L358] SORT_2 var_139_arg_1 = var_138; [L359] SORT_2 var_139 = var_139_arg_0 ^ var_139_arg_1; [L360] SORT_2 next_140_arg_1 = var_139; [L361] SORT_2 var_141_arg_0 = var_89; [L362] SORT_2 var_141_arg_1 = state_28; [L363] SORT_2 var_141 = var_141_arg_0 ^ var_141_arg_1; [L364] var_141 = var_141 & mask_SORT_2 [L365] SORT_2 var_142_arg_0 = var_89; [L366] SORT_2 var_142_arg_1 = var_141; [L367] SORT_2 var_142 = var_142_arg_0 ^ var_142_arg_1; [L368] SORT_2 next_143_arg_1 = var_142; [L369] SORT_2 next_144_arg_1 = state_30; [L370] SORT_2 next_145_arg_1 = state_32; [L371] SORT_2 next_146_arg_1 = state_34; [L372] SORT_2 var_147_arg_0 = var_89; [L373] SORT_2 var_147_arg_1 = state_36; [L374] SORT_2 var_147 = var_147_arg_0 ^ var_147_arg_1; [L375] var_147 = var_147 & mask_SORT_2 [L376] SORT_2 var_148_arg_0 = var_89; [L377] SORT_2 var_148_arg_1 = var_147; [L378] SORT_2 var_148 = var_148_arg_0 ^ var_148_arg_1; [L379] SORT_2 next_149_arg_1 = var_148; [L380] SORT_2 var_150_arg_0 = var_89; [L381] SORT_2 var_150_arg_1 = state_38; [L382] SORT_2 var_150 = var_150_arg_0 ^ var_150_arg_1; [L383] var_150 = var_150 & mask_SORT_2 [L384] SORT_2 var_151_arg_0 = var_89; [L385] SORT_2 var_151_arg_1 = var_150; [L386] SORT_2 var_151 = var_151_arg_0 ^ var_151_arg_1; [L387] SORT_2 next_152_arg_1 = var_151; [L388] SORT_2 next_153_arg_1 = state_40; [L389] SORT_2 next_154_arg_1 = state_42; [L390] SORT_2 var_155_arg_0 = var_89; [L391] SORT_2 var_155_arg_1 = state_44; [L392] SORT_2 var_155 = var_155_arg_0 ^ var_155_arg_1; [L393] var_155 = var_155 & mask_SORT_2 [L394] SORT_2 var_156_arg_0 = var_89; [L395] SORT_2 var_156_arg_1 = var_155; [L396] SORT_2 var_156 = var_156_arg_0 ^ var_156_arg_1; [L397] SORT_2 next_157_arg_1 = var_156; [L398] SORT_2 next_158_arg_1 = state_46; [L399] SORT_2 var_159_arg_0 = var_89; [L400] SORT_2 var_159_arg_1 = state_48; [L401] SORT_2 var_159 = var_159_arg_0 ^ var_159_arg_1; [L402] var_159 = var_159 & mask_SORT_2 [L403] SORT_2 var_160_arg_0 = var_89; [L404] SORT_2 var_160_arg_1 = var_159; [L405] SORT_2 var_160 = var_160_arg_0 ^ var_160_arg_1; [L406] SORT_2 next_161_arg_1 = var_160; [L407] SORT_2 var_162_arg_0 = var_89; [L408] SORT_2 var_162_arg_1 = state_50; [L409] SORT_2 var_162 = var_162_arg_0 ^ var_162_arg_1; [L410] var_162 = var_162 & mask_SORT_2 [L411] SORT_2 var_163_arg_0 = var_89; [L412] SORT_2 var_163_arg_1 = var_162; [L413] SORT_2 var_163 = var_163_arg_0 ^ var_163_arg_1; [L414] SORT_2 next_164_arg_1 = var_163; [L415] SORT_2 next_165_arg_1 = state_52; [L416] SORT_2 next_166_arg_1 = state_54; [L417] SORT_2 next_167_arg_1 = state_56; [L418] SORT_2 next_168_arg_1 = state_58; [L419] SORT_2 next_169_arg_1 = state_60; [L420] SORT_1 var_180_arg_0 = input_178; [L421] SORT_2 var_180_arg_1 = var_179; [L422] SORT_2 var_180_arg_2 = state_62; [L423] EXPR var_180_arg_0 ? var_180_arg_1 : var_180_arg_2 [L423] SORT_2 var_180 = var_180_arg_0 ? var_180_arg_1 : var_180_arg_2; [L424] SORT_1 var_181_arg_0 = input_177; [L425] SORT_2 var_181_arg_1 = var_89; [L426] SORT_2 var_181_arg_2 = var_180; [L427] EXPR var_181_arg_0 ? var_181_arg_1 : var_181_arg_2 [L427] SORT_2 var_181 = var_181_arg_0 ? var_181_arg_1 : var_181_arg_2; [L428] SORT_1 var_182_arg_0 = input_176; [L429] SORT_2 var_182_arg_1 = var_97; [L430] SORT_2 var_182_arg_2 = var_181; [L431] EXPR var_182_arg_0 ? var_182_arg_1 : var_182_arg_2 [L431] SORT_2 var_182 = var_182_arg_0 ? var_182_arg_1 : var_182_arg_2; [L432] SORT_1 var_183_arg_0 = input_175; [L433] SORT_2 var_183_arg_1 = var_105; [L434] SORT_2 var_183_arg_2 = var_182; [L435] EXPR var_183_arg_0 ? var_183_arg_1 : var_183_arg_2 [L435] SORT_2 var_183 = var_183_arg_0 ? var_183_arg_1 : var_183_arg_2; [L436] SORT_1 var_184_arg_0 = input_174; [L437] SORT_2 var_184_arg_1 = var_113; [L438] SORT_2 var_184_arg_2 = var_183; [L439] EXPR var_184_arg_0 ? var_184_arg_1 : var_184_arg_2 [L439] SORT_2 var_184 = var_184_arg_0 ? var_184_arg_1 : var_184_arg_2; [L440] SORT_1 var_185_arg_0 = input_172; [L441] SORT_2 var_185_arg_1 = var_173; [L442] SORT_2 var_185_arg_2 = var_184; [L443] EXPR var_185_arg_0 ? var_185_arg_1 : var_185_arg_2 [L443] SORT_2 var_185 = var_185_arg_0 ? var_185_arg_1 : var_185_arg_2; [L444] SORT_1 var_186_arg_0 = input_170; [L445] SORT_2 var_186_arg_1 = var_171; [L446] SORT_2 var_186_arg_2 = var_185; [L447] EXPR var_186_arg_0 ? var_186_arg_1 : var_186_arg_2 [L447] SORT_2 var_186 = var_186_arg_0 ? var_186_arg_1 : var_186_arg_2; [L448] var_186 = var_186 & mask_SORT_2 [L449] SORT_2 next_187_arg_1 = var_186; [L450] SORT_3 var_189_arg_0 = var_188; [L451] SORT_2 var_189_arg_1 = state_64; [L452] SORT_4 var_189 = ((SORT_4)var_189_arg_0 << 8) | var_189_arg_1; [L453] SORT_3 var_190_arg_0 = var_188; [L454] SORT_2 var_190_arg_1 = state_32; [L455] SORT_4 var_190 = ((SORT_4)var_190_arg_0 << 8) | var_190_arg_1; [L456] SORT_4 var_191_arg_0 = var_189; [L457] SORT_4 var_191_arg_1 = var_190; [L458] SORT_4 var_191 = var_191_arg_0 - var_191_arg_1; [L459] SORT_4 var_192_arg_0 = var_191; [L460] SORT_2 var_192 = var_192_arg_0 >> 0; [L461] SORT_3 var_193_arg_0 = var_188; [L462] SORT_2 var_193_arg_1 = state_30; [L463] SORT_4 var_193 = ((SORT_4)var_193_arg_0 << 8) | var_193_arg_1; [L464] SORT_4 var_194_arg_0 = var_189; [L465] SORT_4 var_194_arg_1 = var_193; [L466] SORT_4 var_194 = var_194_arg_0 - var_194_arg_1; [L467] SORT_4 var_195_arg_0 = var_194; [L468] SORT_2 var_195 = var_195_arg_0 >> 0; [L469] SORT_3 var_196_arg_0 = var_188; [L470] SORT_2 var_196_arg_1 = var_141; [L471] SORT_4 var_196 = ((SORT_4)var_196_arg_0 << 8) | var_196_arg_1; [L472] SORT_4 var_197_arg_0 = var_189; [L473] SORT_4 var_197_arg_1 = var_196; [L474] SORT_4 var_197 = var_197_arg_0 - var_197_arg_1; [L475] SORT_4 var_198_arg_0 = var_197; [L476] SORT_2 var_198 = var_198_arg_0 >> 0; [L477] SORT_3 var_199_arg_0 = var_188; [L478] SORT_2 var_199_arg_1 = var_138; [L479] SORT_4 var_199 = ((SORT_4)var_199_arg_0 << 8) | var_199_arg_1; [L480] SORT_4 var_200_arg_0 = var_189; [L481] SORT_4 var_200_arg_1 = var_199; [L482] SORT_4 var_200 = var_200_arg_0 - var_200_arg_1; [L483] SORT_4 var_201_arg_0 = var_200; [L484] SORT_2 var_201 = var_201_arg_0 >> 0; [L485] SORT_3 var_202_arg_0 = var_188; [L486] SORT_2 var_202_arg_1 = state_24; [L487] SORT_4 var_202 = ((SORT_4)var_202_arg_0 << 8) | var_202_arg_1; [L488] SORT_4 var_203_arg_0 = var_189; [L489] SORT_4 var_203_arg_1 = var_202; [L490] SORT_4 var_203 = var_203_arg_0 - var_203_arg_1; [L491] SORT_4 var_204_arg_0 = var_203; [L492] SORT_2 var_204 = var_204_arg_0 >> 0; [L493] SORT_3 var_205_arg_0 = var_188; [L494] SORT_2 var_205_arg_1 = state_22; [L495] SORT_4 var_205 = ((SORT_4)var_205_arg_0 << 8) | var_205_arg_1; [L496] SORT_4 var_206_arg_0 = var_189; [L497] SORT_4 var_206_arg_1 = var_205; [L498] SORT_4 var_206 = var_206_arg_0 - var_206_arg_1; [L499] SORT_4 var_207_arg_0 = var_206; [L500] SORT_2 var_207 = var_207_arg_0 >> 0; [L501] SORT_3 var_208_arg_0 = var_188; [L502] SORT_2 var_208_arg_1 = var_133; [L503] SORT_4 var_208 = ((SORT_4)var_208_arg_0 << 8) | var_208_arg_1; [L504] SORT_4 var_209_arg_0 = var_189; [L505] SORT_4 var_209_arg_1 = var_208; [L506] SORT_4 var_209 = var_209_arg_0 - var_209_arg_1; [L507] SORT_4 var_210_arg_0 = var_209; [L508] SORT_2 var_210 = var_210_arg_0 >> 0; [L509] SORT_4 var_211_arg_0 = var_189; [L510] SORT_4 var_211_arg_1 = var_190; [L511] SORT_4 var_211 = var_211_arg_0 + var_211_arg_1; [L512] SORT_4 var_212_arg_0 = var_211; [L513] SORT_2 var_212 = var_212_arg_0 >> 0; [L514] SORT_4 var_213_arg_0 = var_189; [L515] SORT_4 var_213_arg_1 = var_193; [L516] SORT_4 var_213 = var_213_arg_0 + var_213_arg_1; [L517] SORT_4 var_214_arg_0 = var_213; [L518] SORT_2 var_214 = var_214_arg_0 >> 0; [L519] SORT_4 var_215_arg_0 = var_189; [L520] SORT_4 var_215_arg_1 = var_196; [L521] SORT_4 var_215 = var_215_arg_0 + var_215_arg_1; [L522] SORT_4 var_216_arg_0 = var_215; [L523] SORT_2 var_216 = var_216_arg_0 >> 0; [L524] SORT_4 var_217_arg_0 = var_189; [L525] SORT_4 var_217_arg_1 = var_199; [L526] SORT_4 var_217 = var_217_arg_0 + var_217_arg_1; [L527] SORT_4 var_218_arg_0 = var_217; [L528] SORT_2 var_218 = var_218_arg_0 >> 0; [L529] SORT_4 var_219_arg_0 = var_189; [L530] SORT_4 var_219_arg_1 = var_202; [L531] SORT_4 var_219 = var_219_arg_0 + var_219_arg_1; [L532] SORT_4 var_220_arg_0 = var_219; [L533] SORT_2 var_220 = var_220_arg_0 >> 0; [L534] SORT_4 var_221_arg_0 = var_189; [L535] SORT_4 var_221_arg_1 = var_205; [L536] SORT_4 var_221 = var_221_arg_0 + var_221_arg_1; [L537] SORT_4 var_222_arg_0 = var_221; [L538] SORT_2 var_222 = var_222_arg_0 >> 0; [L539] SORT_4 var_223_arg_0 = var_189; [L540] SORT_4 var_223_arg_1 = var_208; [L541] SORT_4 var_223 = var_223_arg_0 + var_223_arg_1; [L542] SORT_4 var_224_arg_0 = var_223; [L543] SORT_2 var_224 = var_224_arg_0 >> 0; [L544] SORT_1 var_225_arg_0 = input_84; [L545] SORT_2 var_225_arg_1 = var_224; [L546] SORT_2 var_225_arg_2 = state_64; [L547] EXPR var_225_arg_0 ? var_225_arg_1 : var_225_arg_2 [L547] SORT_2 var_225 = var_225_arg_0 ? var_225_arg_1 : var_225_arg_2; [L548] SORT_1 var_226_arg_0 = input_91; [L549] SORT_2 var_226_arg_1 = var_222; [L550] SORT_2 var_226_arg_2 = var_225; [L551] EXPR var_226_arg_0 ? var_226_arg_1 : var_226_arg_2 [L551] SORT_2 var_226 = var_226_arg_0 ? var_226_arg_1 : var_226_arg_2; [L552] SORT_1 var_227_arg_0 = input_99; [L553] SORT_2 var_227_arg_1 = var_220; [L554] SORT_2 var_227_arg_2 = var_226; [L555] EXPR var_227_arg_0 ? var_227_arg_1 : var_227_arg_2 [L555] SORT_2 var_227 = var_227_arg_0 ? var_227_arg_1 : var_227_arg_2; [L556] SORT_1 var_228_arg_0 = input_107; [L557] SORT_2 var_228_arg_1 = var_218; [L558] SORT_2 var_228_arg_2 = var_227; [L559] EXPR var_228_arg_0 ? var_228_arg_1 : var_228_arg_2 [L559] SORT_2 var_228 = var_228_arg_0 ? var_228_arg_1 : var_228_arg_2; [L560] SORT_1 var_229_arg_0 = input_115; [L561] SORT_2 var_229_arg_1 = var_216; [L562] SORT_2 var_229_arg_2 = var_228; [L563] EXPR var_229_arg_0 ? var_229_arg_1 : var_229_arg_2 [L563] SORT_2 var_229 = var_229_arg_0 ? var_229_arg_1 : var_229_arg_2; [L564] SORT_1 var_230_arg_0 = input_122; [L565] SORT_2 var_230_arg_1 = var_214; [L566] SORT_2 var_230_arg_2 = var_229; [L567] EXPR var_230_arg_0 ? var_230_arg_1 : var_230_arg_2 [L567] SORT_2 var_230 = var_230_arg_0 ? var_230_arg_1 : var_230_arg_2; [L568] SORT_1 var_231_arg_0 = input_127; [L569] SORT_2 var_231_arg_1 = var_212; [L570] SORT_2 var_231_arg_2 = var_230; [L571] EXPR var_231_arg_0 ? var_231_arg_1 : var_231_arg_2 [L571] SORT_2 var_231 = var_231_arg_0 ? var_231_arg_1 : var_231_arg_2; [L572] SORT_1 var_232_arg_0 = input_83; [L573] SORT_2 var_232_arg_1 = var_210; [L574] SORT_2 var_232_arg_2 = var_231; [L575] EXPR var_232_arg_0 ? var_232_arg_1 : var_232_arg_2 [L575] SORT_2 var_232 = var_232_arg_0 ? var_232_arg_1 : var_232_arg_2; [L576] SORT_1 var_233_arg_0 = input_90; [L577] SORT_2 var_233_arg_1 = var_207; [L578] SORT_2 var_233_arg_2 = var_232; [L579] EXPR var_233_arg_0 ? var_233_arg_1 : var_233_arg_2 [L579] SORT_2 var_233 = var_233_arg_0 ? var_233_arg_1 : var_233_arg_2; [L580] SORT_1 var_234_arg_0 = input_98; [L581] SORT_2 var_234_arg_1 = var_204; [L582] SORT_2 var_234_arg_2 = var_233; [L583] EXPR var_234_arg_0 ? var_234_arg_1 : var_234_arg_2 [L583] SORT_2 var_234 = var_234_arg_0 ? var_234_arg_1 : var_234_arg_2; [L584] SORT_1 var_235_arg_0 = input_106; [L585] SORT_2 var_235_arg_1 = var_201; [L586] SORT_2 var_235_arg_2 = var_234; [L587] EXPR var_235_arg_0 ? var_235_arg_1 : var_235_arg_2 [L587] SORT_2 var_235 = var_235_arg_0 ? var_235_arg_1 : var_235_arg_2; [L588] SORT_1 var_236_arg_0 = input_114; [L589] SORT_2 var_236_arg_1 = var_198; [L590] SORT_2 var_236_arg_2 = var_235; [L591] EXPR var_236_arg_0 ? var_236_arg_1 : var_236_arg_2 [L591] SORT_2 var_236 = var_236_arg_0 ? var_236_arg_1 : var_236_arg_2; [L592] SORT_1 var_237_arg_0 = input_121; [L593] SORT_2 var_237_arg_1 = var_195; [L594] SORT_2 var_237_arg_2 = var_236; [L595] EXPR var_237_arg_0 ? var_237_arg_1 : var_237_arg_2 [L595] SORT_2 var_237 = var_237_arg_0 ? var_237_arg_1 : var_237_arg_2; [L596] SORT_1 var_238_arg_0 = input_126; [L597] SORT_2 var_238_arg_1 = var_192; [L598] SORT_2 var_238_arg_2 = var_237; [L599] EXPR var_238_arg_0 ? var_238_arg_1 : var_238_arg_2 [L599] SORT_2 var_238 = var_238_arg_0 ? var_238_arg_1 : var_238_arg_2; [L600] var_238 = var_238 & mask_SORT_2 [L601] SORT_2 next_239_arg_1 = var_238; [L602] SORT_3 var_240_arg_0 = var_188; [L603] SORT_2 var_240_arg_1 = state_66; [L604] SORT_4 var_240 = ((SORT_4)var_240_arg_0 << 8) | var_240_arg_1; [L605] SORT_3 var_241_arg_0 = var_188; [L606] SORT_2 var_241_arg_1 = state_46; [L607] SORT_4 var_241 = ((SORT_4)var_241_arg_0 << 8) | var_241_arg_1; [L608] SORT_4 var_242_arg_0 = var_240; [L609] SORT_4 var_242_arg_1 = var_241; [L610] SORT_4 var_242 = var_242_arg_0 - var_242_arg_1; [L611] SORT_4 var_243_arg_0 = var_242; [L612] SORT_2 var_243 = var_243_arg_0 >> 0; [L613] SORT_3 var_244_arg_0 = var_188; [L614] SORT_2 var_244_arg_1 = var_155; [L615] SORT_4 var_244 = ((SORT_4)var_244_arg_0 << 8) | var_244_arg_1; [L616] SORT_4 var_245_arg_0 = var_240; [L617] SORT_4 var_245_arg_1 = var_244; [L618] SORT_4 var_245 = var_245_arg_0 - var_245_arg_1; [L619] SORT_4 var_246_arg_0 = var_245; [L620] SORT_2 var_246 = var_246_arg_0 >> 0; [L621] SORT_3 var_247_arg_0 = var_188; [L622] SORT_2 var_247_arg_1 = state_42; [L623] SORT_4 var_247 = ((SORT_4)var_247_arg_0 << 8) | var_247_arg_1; [L624] SORT_4 var_248_arg_0 = var_240; [L625] SORT_4 var_248_arg_1 = var_247; [L626] SORT_4 var_248 = var_248_arg_0 - var_248_arg_1; [L627] SORT_4 var_249_arg_0 = var_248; [L628] SORT_2 var_249 = var_249_arg_0 >> 0; [L629] SORT_3 var_250_arg_0 = var_188; [L630] SORT_2 var_250_arg_1 = state_40; [L631] SORT_4 var_250 = ((SORT_4)var_250_arg_0 << 8) | var_250_arg_1; [L632] SORT_4 var_251_arg_0 = var_240; [L633] SORT_4 var_251_arg_1 = var_250; [L634] SORT_4 var_251 = var_251_arg_0 - var_251_arg_1; [L635] SORT_4 var_252_arg_0 = var_251; [L636] SORT_2 var_252 = var_252_arg_0 >> 0; [L637] SORT_3 var_253_arg_0 = var_188; [L638] SORT_2 var_253_arg_1 = var_150; [L639] SORT_4 var_253 = ((SORT_4)var_253_arg_0 << 8) | var_253_arg_1; [L640] SORT_4 var_254_arg_0 = var_240; [L641] SORT_4 var_254_arg_1 = var_253; [L642] SORT_4 var_254 = var_254_arg_0 - var_254_arg_1; [L643] SORT_4 var_255_arg_0 = var_254; [L644] SORT_2 var_255 = var_255_arg_0 >> 0; [L645] SORT_3 var_256_arg_0 = var_188; [L646] SORT_2 var_256_arg_1 = var_147; [L647] SORT_4 var_256 = ((SORT_4)var_256_arg_0 << 8) | var_256_arg_1; [L648] SORT_4 var_257_arg_0 = var_240; [L649] SORT_4 var_257_arg_1 = var_256; [L650] SORT_4 var_257 = var_257_arg_0 - var_257_arg_1; [L651] SORT_4 var_258_arg_0 = var_257; [L652] SORT_2 var_258 = var_258_arg_0 >> 0; [L653] SORT_3 var_259_arg_0 = var_188; [L654] SORT_2 var_259_arg_1 = state_34; [L655] SORT_4 var_259 = ((SORT_4)var_259_arg_0 << 8) | var_259_arg_1; [L656] SORT_4 var_260_arg_0 = var_240; [L657] SORT_4 var_260_arg_1 = var_259; [L658] SORT_4 var_260 = var_260_arg_0 - var_260_arg_1; [L659] SORT_4 var_261_arg_0 = var_260; [L660] SORT_2 var_261 = var_261_arg_0 >> 0; [L661] SORT_4 var_262_arg_0 = var_240; [L662] SORT_4 var_262_arg_1 = var_241; [L663] SORT_4 var_262 = var_262_arg_0 + var_262_arg_1; [L664] SORT_4 var_263_arg_0 = var_262; [L665] SORT_2 var_263 = var_263_arg_0 >> 0; [L666] SORT_4 var_264_arg_0 = var_240; [L667] SORT_4 var_264_arg_1 = var_244; [L668] SORT_4 var_264 = var_264_arg_0 + var_264_arg_1; [L669] SORT_4 var_265_arg_0 = var_264; [L670] SORT_2 var_265 = var_265_arg_0 >> 0; [L671] SORT_4 var_266_arg_0 = var_240; [L672] SORT_4 var_266_arg_1 = var_247; [L673] SORT_4 var_266 = var_266_arg_0 + var_266_arg_1; [L674] SORT_4 var_267_arg_0 = var_266; [L675] SORT_2 var_267 = var_267_arg_0 >> 0; [L676] SORT_4 var_268_arg_0 = var_240; [L677] SORT_4 var_268_arg_1 = var_250; [L678] SORT_4 var_268 = var_268_arg_0 + var_268_arg_1; [L679] SORT_4 var_269_arg_0 = var_268; [L680] SORT_2 var_269 = var_269_arg_0 >> 0; [L681] SORT_4 var_270_arg_0 = var_240; [L682] SORT_4 var_270_arg_1 = var_253; [L683] SORT_4 var_270 = var_270_arg_0 + var_270_arg_1; [L684] SORT_4 var_271_arg_0 = var_270; [L685] SORT_2 var_271 = var_271_arg_0 >> 0; [L686] SORT_4 var_272_arg_0 = var_240; [L687] SORT_4 var_272_arg_1 = var_256; [L688] SORT_4 var_272 = var_272_arg_0 + var_272_arg_1; [L689] SORT_4 var_273_arg_0 = var_272; [L690] SORT_2 var_273 = var_273_arg_0 >> 0; [L691] SORT_4 var_274_arg_0 = var_240; [L692] SORT_4 var_274_arg_1 = var_259; [L693] SORT_4 var_274 = var_274_arg_0 + var_274_arg_1; [L694] SORT_4 var_275_arg_0 = var_274; [L695] SORT_2 var_275 = var_275_arg_0 >> 0; [L696] SORT_1 var_276_arg_0 = input_84; [L697] SORT_2 var_276_arg_1 = var_275; [L698] SORT_2 var_276_arg_2 = state_66; [L699] EXPR var_276_arg_0 ? var_276_arg_1 : var_276_arg_2 [L699] SORT_2 var_276 = var_276_arg_0 ? var_276_arg_1 : var_276_arg_2; [L700] SORT_1 var_277_arg_0 = input_91; [L701] SORT_2 var_277_arg_1 = var_273; [L702] SORT_2 var_277_arg_2 = var_276; [L703] EXPR var_277_arg_0 ? var_277_arg_1 : var_277_arg_2 [L703] SORT_2 var_277 = var_277_arg_0 ? var_277_arg_1 : var_277_arg_2; [L704] SORT_1 var_278_arg_0 = input_99; [L705] SORT_2 var_278_arg_1 = var_271; [L706] SORT_2 var_278_arg_2 = var_277; [L707] EXPR var_278_arg_0 ? var_278_arg_1 : var_278_arg_2 [L707] SORT_2 var_278 = var_278_arg_0 ? var_278_arg_1 : var_278_arg_2; [L708] SORT_1 var_279_arg_0 = input_107; [L709] SORT_2 var_279_arg_1 = var_269; [L710] SORT_2 var_279_arg_2 = var_278; [L711] EXPR var_279_arg_0 ? var_279_arg_1 : var_279_arg_2 [L711] SORT_2 var_279 = var_279_arg_0 ? var_279_arg_1 : var_279_arg_2; [L712] SORT_1 var_280_arg_0 = input_115; [L713] SORT_2 var_280_arg_1 = var_267; [L714] SORT_2 var_280_arg_2 = var_279; [L715] EXPR var_280_arg_0 ? var_280_arg_1 : var_280_arg_2 [L715] SORT_2 var_280 = var_280_arg_0 ? var_280_arg_1 : var_280_arg_2; [L716] SORT_1 var_281_arg_0 = input_122; [L717] SORT_2 var_281_arg_1 = var_265; [L718] SORT_2 var_281_arg_2 = var_280; [L719] EXPR var_281_arg_0 ? var_281_arg_1 : var_281_arg_2 [L719] SORT_2 var_281 = var_281_arg_0 ? var_281_arg_1 : var_281_arg_2; [L720] SORT_1 var_282_arg_0 = input_127; [L721] SORT_2 var_282_arg_1 = var_263; [L722] SORT_2 var_282_arg_2 = var_281; [L723] EXPR var_282_arg_0 ? var_282_arg_1 : var_282_arg_2 [L723] SORT_2 var_282 = var_282_arg_0 ? var_282_arg_1 : var_282_arg_2; [L724] SORT_1 var_283_arg_0 = input_83; [L725] SORT_2 var_283_arg_1 = var_261; [L726] SORT_2 var_283_arg_2 = var_282; [L727] EXPR var_283_arg_0 ? var_283_arg_1 : var_283_arg_2 [L727] SORT_2 var_283 = var_283_arg_0 ? var_283_arg_1 : var_283_arg_2; [L728] SORT_1 var_284_arg_0 = input_90; [L729] SORT_2 var_284_arg_1 = var_258; [L730] SORT_2 var_284_arg_2 = var_283; [L731] EXPR var_284_arg_0 ? var_284_arg_1 : var_284_arg_2 [L731] SORT_2 var_284 = var_284_arg_0 ? var_284_arg_1 : var_284_arg_2; [L732] SORT_1 var_285_arg_0 = input_98; [L733] SORT_2 var_285_arg_1 = var_255; [L734] SORT_2 var_285_arg_2 = var_284; [L735] EXPR var_285_arg_0 ? var_285_arg_1 : var_285_arg_2 [L735] SORT_2 var_285 = var_285_arg_0 ? var_285_arg_1 : var_285_arg_2; [L736] SORT_1 var_286_arg_0 = input_106; [L737] SORT_2 var_286_arg_1 = var_252; [L738] SORT_2 var_286_arg_2 = var_285; [L739] EXPR var_286_arg_0 ? var_286_arg_1 : var_286_arg_2 [L739] SORT_2 var_286 = var_286_arg_0 ? var_286_arg_1 : var_286_arg_2; [L740] SORT_1 var_287_arg_0 = input_114; [L741] SORT_2 var_287_arg_1 = var_249; [L742] SORT_2 var_287_arg_2 = var_286; [L743] EXPR var_287_arg_0 ? var_287_arg_1 : var_287_arg_2 [L743] SORT_2 var_287 = var_287_arg_0 ? var_287_arg_1 : var_287_arg_2; [L744] SORT_1 var_288_arg_0 = input_121; [L745] SORT_2 var_288_arg_1 = var_246; [L746] SORT_2 var_288_arg_2 = var_287; [L747] EXPR var_288_arg_0 ? var_288_arg_1 : var_288_arg_2 [L747] SORT_2 var_288 = var_288_arg_0 ? var_288_arg_1 : var_288_arg_2; [L748] SORT_1 var_289_arg_0 = input_126; [L749] SORT_2 var_289_arg_1 = var_243; [L750] SORT_2 var_289_arg_2 = var_288; [L751] EXPR var_289_arg_0 ? var_289_arg_1 : var_289_arg_2 [L751] SORT_2 var_289 = var_289_arg_0 ? var_289_arg_1 : var_289_arg_2; [L752] var_289 = var_289 & mask_SORT_2 [L753] SORT_2 next_290_arg_1 = var_289; [L754] SORT_3 var_291_arg_0 = var_188; [L755] SORT_2 var_291_arg_1 = state_68; [L756] SORT_4 var_291 = ((SORT_4)var_291_arg_0 << 8) | var_291_arg_1; [L757] var_291 = var_291 & mask_SORT_4 [L758] SORT_4 var_293_arg_0 = var_291; [L759] SORT_4 var_293_arg_1 = var_292; [L760] SORT_4 var_293 = var_293_arg_0 - var_293_arg_1; [L761] SORT_4 var_294_arg_0 = var_293; [L762] SORT_2 var_294 = var_294_arg_0 >> 0; [L763] SORT_4 var_295_arg_0 = var_292; [L764] SORT_4 var_295_arg_1 = var_291; [L765] SORT_4 var_295 = var_295_arg_0 + var_295_arg_1; [L766] SORT_4 var_296_arg_0 = var_295; [L767] SORT_2 var_296 = var_296_arg_0 >> 0; [L768] SORT_1 var_297_arg_0 = input_84; [L769] SORT_2 var_297_arg_1 = var_296; [L770] SORT_2 var_297_arg_2 = state_68; [L771] EXPR var_297_arg_0 ? var_297_arg_1 : var_297_arg_2 [L771] SORT_2 var_297 = var_297_arg_0 ? var_297_arg_1 : var_297_arg_2; [L772] SORT_1 var_298_arg_0 = input_91; [L773] SORT_2 var_298_arg_1 = var_296; [L774] SORT_2 var_298_arg_2 = var_297; [L775] EXPR var_298_arg_0 ? var_298_arg_1 : var_298_arg_2 [L775] SORT_2 var_298 = var_298_arg_0 ? var_298_arg_1 : var_298_arg_2; [L776] SORT_1 var_299_arg_0 = input_99; [L777] SORT_2 var_299_arg_1 = var_296; [L778] SORT_2 var_299_arg_2 = var_298; [L779] EXPR var_299_arg_0 ? var_299_arg_1 : var_299_arg_2 [L779] SORT_2 var_299 = var_299_arg_0 ? var_299_arg_1 : var_299_arg_2; [L780] SORT_1 var_300_arg_0 = input_107; [L781] SORT_2 var_300_arg_1 = var_296; [L782] SORT_2 var_300_arg_2 = var_299; [L783] EXPR var_300_arg_0 ? var_300_arg_1 : var_300_arg_2 [L783] SORT_2 var_300 = var_300_arg_0 ? var_300_arg_1 : var_300_arg_2; [L784] SORT_1 var_301_arg_0 = input_115; [L785] SORT_2 var_301_arg_1 = var_296; [L786] SORT_2 var_301_arg_2 = var_300; [L787] EXPR var_301_arg_0 ? var_301_arg_1 : var_301_arg_2 [L787] SORT_2 var_301 = var_301_arg_0 ? var_301_arg_1 : var_301_arg_2; [L788] SORT_1 var_302_arg_0 = input_122; [L789] SORT_2 var_302_arg_1 = var_296; [L790] SORT_2 var_302_arg_2 = var_301; [L791] EXPR var_302_arg_0 ? var_302_arg_1 : var_302_arg_2 [L791] SORT_2 var_302 = var_302_arg_0 ? var_302_arg_1 : var_302_arg_2; [L792] SORT_1 var_303_arg_0 = input_127; [L793] SORT_2 var_303_arg_1 = var_296; [L794] SORT_2 var_303_arg_2 = var_302; [L795] EXPR var_303_arg_0 ? var_303_arg_1 : var_303_arg_2 [L795] SORT_2 var_303 = var_303_arg_0 ? var_303_arg_1 : var_303_arg_2; [L796] SORT_1 var_304_arg_0 = input_83; [L797] SORT_2 var_304_arg_1 = var_294; [L798] SORT_2 var_304_arg_2 = var_303; [L799] EXPR var_304_arg_0 ? var_304_arg_1 : var_304_arg_2 [L799] SORT_2 var_304 = var_304_arg_0 ? var_304_arg_1 : var_304_arg_2; [L800] SORT_1 var_305_arg_0 = input_90; [L801] SORT_2 var_305_arg_1 = var_294; [L802] SORT_2 var_305_arg_2 = var_304; [L803] EXPR var_305_arg_0 ? var_305_arg_1 : var_305_arg_2 [L803] SORT_2 var_305 = var_305_arg_0 ? var_305_arg_1 : var_305_arg_2; [L804] SORT_1 var_306_arg_0 = input_98; [L805] SORT_2 var_306_arg_1 = var_294; [L806] SORT_2 var_306_arg_2 = var_305; [L807] EXPR var_306_arg_0 ? var_306_arg_1 : var_306_arg_2 [L807] SORT_2 var_306 = var_306_arg_0 ? var_306_arg_1 : var_306_arg_2; [L808] SORT_1 var_307_arg_0 = input_106; [L809] SORT_2 var_307_arg_1 = var_294; [L810] SORT_2 var_307_arg_2 = var_306; [L811] EXPR var_307_arg_0 ? var_307_arg_1 : var_307_arg_2 [L811] SORT_2 var_307 = var_307_arg_0 ? var_307_arg_1 : var_307_arg_2; [L812] SORT_1 var_308_arg_0 = input_114; [L813] SORT_2 var_308_arg_1 = var_294; [L814] SORT_2 var_308_arg_2 = var_307; [L815] EXPR var_308_arg_0 ? var_308_arg_1 : var_308_arg_2 [L815] SORT_2 var_308 = var_308_arg_0 ? var_308_arg_1 : var_308_arg_2; [L816] SORT_1 var_309_arg_0 = input_121; [L817] SORT_2 var_309_arg_1 = var_294; [L818] SORT_2 var_309_arg_2 = var_308; [L819] EXPR var_309_arg_0 ? var_309_arg_1 : var_309_arg_2 [L819] SORT_2 var_309 = var_309_arg_0 ? var_309_arg_1 : var_309_arg_2; [L820] SORT_1 var_310_arg_0 = input_126; [L821] SORT_2 var_310_arg_1 = var_294; [L822] SORT_2 var_310_arg_2 = var_309; [L823] EXPR var_310_arg_0 ? var_310_arg_1 : var_310_arg_2 [L823] SORT_2 var_310 = var_310_arg_0 ? var_310_arg_1 : var_310_arg_2; [L824] var_310 = var_310 & mask_SORT_2 [L825] SORT_2 next_311_arg_1 = var_310; [L826] SORT_3 var_312_arg_0 = var_188; [L827] SORT_2 var_312_arg_1 = state_70; [L828] SORT_4 var_312 = ((SORT_4)var_312_arg_0 << 8) | var_312_arg_1; [L829] SORT_3 var_313_arg_0 = var_188; [L830] SORT_2 var_313_arg_1 = state_60; [L831] SORT_4 var_313 = ((SORT_4)var_313_arg_0 << 8) | var_313_arg_1; [L832] SORT_4 var_314_arg_0 = var_312; [L833] SORT_4 var_314_arg_1 = var_313; [L834] SORT_4 var_314 = var_314_arg_0 - var_314_arg_1; [L835] var_314 = var_314 & mask_SORT_4 [L836] SORT_4 var_315_arg_0 = var_314; [L837] SORT_2 var_315 = var_315_arg_0 >> 0; [L838] SORT_3 var_316_arg_0 = var_188; [L839] SORT_2 var_316_arg_1 = state_58; [L840] SORT_4 var_316 = ((SORT_4)var_316_arg_0 << 8) | var_316_arg_1; [L841] SORT_4 var_317_arg_0 = var_312; [L842] SORT_4 var_317_arg_1 = var_316; [L843] SORT_4 var_317 = var_317_arg_0 - var_317_arg_1; [L844] var_317 = var_317 & mask_SORT_4 [L845] SORT_4 var_318_arg_0 = var_317; [L846] SORT_2 var_318 = var_318_arg_0 >> 0; [L847] SORT_3 var_319_arg_0 = var_188; [L848] SORT_2 var_319_arg_1 = state_56; [L849] SORT_4 var_319 = ((SORT_4)var_319_arg_0 << 8) | var_319_arg_1; [L850] SORT_4 var_320_arg_0 = var_312; [L851] SORT_4 var_320_arg_1 = var_319; [L852] SORT_4 var_320 = var_320_arg_0 - var_320_arg_1; [L853] var_320 = var_320 & mask_SORT_4 [L854] SORT_4 var_321_arg_0 = var_320; [L855] SORT_2 var_321 = var_321_arg_0 >> 0; [L856] SORT_3 var_322_arg_0 = var_188; [L857] SORT_2 var_322_arg_1 = state_54; [L858] SORT_4 var_322 = ((SORT_4)var_322_arg_0 << 8) | var_322_arg_1; [L859] SORT_4 var_323_arg_0 = var_312; [L860] SORT_4 var_323_arg_1 = var_322; [L861] SORT_4 var_323 = var_323_arg_0 - var_323_arg_1; [L862] var_323 = var_323 & mask_SORT_4 [L863] SORT_4 var_324_arg_0 = var_323; [L864] SORT_2 var_324 = var_324_arg_0 >> 0; [L865] SORT_3 var_325_arg_0 = var_188; [L866] SORT_2 var_325_arg_1 = state_52; [L867] SORT_4 var_325 = ((SORT_4)var_325_arg_0 << 8) | var_325_arg_1; [L868] SORT_4 var_326_arg_0 = var_312; [L869] SORT_4 var_326_arg_1 = var_325; [L870] SORT_4 var_326 = var_326_arg_0 - var_326_arg_1; [L871] var_326 = var_326 & mask_SORT_4 [L872] SORT_4 var_327_arg_0 = var_326; [L873] SORT_2 var_327 = var_327_arg_0 >> 0; [L874] SORT_3 var_328_arg_0 = var_188; [L875] SORT_2 var_328_arg_1 = var_162; [L876] SORT_4 var_328 = ((SORT_4)var_328_arg_0 << 8) | var_328_arg_1; [L877] SORT_4 var_329_arg_0 = var_312; [L878] SORT_4 var_329_arg_1 = var_328; [L879] SORT_4 var_329 = var_329_arg_0 - var_329_arg_1; [L880] var_329 = var_329 & mask_SORT_4 [L881] SORT_4 var_330_arg_0 = var_329; [L882] SORT_2 var_330 = var_330_arg_0 >> 0; [L883] SORT_3 var_331_arg_0 = var_188; [L884] SORT_2 var_331_arg_1 = var_159; [L885] SORT_4 var_331 = ((SORT_4)var_331_arg_0 << 8) | var_331_arg_1; [L886] SORT_4 var_332_arg_0 = var_312; [L887] SORT_4 var_332_arg_1 = var_331; [L888] SORT_4 var_332 = var_332_arg_0 - var_332_arg_1; [L889] var_332 = var_332 & mask_SORT_4 [L890] SORT_4 var_333_arg_0 = var_332; [L891] SORT_2 var_333 = var_333_arg_0 >> 0; [L892] SORT_4 var_334_arg_0 = var_312; [L893] SORT_4 var_334_arg_1 = var_313; [L894] SORT_4 var_334 = var_334_arg_0 + var_334_arg_1; [L895] SORT_4 var_335_arg_0 = var_334; [L896] SORT_2 var_335 = var_335_arg_0 >> 0; [L897] SORT_4 var_336_arg_0 = var_312; [L898] SORT_4 var_336_arg_1 = var_316; [L899] SORT_4 var_336 = var_336_arg_0 + var_336_arg_1; [L900] SORT_4 var_337_arg_0 = var_336; [L901] SORT_2 var_337 = var_337_arg_0 >> 0; [L902] SORT_4 var_338_arg_0 = var_312; [L903] SORT_4 var_338_arg_1 = var_319; [L904] SORT_4 var_338 = var_338_arg_0 + var_338_arg_1; [L905] SORT_4 var_339_arg_0 = var_338; [L906] SORT_2 var_339 = var_339_arg_0 >> 0; [L907] SORT_4 var_340_arg_0 = var_312; [L908] SORT_4 var_340_arg_1 = var_322; [L909] SORT_4 var_340 = var_340_arg_0 + var_340_arg_1; [L910] SORT_4 var_341_arg_0 = var_340; [L911] SORT_2 var_341 = var_341_arg_0 >> 0; [L912] SORT_4 var_342_arg_0 = var_312; [L913] SORT_4 var_342_arg_1 = var_325; [L914] SORT_4 var_342 = var_342_arg_0 + var_342_arg_1; [L915] SORT_4 var_343_arg_0 = var_342; [L916] SORT_2 var_343 = var_343_arg_0 >> 0; [L917] SORT_4 var_344_arg_0 = var_312; [L918] SORT_4 var_344_arg_1 = var_328; [L919] SORT_4 var_344 = var_344_arg_0 + var_344_arg_1; [L920] SORT_4 var_345_arg_0 = var_344; [L921] SORT_2 var_345 = var_345_arg_0 >> 0; [L922] SORT_4 var_346_arg_0 = var_312; [L923] SORT_4 var_346_arg_1 = var_331; [L924] SORT_4 var_346 = var_346_arg_0 + var_346_arg_1; [L925] SORT_4 var_347_arg_0 = var_346; [L926] SORT_2 var_347 = var_347_arg_0 >> 0; [L927] SORT_1 var_348_arg_0 = input_84; [L928] SORT_2 var_348_arg_1 = var_347; [L929] SORT_2 var_348_arg_2 = state_70; [L930] EXPR var_348_arg_0 ? var_348_arg_1 : var_348_arg_2 [L930] SORT_2 var_348 = var_348_arg_0 ? var_348_arg_1 : var_348_arg_2; [L931] SORT_1 var_349_arg_0 = input_91; [L932] SORT_2 var_349_arg_1 = var_345; [L933] SORT_2 var_349_arg_2 = var_348; [L934] EXPR var_349_arg_0 ? var_349_arg_1 : var_349_arg_2 [L934] SORT_2 var_349 = var_349_arg_0 ? var_349_arg_1 : var_349_arg_2; [L935] SORT_1 var_350_arg_0 = input_99; [L936] SORT_2 var_350_arg_1 = var_343; [L937] SORT_2 var_350_arg_2 = var_349; [L938] EXPR var_350_arg_0 ? var_350_arg_1 : var_350_arg_2 [L938] SORT_2 var_350 = var_350_arg_0 ? var_350_arg_1 : var_350_arg_2; [L939] SORT_1 var_351_arg_0 = input_107; [L940] SORT_2 var_351_arg_1 = var_341; [L941] SORT_2 var_351_arg_2 = var_350; [L942] EXPR var_351_arg_0 ? var_351_arg_1 : var_351_arg_2 [L942] SORT_2 var_351 = var_351_arg_0 ? var_351_arg_1 : var_351_arg_2; [L943] SORT_1 var_352_arg_0 = input_115; [L944] SORT_2 var_352_arg_1 = var_339; [L945] SORT_2 var_352_arg_2 = var_351; [L946] EXPR var_352_arg_0 ? var_352_arg_1 : var_352_arg_2 [L946] SORT_2 var_352 = var_352_arg_0 ? var_352_arg_1 : var_352_arg_2; [L947] SORT_1 var_353_arg_0 = input_122; [L948] SORT_2 var_353_arg_1 = var_337; [L949] SORT_2 var_353_arg_2 = var_352; [L950] EXPR var_353_arg_0 ? var_353_arg_1 : var_353_arg_2 [L950] SORT_2 var_353 = var_353_arg_0 ? var_353_arg_1 : var_353_arg_2; [L951] SORT_1 var_354_arg_0 = input_127; [L952] SORT_2 var_354_arg_1 = var_335; [L953] SORT_2 var_354_arg_2 = var_353; [L954] EXPR var_354_arg_0 ? var_354_arg_1 : var_354_arg_2 [L954] SORT_2 var_354 = var_354_arg_0 ? var_354_arg_1 : var_354_arg_2; [L955] SORT_1 var_355_arg_0 = input_83; [L956] SORT_2 var_355_arg_1 = var_333; [L957] SORT_2 var_355_arg_2 = var_354; [L958] EXPR var_355_arg_0 ? var_355_arg_1 : var_355_arg_2 [L958] SORT_2 var_355 = var_355_arg_0 ? var_355_arg_1 : var_355_arg_2; [L959] SORT_1 var_356_arg_0 = input_90; [L960] SORT_2 var_356_arg_1 = var_330; [L961] SORT_2 var_356_arg_2 = var_355; [L962] EXPR var_356_arg_0 ? var_356_arg_1 : var_356_arg_2 [L962] SORT_2 var_356 = var_356_arg_0 ? var_356_arg_1 : var_356_arg_2; [L963] SORT_1 var_357_arg_0 = input_98; [L964] SORT_2 var_357_arg_1 = var_327; [L965] SORT_2 var_357_arg_2 = var_356; [L966] EXPR var_357_arg_0 ? var_357_arg_1 : var_357_arg_2 [L966] SORT_2 var_357 = var_357_arg_0 ? var_357_arg_1 : var_357_arg_2; [L967] SORT_1 var_358_arg_0 = input_106; [L968] SORT_2 var_358_arg_1 = var_324; [L969] SORT_2 var_358_arg_2 = var_357; [L970] EXPR var_358_arg_0 ? var_358_arg_1 : var_358_arg_2 [L970] SORT_2 var_358 = var_358_arg_0 ? var_358_arg_1 : var_358_arg_2; [L971] SORT_1 var_359_arg_0 = input_114; [L972] SORT_2 var_359_arg_1 = var_321; [L973] SORT_2 var_359_arg_2 = var_358; [L974] EXPR var_359_arg_0 ? var_359_arg_1 : var_359_arg_2 [L974] SORT_2 var_359 = var_359_arg_0 ? var_359_arg_1 : var_359_arg_2; [L975] SORT_1 var_360_arg_0 = input_121; [L976] SORT_2 var_360_arg_1 = var_318; [L977] SORT_2 var_360_arg_2 = var_359; [L978] EXPR var_360_arg_0 ? var_360_arg_1 : var_360_arg_2 [L978] SORT_2 var_360 = var_360_arg_0 ? var_360_arg_1 : var_360_arg_2; [L979] SORT_1 var_361_arg_0 = input_126; [L980] SORT_2 var_361_arg_1 = var_315; [L981] SORT_2 var_361_arg_2 = var_360; [L982] EXPR var_361_arg_0 ? var_361_arg_1 : var_361_arg_2 [L982] SORT_2 var_361 = var_361_arg_0 ? var_361_arg_1 : var_361_arg_2; [L983] var_361 = var_361 & mask_SORT_2 [L984] SORT_2 next_362_arg_1 = var_361; [L985] SORT_2 next_363_arg_1 = state_72; [L986] SORT_1 var_365_arg_0 = ~state_75; [L987] var_365_arg_0 = var_365_arg_0 & mask_SORT_1 [L988] SORT_1 var_365_arg_1 = ~input_364; [L989] var_365_arg_1 = var_365_arg_1 & mask_SORT_1 [L990] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L991] SORT_1 next_366_arg_1 = ~var_365; [L992] next_366_arg_1 = next_366_arg_1 & mask_SORT_1 [L993] SORT_1 var_367_arg_0 = state_77; [L994] SORT_1 var_367_arg_1 = input_364; [L995] SORT_1 var_367 = var_367_arg_0 | var_367_arg_1; [L996] SORT_1 next_368_arg_1 = var_367; [L997] SORT_2 var_369_arg_0 = var_179; [L998] SORT_2 var_369_arg_1 = state_6; [L999] SORT_1 var_369 = var_369_arg_0 == var_369_arg_1; [L1000] SORT_2 var_370_arg_0 = var_179; [L1001] SORT_2 var_370_arg_1 = var_92; [L1002] SORT_1 var_370 = var_370_arg_0 == var_370_arg_1; [L1003] SORT_1 var_371_arg_0 = var_369; [L1004] SORT_1 var_371_arg_1 = var_370; [L1005] SORT_1 var_371 = var_371_arg_0 & var_371_arg_1; [L1006] SORT_2 var_372_arg_0 = var_179; [L1007] SORT_2 var_372_arg_1 = var_100; [L1008] SORT_1 var_372 = var_372_arg_0 == var_372_arg_1; [L1009] SORT_1 var_373_arg_0 = var_371; [L1010] SORT_1 var_373_arg_1 = var_372; [L1011] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L1012] SORT_2 var_374_arg_0 = var_179; [L1013] SORT_2 var_374_arg_1 = var_108; [L1014] SORT_1 var_374 = var_374_arg_0 == var_374_arg_1; [L1015] SORT_1 var_375_arg_0 = var_373; [L1016] SORT_1 var_375_arg_1 = var_374; [L1017] SORT_1 var_375 = var_375_arg_0 & var_375_arg_1; [L1018] SORT_2 var_376_arg_0 = var_179; [L1019] SORT_2 var_376_arg_1 = var_116; [L1020] SORT_1 var_376 = var_376_arg_0 == var_376_arg_1; [L1021] SORT_1 var_377_arg_0 = var_375; [L1022] SORT_1 var_377_arg_1 = var_376; [L1023] SORT_1 var_377 = var_377_arg_0 & var_377_arg_1; [L1024] SORT_2 var_378_arg_0 = var_179; [L1025] SORT_2 var_378_arg_1 = state_16; [L1026] SORT_1 var_378 = var_378_arg_0 == var_378_arg_1; [L1027] SORT_1 var_379_arg_0 = var_377; [L1028] SORT_1 var_379_arg_1 = var_378; [L1029] SORT_1 var_379 = var_379_arg_0 & var_379_arg_1; [L1030] SORT_2 var_380_arg_0 = var_179; [L1031] SORT_2 var_380_arg_1 = var_128; [L1032] SORT_1 var_380 = var_380_arg_0 == var_380_arg_1; [L1033] SORT_1 var_381_arg_0 = var_379; [L1034] SORT_1 var_381_arg_1 = var_380; [L1035] SORT_1 var_381 = var_381_arg_0 & var_381_arg_1; [L1036] SORT_1 var_382_arg_0 = ~state_75; [L1037] var_382_arg_0 = var_382_arg_0 & mask_SORT_1 [L1038] SORT_1 var_382_arg_1 = var_381; [L1039] SORT_1 var_382 = var_382_arg_0 & var_382_arg_1; [L1040] SORT_1 var_383_arg_0 = ~input_364; [L1041] var_383_arg_0 = var_383_arg_0 & mask_SORT_1 [L1042] SORT_1 var_383_arg_1 = var_382; [L1043] SORT_1 var_383 = var_383_arg_0 | var_383_arg_1; [L1044] SORT_2 var_384_arg_0 = state_6; [L1045] SORT_2 var_384_arg_1 = state_62; [L1046] SORT_1 var_384 = var_384_arg_0 == var_384_arg_1; [L1047] SORT_4 var_386_arg_0 = var_385; [L1048] SORT_4 var_386_arg_1 = var_291; [L1049] SORT_1 var_386 = var_386_arg_0 <= var_386_arg_1; [L1050] SORT_1 var_387_arg_0 = var_384; [L1051] SORT_1 var_387_arg_1 = ~var_386; [L1052] var_387_arg_1 = var_387_arg_1 & mask_SORT_1 [L1053] SORT_1 var_387 = var_387_arg_0 & var_387_arg_1; [L1054] SORT_2 var_388_arg_0 = var_179; [L1055] SORT_2 var_388_arg_1 = var_133; [L1056] SORT_1 var_388 = var_388_arg_0 == var_388_arg_1; [L1057] SORT_2 var_389_arg_0 = var_179; [L1058] SORT_2 var_389_arg_1 = state_66; [L1059] SORT_1 var_389 = var_389_arg_0 == var_389_arg_1; [L1060] SORT_1 var_390_arg_0 = var_388; [L1061] SORT_1 var_390_arg_1 = var_389; [L1062] SORT_1 var_390 = var_390_arg_0 | var_390_arg_1; [L1063] SORT_1 var_391_arg_0 = var_387; [L1064] SORT_1 var_391_arg_1 = var_390; [L1065] SORT_1 var_391 = var_391_arg_0 & var_391_arg_1; [L1066] SORT_2 var_392_arg_0 = var_179; [L1067] SORT_2 var_392_arg_1 = state_34; [L1068] SORT_1 var_392 = var_392_arg_0 == var_392_arg_1; [L1069] SORT_2 var_393_arg_0 = var_179; [L1070] SORT_2 var_393_arg_1 = state_64; [L1071] SORT_1 var_393 = var_393_arg_0 == var_393_arg_1; [L1072] SORT_1 var_394_arg_0 = var_392; [L1073] SORT_1 var_394_arg_1 = var_393; [L1074] SORT_1 var_394 = var_394_arg_0 | var_394_arg_1; [L1075] SORT_1 var_395_arg_0 = var_391; [L1076] SORT_1 var_395_arg_1 = var_394; [L1077] SORT_1 var_395 = var_395_arg_0 & var_395_arg_1; [L1078] SORT_2 var_396_arg_0 = var_179; [L1079] SORT_2 var_396_arg_1 = var_159; [L1080] SORT_1 var_396 = var_396_arg_0 == var_396_arg_1; [L1081] SORT_4 var_398_arg_0 = var_291; [L1082] SORT_4 var_398_arg_1 = var_397; [L1083] SORT_1 var_398 = var_398_arg_0 <= var_398_arg_1; [L1084] SORT_1 var_399_arg_0 = var_396; [L1085] SORT_1 var_399_arg_1 = ~var_398; [L1086] var_399_arg_1 = var_399_arg_1 & mask_SORT_1 [L1087] SORT_1 var_399 = var_399_arg_0 | var_399_arg_1; [L1088] SORT_1 var_400_arg_0 = var_395; [L1089] SORT_1 var_400_arg_1 = var_399; [L1090] SORT_1 var_400 = var_400_arg_0 & var_400_arg_1; [L1091] SORT_1 var_401_arg_0 = ~state_75; [L1092] var_401_arg_0 = var_401_arg_0 & mask_SORT_1 [L1093] SORT_1 var_401_arg_1 = var_400; [L1094] SORT_1 var_401 = var_401_arg_0 & var_401_arg_1; [L1095] SORT_1 var_402_arg_0 = ~input_84; [L1096] var_402_arg_0 = var_402_arg_0 & mask_SORT_1 [L1097] SORT_1 var_402_arg_1 = var_401; [L1098] SORT_1 var_402 = var_402_arg_0 | var_402_arg_1; [L1099] SORT_1 var_403_arg_0 = var_383; [L1100] SORT_1 var_403_arg_1 = var_402; [L1101] SORT_1 var_403 = var_403_arg_0 & var_403_arg_1; [L1102] SORT_2 var_404_arg_0 = var_92; [L1103] SORT_2 var_404_arg_1 = state_62; [L1104] SORT_1 var_404 = var_404_arg_0 == var_404_arg_1; [L1105] SORT_1 var_405_arg_0 = ~var_386; [L1106] var_405_arg_0 = var_405_arg_0 & mask_SORT_1 [L1107] SORT_1 var_405_arg_1 = var_404; [L1108] SORT_1 var_405 = var_405_arg_0 & var_405_arg_1; [L1109] SORT_2 var_406_arg_0 = var_179; [L1110] SORT_2 var_406_arg_1 = state_22; [L1111] SORT_1 var_406 = var_406_arg_0 == var_406_arg_1; [L1112] SORT_1 var_407_arg_0 = var_389; [L1113] SORT_1 var_407_arg_1 = var_406; [L1114] SORT_1 var_407 = var_407_arg_0 | var_407_arg_1; [L1115] SORT_1 var_408_arg_0 = var_405; [L1116] SORT_1 var_408_arg_1 = var_407; [L1117] SORT_1 var_408 = var_408_arg_0 & var_408_arg_1; [L1118] SORT_2 var_409_arg_0 = var_179; [L1119] SORT_2 var_409_arg_1 = var_147; [L1120] SORT_1 var_409 = var_409_arg_0 == var_409_arg_1; [L1121] SORT_1 var_410_arg_0 = var_393; [L1122] SORT_1 var_410_arg_1 = var_409; [L1123] SORT_1 var_410 = var_410_arg_0 | var_410_arg_1; [L1124] SORT_1 var_411_arg_0 = var_408; [L1125] SORT_1 var_411_arg_1 = var_410; [L1126] SORT_1 var_411 = var_411_arg_0 & var_411_arg_1; [L1127] SORT_2 var_412_arg_0 = var_179; [L1128] SORT_2 var_412_arg_1 = var_162; [L1129] SORT_1 var_412 = var_412_arg_0 == var_412_arg_1; [L1130] SORT_1 var_413_arg_0 = ~var_398; [L1131] var_413_arg_0 = var_413_arg_0 & mask_SORT_1 [L1132] SORT_1 var_413_arg_1 = var_412; [L1133] SORT_1 var_413 = var_413_arg_0 | var_413_arg_1; [L1134] SORT_1 var_414_arg_0 = var_411; [L1135] SORT_1 var_414_arg_1 = var_413; [L1136] SORT_1 var_414 = var_414_arg_0 & var_414_arg_1; [L1137] SORT_1 var_415_arg_0 = ~state_75; [L1138] var_415_arg_0 = var_415_arg_0 & mask_SORT_1 [L1139] SORT_1 var_415_arg_1 = var_414; [L1140] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1141] SORT_1 var_416_arg_0 = ~input_91; [L1142] var_416_arg_0 = var_416_arg_0 & mask_SORT_1 [L1143] SORT_1 var_416_arg_1 = var_415; [L1144] SORT_1 var_416 = var_416_arg_0 | var_416_arg_1; [L1145] SORT_1 var_417_arg_0 = var_403; [L1146] SORT_1 var_417_arg_1 = var_416; [L1147] SORT_1 var_417 = var_417_arg_0 & var_417_arg_1; [L1148] SORT_2 var_418_arg_0 = var_100; [L1149] SORT_2 var_418_arg_1 = state_62; [L1150] SORT_1 var_418 = var_418_arg_0 == var_418_arg_1; [L1151] SORT_1 var_419_arg_0 = ~var_386; [L1152] var_419_arg_0 = var_419_arg_0 & mask_SORT_1 [L1153] SORT_1 var_419_arg_1 = var_418; [L1154] SORT_1 var_419 = var_419_arg_0 & var_419_arg_1; [L1155] SORT_2 var_420_arg_0 = var_179; [L1156] SORT_2 var_420_arg_1 = state_24; [L1157] SORT_1 var_420 = var_420_arg_0 == var_420_arg_1; [L1158] SORT_1 var_421_arg_0 = var_389; [L1159] SORT_1 var_421_arg_1 = var_420; [L1160] SORT_1 var_421 = var_421_arg_0 | var_421_arg_1; [L1161] SORT_1 var_422_arg_0 = var_419; [L1162] SORT_1 var_422_arg_1 = var_421; [L1163] SORT_1 var_422 = var_422_arg_0 & var_422_arg_1; [L1164] SORT_2 var_423_arg_0 = var_179; [L1165] SORT_2 var_423_arg_1 = var_150; [L1166] SORT_1 var_423 = var_423_arg_0 == var_423_arg_1; [L1167] SORT_1 var_424_arg_0 = var_393; [L1168] SORT_1 var_424_arg_1 = var_423; [L1169] SORT_1 var_424 = var_424_arg_0 | var_424_arg_1; [L1170] SORT_1 var_425_arg_0 = var_422; [L1171] SORT_1 var_425_arg_1 = var_424; [L1172] SORT_1 var_425 = var_425_arg_0 & var_425_arg_1; [L1173] SORT_2 var_426_arg_0 = var_179; [L1174] SORT_2 var_426_arg_1 = state_52; [L1175] SORT_1 var_426 = var_426_arg_0 == var_426_arg_1; [L1176] SORT_1 var_427_arg_0 = ~var_398; [L1177] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L1178] SORT_1 var_427_arg_1 = var_426; [L1179] SORT_1 var_427 = var_427_arg_0 | var_427_arg_1; [L1180] SORT_1 var_428_arg_0 = var_425; [L1181] SORT_1 var_428_arg_1 = var_427; [L1182] SORT_1 var_428 = var_428_arg_0 & var_428_arg_1; [L1183] SORT_1 var_429_arg_0 = ~state_75; [L1184] var_429_arg_0 = var_429_arg_0 & mask_SORT_1 [L1185] SORT_1 var_429_arg_1 = var_428; [L1186] SORT_1 var_429 = var_429_arg_0 & var_429_arg_1; [L1187] SORT_1 var_430_arg_0 = ~input_99; [L1188] var_430_arg_0 = var_430_arg_0 & mask_SORT_1 [L1189] SORT_1 var_430_arg_1 = var_429; [L1190] SORT_1 var_430 = var_430_arg_0 | var_430_arg_1; [L1191] SORT_1 var_431_arg_0 = var_417; [L1192] SORT_1 var_431_arg_1 = var_430; [L1193] SORT_1 var_431 = var_431_arg_0 & var_431_arg_1; [L1194] SORT_2 var_432_arg_0 = var_108; [L1195] SORT_2 var_432_arg_1 = state_62; [L1196] SORT_1 var_432 = var_432_arg_0 == var_432_arg_1; [L1197] SORT_1 var_433_arg_0 = ~var_386; [L1198] var_433_arg_0 = var_433_arg_0 & mask_SORT_1 [L1199] SORT_1 var_433_arg_1 = var_432; [L1200] SORT_1 var_433 = var_433_arg_0 & var_433_arg_1; [L1201] SORT_2 var_434_arg_0 = var_179; [L1202] SORT_2 var_434_arg_1 = var_138; [L1203] SORT_1 var_434 = var_434_arg_0 == var_434_arg_1; [L1204] SORT_1 var_435_arg_0 = var_389; [L1205] SORT_1 var_435_arg_1 = var_434; [L1206] SORT_1 var_435 = var_435_arg_0 | var_435_arg_1; [L1207] SORT_1 var_436_arg_0 = var_433; [L1208] SORT_1 var_436_arg_1 = var_435; [L1209] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1210] SORT_2 var_437_arg_0 = var_179; [L1211] SORT_2 var_437_arg_1 = state_40; [L1212] SORT_1 var_437 = var_437_arg_0 == var_437_arg_1; [L1213] SORT_1 var_438_arg_0 = var_393; [L1214] SORT_1 var_438_arg_1 = var_437; [L1215] SORT_1 var_438 = var_438_arg_0 | var_438_arg_1; [L1216] SORT_1 var_439_arg_0 = var_436; [L1217] SORT_1 var_439_arg_1 = var_438; [L1218] SORT_1 var_439 = var_439_arg_0 & var_439_arg_1; [L1219] SORT_2 var_440_arg_0 = var_179; [L1220] SORT_2 var_440_arg_1 = state_54; [L1221] SORT_1 var_440 = var_440_arg_0 == var_440_arg_1; [L1222] SORT_1 var_441_arg_0 = ~var_398; [L1223] var_441_arg_0 = var_441_arg_0 & mask_SORT_1 [L1224] SORT_1 var_441_arg_1 = var_440; [L1225] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1226] SORT_1 var_442_arg_0 = var_439; [L1227] SORT_1 var_442_arg_1 = var_441; [L1228] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1229] SORT_1 var_443_arg_0 = ~state_75; [L1230] var_443_arg_0 = var_443_arg_0 & mask_SORT_1 [L1231] SORT_1 var_443_arg_1 = var_442; [L1232] SORT_1 var_443 = var_443_arg_0 & var_443_arg_1; [L1233] SORT_1 var_444_arg_0 = ~input_107; [L1234] var_444_arg_0 = var_444_arg_0 & mask_SORT_1 [L1235] SORT_1 var_444_arg_1 = var_443; [L1236] SORT_1 var_444 = var_444_arg_0 | var_444_arg_1; [L1237] SORT_1 var_445_arg_0 = var_431; [L1238] SORT_1 var_445_arg_1 = var_444; [L1239] SORT_1 var_445 = var_445_arg_0 & var_445_arg_1; [L1240] SORT_2 var_446_arg_0 = var_116; [L1241] SORT_2 var_446_arg_1 = state_62; [L1242] SORT_1 var_446 = var_446_arg_0 == var_446_arg_1; [L1243] SORT_1 var_447_arg_0 = ~var_386; [L1244] var_447_arg_0 = var_447_arg_0 & mask_SORT_1 [L1245] SORT_1 var_447_arg_1 = var_446; [L1246] SORT_1 var_447 = var_447_arg_0 & var_447_arg_1; [L1247] SORT_2 var_448_arg_0 = var_179; [L1248] SORT_2 var_448_arg_1 = var_141; [L1249] SORT_1 var_448 = var_448_arg_0 == var_448_arg_1; [L1250] SORT_1 var_449_arg_0 = var_389; [L1251] SORT_1 var_449_arg_1 = var_448; [L1252] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1253] SORT_1 var_450_arg_0 = var_447; [L1254] SORT_1 var_450_arg_1 = var_449; [L1255] SORT_1 var_450 = var_450_arg_0 & var_450_arg_1; [L1256] SORT_2 var_451_arg_0 = var_179; [L1257] SORT_2 var_451_arg_1 = state_42; [L1258] SORT_1 var_451 = var_451_arg_0 == var_451_arg_1; [L1259] SORT_1 var_452_arg_0 = var_393; [L1260] SORT_1 var_452_arg_1 = var_451; [L1261] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1262] SORT_1 var_453_arg_0 = var_450; [L1263] SORT_1 var_453_arg_1 = var_452; [L1264] SORT_1 var_453 = var_453_arg_0 & var_453_arg_1; [L1265] SORT_2 var_454_arg_0 = var_179; [L1266] SORT_2 var_454_arg_1 = state_56; [L1267] SORT_1 var_454 = var_454_arg_0 == var_454_arg_1; [L1268] SORT_1 var_455_arg_0 = ~var_398; [L1269] var_455_arg_0 = var_455_arg_0 & mask_SORT_1 [L1270] SORT_1 var_455_arg_1 = var_454; [L1271] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1272] SORT_1 var_456_arg_0 = var_453; [L1273] SORT_1 var_456_arg_1 = var_455; [L1274] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1275] SORT_1 var_457_arg_0 = ~state_75; [L1276] var_457_arg_0 = var_457_arg_0 & mask_SORT_1 [L1277] SORT_1 var_457_arg_1 = var_456; [L1278] SORT_1 var_457 = var_457_arg_0 & var_457_arg_1; [L1279] SORT_1 var_458_arg_0 = ~input_115; [L1280] var_458_arg_0 = var_458_arg_0 & mask_SORT_1 [L1281] SORT_1 var_458_arg_1 = var_457; [L1282] SORT_1 var_458 = var_458_arg_0 | var_458_arg_1; [L1283] SORT_1 var_459_arg_0 = var_445; [L1284] SORT_1 var_459_arg_1 = var_458; [L1285] SORT_1 var_459 = var_459_arg_0 & var_459_arg_1; [L1286] SORT_2 var_460_arg_0 = state_16; [L1287] SORT_2 var_460_arg_1 = state_62; [L1288] SORT_1 var_460 = var_460_arg_0 == var_460_arg_1; [L1289] SORT_1 var_461_arg_0 = ~var_386; [L1290] var_461_arg_0 = var_461_arg_0 & mask_SORT_1 [L1291] SORT_1 var_461_arg_1 = var_460; [L1292] SORT_1 var_461 = var_461_arg_0 & var_461_arg_1; [L1293] SORT_2 var_462_arg_0 = var_179; [L1294] SORT_2 var_462_arg_1 = state_30; [L1295] SORT_1 var_462 = var_462_arg_0 == var_462_arg_1; [L1296] SORT_1 var_463_arg_0 = var_389; [L1297] SORT_1 var_463_arg_1 = var_462; [L1298] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1299] SORT_1 var_464_arg_0 = var_461; [L1300] SORT_1 var_464_arg_1 = var_463; [L1301] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1302] SORT_2 var_465_arg_0 = var_179; [L1303] SORT_2 var_465_arg_1 = var_155; [L1304] SORT_1 var_465 = var_465_arg_0 == var_465_arg_1; [L1305] SORT_1 var_466_arg_0 = var_393; [L1306] SORT_1 var_466_arg_1 = var_465; [L1307] SORT_1 var_466 = var_466_arg_0 | var_466_arg_1; [L1308] SORT_1 var_467_arg_0 = var_464; [L1309] SORT_1 var_467_arg_1 = var_466; [L1310] SORT_1 var_467 = var_467_arg_0 & var_467_arg_1; [L1311] SORT_2 var_468_arg_0 = var_179; [L1312] SORT_2 var_468_arg_1 = state_58; [L1313] SORT_1 var_468 = var_468_arg_0 == var_468_arg_1; [L1314] SORT_1 var_469_arg_0 = ~var_398; [L1315] var_469_arg_0 = var_469_arg_0 & mask_SORT_1 [L1316] SORT_1 var_469_arg_1 = var_468; [L1317] SORT_1 var_469 = var_469_arg_0 | var_469_arg_1; [L1318] SORT_1 var_470_arg_0 = var_467; [L1319] SORT_1 var_470_arg_1 = var_469; [L1320] SORT_1 var_470 = var_470_arg_0 & var_470_arg_1; [L1321] SORT_1 var_471_arg_0 = ~state_75; [L1322] var_471_arg_0 = var_471_arg_0 & mask_SORT_1 [L1323] SORT_1 var_471_arg_1 = var_470; [L1324] SORT_1 var_471 = var_471_arg_0 & var_471_arg_1; [L1325] SORT_1 var_472_arg_0 = ~input_122; [L1326] var_472_arg_0 = var_472_arg_0 & mask_SORT_1 [L1327] SORT_1 var_472_arg_1 = var_471; [L1328] SORT_1 var_472 = var_472_arg_0 | var_472_arg_1; [L1329] SORT_1 var_473_arg_0 = var_459; [L1330] SORT_1 var_473_arg_1 = var_472; [L1331] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1332] SORT_2 var_474_arg_0 = var_128; [L1333] SORT_2 var_474_arg_1 = state_62; [L1334] SORT_1 var_474 = var_474_arg_0 == var_474_arg_1; [L1335] SORT_1 var_475_arg_0 = ~var_386; [L1336] var_475_arg_0 = var_475_arg_0 & mask_SORT_1 [L1337] SORT_1 var_475_arg_1 = var_474; [L1338] SORT_1 var_475 = var_475_arg_0 & var_475_arg_1; [L1339] SORT_2 var_476_arg_0 = var_179; [L1340] SORT_2 var_476_arg_1 = state_32; [L1341] SORT_1 var_476 = var_476_arg_0 == var_476_arg_1; [L1342] SORT_1 var_477_arg_0 = var_389; [L1343] SORT_1 var_477_arg_1 = var_476; [L1344] SORT_1 var_477 = var_477_arg_0 | var_477_arg_1; [L1345] SORT_1 var_478_arg_0 = var_475; [L1346] SORT_1 var_478_arg_1 = var_477; [L1347] SORT_1 var_478 = var_478_arg_0 & var_478_arg_1; [L1348] SORT_2 var_479_arg_0 = var_179; [L1349] SORT_2 var_479_arg_1 = state_46; [L1350] SORT_1 var_479 = var_479_arg_0 == var_479_arg_1; [L1351] SORT_1 var_480_arg_0 = var_393; [L1352] SORT_1 var_480_arg_1 = var_479; [L1353] SORT_1 var_480 = var_480_arg_0 | var_480_arg_1; [L1354] SORT_1 var_481_arg_0 = var_478; [L1355] SORT_1 var_481_arg_1 = var_480; [L1356] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1357] SORT_2 var_482_arg_0 = var_179; [L1358] SORT_2 var_482_arg_1 = state_60; [L1359] SORT_1 var_482 = var_482_arg_0 == var_482_arg_1; [L1360] SORT_1 var_483_arg_0 = ~var_398; [L1361] var_483_arg_0 = var_483_arg_0 & mask_SORT_1 [L1362] SORT_1 var_483_arg_1 = var_482; [L1363] SORT_1 var_483 = var_483_arg_0 | var_483_arg_1; [L1364] SORT_1 var_484_arg_0 = var_481; [L1365] SORT_1 var_484_arg_1 = var_483; [L1366] SORT_1 var_484 = var_484_arg_0 & var_484_arg_1; [L1367] SORT_1 var_485_arg_0 = ~state_75; [L1368] var_485_arg_0 = var_485_arg_0 & mask_SORT_1 [L1369] SORT_1 var_485_arg_1 = var_484; [L1370] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1371] SORT_1 var_486_arg_0 = ~input_127; [L1372] var_486_arg_0 = var_486_arg_0 & mask_SORT_1 [L1373] SORT_1 var_486_arg_1 = var_485; [L1374] SORT_1 var_486 = var_486_arg_0 | var_486_arg_1; [L1375] SORT_1 var_487_arg_0 = var_473; [L1376] SORT_1 var_487_arg_1 = var_486; [L1377] SORT_1 var_487 = var_487_arg_0 & var_487_arg_1; [L1378] SORT_2 var_488_arg_0 = var_85; [L1379] SORT_2 var_488_arg_1 = state_6; [L1380] SORT_1 var_488 = var_488_arg_0 == var_488_arg_1; [L1381] SORT_4 var_490_arg_0 = var_291; [L1382] SORT_4 var_490_arg_1 = var_489; [L1383] SORT_1 var_490 = var_490_arg_0 <= var_490_arg_1; [L1384] SORT_4 var_491_arg_0 = var_397; [L1385] SORT_4 var_491_arg_1 = var_332; [L1386] SORT_1 var_491 = var_491_arg_0 == var_491_arg_1; [L1387] SORT_1 var_492_arg_0 = ~var_490; [L1388] var_492_arg_0 = var_492_arg_0 & mask_SORT_1 [L1389] SORT_1 var_492_arg_1 = var_491; [L1390] SORT_1 var_492 = var_492_arg_0 | var_492_arg_1; [L1391] SORT_1 var_493_arg_0 = var_488; [L1392] SORT_1 var_493_arg_1 = var_492; [L1393] SORT_1 var_493 = var_493_arg_0 & var_493_arg_1; [L1394] SORT_1 var_494_arg_0 = ~state_75; [L1395] var_494_arg_0 = var_494_arg_0 & mask_SORT_1 [L1396] SORT_1 var_494_arg_1 = var_493; [L1397] SORT_1 var_494 = var_494_arg_0 & var_494_arg_1; [L1398] SORT_1 var_495_arg_0 = ~input_83; [L1399] var_495_arg_0 = var_495_arg_0 & mask_SORT_1 [L1400] SORT_1 var_495_arg_1 = var_494; [L1401] SORT_1 var_495 = var_495_arg_0 | var_495_arg_1; [L1402] SORT_1 var_496_arg_0 = var_487; [L1403] SORT_1 var_496_arg_1 = var_495; [L1404] SORT_1 var_496 = var_496_arg_0 & var_496_arg_1; [L1405] SORT_2 var_497_arg_0 = var_85; [L1406] SORT_2 var_497_arg_1 = var_92; [L1407] SORT_1 var_497 = var_497_arg_0 == var_497_arg_1; [L1408] SORT_4 var_498_arg_0 = var_397; [L1409] SORT_4 var_498_arg_1 = var_329; [L1410] SORT_1 var_498 = var_498_arg_0 == var_498_arg_1; [L1411] SORT_1 var_499_arg_0 = ~var_490; [L1412] var_499_arg_0 = var_499_arg_0 & mask_SORT_1 [L1413] SORT_1 var_499_arg_1 = var_498; [L1414] SORT_1 var_499 = var_499_arg_0 | var_499_arg_1; [L1415] SORT_1 var_500_arg_0 = var_497; [L1416] SORT_1 var_500_arg_1 = var_499; [L1417] SORT_1 var_500 = var_500_arg_0 & var_500_arg_1; [L1418] SORT_1 var_501_arg_0 = ~state_75; [L1419] var_501_arg_0 = var_501_arg_0 & mask_SORT_1 [L1420] SORT_1 var_501_arg_1 = var_500; [L1421] SORT_1 var_501 = var_501_arg_0 & var_501_arg_1; [L1422] SORT_1 var_502_arg_0 = ~input_90; [L1423] var_502_arg_0 = var_502_arg_0 & mask_SORT_1 [L1424] SORT_1 var_502_arg_1 = var_501; [L1425] SORT_1 var_502 = var_502_arg_0 | var_502_arg_1; [L1426] SORT_1 var_503_arg_0 = var_496; [L1427] SORT_1 var_503_arg_1 = var_502; [L1428] SORT_1 var_503 = var_503_arg_0 & var_503_arg_1; [L1429] SORT_2 var_504_arg_0 = var_85; [L1430] SORT_2 var_504_arg_1 = var_100; [L1431] SORT_1 var_504 = var_504_arg_0 == var_504_arg_1; [L1432] SORT_4 var_505_arg_0 = var_397; [L1433] SORT_4 var_505_arg_1 = var_326; [L1434] SORT_1 var_505 = var_505_arg_0 == var_505_arg_1; [L1435] SORT_1 var_506_arg_0 = ~var_490; [L1436] var_506_arg_0 = var_506_arg_0 & mask_SORT_1 [L1437] SORT_1 var_506_arg_1 = var_505; [L1438] SORT_1 var_506 = var_506_arg_0 | var_506_arg_1; [L1439] SORT_1 var_507_arg_0 = var_504; [L1440] SORT_1 var_507_arg_1 = var_506; [L1441] SORT_1 var_507 = var_507_arg_0 & var_507_arg_1; [L1442] SORT_1 var_508_arg_0 = ~state_75; [L1443] var_508_arg_0 = var_508_arg_0 & mask_SORT_1 [L1444] SORT_1 var_508_arg_1 = var_507; [L1445] SORT_1 var_508 = var_508_arg_0 & var_508_arg_1; [L1446] SORT_1 var_509_arg_0 = ~input_98; [L1447] var_509_arg_0 = var_509_arg_0 & mask_SORT_1 [L1448] SORT_1 var_509_arg_1 = var_508; [L1449] SORT_1 var_509 = var_509_arg_0 | var_509_arg_1; [L1450] SORT_1 var_510_arg_0 = var_503; [L1451] SORT_1 var_510_arg_1 = var_509; [L1452] SORT_1 var_510 = var_510_arg_0 & var_510_arg_1; [L1453] SORT_2 var_511_arg_0 = var_85; [L1454] SORT_2 var_511_arg_1 = var_108; [L1455] SORT_1 var_511 = var_511_arg_0 == var_511_arg_1; [L1456] SORT_4 var_512_arg_0 = var_397; [L1457] SORT_4 var_512_arg_1 = var_323; [L1458] SORT_1 var_512 = var_512_arg_0 == var_512_arg_1; [L1459] SORT_1 var_513_arg_0 = ~var_490; [L1460] var_513_arg_0 = var_513_arg_0 & mask_SORT_1 [L1461] SORT_1 var_513_arg_1 = var_512; [L1462] SORT_1 var_513 = var_513_arg_0 | var_513_arg_1; [L1463] SORT_1 var_514_arg_0 = var_511; [L1464] SORT_1 var_514_arg_1 = var_513; [L1465] SORT_1 var_514 = var_514_arg_0 & var_514_arg_1; [L1466] SORT_1 var_515_arg_0 = ~state_75; [L1467] var_515_arg_0 = var_515_arg_0 & mask_SORT_1 [L1468] SORT_1 var_515_arg_1 = var_514; [L1469] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1470] SORT_1 var_516_arg_0 = ~input_106; [L1471] var_516_arg_0 = var_516_arg_0 & mask_SORT_1 [L1472] SORT_1 var_516_arg_1 = var_515; [L1473] SORT_1 var_516 = var_516_arg_0 | var_516_arg_1; [L1474] SORT_1 var_517_arg_0 = var_510; [L1475] SORT_1 var_517_arg_1 = var_516; [L1476] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L1477] SORT_2 var_518_arg_0 = var_85; [L1478] SORT_2 var_518_arg_1 = var_116; [L1479] SORT_1 var_518 = var_518_arg_0 == var_518_arg_1; [L1480] SORT_4 var_519_arg_0 = var_397; [L1481] SORT_4 var_519_arg_1 = var_320; [L1482] SORT_1 var_519 = var_519_arg_0 == var_519_arg_1; [L1483] SORT_1 var_520_arg_0 = ~var_490; [L1484] var_520_arg_0 = var_520_arg_0 & mask_SORT_1 [L1485] SORT_1 var_520_arg_1 = var_519; [L1486] SORT_1 var_520 = var_520_arg_0 | var_520_arg_1; [L1487] SORT_1 var_521_arg_0 = var_518; [L1488] SORT_1 var_521_arg_1 = var_520; [L1489] SORT_1 var_521 = var_521_arg_0 & var_521_arg_1; [L1490] SORT_1 var_522_arg_0 = ~state_75; [L1491] var_522_arg_0 = var_522_arg_0 & mask_SORT_1 [L1492] SORT_1 var_522_arg_1 = var_521; [L1493] SORT_1 var_522 = var_522_arg_0 & var_522_arg_1; [L1494] SORT_1 var_523_arg_0 = ~input_114; [L1495] var_523_arg_0 = var_523_arg_0 & mask_SORT_1 [L1496] SORT_1 var_523_arg_1 = var_522; [L1497] SORT_1 var_523 = var_523_arg_0 | var_523_arg_1; [L1498] SORT_1 var_524_arg_0 = var_517; [L1499] SORT_1 var_524_arg_1 = var_523; [L1500] SORT_1 var_524 = var_524_arg_0 & var_524_arg_1; [L1501] SORT_2 var_525_arg_0 = var_85; [L1502] SORT_2 var_525_arg_1 = state_16; [L1503] SORT_1 var_525 = var_525_arg_0 == var_525_arg_1; [L1504] SORT_4 var_526_arg_0 = var_397; [L1505] SORT_4 var_526_arg_1 = var_317; [L1506] SORT_1 var_526 = var_526_arg_0 == var_526_arg_1; [L1507] SORT_1 var_527_arg_0 = ~var_490; [L1508] var_527_arg_0 = var_527_arg_0 & mask_SORT_1 [L1509] SORT_1 var_527_arg_1 = var_526; [L1510] SORT_1 var_527 = var_527_arg_0 | var_527_arg_1; [L1511] SORT_1 var_528_arg_0 = var_525; [L1512] SORT_1 var_528_arg_1 = var_527; [L1513] SORT_1 var_528 = var_528_arg_0 & var_528_arg_1; [L1514] SORT_1 var_529_arg_0 = ~state_75; [L1515] var_529_arg_0 = var_529_arg_0 & mask_SORT_1 [L1516] SORT_1 var_529_arg_1 = var_528; [L1517] SORT_1 var_529 = var_529_arg_0 & var_529_arg_1; [L1518] SORT_1 var_530_arg_0 = ~input_121; [L1519] var_530_arg_0 = var_530_arg_0 & mask_SORT_1 [L1520] SORT_1 var_530_arg_1 = var_529; [L1521] SORT_1 var_530 = var_530_arg_0 | var_530_arg_1; [L1522] SORT_1 var_531_arg_0 = var_524; [L1523] SORT_1 var_531_arg_1 = var_530; [L1524] SORT_1 var_531 = var_531_arg_0 & var_531_arg_1; [L1525] SORT_2 var_532_arg_0 = var_85; [L1526] SORT_2 var_532_arg_1 = var_128; [L1527] SORT_1 var_532 = var_532_arg_0 == var_532_arg_1; [L1528] SORT_4 var_533_arg_0 = var_397; [L1529] SORT_4 var_533_arg_1 = var_314; [L1530] SORT_1 var_533 = var_533_arg_0 == var_533_arg_1; [L1531] SORT_1 var_534_arg_0 = ~var_490; [L1532] var_534_arg_0 = var_534_arg_0 & mask_SORT_1 [L1533] SORT_1 var_534_arg_1 = var_533; [L1534] SORT_1 var_534 = var_534_arg_0 | var_534_arg_1; [L1535] SORT_1 var_535_arg_0 = var_532; [L1536] SORT_1 var_535_arg_1 = var_534; [L1537] SORT_1 var_535 = var_535_arg_0 & var_535_arg_1; [L1538] SORT_1 var_536_arg_0 = ~state_75; [L1539] var_536_arg_0 = var_536_arg_0 & mask_SORT_1 [L1540] SORT_1 var_536_arg_1 = var_535; [L1541] SORT_1 var_536 = var_536_arg_0 & var_536_arg_1; [L1542] SORT_1 var_537_arg_0 = ~input_126; [L1543] var_537_arg_0 = var_537_arg_0 & mask_SORT_1 [L1544] SORT_1 var_537_arg_1 = var_536; [L1545] SORT_1 var_537 = var_537_arg_0 | var_537_arg_1; [L1546] SORT_1 var_538_arg_0 = var_531; [L1547] SORT_1 var_538_arg_1 = var_537; [L1548] SORT_1 var_538 = var_538_arg_0 & var_538_arg_1; [L1549] SORT_1 var_539_arg_0 = ~state_75; [L1550] var_539_arg_0 = var_539_arg_0 & mask_SORT_1 [L1551] SORT_1 var_539_arg_1 = ~input_178; [L1552] var_539_arg_1 = var_539_arg_1 & mask_SORT_1 [L1553] SORT_1 var_539 = var_539_arg_0 | var_539_arg_1; [L1554] SORT_1 var_540_arg_0 = var_538; [L1555] SORT_1 var_540_arg_1 = var_539; [L1556] SORT_1 var_540 = var_540_arg_0 & var_540_arg_1; [L1557] SORT_1 var_541_arg_0 = ~state_75; [L1558] var_541_arg_0 = var_541_arg_0 & mask_SORT_1 [L1559] SORT_1 var_541_arg_1 = ~input_177; [L1560] var_541_arg_1 = var_541_arg_1 & mask_SORT_1 [L1561] SORT_1 var_541 = var_541_arg_0 | var_541_arg_1; [L1562] SORT_1 var_542_arg_0 = var_540; [L1563] SORT_1 var_542_arg_1 = var_541; [L1564] SORT_1 var_542 = var_542_arg_0 & var_542_arg_1; [L1565] SORT_1 var_543_arg_0 = ~state_75; [L1566] var_543_arg_0 = var_543_arg_0 & mask_SORT_1 [L1567] SORT_1 var_543_arg_1 = ~input_176; [L1568] var_543_arg_1 = var_543_arg_1 & mask_SORT_1 [L1569] SORT_1 var_543 = var_543_arg_0 | var_543_arg_1; [L1570] SORT_1 var_544_arg_0 = var_542; [L1571] SORT_1 var_544_arg_1 = var_543; [L1572] SORT_1 var_544 = var_544_arg_0 & var_544_arg_1; [L1573] SORT_1 var_545_arg_0 = ~state_75; [L1574] var_545_arg_0 = var_545_arg_0 & mask_SORT_1 [L1575] SORT_1 var_545_arg_1 = ~input_175; [L1576] var_545_arg_1 = var_545_arg_1 & mask_SORT_1 [L1577] SORT_1 var_545 = var_545_arg_0 | var_545_arg_1; [L1578] SORT_1 var_546_arg_0 = var_544; [L1579] SORT_1 var_546_arg_1 = var_545; [L1580] SORT_1 var_546 = var_546_arg_0 & var_546_arg_1; [L1581] SORT_1 var_547_arg_0 = ~state_75; [L1582] var_547_arg_0 = var_547_arg_0 & mask_SORT_1 [L1583] SORT_1 var_547_arg_1 = ~input_174; [L1584] var_547_arg_1 = var_547_arg_1 & mask_SORT_1 [L1585] SORT_1 var_547 = var_547_arg_0 | var_547_arg_1; [L1586] SORT_1 var_548_arg_0 = var_546; [L1587] SORT_1 var_548_arg_1 = var_547; [L1588] SORT_1 var_548 = var_548_arg_0 & var_548_arg_1; [L1589] SORT_1 var_549_arg_0 = ~state_75; [L1590] var_549_arg_0 = var_549_arg_0 & mask_SORT_1 [L1591] SORT_1 var_549_arg_1 = ~input_172; [L1592] var_549_arg_1 = var_549_arg_1 & mask_SORT_1 [L1593] SORT_1 var_549 = var_549_arg_0 | var_549_arg_1; [L1594] SORT_1 var_550_arg_0 = var_548; [L1595] SORT_1 var_550_arg_1 = var_549; [L1596] SORT_1 var_550 = var_550_arg_0 & var_550_arg_1; [L1597] SORT_1 var_551_arg_0 = ~state_75; [L1598] var_551_arg_0 = var_551_arg_0 & mask_SORT_1 [L1599] SORT_1 var_551_arg_1 = ~input_170; [L1600] var_551_arg_1 = var_551_arg_1 & mask_SORT_1 [L1601] SORT_1 var_551 = var_551_arg_0 | var_551_arg_1; [L1602] SORT_1 var_552_arg_0 = var_550; [L1603] SORT_1 var_552_arg_1 = var_551; [L1604] SORT_1 var_552 = var_552_arg_0 & var_552_arg_1; [L1605] SORT_1 var_553_arg_0 = input_364; [L1606] SORT_1 var_553_arg_1 = input_84; [L1607] SORT_1 var_553 = var_553_arg_0 | var_553_arg_1; [L1608] SORT_1 var_554_arg_0 = input_91; [L1609] SORT_1 var_554_arg_1 = var_553; [L1610] SORT_1 var_554 = var_554_arg_0 | var_554_arg_1; [L1611] SORT_1 var_555_arg_0 = input_99; [L1612] SORT_1 var_555_arg_1 = var_554; [L1613] SORT_1 var_555 = var_555_arg_0 | var_555_arg_1; [L1614] SORT_1 var_556_arg_0 = input_107; [L1615] SORT_1 var_556_arg_1 = var_555; [L1616] SORT_1 var_556 = var_556_arg_0 | var_556_arg_1; [L1617] SORT_1 var_557_arg_0 = input_115; [L1618] SORT_1 var_557_arg_1 = var_556; [L1619] SORT_1 var_557 = var_557_arg_0 | var_557_arg_1; [L1620] SORT_1 var_558_arg_0 = input_122; [L1621] SORT_1 var_558_arg_1 = var_557; [L1622] SORT_1 var_558 = var_558_arg_0 | var_558_arg_1; [L1623] SORT_1 var_559_arg_0 = input_127; [L1624] SORT_1 var_559_arg_1 = var_558; [L1625] SORT_1 var_559 = var_559_arg_0 | var_559_arg_1; [L1626] SORT_1 var_560_arg_0 = input_83; [L1627] SORT_1 var_560_arg_1 = var_559; [L1628] SORT_1 var_560 = var_560_arg_0 | var_560_arg_1; [L1629] SORT_1 var_561_arg_0 = input_90; [L1630] SORT_1 var_561_arg_1 = var_560; [L1631] SORT_1 var_561 = var_561_arg_0 | var_561_arg_1; [L1632] SORT_1 var_562_arg_0 = input_98; [L1633] SORT_1 var_562_arg_1 = var_561; [L1634] SORT_1 var_562 = var_562_arg_0 | var_562_arg_1; [L1635] SORT_1 var_563_arg_0 = input_106; [L1636] SORT_1 var_563_arg_1 = var_562; [L1637] SORT_1 var_563 = var_563_arg_0 | var_563_arg_1; [L1638] SORT_1 var_564_arg_0 = input_114; [L1639] SORT_1 var_564_arg_1 = var_563; [L1640] SORT_1 var_564 = var_564_arg_0 | var_564_arg_1; [L1641] SORT_1 var_565_arg_0 = input_121; [L1642] SORT_1 var_565_arg_1 = var_564; [L1643] SORT_1 var_565 = var_565_arg_0 | var_565_arg_1; [L1644] SORT_1 var_566_arg_0 = input_126; [L1645] SORT_1 var_566_arg_1 = var_565; [L1646] SORT_1 var_566 = var_566_arg_0 | var_566_arg_1; [L1647] SORT_1 var_567_arg_0 = input_178; [L1648] SORT_1 var_567_arg_1 = var_566; [L1649] SORT_1 var_567 = var_567_arg_0 | var_567_arg_1; [L1650] SORT_1 var_568_arg_0 = input_177; [L1651] SORT_1 var_568_arg_1 = var_567; [L1652] SORT_1 var_568 = var_568_arg_0 | var_568_arg_1; [L1653] SORT_1 var_569_arg_0 = input_176; [L1654] SORT_1 var_569_arg_1 = var_568; [L1655] SORT_1 var_569 = var_569_arg_0 | var_569_arg_1; [L1656] SORT_1 var_570_arg_0 = input_175; [L1657] SORT_1 var_570_arg_1 = var_569; [L1658] SORT_1 var_570 = var_570_arg_0 | var_570_arg_1; [L1659] SORT_1 var_571_arg_0 = input_174; [L1660] SORT_1 var_571_arg_1 = var_570; [L1661] SORT_1 var_571 = var_571_arg_0 | var_571_arg_1; [L1662] SORT_1 var_572_arg_0 = input_172; [L1663] SORT_1 var_572_arg_1 = var_571; [L1664] SORT_1 var_572 = var_572_arg_0 | var_572_arg_1; [L1665] SORT_1 var_573_arg_0 = input_170; [L1666] SORT_1 var_573_arg_1 = var_572; [L1667] SORT_1 var_573 = var_573_arg_0 | var_573_arg_1; [L1668] SORT_1 var_574_arg_0 = var_552; [L1669] SORT_1 var_574_arg_1 = var_573; [L1670] SORT_1 var_574 = var_574_arg_0 & var_574_arg_1; [L1671] SORT_1 var_575_arg_0 = input_364; [L1672] SORT_1 var_575_arg_1 = input_84; [L1673] SORT_1 var_575 = var_575_arg_0 & var_575_arg_1; [L1674] SORT_1 var_576_arg_0 = input_91; [L1675] SORT_1 var_576_arg_1 = var_553; [L1676] SORT_1 var_576 = var_576_arg_0 & var_576_arg_1; [L1677] SORT_1 var_577_arg_0 = var_575; [L1678] SORT_1 var_577_arg_1 = var_576; [L1679] SORT_1 var_577 = var_577_arg_0 | var_577_arg_1; [L1680] SORT_1 var_578_arg_0 = input_99; [L1681] SORT_1 var_578_arg_1 = var_554; [L1682] SORT_1 var_578 = var_578_arg_0 & var_578_arg_1; [L1683] SORT_1 var_579_arg_0 = var_577; [L1684] SORT_1 var_579_arg_1 = var_578; [L1685] SORT_1 var_579 = var_579_arg_0 | var_579_arg_1; [L1686] SORT_1 var_580_arg_0 = input_107; [L1687] SORT_1 var_580_arg_1 = var_555; [L1688] SORT_1 var_580 = var_580_arg_0 & var_580_arg_1; [L1689] SORT_1 var_581_arg_0 = var_579; [L1690] SORT_1 var_581_arg_1 = var_580; [L1691] SORT_1 var_581 = var_581_arg_0 | var_581_arg_1; [L1692] SORT_1 var_582_arg_0 = input_115; [L1693] SORT_1 var_582_arg_1 = var_556; [L1694] SORT_1 var_582 = var_582_arg_0 & var_582_arg_1; [L1695] SORT_1 var_583_arg_0 = var_581; [L1696] SORT_1 var_583_arg_1 = var_582; [L1697] SORT_1 var_583 = var_583_arg_0 | var_583_arg_1; [L1698] SORT_1 var_584_arg_0 = input_122; [L1699] SORT_1 var_584_arg_1 = var_557; [L1700] SORT_1 var_584 = var_584_arg_0 & var_584_arg_1; [L1701] SORT_1 var_585_arg_0 = var_583; [L1702] SORT_1 var_585_arg_1 = var_584; [L1703] SORT_1 var_585 = var_585_arg_0 | var_585_arg_1; [L1704] SORT_1 var_586_arg_0 = input_127; [L1705] SORT_1 var_586_arg_1 = var_558; [L1706] SORT_1 var_586 = var_586_arg_0 & var_586_arg_1; [L1707] SORT_1 var_587_arg_0 = var_585; [L1708] SORT_1 var_587_arg_1 = var_586; [L1709] SORT_1 var_587 = var_587_arg_0 | var_587_arg_1; [L1710] SORT_1 var_588_arg_0 = input_83; [L1711] SORT_1 var_588_arg_1 = var_559; [L1712] SORT_1 var_588 = var_588_arg_0 & var_588_arg_1; [L1713] SORT_1 var_589_arg_0 = var_587; [L1714] SORT_1 var_589_arg_1 = var_588; [L1715] SORT_1 var_589 = var_589_arg_0 | var_589_arg_1; [L1716] SORT_1 var_590_arg_0 = input_90; [L1717] SORT_1 var_590_arg_1 = var_560; [L1718] SORT_1 var_590 = var_590_arg_0 & var_590_arg_1; [L1719] SORT_1 var_591_arg_0 = var_589; [L1720] SORT_1 var_591_arg_1 = var_590; [L1721] SORT_1 var_591 = var_591_arg_0 | var_591_arg_1; [L1722] SORT_1 var_592_arg_0 = input_98; [L1723] SORT_1 var_592_arg_1 = var_561; [L1724] SORT_1 var_592 = var_592_arg_0 & var_592_arg_1; [L1725] SORT_1 var_593_arg_0 = var_591; [L1726] SORT_1 var_593_arg_1 = var_592; [L1727] SORT_1 var_593 = var_593_arg_0 | var_593_arg_1; [L1728] SORT_1 var_594_arg_0 = input_106; [L1729] SORT_1 var_594_arg_1 = var_562; [L1730] SORT_1 var_594 = var_594_arg_0 & var_594_arg_1; [L1731] SORT_1 var_595_arg_0 = var_593; [L1732] SORT_1 var_595_arg_1 = var_594; [L1733] SORT_1 var_595 = var_595_arg_0 | var_595_arg_1; [L1734] SORT_1 var_596_arg_0 = input_114; [L1735] SORT_1 var_596_arg_1 = var_563; [L1736] SORT_1 var_596 = var_596_arg_0 & var_596_arg_1; [L1737] SORT_1 var_597_arg_0 = var_595; [L1738] SORT_1 var_597_arg_1 = var_596; [L1739] SORT_1 var_597 = var_597_arg_0 | var_597_arg_1; [L1740] SORT_1 var_598_arg_0 = input_121; [L1741] SORT_1 var_598_arg_1 = var_564; [L1742] SORT_1 var_598 = var_598_arg_0 & var_598_arg_1; [L1743] SORT_1 var_599_arg_0 = var_597; [L1744] SORT_1 var_599_arg_1 = var_598; [L1745] SORT_1 var_599 = var_599_arg_0 | var_599_arg_1; [L1746] SORT_1 var_600_arg_0 = input_126; [L1747] SORT_1 var_600_arg_1 = var_565; [L1748] SORT_1 var_600 = var_600_arg_0 & var_600_arg_1; [L1749] SORT_1 var_601_arg_0 = var_599; [L1750] SORT_1 var_601_arg_1 = var_600; [L1751] SORT_1 var_601 = var_601_arg_0 | var_601_arg_1; [L1752] SORT_1 var_602_arg_0 = input_178; [L1753] SORT_1 var_602_arg_1 = var_566; [L1754] SORT_1 var_602 = var_602_arg_0 & var_602_arg_1; [L1755] SORT_1 var_603_arg_0 = var_601; [L1756] SORT_1 var_603_arg_1 = var_602; [L1757] SORT_1 var_603 = var_603_arg_0 | var_603_arg_1; [L1758] SORT_1 var_604_arg_0 = input_177; [L1759] SORT_1 var_604_arg_1 = var_567; [L1760] SORT_1 var_604 = var_604_arg_0 & var_604_arg_1; [L1761] SORT_1 var_605_arg_0 = var_603; [L1762] SORT_1 var_605_arg_1 = var_604; [L1763] SORT_1 var_605 = var_605_arg_0 | var_605_arg_1; [L1764] SORT_1 var_606_arg_0 = input_176; [L1765] SORT_1 var_606_arg_1 = var_568; [L1766] SORT_1 var_606 = var_606_arg_0 & var_606_arg_1; [L1767] SORT_1 var_607_arg_0 = var_605; [L1768] SORT_1 var_607_arg_1 = var_606; [L1769] SORT_1 var_607 = var_607_arg_0 | var_607_arg_1; [L1770] SORT_1 var_608_arg_0 = input_175; [L1771] SORT_1 var_608_arg_1 = var_569; [L1772] SORT_1 var_608 = var_608_arg_0 & var_608_arg_1; [L1773] SORT_1 var_609_arg_0 = var_607; [L1774] SORT_1 var_609_arg_1 = var_608; [L1775] SORT_1 var_609 = var_609_arg_0 | var_609_arg_1; [L1776] SORT_1 var_610_arg_0 = input_174; [L1777] SORT_1 var_610_arg_1 = var_570; [L1778] SORT_1 var_610 = var_610_arg_0 & var_610_arg_1; [L1779] SORT_1 var_611_arg_0 = var_609; [L1780] SORT_1 var_611_arg_1 = var_610; [L1781] SORT_1 var_611 = var_611_arg_0 | var_611_arg_1; [L1782] SORT_1 var_612_arg_0 = input_172; [L1783] SORT_1 var_612_arg_1 = var_571; [L1784] SORT_1 var_612 = var_612_arg_0 & var_612_arg_1; [L1785] SORT_1 var_613_arg_0 = var_611; [L1786] SORT_1 var_613_arg_1 = var_612; [L1787] SORT_1 var_613 = var_613_arg_0 | var_613_arg_1; [L1788] SORT_1 var_614_arg_0 = input_170; [L1789] SORT_1 var_614_arg_1 = var_572; [L1790] SORT_1 var_614 = var_614_arg_0 & var_614_arg_1; [L1791] SORT_1 var_615_arg_0 = var_613; [L1792] SORT_1 var_615_arg_1 = var_614; [L1793] SORT_1 var_615 = var_615_arg_0 | var_615_arg_1; [L1794] SORT_1 var_616_arg_0 = var_574; [L1795] SORT_1 var_616_arg_1 = ~var_615; [L1796] var_616_arg_1 = var_616_arg_1 & mask_SORT_1 [L1797] SORT_1 var_616 = var_616_arg_0 & var_616_arg_1; [L1798] SORT_1 var_617_arg_0 = ~state_75; [L1799] var_617_arg_0 = var_617_arg_0 & mask_SORT_1 [L1800] SORT_1 var_617_arg_1 = state_77; [L1801] SORT_1 var_617 = var_617_arg_0 & var_617_arg_1; [L1802] SORT_1 var_618_arg_0 = ~state_75; [L1803] var_618_arg_0 = var_618_arg_0 & mask_SORT_1 [L1804] SORT_1 var_618_arg_1 = state_77; [L1805] SORT_1 var_618 = var_618_arg_0 | var_618_arg_1; [L1806] SORT_1 var_619_arg_0 = ~var_617; [L1807] var_619_arg_0 = var_619_arg_0 & mask_SORT_1 [L1808] SORT_1 var_619_arg_1 = var_618; [L1809] SORT_1 var_619 = var_619_arg_0 & var_619_arg_1; [L1810] SORT_1 var_620_arg_0 = var_616; [L1811] SORT_1 var_620_arg_1 = var_619; [L1812] SORT_1 var_620 = var_620_arg_0 & var_620_arg_1; [L1813] SORT_1 var_621_arg_0 = var_365; [L1814] SORT_1 var_621_arg_1 = var_367; [L1815] SORT_1 var_621 = var_621_arg_0 & var_621_arg_1; [L1816] SORT_1 var_622_arg_0 = var_365; [L1817] SORT_1 var_622_arg_1 = var_367; [L1818] SORT_1 var_622 = var_622_arg_0 | var_622_arg_1; [L1819] SORT_1 var_623_arg_0 = ~var_621; [L1820] var_623_arg_0 = var_623_arg_0 & mask_SORT_1 [L1821] SORT_1 var_623_arg_1 = var_622; [L1822] SORT_1 var_623 = var_623_arg_0 & var_623_arg_1; [L1823] SORT_1 var_624_arg_0 = var_620; [L1824] SORT_1 var_624_arg_1 = var_623; [L1825] SORT_1 var_624 = var_624_arg_0 & var_624_arg_1; [L1826] SORT_1 var_625_arg_0 = var_624; [L1827] SORT_1 var_625_arg_1 = ~state_79; [L1828] var_625_arg_1 = var_625_arg_1 & mask_SORT_1 [L1829] SORT_1 var_625 = var_625_arg_0 & var_625_arg_1; [L1830] SORT_1 next_626_arg_1 = ~var_625; [L1831] next_626_arg_1 = next_626_arg_1 & mask_SORT_1 [L1833] state_6 = next_88_arg_1 [L1834] state_8 = next_96_arg_1 [L1835] state_10 = next_104_arg_1 [L1836] state_12 = next_112_arg_1 [L1837] state_14 = next_120_arg_1 [L1838] state_16 = next_125_arg_1 [L1839] state_18 = next_132_arg_1 [L1840] state_20 = next_135_arg_1 [L1841] state_22 = next_136_arg_1 [L1842] state_24 = next_137_arg_1 [L1843] state_26 = next_140_arg_1 [L1844] state_28 = next_143_arg_1 [L1845] state_30 = next_144_arg_1 [L1846] state_32 = next_145_arg_1 [L1847] state_34 = next_146_arg_1 [L1848] state_36 = next_149_arg_1 [L1849] state_38 = next_152_arg_1 [L1850] state_40 = next_153_arg_1 [L1851] state_42 = next_154_arg_1 [L1852] state_44 = next_157_arg_1 [L1853] state_46 = next_158_arg_1 [L1854] state_48 = next_161_arg_1 [L1855] state_50 = next_164_arg_1 [L1856] state_52 = next_165_arg_1 [L1857] state_54 = next_166_arg_1 [L1858] state_56 = next_167_arg_1 [L1859] state_58 = next_168_arg_1 [L1860] state_60 = next_169_arg_1 [L1861] state_62 = next_187_arg_1 [L1862] state_64 = next_239_arg_1 [L1863] state_66 = next_290_arg_1 [L1864] state_68 = next_311_arg_1 [L1865] state_70 = next_362_arg_1 [L1866] state_72 = next_363_arg_1 [L1867] state_75 = next_366_arg_1 [L1868] state_77 = next_368_arg_1 [L1869] state_79 = next_626_arg_1 VAL [bad_82_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_31_arg_1=0, init_33_arg_1=0, init_35_arg_1=0, init_37_arg_1=0, init_39_arg_1=0, init_41_arg_1=0, init_43_arg_1=0, init_45_arg_1=0, init_47_arg_1=0, init_49_arg_1=0, init_51_arg_1=0, init_53_arg_1=0, init_55_arg_1=0, init_57_arg_1=0, init_59_arg_1=0, init_61_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, init_76_arg_1=0, init_78_arg_1=0, init_7_arg_1=0, init_80_arg_1=0, init_9_arg_1=0, input_106=1, input_107=0, input_114=1, input_115=1, input_121=0, input_122=1, input_126=0, input_127=0, input_170=1, input_172=0, input_174=0, input_175=0, input_176=1, input_177=0, input_178=0, input_364=57, input_83=0, input_84=1, input_90=1, input_91=0, input_98=0, input_99=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, next_104_arg_1=2, next_112_arg_1=3, next_120_arg_1=4, next_125_arg_1=0, next_132_arg_1=3, next_135_arg_1=0, next_136_arg_1=0, next_137_arg_1=0, next_140_arg_1=0, next_143_arg_1=0, next_144_arg_1=0, next_145_arg_1=0, next_146_arg_1=0, next_149_arg_1=0, next_152_arg_1=0, next_153_arg_1=0, next_154_arg_1=0, next_157_arg_1=0, next_158_arg_1=0, next_161_arg_1=0, next_164_arg_1=0, next_165_arg_1=0, next_166_arg_1=0, next_167_arg_1=0, next_168_arg_1=0, next_169_arg_1=0, next_187_arg_1=9, next_239_arg_1=0, next_290_arg_1=0, next_311_arg_1=2, next_362_arg_1=0, next_363_arg_1=0, next_366_arg_1=1, next_368_arg_1=7, next_626_arg_1=0, next_88_arg_1=0, next_96_arg_1=1, state_10=2, state_12=3, state_14=4, state_16=0, state_18=3, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_30=0, state_32=0, state_34=0, state_36=0, state_38=0, state_40=0, state_42=0, state_44=0, state_46=0, state_48=0, state_50=0, state_52=0, state_54=0, state_56=0, state_58=0, state_6=0, state_60=0, state_62=9, state_64=0, state_66=0, state_68=2, state_70=0, state_72=0, state_75=1, state_77=7, state_79=0, state_8=1, var_100=0, var_100_arg_0=2, var_100_arg_1=0, var_101=0, var_101_arg_0=0, var_101_arg_1=255, var_101_arg_2=0, var_102=0, var_102_arg_0=0, var_102_arg_1=0, var_102_arg_2=0, var_103=2, var_103_arg_0=2, var_103_arg_1=0, var_105=3, var_108=255, var_108_arg_0=3, var_108_arg_1=0, var_109=255, var_109_arg_0=0, var_109_arg_1=255, var_109_arg_2=255, var_110=0, var_110_arg_0=1, var_110_arg_1=0, var_110_arg_2=255, var_111=3, var_111_arg_0=3, var_111_arg_1=0, var_113=4, var_116=0, var_116_arg_0=4, var_116_arg_1=0, var_117=255, var_117_arg_0=1, var_117_arg_1=255, var_117_arg_2=0, var_118=0, var_118_arg_0=1, var_118_arg_1=0, var_118_arg_2=255, var_119=4, var_119_arg_0=4, var_119_arg_1=0, var_123=255, var_123_arg_0=1, var_123_arg_1=255, var_123_arg_2=0, var_124=0, var_124_arg_0=0, var_124_arg_1=0, var_124_arg_2=255, var_128=0, var_128_arg_0=3, var_128_arg_1=0, var_129=0, var_129_arg_0=0, var_129_arg_1=255, var_129_arg_2=0, var_130=0, var_130_arg_0=0, var_130_arg_1=0, var_130_arg_2=0, var_131=3, var_131_arg_0=3, var_131_arg_1=0, var_133=1, var_133_arg_0=1, var_133_arg_1=0, var_134=0, var_134_arg_0=1, var_134_arg_1=1, var_138=1, var_138_arg_0=1, var_138_arg_1=0, var_139=0, var_139_arg_0=1, var_139_arg_1=1, var_141=1, var_141_arg_0=1, var_141_arg_1=0, var_142=0, var_142_arg_0=1, var_142_arg_1=1, var_147=1, var_147_arg_0=1, var_147_arg_1=0, var_148=0, var_148_arg_0=1, var_148_arg_1=1, var_150=1, var_150_arg_0=1, var_150_arg_1=0, var_151=0, var_151_arg_0=1, var_151_arg_1=1, var_155=1, var_155_arg_0=1, var_155_arg_1=0, var_156=0, var_156_arg_0=1, var_156_arg_1=1, var_159=1, var_159_arg_0=1, var_159_arg_1=0, var_160=0, var_160_arg_0=1, var_160_arg_1=1, var_162=1, var_162_arg_0=1, var_162_arg_1=0, var_163=0, var_163_arg_0=1, var_163_arg_1=1, var_171=6, var_173=5, var_179=0, var_180=0, var_180_arg_0=0, var_180_arg_1=0, var_180_arg_2=0, var_181=0, var_181_arg_0=0, var_181_arg_1=1, var_181_arg_2=0, var_182=2, var_182_arg_0=1, var_182_arg_1=2, var_182_arg_2=0, var_183=2, var_183_arg_0=0, var_183_arg_1=3, var_183_arg_2=2, var_184=2, var_184_arg_0=0, var_184_arg_1=4, var_184_arg_2=2, var_185=2, var_185_arg_0=0, var_185_arg_1=5, var_185_arg_2=2, var_186=9, var_186_arg_0=1, var_186_arg_1=6, var_186_arg_2=2, var_188=0, var_189=0, var_189_arg_0=0, var_189_arg_1=0, var_190=0, var_190_arg_0=0, var_190_arg_1=0, var_191=0, var_191_arg_0=0, var_191_arg_1=0, var_192=0, var_192_arg_0=0, var_193=0, var_193_arg_0=0, var_193_arg_1=0, var_194=0, var_194_arg_0=0, var_194_arg_1=0, var_195=0, var_195_arg_0=0, var_196=1, var_196_arg_0=0, var_196_arg_1=1, var_197=4294967295, var_197_arg_0=0, var_197_arg_1=1, var_198=255, var_198_arg_0=4294967295, var_199=1, var_199_arg_0=0, var_199_arg_1=1, var_200=4294967295, var_200_arg_0=0, var_200_arg_1=1, var_201=255, var_201_arg_0=4294967295, var_202=0, var_202_arg_0=0, var_202_arg_1=0, var_203=0, var_203_arg_0=0, var_203_arg_1=0, var_204=0, var_204_arg_0=0, var_205=0, var_205_arg_0=0, var_205_arg_1=0, var_206=0, var_206_arg_0=0, var_206_arg_1=0, var_207=0, var_207_arg_0=0, var_208=1, var_208_arg_0=0, var_208_arg_1=1, var_209=4294967295, var_209_arg_0=0, var_209_arg_1=1, var_210=255, var_210_arg_0=4294967295, var_211=0, var_211_arg_0=0, var_211_arg_1=0, var_212=0, var_212_arg_0=0, var_213=0, var_213_arg_0=0, var_213_arg_1=0, var_214=0, var_214_arg_0=0, var_215=1, var_215_arg_0=0, var_215_arg_1=1, var_216=1, var_216_arg_0=1, var_217=1, var_217_arg_0=0, var_217_arg_1=1, var_218=1, var_218_arg_0=1, var_219=0, var_219_arg_0=0, var_219_arg_1=0, var_220=0, var_220_arg_0=0, var_221=0, var_221_arg_0=0, var_221_arg_1=0, var_222=0, var_222_arg_0=0, var_223=1, var_223_arg_0=0, var_223_arg_1=1, var_224=1, var_224_arg_0=1, var_225=1, var_225_arg_0=1, var_225_arg_1=1, var_225_arg_2=0, var_226=1, var_226_arg_0=0, var_226_arg_1=0, var_226_arg_2=1, var_227=1, var_227_arg_0=0, var_227_arg_1=0, var_227_arg_2=1, var_228=1, var_228_arg_0=0, var_228_arg_1=1, var_228_arg_2=1, var_229=1, var_229_arg_0=1, var_229_arg_1=1, var_229_arg_2=1, var_230=0, var_230_arg_0=1, var_230_arg_1=0, var_230_arg_2=1, var_231=0, var_231_arg_0=0, var_231_arg_1=0, var_231_arg_2=0, var_232=0, var_232_arg_0=0, var_232_arg_1=255, var_232_arg_2=0, var_233=0, var_233_arg_0=1, var_233_arg_1=0, var_233_arg_2=0, var_234=0, var_234_arg_0=0, var_234_arg_1=0, var_234_arg_2=0, var_235=255, var_235_arg_0=1, var_235_arg_1=255, var_235_arg_2=0, var_236=255, var_236_arg_0=1, var_236_arg_1=255, var_236_arg_2=255, var_237=255, var_237_arg_0=0, var_237_arg_1=0, var_237_arg_2=255, var_238=0, var_238_arg_0=0, var_238_arg_1=0, var_238_arg_2=255, var_240=0, var_240_arg_0=0, var_240_arg_1=0, var_241=0, var_241_arg_0=0, var_241_arg_1=0, var_242=0, var_242_arg_0=0, var_242_arg_1=0, var_243=0, var_243_arg_0=0, var_244=1, var_244_arg_0=0, var_244_arg_1=1, var_245=4294967295, var_245_arg_0=0, var_245_arg_1=1, var_246=255, var_246_arg_0=4294967295, var_247=0, var_247_arg_0=0, var_247_arg_1=0, var_248=0, var_248_arg_0=0, var_248_arg_1=0, var_249=0, var_249_arg_0=0, var_250=0, var_250_arg_0=0, var_250_arg_1=0, var_251=0, var_251_arg_0=0, var_251_arg_1=0, var_252=0, var_252_arg_0=0, var_253=1, var_253_arg_0=0, var_253_arg_1=1, var_254=4294967295, var_254_arg_0=0, var_254_arg_1=1, var_255=255, var_255_arg_0=4294967295, var_256=1, var_256_arg_0=0, var_256_arg_1=1, var_257=4294967295, var_257_arg_0=0, var_257_arg_1=1, var_258=255, var_258_arg_0=4294967295, var_259=0, var_259_arg_0=0, var_259_arg_1=0, var_260=0, var_260_arg_0=0, var_260_arg_1=0, var_261=0, var_261_arg_0=0, var_262=0, var_262_arg_0=0, var_262_arg_1=0, var_263=0, var_263_arg_0=0, var_264=1, var_264_arg_0=0, var_264_arg_1=1, var_265=1, var_265_arg_0=1, var_266=0, var_266_arg_0=0, var_266_arg_1=0, var_267=0, var_267_arg_0=0, var_268=0, var_268_arg_0=0, var_268_arg_1=0, var_269=0, var_269_arg_0=0, var_270=1, var_270_arg_0=0, var_270_arg_1=1, var_271=1, var_271_arg_0=1, var_272=1, var_272_arg_0=0, var_272_arg_1=1, var_273=1, var_273_arg_0=1, var_274=0, var_274_arg_0=0, var_274_arg_1=0, var_275=0, var_275_arg_0=0, var_276=0, var_276_arg_0=1, var_276_arg_1=0, var_276_arg_2=0, var_277=0, var_277_arg_0=0, var_277_arg_1=1, var_277_arg_2=0, var_278=0, var_278_arg_0=0, var_278_arg_1=1, var_278_arg_2=0, var_279=0, var_279_arg_0=0, var_279_arg_1=0, var_279_arg_2=0, var_280=0, var_280_arg_0=1, var_280_arg_1=0, var_280_arg_2=0, var_281=1, var_281_arg_0=1, var_281_arg_1=1, var_281_arg_2=0, var_282=1, var_282_arg_0=0, var_282_arg_1=0, var_282_arg_2=1, var_283=1, var_283_arg_0=0, var_283_arg_1=0, var_283_arg_2=1, var_284=255, var_284_arg_0=1, var_284_arg_1=255, var_284_arg_2=1, var_285=255, var_285_arg_0=0, var_285_arg_1=255, var_285_arg_2=255, var_286=0, var_286_arg_0=1, var_286_arg_1=0, var_286_arg_2=255, var_287=0, var_287_arg_0=1, var_287_arg_1=0, var_287_arg_2=0, var_288=0, var_288_arg_0=0, var_288_arg_1=255, var_288_arg_2=0, var_289=0, var_289_arg_0=0, var_289_arg_1=0, var_289_arg_2=0, var_291=0, var_291_arg_0=0, var_291_arg_1=0, var_292=1, var_293=4294967295, var_293_arg_0=0, var_293_arg_1=1, var_294=255, var_294_arg_0=4294967295, var_295=1, var_295_arg_0=1, var_295_arg_1=0, var_296=1, var_296_arg_0=1, var_297=1, var_297_arg_0=1, var_297_arg_1=1, var_297_arg_2=0, var_298=1, var_298_arg_0=0, var_298_arg_1=1, var_298_arg_2=1, var_299=1, var_299_arg_0=0, var_299_arg_1=1, var_299_arg_2=1, var_300=1, var_300_arg_0=0, var_300_arg_1=1, var_300_arg_2=1, var_301=1, var_301_arg_0=1, var_301_arg_1=1, var_301_arg_2=1, var_302=1, var_302_arg_0=1, var_302_arg_1=1, var_302_arg_2=1, var_303=1, var_303_arg_0=0, var_303_arg_1=1, var_303_arg_2=1, var_304=1, var_304_arg_0=0, var_304_arg_1=255, var_304_arg_2=1, var_305=255, var_305_arg_0=1, var_305_arg_1=255, var_305_arg_2=1, var_306=255, var_306_arg_0=0, var_306_arg_1=255, var_306_arg_2=255, var_307=255, var_307_arg_0=1, var_307_arg_1=255, var_307_arg_2=255, var_308=255, var_308_arg_0=1, var_308_arg_1=255, var_308_arg_2=255, var_309=255, var_309_arg_0=0, var_309_arg_1=255, var_309_arg_2=255, var_310=2, var_310_arg_0=0, var_310_arg_1=255, var_310_arg_2=255, var_312=0, var_312_arg_0=0, var_312_arg_1=0, var_313=0, var_313_arg_0=0, var_313_arg_1=0, var_314=0, var_314_arg_0=0, var_314_arg_1=0, var_315=0, var_315_arg_0=0, var_316=0, var_316_arg_0=0, var_316_arg_1=0, var_317=0, var_317_arg_0=0, var_317_arg_1=0, var_318=0, var_318_arg_0=0, var_319=0, var_319_arg_0=0, var_319_arg_1=0, var_320=0, var_320_arg_0=0, var_320_arg_1=0, var_321=0, var_321_arg_0=0, var_322=0, var_322_arg_0=0, var_322_arg_1=0, var_323=0, var_323_arg_0=0, var_323_arg_1=0, var_324=0, var_324_arg_0=0, var_325=0, var_325_arg_0=0, var_325_arg_1=0, var_326=0, var_326_arg_0=0, var_326_arg_1=0, var_327=0, var_327_arg_0=0, var_328=1, var_328_arg_0=0, var_328_arg_1=1, var_329=0, var_329_arg_0=0, var_329_arg_1=1, var_330=0, var_330_arg_0=0, var_331=1, var_331_arg_0=0, var_331_arg_1=1, var_332=4294967040, var_332_arg_0=0, var_332_arg_1=1, var_333=0, var_333_arg_0=4294967040, var_334=0, var_334_arg_0=0, var_334_arg_1=0, var_335=0, var_335_arg_0=0, var_336=0, var_336_arg_0=0, var_336_arg_1=0, var_337=0, var_337_arg_0=0, var_338=0, var_338_arg_0=0, var_338_arg_1=0, var_339=0, var_339_arg_0=0, var_340=0, var_340_arg_0=0, var_340_arg_1=0, var_341=0, var_341_arg_0=0, var_342=0, var_342_arg_0=0, var_342_arg_1=0, var_343=0, var_343_arg_0=0, var_344=1, var_344_arg_0=0, var_344_arg_1=1, var_345=1, var_345_arg_0=1, var_346=1, var_346_arg_0=0, var_346_arg_1=1, var_347=1, var_347_arg_0=1, var_348=1, var_348_arg_0=1, var_348_arg_1=1, var_348_arg_2=0, var_349=1, var_349_arg_0=0, var_349_arg_1=1, var_349_arg_2=1, var_350=1, var_350_arg_0=0, var_350_arg_1=0, var_350_arg_2=1, var_351=1, var_351_arg_0=0, var_351_arg_1=0, var_351_arg_2=1, var_352=0, var_352_arg_0=1, var_352_arg_1=0, var_352_arg_2=1, var_353=0, var_353_arg_0=1, var_353_arg_1=0, var_353_arg_2=0, var_354=0, var_354_arg_0=0, var_354_arg_1=0, var_354_arg_2=0, var_355=0, var_355_arg_0=0, var_355_arg_1=0, var_355_arg_2=0, var_356=0, var_356_arg_0=1, var_356_arg_1=0, var_356_arg_2=0, var_357=0, var_357_arg_0=0, var_357_arg_1=0, var_357_arg_2=0, var_358=0, var_358_arg_0=1, var_358_arg_1=0, var_358_arg_2=0, var_359=0, var_359_arg_0=1, var_359_arg_1=0, var_359_arg_2=0, var_360=0, var_360_arg_0=0, var_360_arg_1=0, var_360_arg_2=0, var_361=0, var_361_arg_0=0, var_361_arg_1=0, var_361_arg_2=0, var_365=1, var_365_arg_0=1, var_365_arg_1=1, var_367=7, var_367_arg_0=0, var_367_arg_1=57, var_369=1, var_369_arg_0=0, var_369_arg_1=0, var_370=0, var_370_arg_0=0, var_370_arg_1=1, var_371=0, var_371_arg_0=1, var_371_arg_1=0, var_372=1, var_372_arg_0=0, var_372_arg_1=0, var_373=0, var_373_arg_0=0, var_373_arg_1=1, var_374=0, var_374_arg_0=0, var_374_arg_1=255, var_375=0, var_375_arg_0=0, var_375_arg_1=0, var_376=1, var_376_arg_0=0, var_376_arg_1=0, var_377=0, var_377_arg_0=0, var_377_arg_1=1, var_378=1, var_378_arg_0=0, var_378_arg_1=0, var_379=0, var_379_arg_0=0, var_379_arg_1=1, var_380=1, var_380_arg_0=0, var_380_arg_1=0, var_381=0, var_381_arg_0=0, var_381_arg_1=1, var_382=0, var_382_arg_0=0, var_382_arg_1=0, var_383=1, var_383_arg_0=1, var_383_arg_1=0, var_384=1, var_384_arg_0=0, var_384_arg_1=0, var_385=3, var_386=0, var_386_arg_0=3, var_386_arg_1=0, var_387=1, var_387_arg_0=1, var_387_arg_1=1, var_388=0, var_388_arg_0=0, var_388_arg_1=1, var_389=1, var_389_arg_0=0, var_389_arg_1=0, var_390=1, var_390_arg_0=0, var_390_arg_1=1, var_391=1, var_391_arg_0=1, var_391_arg_1=1, var_392=1, var_392_arg_0=0, var_392_arg_1=0, var_393=1, var_393_arg_0=0, var_393_arg_1=0, var_394=1, var_394_arg_0=1, var_394_arg_1=1, var_395=1, var_395_arg_0=1, var_395_arg_1=1, var_396=0, var_396_arg_0=0, var_396_arg_1=1, var_397=0, var_398=1, var_398_arg_0=0, var_398_arg_1=0, var_399=1, var_399_arg_0=0, var_399_arg_1=1, var_400=1, var_400_arg_0=1, var_400_arg_1=1, var_401=0, var_401_arg_0=0, var_401_arg_1=1, var_402=1, var_402_arg_0=1, var_402_arg_1=0, var_403=1, var_403_arg_0=1, var_403_arg_1=1, var_404=0, var_404_arg_0=1, var_404_arg_1=0, var_405=0, var_405_arg_0=1, var_405_arg_1=0, var_406=1, var_406_arg_0=0, var_406_arg_1=0, var_407=1, var_407_arg_0=1, var_407_arg_1=1, var_408=0, var_408_arg_0=0, var_408_arg_1=1, var_409=0, var_409_arg_0=0, var_409_arg_1=1, var_410=1, var_410_arg_0=1, var_410_arg_1=0, var_411=0, var_411_arg_0=0, var_411_arg_1=1, var_412=0, var_412_arg_0=0, var_412_arg_1=1, var_413=1, var_413_arg_0=1, var_413_arg_1=0, var_414=0, var_414_arg_0=0, var_414_arg_1=1, var_415=0, var_415_arg_0=1, var_415_arg_1=0, var_416=1, var_416_arg_0=1, var_416_arg_1=0, var_417=1, var_417_arg_0=1, var_417_arg_1=1, var_418=1, var_418_arg_0=0, var_418_arg_1=0, var_419=0, var_419_arg_0=0, var_419_arg_1=1, var_420=1, var_420_arg_0=0, var_420_arg_1=0, var_421=1, var_421_arg_0=1, var_421_arg_1=1, var_422=0, var_422_arg_0=0, var_422_arg_1=1, var_423=0, var_423_arg_0=0, var_423_arg_1=1, var_424=1, var_424_arg_0=1, var_424_arg_1=0, var_425=0, var_425_arg_0=0, var_425_arg_1=1, var_426=1, var_426_arg_0=0, var_426_arg_1=0, var_427=1, var_427_arg_0=0, var_427_arg_1=1, var_428=0, var_428_arg_0=0, var_428_arg_1=1, var_429=0, var_429_arg_0=1, var_429_arg_1=0, var_430=1, var_430_arg_0=1, var_430_arg_1=0, var_431=1, var_431_arg_0=1, var_431_arg_1=1, var_432=0, var_432_arg_0=255, var_432_arg_1=0, var_433=0, var_433_arg_0=1, var_433_arg_1=0, var_434=0, var_434_arg_0=0, var_434_arg_1=1, var_435=1, var_435_arg_0=1, var_435_arg_1=0, var_436=0, var_436_arg_0=0, var_436_arg_1=1, var_437=1, var_437_arg_0=0, var_437_arg_1=0, var_438=1, var_438_arg_0=1, var_438_arg_1=1, var_439=0, var_439_arg_0=0, var_439_arg_1=1, var_440=1, var_440_arg_0=0, var_440_arg_1=0, var_441=1, var_441_arg_0=1, var_441_arg_1=1, var_442=0, var_442_arg_0=0, var_442_arg_1=1, var_443=0, var_443_arg_0=0, var_443_arg_1=0, var_444=1, var_444_arg_0=1, var_444_arg_1=0, var_445=1, var_445_arg_0=1, var_445_arg_1=1, var_446=1, var_446_arg_0=0, var_446_arg_1=0, var_447=0, var_447_arg_0=0, var_447_arg_1=1, var_448=0, var_448_arg_0=0, var_448_arg_1=1, var_449=1, var_449_arg_0=1, var_449_arg_1=0, var_450=0, var_450_arg_0=0, var_450_arg_1=1, var_451=1, var_451_arg_0=0, var_451_arg_1=0, var_452=1, var_452_arg_0=1, var_452_arg_1=1, var_453=0, var_453_arg_0=0, var_453_arg_1=1, var_454=1, var_454_arg_0=0, var_454_arg_1=0, var_455=1, var_455_arg_0=1, var_455_arg_1=1, var_456=0, var_456_arg_0=0, var_456_arg_1=1, var_457=0, var_457_arg_0=0, var_457_arg_1=0, var_458=1, var_458_arg_0=1, var_458_arg_1=0, var_459=1, var_459_arg_0=1, var_459_arg_1=1, var_460=1, var_460_arg_0=0, var_460_arg_1=0, var_461=1, var_461_arg_0=1, var_461_arg_1=1, var_462=1, var_462_arg_0=0, var_462_arg_1=0, var_463=1, var_463_arg_0=1, var_463_arg_1=1, var_464=1, var_464_arg_0=1, var_464_arg_1=1, var_465=0, var_465_arg_0=0, var_465_arg_1=1, var_466=1, var_466_arg_0=1, var_466_arg_1=0, var_467=1, var_467_arg_0=1, var_467_arg_1=1, var_468=1, var_468_arg_0=0, var_468_arg_1=0, var_469=1, var_469_arg_0=0, var_469_arg_1=1, var_470=1, var_470_arg_0=1, var_470_arg_1=1, var_471=0, var_471_arg_0=0, var_471_arg_1=1, var_472=1, var_472_arg_0=1, var_472_arg_1=0, var_473=1, var_473_arg_0=1, var_473_arg_1=1, var_474=1, var_474_arg_0=0, var_474_arg_1=0, var_475=0, var_475_arg_0=0, var_475_arg_1=1, var_476=1, var_476_arg_0=0, var_476_arg_1=0, var_477=1, var_477_arg_0=1, var_477_arg_1=1, var_478=0, var_478_arg_0=0, var_478_arg_1=1, var_479=1, var_479_arg_0=0, var_479_arg_1=0, var_480=1, var_480_arg_0=1, var_480_arg_1=1, var_481=0, var_481_arg_0=0, var_481_arg_1=1, var_482=1, var_482_arg_0=0, var_482_arg_1=0, var_483=1, var_483_arg_0=1, var_483_arg_1=1, var_484=0, var_484_arg_0=0, var_484_arg_1=1, var_485=0, var_485_arg_0=1, var_485_arg_1=0, var_486=0, var_486_arg_0=0, var_486_arg_1=0, var_487=0, var_487_arg_0=1, var_487_arg_1=0, var_488=0, var_488_arg_0=255, var_488_arg_1=0, var_489=2, var_490=1, var_490_arg_0=0, var_490_arg_1=2, var_491=0, var_491_arg_0=0, var_491_arg_1=4294967040, var_492=0, var_492_arg_0=0, var_492_arg_1=0, var_493=0, var_493_arg_0=0, var_493_arg_1=0, var_494=0, var_494_arg_0=1, var_494_arg_1=0, var_495=1, var_495_arg_0=1, var_495_arg_1=0, var_496=0, var_496_arg_0=0, var_496_arg_1=1, var_497=0, var_497_arg_0=255, var_497_arg_1=1, var_498=1, var_498_arg_0=0, var_498_arg_1=0, var_499=1, var_499_arg_0=1, var_499_arg_1=1, var_5=0, var_500=0, var_500_arg_0=0, var_500_arg_1=1, var_501=0, var_501_arg_0=1, var_501_arg_1=0, var_502=0, var_502_arg_0=0, var_502_arg_1=0, var_503=0, var_503_arg_0=0, var_503_arg_1=0, var_504=0, var_504_arg_0=255, var_504_arg_1=0, var_505=1, var_505_arg_0=0, var_505_arg_1=0, var_506=1, var_506_arg_0=1, var_506_arg_1=1, var_507=0, var_507_arg_0=0, var_507_arg_1=1, var_508=0, var_508_arg_0=1, var_508_arg_1=0, var_509=0, var_509_arg_0=0, var_509_arg_1=0, var_510=0, var_510_arg_0=0, var_510_arg_1=0, var_511=1, var_511_arg_0=255, var_511_arg_1=255, var_512=1, var_512_arg_0=0, var_512_arg_1=0, var_513=1, var_513_arg_0=1, var_513_arg_1=1, var_514=1, var_514_arg_0=1, var_514_arg_1=1, var_515=1, var_515_arg_0=1, var_515_arg_1=1, var_516=1, var_516_arg_0=1, var_516_arg_1=1, var_517=0, var_517_arg_0=0, var_517_arg_1=1, var_518=0, var_518_arg_0=255, var_518_arg_1=0, var_519=1, var_519_arg_0=0, var_519_arg_1=0, var_520=1, var_520_arg_0=1, var_520_arg_1=1, var_521=0, var_521_arg_0=0, var_521_arg_1=1, var_522=0, var_522_arg_0=1, var_522_arg_1=0, var_523=0, var_523_arg_0=0, var_523_arg_1=0, var_524=0, var_524_arg_0=0, var_524_arg_1=0, var_525=0, var_525_arg_0=255, var_525_arg_1=0, var_526=1, var_526_arg_0=0, var_526_arg_1=0, var_527=1, var_527_arg_0=1, var_527_arg_1=1, var_528=0, var_528_arg_0=0, var_528_arg_1=1, var_529=0, var_529_arg_0=0, var_529_arg_1=0, var_530=0, var_530_arg_0=0, var_530_arg_1=0, var_531=0, var_531_arg_0=0, var_531_arg_1=0, var_532=0, var_532_arg_0=255, var_532_arg_1=0, var_533=1, var_533_arg_0=0, var_533_arg_1=0, var_534=1, var_534_arg_0=1, var_534_arg_1=1, var_535=0, var_535_arg_0=0, var_535_arg_1=1, var_536=0, var_536_arg_0=1, var_536_arg_1=0, var_537=0, var_537_arg_0=0, var_537_arg_1=0, var_538=0, var_538_arg_0=0, var_538_arg_1=0, var_539=0, var_539_arg_0=0, var_539_arg_1=0, var_540=0, var_540_arg_0=0, var_540_arg_1=0, var_541=1, var_541_arg_0=1, var_541_arg_1=0, var_542=0, var_542_arg_0=0, var_542_arg_1=1, var_543=1, var_543_arg_0=1, var_543_arg_1=1, var_544=0, var_544_arg_0=0, var_544_arg_1=1, var_545=0, var_545_arg_0=0, var_545_arg_1=0, var_546=0, var_546_arg_0=0, var_546_arg_1=0, var_547=1, var_547_arg_0=1, var_547_arg_1=0, var_548=0, var_548_arg_0=0, var_548_arg_1=1, var_549=0, var_549_arg_0=0, var_549_arg_1=0, var_550=0, var_550_arg_0=0, var_550_arg_1=0, var_551=0, var_551_arg_0=0, var_551_arg_1=0, var_552=0, var_552_arg_0=0, var_552_arg_1=0, var_553=56, var_553_arg_0=57, var_553_arg_1=1, var_554=50, var_554_arg_0=0, var_554_arg_1=56, var_555=5, var_555_arg_0=0, var_555_arg_1=50, var_556=250, var_556_arg_0=0, var_556_arg_1=5, var_557=27, var_557_arg_0=1, var_557_arg_1=250, var_558=46, var_558_arg_0=1, var_558_arg_1=27, var_559=253, var_559_arg_0=0, var_559_arg_1=46, var_560=251, var_560_arg_0=0, var_560_arg_1=253, var_561=20, var_561_arg_0=1, var_561_arg_1=251, var_562=23, var_562_arg_0=0, var_562_arg_1=20, var_563=1, var_563_arg_0=1, var_563_arg_1=23, var_564=1, var_564_arg_0=1, var_564_arg_1=1, var_565=1, var_565_arg_0=0, var_565_arg_1=1, var_566=1, var_566_arg_0=0, var_566_arg_1=1, var_567=1, var_567_arg_0=0, var_567_arg_1=1, var_568=1, var_568_arg_0=0, var_568_arg_1=1, var_569=1, var_569_arg_0=1, var_569_arg_1=1, var_570=1, var_570_arg_0=0, var_570_arg_1=1, var_571=1, var_571_arg_0=0, var_571_arg_1=1, var_572=1, var_572_arg_0=0, var_572_arg_1=1, var_573=1, var_573_arg_0=1, var_573_arg_1=1, var_574=0, var_574_arg_0=0, var_574_arg_1=1, var_575=1, var_575_arg_0=57, var_575_arg_1=1, var_576=0, var_576_arg_0=0, var_576_arg_1=56, var_577=1, var_577_arg_0=1, var_577_arg_1=0, var_578=0, var_578_arg_0=0, var_578_arg_1=50, var_579=1, var_579_arg_0=1, var_579_arg_1=0, var_580=0, var_580_arg_0=0, var_580_arg_1=5, var_581=1, var_581_arg_0=1, var_581_arg_1=0, var_582=0, var_582_arg_0=1, var_582_arg_1=250, var_583=1, var_583_arg_0=1, var_583_arg_1=0, var_584=1, var_584_arg_0=1, var_584_arg_1=27, var_585=1, var_585_arg_0=1, var_585_arg_1=1, var_586=0, var_586_arg_0=0, var_586_arg_1=46, var_587=1, var_587_arg_0=1, var_587_arg_1=0, var_588=0, var_588_arg_0=0, var_588_arg_1=253, var_589=1, var_589_arg_0=1, var_589_arg_1=0, var_590=1, var_590_arg_0=1, var_590_arg_1=251, var_591=1, var_591_arg_0=1, var_591_arg_1=1, var_592=0, var_592_arg_0=0, var_592_arg_1=20, var_593=1, var_593_arg_0=1, var_593_arg_1=0, var_594=1, var_594_arg_0=1, var_594_arg_1=23, var_595=1, var_595_arg_0=1, var_595_arg_1=1, var_596=1, var_596_arg_0=1, var_596_arg_1=1, var_597=1, var_597_arg_0=1, var_597_arg_1=1, var_598=0, var_598_arg_0=0, var_598_arg_1=1, var_599=1, var_599_arg_0=1, var_599_arg_1=0, var_600=0, var_600_arg_0=0, var_600_arg_1=1, var_601=1, var_601_arg_0=1, var_601_arg_1=0, var_602=0, var_602_arg_0=0, var_602_arg_1=1, var_603=1, var_603_arg_0=1, var_603_arg_1=0, var_604=0, var_604_arg_0=0, var_604_arg_1=1, var_605=1, var_605_arg_0=1, var_605_arg_1=0, var_606=1, var_606_arg_0=1, var_606_arg_1=1, var_607=1, var_607_arg_0=1, var_607_arg_1=1, var_608=0, var_608_arg_0=0, var_608_arg_1=1, var_609=1, var_609_arg_0=1, var_609_arg_1=0, var_610=0, var_610_arg_0=0, var_610_arg_1=1, var_611=1, var_611_arg_0=1, var_611_arg_1=0, var_612=0, var_612_arg_0=0, var_612_arg_1=1, var_613=1, var_613_arg_0=1, var_613_arg_1=0, var_614=1, var_614_arg_0=1, var_614_arg_1=1, var_615=1, var_615_arg_0=1, var_615_arg_1=1, var_616=0, var_616_arg_0=0, var_616_arg_1=0, var_617=0, var_617_arg_0=1, var_617_arg_1=0, var_618=0, var_618_arg_0=0, var_618_arg_1=0, var_619=0, var_619_arg_0=0, var_619_arg_1=0, var_620=0, var_620_arg_0=0, var_620_arg_1=0, var_621=1, var_621_arg_0=1, var_621_arg_1=7, var_622=0, var_622_arg_0=1, var_622_arg_1=7, var_623=0, var_623_arg_0=0, var_623_arg_1=0, var_624=0, var_624_arg_0=0, var_624_arg_1=0, var_625=0, var_625_arg_0=0, var_625_arg_1=0, var_74=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_85=255, var_86=255, var_86_arg_0=1, var_86_arg_1=255, var_86_arg_2=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=255, var_89=1, var_92=1, var_92_arg_0=1, var_92_arg_1=0, var_93=1, var_93_arg_0=0, var_93_arg_1=255, var_93_arg_2=1, var_94=0, var_94_arg_0=1, var_94_arg_1=0, var_94_arg_2=1, var_95=1, var_95_arg_0=1, var_95_arg_1=0, var_97=2] [L190] input_83 = __VERIFIER_nondet_uchar() [L191] input_83 = input_83 & mask_SORT_1 [L192] input_84 = __VERIFIER_nondet_uchar() [L193] input_84 = input_84 & mask_SORT_1 [L194] input_90 = __VERIFIER_nondet_uchar() [L195] input_90 = input_90 & mask_SORT_1 [L196] input_91 = __VERIFIER_nondet_uchar() [L197] input_91 = input_91 & mask_SORT_1 [L198] input_98 = __VERIFIER_nondet_uchar() [L199] input_98 = input_98 & mask_SORT_1 [L200] input_99 = __VERIFIER_nondet_uchar() [L201] input_99 = input_99 & mask_SORT_1 [L202] input_106 = __VERIFIER_nondet_uchar() [L203] input_106 = input_106 & mask_SORT_1 [L204] input_107 = __VERIFIER_nondet_uchar() [L205] input_107 = input_107 & mask_SORT_1 [L206] input_114 = __VERIFIER_nondet_uchar() [L207] input_114 = input_114 & mask_SORT_1 [L208] input_115 = __VERIFIER_nondet_uchar() [L209] input_115 = input_115 & mask_SORT_1 [L210] input_121 = __VERIFIER_nondet_uchar() [L211] input_121 = input_121 & mask_SORT_1 [L212] input_122 = __VERIFIER_nondet_uchar() [L213] input_122 = input_122 & mask_SORT_1 [L214] input_126 = __VERIFIER_nondet_uchar() [L215] input_126 = input_126 & mask_SORT_1 [L216] input_127 = __VERIFIER_nondet_uchar() [L217] input_127 = input_127 & mask_SORT_1 [L218] input_170 = __VERIFIER_nondet_uchar() [L219] input_170 = input_170 & mask_SORT_1 [L220] input_172 = __VERIFIER_nondet_uchar() [L221] input_172 = input_172 & mask_SORT_1 [L222] input_174 = __VERIFIER_nondet_uchar() [L223] input_174 = input_174 & mask_SORT_1 [L224] input_175 = __VERIFIER_nondet_uchar() [L225] input_175 = input_175 & mask_SORT_1 [L226] input_176 = __VERIFIER_nondet_uchar() [L227] input_176 = input_176 & mask_SORT_1 [L228] input_177 = __VERIFIER_nondet_uchar() [L229] input_177 = input_177 & mask_SORT_1 [L230] input_178 = __VERIFIER_nondet_uchar() [L231] input_178 = input_178 & mask_SORT_1 [L232] input_364 = __VERIFIER_nondet_uchar() [L235] SORT_1 var_81_arg_0 = state_77; [L236] SORT_1 var_81_arg_1 = ~state_79; [L237] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L238] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L239] var_81 = var_81 & mask_SORT_1 [L240] SORT_1 bad_82_arg_0 = var_81; [L241] CALL __VERIFIER_assert(!(bad_82_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 343.6s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 2.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 1 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 2.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 2.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 7 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 7 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 179.3s SatisfiabilityAnalysisTime, 1.2s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 8 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:28:06,969 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash a057f8e84c57630b688ef84d43f8a057c3ac3f8873065d131b16909986852b1e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:28:09,431 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:28:09,433 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:28:09,473 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:28:09,474 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:28:09,478 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:28:09,480 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:28:09,484 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:28:09,490 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:28:09,497 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:28:09,498 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:28:09,500 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:28:09,501 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:28:09,503 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:28:09,505 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:28:09,507 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:28:09,508 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:28:09,509 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:28:09,511 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:28:09,518 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:28:09,521 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:28:09,522 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:28:09,525 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:28:09,527 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:28:09,532 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:28:09,536 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:28:09,536 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:28:09,537 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:28:09,539 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:28:09,540 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:28:09,541 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:28:09,541 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:28:09,543 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:28:09,544 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:28:09,545 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:28:09,545 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:28:09,546 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:28:09,546 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:28:09,547 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:28:09,548 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:28:09,549 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:28:09,550 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:28:09,589 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:28:09,589 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:28:09,590 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:28:09,590 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:28:09,592 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:28:09,592 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:28:09,592 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:28:09,592 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:28:09,592 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:28:09,593 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:28:09,594 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:28:09,594 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:28:09,595 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:28:09,596 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:28:09,596 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:28:09,596 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:28:09,596 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:28:09,596 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:28:09,597 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:28:09,597 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:28:09,597 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:28:09,597 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:28:09,597 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:28:09,598 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:28:09,598 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:28:09,598 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:28:09,598 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:28:09,599 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:28:09,599 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:28:09,599 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:28:09,599 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:28:09,599 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:28:09,600 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:28:09,600 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:28:09,600 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:28:09,601 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a057f8e84c57630b688ef84d43f8a057c3ac3f8873065d131b16909986852b1e [2022-11-03 02:28:10,005 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:28:10,039 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:28:10,042 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:28:10,044 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:28:10,045 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:28:10,046 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:28:10,122 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/b936ac7e1/8d9846a5456744a98bee7f24c00dcb05/FLAG0b04f1dcf [2022-11-03 02:28:10,778 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:28:10,780 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:28:10,803 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/b936ac7e1/8d9846a5456744a98bee7f24c00dcb05/FLAG0b04f1dcf [2022-11-03 02:28:10,994 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/data/b936ac7e1/8d9846a5456744a98bee7f24c00dcb05 [2022-11-03 02:28:10,998 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:28:11,000 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:28:11,004 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:28:11,004 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:28:11,007 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:28:11,008 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:28:10" (1/1) ... [2022-11-03 02:28:11,010 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3a7afa25 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11, skipping insertion in model container [2022-11-03 02:28:11,010 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:28:10" (1/1) ... [2022-11-03 02:28:11,017 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:28:11,095 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:28:11,342 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c[1014,1027] [2022-11-03 02:28:11,836 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:28:11,839 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:28:11,850 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c[1014,1027] [2022-11-03 02:28:11,978 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:28:11,990 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:28:11,991 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11 WrapperNode [2022-11-03 02:28:11,991 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:28:11,992 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:28:11,992 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:28:11,993 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:28:12,000 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,069 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,155 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2212 [2022-11-03 02:28:12,156 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:28:12,156 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:28:12,156 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:28:12,156 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:28:12,166 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,166 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,178 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,178 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,226 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,237 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,264 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,273 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,294 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:28:12,305 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:28:12,305 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:28:12,306 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:28:12,308 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (1/1) ... [2022-11-03 02:28:12,315 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:28:12,327 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:28:12,341 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:28:12,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:28:12,421 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:28:12,421 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:28:12,924 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:28:12,926 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:28:15,295 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:28:15,308 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:28:15,308 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:28:15,311 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:28:15 BoogieIcfgContainer [2022-11-03 02:28:15,311 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:28:15,314 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:28:15,314 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:28:15,317 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:28:15,318 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:28:10" (1/3) ... [2022-11-03 02:28:15,318 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a766db8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:28:15, skipping insertion in model container [2022-11-03 02:28:15,319 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:28:11" (2/3) ... [2022-11-03 02:28:15,319 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a766db8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:28:15, skipping insertion in model container [2022-11-03 02:28:15,319 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:28:15" (3/3) ... [2022-11-03 02:28:15,321 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.elevator_planning.2.prop1-func-interl.c [2022-11-03 02:28:15,340 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:28:15,340 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:28:15,412 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:28:15,420 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3332e0f6, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:28:15,421 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:28:15,426 INFO L276 IsEmpty]: Start isEmpty. Operand has 165 states, 163 states have (on average 1.4969325153374233) internal successors, (244), 164 states have internal predecessors, (244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:15,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 02:28:15,432 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:15,433 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 02:28:15,434 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:15,441 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:15,441 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 02:28:15,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:15,457 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1604199258] [2022-11-03 02:28:15,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:15,458 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:15,458 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:15,462 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:15,506 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:28:15,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:15,990 INFO L263 TraceCheckSpWp]: Trace formula consists of 130 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 02:28:16,001 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:16,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:16,121 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:16,121 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:16,122 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1604199258] [2022-11-03 02:28:16,123 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1604199258] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:16,123 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:16,123 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:28:16,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1619932986] [2022-11-03 02:28:16,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:16,132 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:28:16,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:16,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:28:16,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:28:16,172 INFO L87 Difference]: Start difference. First operand has 165 states, 163 states have (on average 1.4969325153374233) internal successors, (244), 164 states have internal predecessors, (244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:16,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:16,430 INFO L93 Difference]: Finished difference Result 482 states and 723 transitions. [2022-11-03 02:28:16,431 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:28:16,433 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 02:28:16,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:16,443 INFO L225 Difference]: With dead ends: 482 [2022-11-03 02:28:16,444 INFO L226 Difference]: Without dead ends: 319 [2022-11-03 02:28:16,447 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:28:16,450 INFO L413 NwaCegarLoop]: 236 mSDtfsCounter, 465 mSDsluCounter, 470 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 465 SdHoareTripleChecker+Valid, 706 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:16,451 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [465 Valid, 706 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:28:16,470 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2022-11-03 02:28:16,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 163. [2022-11-03 02:28:16,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 162 states have (on average 1.4814814814814814) internal successors, (240), 162 states have internal predecessors, (240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:16,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 240 transitions. [2022-11-03 02:28:16,499 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 240 transitions. Word has length 5 [2022-11-03 02:28:16,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:16,499 INFO L495 AbstractCegarLoop]: Abstraction has 163 states and 240 transitions. [2022-11-03 02:28:16,500 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:16,500 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 240 transitions. [2022-11-03 02:28:16,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:16,505 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:16,506 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:16,524 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Ended with exit code 0 [2022-11-03 02:28:16,718 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:16,719 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:16,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:16,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1401986589, now seen corresponding path program 1 times [2022-11-03 02:28:16,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:16,722 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1343791903] [2022-11-03 02:28:16,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:16,723 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:16,723 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:16,724 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:16,728 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:28:17,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:17,931 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:17,944 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:18,546 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:18,546 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:18,546 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:18,547 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1343791903] [2022-11-03 02:28:18,547 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1343791903] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:18,547 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:18,547 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:18,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122843815] [2022-11-03 02:28:18,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:18,554 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:18,555 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:18,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:18,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:18,556 INFO L87 Difference]: Start difference. First operand 163 states and 240 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:18,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:18,805 INFO L93 Difference]: Finished difference Result 372 states and 551 transitions. [2022-11-03 02:28:18,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:18,806 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:18,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:18,808 INFO L225 Difference]: With dead ends: 372 [2022-11-03 02:28:18,808 INFO L226 Difference]: Without dead ends: 213 [2022-11-03 02:28:18,809 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:18,810 INFO L413 NwaCegarLoop]: 232 mSDtfsCounter, 94 mSDsluCounter, 777 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 94 SdHoareTripleChecker+Valid, 1009 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:18,811 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [94 Valid, 1009 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:28:18,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2022-11-03 02:28:18,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 213. [2022-11-03 02:28:18,828 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 212 states have (on average 1.4811320754716981) internal successors, (314), 212 states have internal predecessors, (314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:18,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 314 transitions. [2022-11-03 02:28:18,830 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 314 transitions. Word has length 162 [2022-11-03 02:28:18,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:18,835 INFO L495 AbstractCegarLoop]: Abstraction has 213 states and 314 transitions. [2022-11-03 02:28:18,835 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:18,835 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 314 transitions. [2022-11-03 02:28:18,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:18,838 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:18,838 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:18,872 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:19,059 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:19,060 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:19,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:19,060 INFO L85 PathProgramCache]: Analyzing trace with hash -363402015, now seen corresponding path program 1 times [2022-11-03 02:28:19,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:19,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1855987038] [2022-11-03 02:28:19,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:19,064 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:19,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:19,065 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:19,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:28:20,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:20,201 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:20,235 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:20,493 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:20,494 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:20,494 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:20,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1855987038] [2022-11-03 02:28:20,495 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1855987038] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:20,495 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:20,495 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:20,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561529597] [2022-11-03 02:28:20,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:20,496 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:20,496 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:20,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:20,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:20,497 INFO L87 Difference]: Start difference. First operand 213 states and 314 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:20,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:20,756 INFO L93 Difference]: Finished difference Result 704 states and 1043 transitions. [2022-11-03 02:28:20,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:20,757 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:20,757 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:20,759 INFO L225 Difference]: With dead ends: 704 [2022-11-03 02:28:20,760 INFO L226 Difference]: Without dead ends: 545 [2022-11-03 02:28:20,761 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:20,762 INFO L413 NwaCegarLoop]: 306 mSDtfsCounter, 799 mSDsluCounter, 1185 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 799 SdHoareTripleChecker+Valid, 1491 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:20,762 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [799 Valid, 1491 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 29 Invalid, 0 Unknown, 23 Unchecked, 0.2s Time] [2022-11-03 02:28:20,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2022-11-03 02:28:20,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 283. [2022-11-03 02:28:20,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 283 states, 282 states have (on average 1.4787234042553192) internal successors, (417), 282 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:20,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 283 states to 283 states and 417 transitions. [2022-11-03 02:28:20,778 INFO L78 Accepts]: Start accepts. Automaton has 283 states and 417 transitions. Word has length 162 [2022-11-03 02:28:20,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:20,779 INFO L495 AbstractCegarLoop]: Abstraction has 283 states and 417 transitions. [2022-11-03 02:28:20,779 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:20,779 INFO L276 IsEmpty]: Start isEmpty. Operand 283 states and 417 transitions. [2022-11-03 02:28:20,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:20,782 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:20,782 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:20,814 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:20,998 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:20,998 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:20,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:20,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1789704803, now seen corresponding path program 1 times [2022-11-03 02:28:21,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:21,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1044221765] [2022-11-03 02:28:21,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:21,002 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:21,002 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:21,004 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:21,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 02:28:21,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:22,022 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:22,031 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:22,258 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:22,258 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:22,258 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:22,258 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1044221765] [2022-11-03 02:28:22,258 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1044221765] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:22,258 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:22,259 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:22,259 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876048789] [2022-11-03 02:28:22,259 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:22,259 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:22,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:22,260 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:22,260 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:22,261 INFO L87 Difference]: Start difference. First operand 283 states and 417 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:22,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:22,441 INFO L93 Difference]: Finished difference Result 854 states and 1264 transitions. [2022-11-03 02:28:22,442 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:22,442 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:22,443 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:22,446 INFO L225 Difference]: With dead ends: 854 [2022-11-03 02:28:22,447 INFO L226 Difference]: Without dead ends: 695 [2022-11-03 02:28:22,451 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:22,453 INFO L413 NwaCegarLoop]: 315 mSDtfsCounter, 784 mSDsluCounter, 1305 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 784 SdHoareTripleChecker+Valid, 1620 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 41 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:22,456 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [784 Valid, 1620 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 21 Invalid, 0 Unknown, 41 Unchecked, 0.1s Time] [2022-11-03 02:28:22,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 695 states. [2022-11-03 02:28:22,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 695 to 439. [2022-11-03 02:28:22,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 439 states, 438 states have (on average 1.4771689497716896) internal successors, (647), 438 states have internal predecessors, (647), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:22,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 439 states to 439 states and 647 transitions. [2022-11-03 02:28:22,487 INFO L78 Accepts]: Start accepts. Automaton has 439 states and 647 transitions. Word has length 162 [2022-11-03 02:28:22,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:22,488 INFO L495 AbstractCegarLoop]: Abstraction has 439 states and 647 transitions. [2022-11-03 02:28:22,488 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:22,495 INFO L276 IsEmpty]: Start isEmpty. Operand 439 states and 647 transitions. [2022-11-03 02:28:22,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:22,499 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:22,499 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:22,520 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:22,703 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:22,704 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:22,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:22,705 INFO L85 PathProgramCache]: Analyzing trace with hash 482562405, now seen corresponding path program 1 times [2022-11-03 02:28:22,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:22,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1097131093] [2022-11-03 02:28:22,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:22,709 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:22,709 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:22,710 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:22,720 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 02:28:23,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:23,689 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:23,702 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:24,186 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:24,187 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:24,187 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:24,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1097131093] [2022-11-03 02:28:24,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1097131093] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:24,188 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:24,188 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:24,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880057832] [2022-11-03 02:28:24,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:24,189 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:24,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:24,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:24,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:24,190 INFO L87 Difference]: Start difference. First operand 439 states and 647 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:24,431 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:24,431 INFO L93 Difference]: Finished difference Result 842 states and 1242 transitions. [2022-11-03 02:28:24,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:24,433 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:24,433 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:24,435 INFO L225 Difference]: With dead ends: 842 [2022-11-03 02:28:24,435 INFO L226 Difference]: Without dead ends: 683 [2022-11-03 02:28:24,436 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:24,437 INFO L413 NwaCegarLoop]: 232 mSDtfsCounter, 109 mSDsluCounter, 1142 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 109 SdHoareTripleChecker+Valid, 1374 SdHoareTripleChecker+Invalid, 25 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:24,437 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [109 Valid, 1374 Invalid, 25 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 22 Unchecked, 0.2s Time] [2022-11-03 02:28:24,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 683 states. [2022-11-03 02:28:24,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 683 to 683. [2022-11-03 02:28:24,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 683 states, 682 states have (on average 1.4736070381231672) internal successors, (1005), 682 states have internal predecessors, (1005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:24,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 683 states to 683 states and 1005 transitions. [2022-11-03 02:28:24,453 INFO L78 Accepts]: Start accepts. Automaton has 683 states and 1005 transitions. Word has length 162 [2022-11-03 02:28:24,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:24,453 INFO L495 AbstractCegarLoop]: Abstraction has 683 states and 1005 transitions. [2022-11-03 02:28:24,454 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:24,454 INFO L276 IsEmpty]: Start isEmpty. Operand 683 states and 1005 transitions. [2022-11-03 02:28:24,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:24,457 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:24,457 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:24,488 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:24,671 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:24,672 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:24,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:24,672 INFO L85 PathProgramCache]: Analyzing trace with hash -1871822877, now seen corresponding path program 1 times [2022-11-03 02:28:24,674 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:24,674 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1260434805] [2022-11-03 02:28:24,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:24,675 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:24,675 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:24,676 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:24,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 02:28:25,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:25,682 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:25,691 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:25,950 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:25,951 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:25,951 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:25,951 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1260434805] [2022-11-03 02:28:25,951 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1260434805] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:25,951 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:25,952 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:25,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1838270595] [2022-11-03 02:28:25,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:25,952 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:25,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:25,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:25,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:25,954 INFO L87 Difference]: Start difference. First operand 683 states and 1005 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:26,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:26,269 INFO L93 Difference]: Finished difference Result 1132 states and 1669 transitions. [2022-11-03 02:28:26,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:26,270 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:26,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:26,274 INFO L225 Difference]: With dead ends: 1132 [2022-11-03 02:28:26,274 INFO L226 Difference]: Without dead ends: 973 [2022-11-03 02:28:26,275 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:26,276 INFO L413 NwaCegarLoop]: 348 mSDtfsCounter, 584 mSDsluCounter, 1776 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 584 SdHoareTripleChecker+Valid, 2124 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 44 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:26,277 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [584 Valid, 2124 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 44 Unchecked, 0.3s Time] [2022-11-03 02:28:26,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states. [2022-11-03 02:28:26,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 739. [2022-11-03 02:28:26,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 739 states, 738 states have (on average 1.470189701897019) internal successors, (1085), 738 states have internal predecessors, (1085), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:26,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 739 states to 739 states and 1085 transitions. [2022-11-03 02:28:26,294 INFO L78 Accepts]: Start accepts. Automaton has 739 states and 1085 transitions. Word has length 162 [2022-11-03 02:28:26,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:26,295 INFO L495 AbstractCegarLoop]: Abstraction has 739 states and 1085 transitions. [2022-11-03 02:28:26,295 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:26,295 INFO L276 IsEmpty]: Start isEmpty. Operand 739 states and 1085 transitions. [2022-11-03 02:28:26,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:26,298 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:26,298 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:26,320 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:26,506 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:26,507 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:26,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:26,508 INFO L85 PathProgramCache]: Analyzing trace with hash -1631583131, now seen corresponding path program 1 times [2022-11-03 02:28:26,509 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:26,509 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1725140462] [2022-11-03 02:28:26,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:26,509 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:26,509 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:26,510 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:26,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 02:28:27,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:27,448 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:27,458 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:27,971 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:27,971 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:27,971 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:27,971 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1725140462] [2022-11-03 02:28:27,971 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1725140462] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:27,972 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:27,972 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:27,972 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113248664] [2022-11-03 02:28:27,972 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:27,972 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:27,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:27,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:27,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:27,973 INFO L87 Difference]: Start difference. First operand 739 states and 1085 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:28,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:28,169 INFO L93 Difference]: Finished difference Result 1460 states and 2145 transitions. [2022-11-03 02:28:28,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:28,170 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:28,170 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:28,174 INFO L225 Difference]: With dead ends: 1460 [2022-11-03 02:28:28,174 INFO L226 Difference]: Without dead ends: 1301 [2022-11-03 02:28:28,175 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:28,176 INFO L413 NwaCegarLoop]: 231 mSDtfsCounter, 157 mSDsluCounter, 834 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 157 SdHoareTripleChecker+Valid, 1065 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:28,176 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [157 Valid, 1065 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:28:28,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1301 states. [2022-11-03 02:28:28,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1301 to 1301. [2022-11-03 02:28:28,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1301 states, 1300 states have (on average 1.4676923076923076) internal successors, (1908), 1300 states have internal predecessors, (1908), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:28,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1908 transitions. [2022-11-03 02:28:28,201 INFO L78 Accepts]: Start accepts. Automaton has 1301 states and 1908 transitions. Word has length 162 [2022-11-03 02:28:28,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:28,201 INFO L495 AbstractCegarLoop]: Abstraction has 1301 states and 1908 transitions. [2022-11-03 02:28:28,202 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:28,202 INFO L276 IsEmpty]: Start isEmpty. Operand 1301 states and 1908 transitions. [2022-11-03 02:28:28,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:28,206 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:28,206 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:28,232 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:28,425 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:28,425 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:28,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:28,426 INFO L85 PathProgramCache]: Analyzing trace with hash -1658648733, now seen corresponding path program 1 times [2022-11-03 02:28:28,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:28,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1413851288] [2022-11-03 02:28:28,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:28,428 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:28,428 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:28,429 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:28,455 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 02:28:29,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:29,362 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:29,371 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:29,629 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:29,630 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:29,630 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:29,630 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1413851288] [2022-11-03 02:28:29,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1413851288] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:29,630 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:29,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:29,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1575939347] [2022-11-03 02:28:29,631 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:29,631 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:29,631 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:29,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:29,632 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:29,632 INFO L87 Difference]: Start difference. First operand 1301 states and 1908 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:29,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:29,922 INFO L93 Difference]: Finished difference Result 1824 states and 2679 transitions. [2022-11-03 02:28:29,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:29,922 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:29,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:29,927 INFO L225 Difference]: With dead ends: 1824 [2022-11-03 02:28:29,928 INFO L226 Difference]: Without dead ends: 1665 [2022-11-03 02:28:29,929 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:29,932 INFO L413 NwaCegarLoop]: 357 mSDtfsCounter, 568 mSDsluCounter, 1836 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 568 SdHoareTripleChecker+Valid, 2193 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 40 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:29,932 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [568 Valid, 2193 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 40 Unchecked, 0.2s Time] [2022-11-03 02:28:29,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1665 states. [2022-11-03 02:28:29,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1665 to 1437. [2022-11-03 02:28:29,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1437 states, 1436 states have (on average 1.4651810584958218) internal successors, (2104), 1436 states have internal predecessors, (2104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:29,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1437 states to 1437 states and 2104 transitions. [2022-11-03 02:28:29,962 INFO L78 Accepts]: Start accepts. Automaton has 1437 states and 2104 transitions. Word has length 162 [2022-11-03 02:28:29,962 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:29,962 INFO L495 AbstractCegarLoop]: Abstraction has 1437 states and 2104 transitions. [2022-11-03 02:28:29,962 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:29,963 INFO L276 IsEmpty]: Start isEmpty. Operand 1437 states and 2104 transitions. [2022-11-03 02:28:29,966 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:29,970 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:29,970 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:30,003 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:30,187 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:30,187 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:30,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:30,188 INFO L85 PathProgramCache]: Analyzing trace with hash 725276005, now seen corresponding path program 1 times [2022-11-03 02:28:30,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:30,190 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1615240480] [2022-11-03 02:28:30,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:30,190 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:30,190 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:30,192 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:30,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Waiting until timeout for monitored process [2022-11-03 02:28:31,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:31,132 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:31,140 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:31,844 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:31,845 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:31,845 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:31,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1615240480] [2022-11-03 02:28:31,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1615240480] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:31,845 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:31,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:31,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607748590] [2022-11-03 02:28:31,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:31,846 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:31,847 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:31,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:31,847 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:31,848 INFO L87 Difference]: Start difference. First operand 1437 states and 2104 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:32,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:32,051 INFO L93 Difference]: Finished difference Result 2944 states and 4315 transitions. [2022-11-03 02:28:32,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:32,052 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:32,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:32,061 INFO L225 Difference]: With dead ends: 2944 [2022-11-03 02:28:32,061 INFO L226 Difference]: Without dead ends: 2785 [2022-11-03 02:28:32,062 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:32,063 INFO L413 NwaCegarLoop]: 230 mSDtfsCounter, 192 mSDsluCounter, 827 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 1057 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:32,064 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 1057 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:28:32,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2785 states. [2022-11-03 02:28:32,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2785 to 2785. [2022-11-03 02:28:32,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2785 states, 2784 states have (on average 1.4647988505747127) internal successors, (4078), 2784 states have internal predecessors, (4078), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:32,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2785 states to 2785 states and 4078 transitions. [2022-11-03 02:28:32,137 INFO L78 Accepts]: Start accepts. Automaton has 2785 states and 4078 transitions. Word has length 162 [2022-11-03 02:28:32,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:32,137 INFO L495 AbstractCegarLoop]: Abstraction has 2785 states and 4078 transitions. [2022-11-03 02:28:32,138 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:32,138 INFO L276 IsEmpty]: Start isEmpty. Operand 2785 states and 4078 transitions. [2022-11-03 02:28:32,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:32,146 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:32,146 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:32,171 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:32,359 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:32,360 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:32,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:32,365 INFO L85 PathProgramCache]: Analyzing trace with hash 164576227, now seen corresponding path program 1 times [2022-11-03 02:28:32,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:32,368 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1751410378] [2022-11-03 02:28:32,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:32,368 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:32,368 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:32,369 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:32,409 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-03 02:28:33,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:33,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:33,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:33,725 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:33,725 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:33,726 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:33,726 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1751410378] [2022-11-03 02:28:33,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1751410378] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:33,726 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:33,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:33,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237066064] [2022-11-03 02:28:33,726 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:33,727 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:33,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:33,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:33,727 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:33,728 INFO L87 Difference]: Start difference. First operand 2785 states and 4078 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:34,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:34,027 INFO L93 Difference]: Finished difference Result 3218 states and 4714 transitions. [2022-11-03 02:28:34,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:34,030 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:34,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:34,039 INFO L225 Difference]: With dead ends: 3218 [2022-11-03 02:28:34,039 INFO L226 Difference]: Without dead ends: 3059 [2022-11-03 02:28:34,041 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:34,042 INFO L413 NwaCegarLoop]: 390 mSDtfsCounter, 541 mSDsluCounter, 1696 mSDsCounter, 0 mSdLazyCounter, 35 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 541 SdHoareTripleChecker+Valid, 2086 SdHoareTripleChecker+Invalid, 59 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 35 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:34,042 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [541 Valid, 2086 Invalid, 59 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 35 Invalid, 0 Unknown, 23 Unchecked, 0.2s Time] [2022-11-03 02:28:34,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3059 states. [2022-11-03 02:28:34,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3059 to 2853. [2022-11-03 02:28:34,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2853 states, 2852 states have (on average 1.4628330995792427) internal successors, (4172), 2852 states have internal predecessors, (4172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:34,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2853 states to 2853 states and 4172 transitions. [2022-11-03 02:28:34,140 INFO L78 Accepts]: Start accepts. Automaton has 2853 states and 4172 transitions. Word has length 162 [2022-11-03 02:28:34,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:34,140 INFO L495 AbstractCegarLoop]: Abstraction has 2853 states and 4172 transitions. [2022-11-03 02:28:34,140 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:34,141 INFO L276 IsEmpty]: Start isEmpty. Operand 2853 states and 4172 transitions. [2022-11-03 02:28:34,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:34,147 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:34,147 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:34,183 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:34,372 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:34,373 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:34,373 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:34,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1864009883, now seen corresponding path program 1 times [2022-11-03 02:28:34,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:34,375 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1339298993] [2022-11-03 02:28:34,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:34,376 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:34,376 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:34,377 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:34,391 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 02:28:35,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:35,399 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:35,407 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:36,280 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:36,280 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:36,280 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:36,281 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1339298993] [2022-11-03 02:28:36,281 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1339298993] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:36,281 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:36,281 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:36,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [367955822] [2022-11-03 02:28:36,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:36,282 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:36,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:36,282 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:36,283 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:36,283 INFO L87 Difference]: Start difference. First operand 2853 states and 4172 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:36,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:36,567 INFO L93 Difference]: Finished difference Result 5780 states and 8457 transitions. [2022-11-03 02:28:36,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:36,569 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:36,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:36,584 INFO L225 Difference]: With dead ends: 5780 [2022-11-03 02:28:36,584 INFO L226 Difference]: Without dead ends: 5621 [2022-11-03 02:28:36,585 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:36,586 INFO L413 NwaCegarLoop]: 229 mSDtfsCounter, 255 mSDsluCounter, 885 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 255 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:36,587 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [255 Valid, 1114 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:28:36,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5621 states. [2022-11-03 02:28:36,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5621 to 5621. [2022-11-03 02:28:36,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5621 states, 5620 states have (on average 1.4626334519572954) internal successors, (8220), 5620 states have internal predecessors, (8220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:36,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5621 states to 5621 states and 8220 transitions. [2022-11-03 02:28:36,686 INFO L78 Accepts]: Start accepts. Automaton has 5621 states and 8220 transitions. Word has length 162 [2022-11-03 02:28:36,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:36,687 INFO L495 AbstractCegarLoop]: Abstraction has 5621 states and 8220 transitions. [2022-11-03 02:28:36,687 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:36,687 INFO L276 IsEmpty]: Start isEmpty. Operand 5621 states and 8220 transitions. [2022-11-03 02:28:36,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:36,699 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:36,700 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:36,732 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:36,923 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:36,923 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:36,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:36,924 INFO L85 PathProgramCache]: Analyzing trace with hash 507729379, now seen corresponding path program 1 times [2022-11-03 02:28:36,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:36,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [86733285] [2022-11-03 02:28:36,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:36,925 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:36,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:36,926 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:36,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 02:28:37,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:37,812 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:37,818 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:38,230 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:38,230 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:38,230 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:38,230 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [86733285] [2022-11-03 02:28:38,231 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [86733285] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:38,231 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:38,231 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:38,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2128366781] [2022-11-03 02:28:38,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:38,232 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:38,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:38,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:38,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:38,233 INFO L87 Difference]: Start difference. First operand 5621 states and 8220 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:38,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:38,540 INFO L93 Difference]: Finished difference Result 6010 states and 8796 transitions. [2022-11-03 02:28:38,540 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:38,541 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:38,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:38,559 INFO L225 Difference]: With dead ends: 6010 [2022-11-03 02:28:38,560 INFO L226 Difference]: Without dead ends: 5851 [2022-11-03 02:28:38,562 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:38,563 INFO L413 NwaCegarLoop]: 432 mSDtfsCounter, 498 mSDsluCounter, 1736 mSDsCounter, 0 mSdLazyCounter, 36 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 498 SdHoareTripleChecker+Valid, 2168 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 36 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:38,563 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [498 Valid, 2168 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 36 Invalid, 0 Unknown, 24 Unchecked, 0.2s Time] [2022-11-03 02:28:38,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5851 states. [2022-11-03 02:28:38,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5851 to 5673. [2022-11-03 02:28:38,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5673 states, 5672 states have (on average 1.46262341325811) internal successors, (8296), 5672 states have internal predecessors, (8296), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:38,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5673 states to 5673 states and 8296 transitions. [2022-11-03 02:28:38,714 INFO L78 Accepts]: Start accepts. Automaton has 5673 states and 8296 transitions. Word has length 162 [2022-11-03 02:28:38,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:38,715 INFO L495 AbstractCegarLoop]: Abstraction has 5673 states and 8296 transitions. [2022-11-03 02:28:38,716 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:38,716 INFO L276 IsEmpty]: Start isEmpty. Operand 5673 states and 8296 transitions. [2022-11-03 02:28:38,727 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:38,728 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:38,728 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:38,756 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:38,952 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:38,952 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:38,953 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:38,953 INFO L85 PathProgramCache]: Analyzing trace with hash -1297708955, now seen corresponding path program 1 times [2022-11-03 02:28:38,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:38,955 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1771469628] [2022-11-03 02:28:38,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:38,955 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:38,955 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:38,957 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:38,963 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 02:28:39,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:39,951 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:39,958 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:40,329 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:40,329 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:40,330 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:40,331 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1771469628] [2022-11-03 02:28:40,331 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1771469628] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:40,331 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:40,331 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:40,331 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1871891892] [2022-11-03 02:28:40,331 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:40,332 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:40,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:40,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:40,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:40,333 INFO L87 Difference]: Start difference. First operand 5673 states and 8296 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:40,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:40,628 INFO L93 Difference]: Finished difference Result 6258 states and 9158 transitions. [2022-11-03 02:28:40,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:28:40,628 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:40,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:40,647 INFO L225 Difference]: With dead ends: 6258 [2022-11-03 02:28:40,647 INFO L226 Difference]: Without dead ends: 6099 [2022-11-03 02:28:40,650 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:28:40,651 INFO L413 NwaCegarLoop]: 441 mSDtfsCounter, 570 mSDsluCounter, 1550 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 570 SdHoareTripleChecker+Valid, 1991 SdHoareTripleChecker+Invalid, 69 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 39 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:40,651 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [570 Valid, 1991 Invalid, 69 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 29 Invalid, 0 Unknown, 39 Unchecked, 0.2s Time] [2022-11-03 02:28:40,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6099 states. [2022-11-03 02:28:40,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6099 to 5927. [2022-11-03 02:28:40,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5927 states, 5926 states have (on average 1.4625379682753965) internal successors, (8667), 5926 states have internal predecessors, (8667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:40,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5927 states to 5927 states and 8667 transitions. [2022-11-03 02:28:40,755 INFO L78 Accepts]: Start accepts. Automaton has 5927 states and 8667 transitions. Word has length 162 [2022-11-03 02:28:40,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:40,755 INFO L495 AbstractCegarLoop]: Abstraction has 5927 states and 8667 transitions. [2022-11-03 02:28:40,755 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:40,756 INFO L276 IsEmpty]: Start isEmpty. Operand 5927 states and 8667 transitions. [2022-11-03 02:28:40,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:40,799 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:40,799 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:40,832 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:41,009 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:41,009 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:41,010 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:41,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1408910439, now seen corresponding path program 1 times [2022-11-03 02:28:41,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:41,012 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [252932858] [2022-11-03 02:28:41,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:41,012 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:41,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:41,014 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:41,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 02:28:41,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:42,011 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:28:42,018 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:42,966 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:42,967 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:42,967 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:42,967 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [252932858] [2022-11-03 02:28:42,967 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [252932858] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:42,967 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:42,967 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:28:42,967 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841335169] [2022-11-03 02:28:42,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:42,968 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:28:42,968 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:42,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:28:42,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:28:42,969 INFO L87 Difference]: Start difference. First operand 5927 states and 8667 transitions. Second operand has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:43,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:43,283 INFO L93 Difference]: Finished difference Result 11926 states and 17444 transitions. [2022-11-03 02:28:43,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:28:43,284 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:43,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:43,305 INFO L225 Difference]: With dead ends: 11926 [2022-11-03 02:28:43,306 INFO L226 Difference]: Without dead ends: 11767 [2022-11-03 02:28:43,311 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 156 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:43,311 INFO L413 NwaCegarLoop]: 229 mSDtfsCounter, 283 mSDsluCounter, 909 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 283 SdHoareTripleChecker+Valid, 1138 SdHoareTripleChecker+Invalid, 19 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:43,312 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [283 Valid, 1138 Invalid, 19 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:28:43,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11767 states. [2022-11-03 02:28:43,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11767 to 11767. [2022-11-03 02:28:43,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11767 states, 11766 states have (on average 1.462434132245453) internal successors, (17207), 11766 states have internal predecessors, (17207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:43,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11767 states to 11767 states and 17207 transitions. [2022-11-03 02:28:43,542 INFO L78 Accepts]: Start accepts. Automaton has 11767 states and 17207 transitions. Word has length 162 [2022-11-03 02:28:43,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:43,543 INFO L495 AbstractCegarLoop]: Abstraction has 11767 states and 17207 transitions. [2022-11-03 02:28:43,543 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 23.142857142857142) internal successors, (162), 7 states have internal predecessors, (162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:43,543 INFO L276 IsEmpty]: Start isEmpty. Operand 11767 states and 17207 transitions. [2022-11-03 02:28:43,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:43,568 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:43,569 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:43,601 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:43,791 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:43,791 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:43,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:43,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1995716453, now seen corresponding path program 1 times [2022-11-03 02:28:43,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:43,794 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2121405477] [2022-11-03 02:28:43,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:43,794 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:43,794 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:43,796 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:43,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 02:28:44,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:44,782 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 02:28:44,791 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:47,548 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:47,548 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:50,984 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:50,985 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:50,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2121405477] [2022-11-03 02:28:50,985 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2121405477] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:50,985 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [97562912] [2022-11-03 02:28:50,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:50,985 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:28:50,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:28:50,987 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:28:50,989 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2022-11-03 02:28:52,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:52,827 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 02:28:52,835 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:55,291 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:55,291 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:29:44,565 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:44,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [97562912] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:29:44,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [623921736] [2022-11-03 02:29:44,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:29:44,565 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:29:44,565 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:29:44,567 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:29:44,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-03 02:29:45,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:29:45,335 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 02:29:45,344 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:29:48,158 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:48,159 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:30:07,530 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:30:07,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [623921736] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:30:07,530 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:30:07,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 11, 11] total 37 [2022-11-03 02:30:07,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335043364] [2022-11-03 02:30:07,531 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:30:07,532 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-11-03 02:30:07,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:30:07,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-03 02:30:07,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=215, Invalid=1091, Unknown=26, NotChecked=0, Total=1332 [2022-11-03 02:30:07,534 INFO L87 Difference]: Start difference. First operand 11767 states and 17207 transitions. Second operand has 37 states, 37 states have (on average 21.486486486486488) internal successors, (795), 37 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:30:08,539 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:30:08,539 INFO L93 Difference]: Finished difference Result 19242 states and 27978 transitions. [2022-11-03 02:30:08,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-03 02:30:08,540 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 21.486486486486488) internal successors, (795), 37 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:30:08,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:30:08,564 INFO L225 Difference]: With dead ends: 19242 [2022-11-03 02:30:08,564 INFO L226 Difference]: Without dead ends: 19240 [2022-11-03 02:30:08,570 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 977 GetRequests, 929 SyntacticMatches, 4 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 645 ImplicationChecksByTransitivity, 68.2s TimeCoverageRelationStatistics Valid=404, Invalid=1640, Unknown=26, NotChecked=0, Total=2070 [2022-11-03 02:30:08,571 INFO L413 NwaCegarLoop]: 226 mSDtfsCounter, 1860 mSDsluCounter, 5450 mSDsCounter, 0 mSdLazyCounter, 5 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1860 SdHoareTripleChecker+Valid, 5676 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 5 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 34 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:30:08,571 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1860 Valid, 5676 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 5 Invalid, 0 Unknown, 34 Unchecked, 0.0s Time] [2022-11-03 02:30:08,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19240 states. [2022-11-03 02:30:08,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19240 to 19240. [2022-11-03 02:30:08,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19240 states, 19239 states have (on average 1.4541296325172826) internal successors, (27976), 19239 states have internal predecessors, (27976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:30:08,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19240 states to 19240 states and 27976 transitions. [2022-11-03 02:30:08,835 INFO L78 Accepts]: Start accepts. Automaton has 19240 states and 27976 transitions. Word has length 162 [2022-11-03 02:30:08,836 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:30:08,836 INFO L495 AbstractCegarLoop]: Abstraction has 19240 states and 27976 transitions. [2022-11-03 02:30:08,836 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 21.486486486486488) internal successors, (795), 37 states have internal predecessors, (795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:30:08,837 INFO L276 IsEmpty]: Start isEmpty. Operand 19240 states and 27976 transitions. [2022-11-03 02:30:08,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:30:08,863 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:30:08,864 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:30:08,890 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Forceful destruction successful, exit code 0 [2022-11-03 02:30:09,090 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Forceful destruction successful, exit code 0 [2022-11-03 02:30:09,325 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-03 02:30:09,478 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:30:09,479 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:30:09,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:30:09,479 INFO L85 PathProgramCache]: Analyzing trace with hash 273713767, now seen corresponding path program 1 times [2022-11-03 02:30:09,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:30:09,481 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1910262076] [2022-11-03 02:30:09,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:30:09,481 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:30:09,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:30:09,482 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:30:09,484 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-03 02:30:10,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:30:10,295 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 02:30:10,300 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:30:12,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:30:12,841 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:30:16,373 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:30:16,373 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:30:16,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1910262076] [2022-11-03 02:30:16,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1910262076] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:30:16,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1944145070] [2022-11-03 02:30:16,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:30:16,374 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:30:16,374 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:30:16,375 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:30:16,377 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Waiting until timeout for monitored process [2022-11-03 02:30:17,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:30:17,982 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 02:30:17,988 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:30:20,213 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:30:20,213 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:31:15,991 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:31:15,992 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1944145070] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:31:15,992 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2497836] [2022-11-03 02:31:15,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:15,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:31:15,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:31:15,994 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:31:15,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-03 02:31:16,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:16,721 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 02:31:16,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:19,179 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:31:19,179 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:33:17,694 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:33:17,694 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2497836] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:33:17,695 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:33:17,695 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 11, 11] total 32 [2022-11-03 02:33:17,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1262081293] [2022-11-03 02:33:17,696 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:33:17,697 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-11-03 02:33:17,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:33:17,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-11-03 02:33:17,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=736, Unknown=73, NotChecked=0, Total=992 [2022-11-03 02:33:17,698 INFO L87 Difference]: Start difference. First operand 19240 states and 27976 transitions. Second operand has 32 states, 32 states have (on average 20.0) internal successors, (640), 32 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:33:17,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:33:17,931 INFO L93 Difference]: Finished difference Result 25695 states and 37217 transitions. [2022-11-03 02:33:17,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:33:17,932 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 20.0) internal successors, (640), 32 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:33:17,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:33:17,983 INFO L225 Difference]: With dead ends: 25695 [2022-11-03 02:33:17,983 INFO L226 Difference]: Without dead ends: 25693 [2022-11-03 02:33:17,992 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 967 GetRequests, 932 SyntacticMatches, 4 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 383 ImplicationChecksByTransitivity, 173.0s TimeCoverageRelationStatistics Valid=197, Invalid=786, Unknown=73, NotChecked=0, Total=1056 [2022-11-03 02:33:17,993 INFO L413 NwaCegarLoop]: 229 mSDtfsCounter, 1855 mSDsluCounter, 4214 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1855 SdHoareTripleChecker+Valid, 4443 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 36 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:33:17,994 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1855 Valid, 4443 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 4 Invalid, 0 Unknown, 36 Unchecked, 0.0s Time] [2022-11-03 02:33:18,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25693 states. [2022-11-03 02:33:18,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25693 to 19240. [2022-11-03 02:33:18,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19240 states, 19239 states have (on average 1.4541296325172826) internal successors, (27976), 19239 states have internal predecessors, (27976), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:33:18,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19240 states to 19240 states and 27976 transitions. [2022-11-03 02:33:18,406 INFO L78 Accepts]: Start accepts. Automaton has 19240 states and 27976 transitions. Word has length 162 [2022-11-03 02:33:18,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:33:18,407 INFO L495 AbstractCegarLoop]: Abstraction has 19240 states and 27976 transitions. [2022-11-03 02:33:18,407 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 20.0) internal successors, (640), 32 states have internal predecessors, (640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:33:18,407 INFO L276 IsEmpty]: Start isEmpty. Operand 19240 states and 27976 transitions. [2022-11-03 02:33:18,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:33:18,437 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:33:18,438 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:33:18,469 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-03 02:33:18,670 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Forceful destruction successful, exit code 0 [2022-11-03 02:33:18,879 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-11-03 02:33:19,051 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:33:19,052 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:33:19,052 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:33:19,053 INFO L85 PathProgramCache]: Analyzing trace with hash 713544167, now seen corresponding path program 1 times [2022-11-03 02:33:19,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:33:19,054 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [471292076] [2022-11-03 02:33:19,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:33:19,054 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:33:19,055 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:33:19,055 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:33:19,058 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Waiting until timeout for monitored process [2022-11-03 02:33:19,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:33:19,876 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-03 02:33:19,881 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:33:22,591 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:33:22,591 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:33:29,706 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:33:29,706 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:33:29,706 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [471292076] [2022-11-03 02:33:29,707 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [471292076] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:33:29,707 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1936521935] [2022-11-03 02:33:29,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:33:29,707 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:33:29,707 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:33:29,710 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:33:29,711 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (23)] Waiting until timeout for monitored process [2022-11-03 02:33:31,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:33:31,396 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 36 conjunts are in the unsatisfiable core [2022-11-03 02:33:31,402 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:33:33,695 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:33:33,695 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:34:32,142 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:34:32,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1936521935] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:34:32,143 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1811875173] [2022-11-03 02:34:32,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:34:32,143 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:34:32,143 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:34:32,144 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:34:32,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_5307e330-e7f0-4db6-8796-171fcfae6b25/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-03 02:34:32,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:34:32,866 INFO L263 TraceCheckSpWp]: Trace formula consists of 1836 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 02:34:32,872 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:34:35,971 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:34:35,972 INFO L328 TraceCheckSpWp]: Computing backward predicates...