./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 4a0901411443e2369cdef97e7f5c792ca60bb368bf9c988b6ac394cdcdf4c250 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:24:35,465 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:24:35,467 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:24:35,494 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:24:35,494 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:24:35,495 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:24:35,497 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:24:35,498 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:24:35,500 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:24:35,501 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:24:35,502 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:24:35,503 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:24:35,503 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:24:35,508 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:24:35,509 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:24:35,510 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:24:35,511 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:24:35,515 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:24:35,516 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:24:35,518 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:24:35,520 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:24:35,525 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:24:35,527 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:24:35,527 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:24:35,531 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:24:35,532 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:24:35,532 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:24:35,533 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:24:35,533 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:24:35,534 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:24:35,542 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:24:35,543 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:24:35,546 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:24:35,547 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:24:35,548 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:24:35,549 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:24:35,549 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:24:35,550 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:24:35,550 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:24:35,551 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:24:35,552 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:24:35,552 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:24:35,604 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:24:35,604 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:24:35,605 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:24:35,605 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:24:35,606 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:24:35,606 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:24:35,606 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:24:35,606 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:24:35,607 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:24:35,607 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:24:35,608 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:24:35,608 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:24:35,608 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:24:35,608 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:24:35,609 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:24:35,609 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:24:35,609 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:24:35,609 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:24:35,610 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:24:35,610 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:24:35,610 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:24:35,611 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:24:35,611 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:24:35,612 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:24:35,613 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:24:35,613 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:24:35,613 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:24:35,613 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:24:35,613 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:24:35,614 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:24:35,614 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:24:35,614 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:24:35,614 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:24:35,615 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:24:35,615 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:24:35,615 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:24:35,615 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:24:35,616 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:24:35,616 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4a0901411443e2369cdef97e7f5c792ca60bb368bf9c988b6ac394cdcdf4c250 [2022-11-03 02:24:35,902 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:24:35,939 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:24:35,942 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:24:35,943 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:24:35,944 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:24:35,945 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:36,013 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/354334e74/0e8e4d4a4a7e49efb29a5c567c13a9e7/FLAGb4eaa6a03 [2022-11-03 02:24:36,478 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:24:36,478 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:36,505 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/354334e74/0e8e4d4a4a7e49efb29a5c567c13a9e7/FLAGb4eaa6a03 [2022-11-03 02:24:36,809 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/354334e74/0e8e4d4a4a7e49efb29a5c567c13a9e7 [2022-11-03 02:24:36,812 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:24:36,813 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:24:36,816 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:24:36,816 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:24:36,819 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:24:36,821 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:24:36" (1/1) ... [2022-11-03 02:24:36,823 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46bd391e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:36, skipping insertion in model container [2022-11-03 02:24:36,823 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:24:36" (1/1) ... [2022-11-03 02:24:36,831 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:24:36,880 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:24:37,068 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c[1107,1120] [2022-11-03 02:24:37,161 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:24:37,164 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:24:37,175 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c[1107,1120] [2022-11-03 02:24:37,228 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:24:37,239 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:24:37,240 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37 WrapperNode [2022-11-03 02:24:37,240 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:24:37,241 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:24:37,241 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:24:37,241 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:24:37,254 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,262 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,322 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 419 [2022-11-03 02:24:37,322 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:24:37,323 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:24:37,323 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:24:37,323 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:24:37,332 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,332 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,341 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,342 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,355 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,361 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,366 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,372 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,384 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:24:37,399 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:24:37,399 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:24:37,400 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:24:37,401 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (1/1) ... [2022-11-03 02:24:37,407 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:24:37,419 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:24:37,431 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:24:37,446 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:24:37,483 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:24:37,483 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:24:37,647 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:24:37,649 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:24:38,264 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:24:38,822 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:24:38,822 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:24:38,824 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:38 BoogieIcfgContainer [2022-11-03 02:24:38,825 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:24:38,828 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:24:38,828 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:24:38,832 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:24:38,832 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:24:36" (1/3) ... [2022-11-03 02:24:38,833 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6fa8b8c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:24:38, skipping insertion in model container [2022-11-03 02:24:38,833 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:37" (2/3) ... [2022-11-03 02:24:38,834 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6fa8b8c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:24:38, skipping insertion in model container [2022-11-03 02:24:38,834 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:38" (3/3) ... [2022-11-03 02:24:38,837 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:38,859 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:24:38,859 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:24:38,916 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:24:38,923 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@610c1083, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:24:38,923 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:24:38,927 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:38,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:24:38,933 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:38,934 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:24:38,935 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:38,939 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:38,940 INFO L85 PathProgramCache]: Analyzing trace with hash 7062294, now seen corresponding path program 1 times [2022-11-03 02:24:38,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:24:38,948 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [55420283] [2022-11-03 02:24:38,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:38,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:24:39,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:24:39,375 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:24:39,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:24:39,643 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:24:39,645 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:24:39,646 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:24:39,649 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:24:39,653 INFO L444 BasicCegarLoop]: Path program histogram: [1] [2022-11-03 02:24:39,657 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:24:39,694 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:24:39,711 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:24:39 BoogieIcfgContainer [2022-11-03 02:24:39,712 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:24:39,714 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:24:39,714 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:24:39,714 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:24:39,715 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:38" (3/4) ... [2022-11-03 02:24:39,719 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:24:39,719 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:24:39,721 INFO L158 Benchmark]: Toolchain (without parser) took 2907.80ms. Allocated memory was 98.6MB in the beginning and 148.9MB in the end (delta: 50.3MB). Free memory was 60.6MB in the beginning and 97.0MB in the end (delta: -36.4MB). Peak memory consumption was 14.4MB. Max. memory is 16.1GB. [2022-11-03 02:24:39,722 INFO L158 Benchmark]: CDTParser took 0.22ms. Allocated memory is still 98.6MB. Free memory was 71.1MB in the beginning and 71.1MB in the end (delta: 25.6kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:24:39,723 INFO L158 Benchmark]: CACSL2BoogieTranslator took 424.43ms. Allocated memory is still 98.6MB. Free memory was 60.4MB in the beginning and 64.9MB in the end (delta: -4.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-03 02:24:39,724 INFO L158 Benchmark]: Boogie Procedure Inliner took 81.31ms. Allocated memory is still 98.6MB. Free memory was 64.9MB in the beginning and 59.8MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2022-11-03 02:24:39,730 INFO L158 Benchmark]: Boogie Preprocessor took 75.44ms. Allocated memory is still 98.6MB. Free memory was 59.8MB in the beginning and 56.9MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:24:39,730 INFO L158 Benchmark]: RCFGBuilder took 1425.84ms. Allocated memory was 98.6MB in the beginning and 119.5MB in the end (delta: 21.0MB). Free memory was 56.5MB in the beginning and 68.6MB in the end (delta: -12.1MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. [2022-11-03 02:24:39,732 INFO L158 Benchmark]: TraceAbstraction took 884.04ms. Allocated memory was 119.5MB in the beginning and 148.9MB in the end (delta: 29.4MB). Free memory was 67.8MB in the beginning and 97.0MB in the end (delta: -29.3MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:24:39,732 INFO L158 Benchmark]: Witness Printer took 6.14ms. Allocated memory is still 148.9MB. Free memory is still 97.0MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:24:39,740 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22ms. Allocated memory is still 98.6MB. Free memory was 71.1MB in the beginning and 71.1MB in the end (delta: 25.6kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 424.43ms. Allocated memory is still 98.6MB. Free memory was 60.4MB in the beginning and 64.9MB in the end (delta: -4.5MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 81.31ms. Allocated memory is still 98.6MB. Free memory was 64.9MB in the beginning and 59.8MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 75.44ms. Allocated memory is still 98.6MB. Free memory was 59.8MB in the beginning and 56.9MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1425.84ms. Allocated memory was 98.6MB in the beginning and 119.5MB in the end (delta: 21.0MB). Free memory was 56.5MB in the beginning and 68.6MB in the end (delta: -12.1MB). Peak memory consumption was 36.1MB. Max. memory is 16.1GB. * TraceAbstraction took 884.04ms. Allocated memory was 119.5MB in the beginning and 148.9MB in the end (delta: 29.4MB). Free memory was 67.8MB in the beginning and 97.0MB in the end (delta: -29.3MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 6.14ms. Allocated memory is still 148.9MB. Free memory is still 97.0MB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 151, overapproximation of bitwiseAnd at line 116. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 8); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (8 - 1); [L28] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 1); [L29] const SORT_5 msb_SORT_5 = (SORT_5)1 << (1 - 1); [L31] const SORT_1 var_9 = 0; [L32] const SORT_5 var_22 = 0; [L33] const SORT_5 var_31 = 1; [L34] const SORT_1 var_109 = 1; [L36] SORT_1 input_2; [L37] SORT_1 input_3; [L38] SORT_1 input_4; [L39] SORT_5 input_6; [L40] SORT_5 input_7; [L41] SORT_5 input_8; [L42] SORT_5 input_35; [L43] SORT_5 input_37; [L44] SORT_5 input_39; [L45] SORT_5 input_51; [L47] SORT_1 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L48] SORT_1 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L49] SORT_1 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L50] SORT_5 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L51] SORT_1 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L52] SORT_5 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L53] SORT_5 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L54] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L55] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L56] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L57] SORT_5 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L58] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L59] SORT_5 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L60] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L61] SORT_1 state_62 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L62] SORT_1 state_64 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L63] SORT_1 state_66 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L64] SORT_1 state_68 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L65] SORT_1 state_70 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L66] SORT_1 state_72 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L68] SORT_1 init_11_arg_1 = var_9; [L69] state_10 = init_11_arg_1 [L70] SORT_1 init_13_arg_1 = var_9; [L71] state_12 = init_13_arg_1 [L72] SORT_1 init_19_arg_1 = var_9; [L73] state_18 = init_19_arg_1 [L74] SORT_5 init_24_arg_1 = var_22; [L75] state_23 = init_24_arg_1 [L76] SORT_1 init_27_arg_1 = var_9; [L77] state_26 = init_27_arg_1 [L78] SORT_5 init_42_arg_1 = var_22; [L79] state_41 = init_42_arg_1 [L80] SORT_5 init_44_arg_1 = var_22; [L81] state_43 = init_44_arg_1 [L82] SORT_1 init_46_arg_1 = var_9; [L83] state_45 = init_46_arg_1 [L84] SORT_1 init_48_arg_1 = var_9; [L85] state_47 = init_48_arg_1 [L86] SORT_1 init_50_arg_1 = var_9; [L87] state_49 = init_50_arg_1 [L88] SORT_5 init_54_arg_1 = var_22; [L89] state_53 = init_54_arg_1 [L90] SORT_1 init_56_arg_1 = var_9; [L91] state_55 = init_56_arg_1 [L92] SORT_5 init_58_arg_1 = var_22; [L93] state_57 = init_58_arg_1 [L94] SORT_1 init_60_arg_1 = var_9; [L95] state_59 = init_60_arg_1 [L96] SORT_1 init_63_arg_1 = var_9; [L97] state_62 = init_63_arg_1 [L98] SORT_1 init_65_arg_1 = var_9; [L99] state_64 = init_65_arg_1 [L100] SORT_1 init_67_arg_1 = var_9; [L101] state_66 = init_67_arg_1 [L102] SORT_1 init_69_arg_1 = var_9; [L103] state_68 = init_69_arg_1 [L104] SORT_1 init_71_arg_1 = var_9; [L105] state_70 = init_71_arg_1 [L106] SORT_1 init_73_arg_1 = var_9; [L107] state_72 = init_73_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_22=0, var_31=1, var_9=0] [L110] input_2 = __VERIFIER_nondet_uchar() [L111] input_3 = __VERIFIER_nondet_uchar() [L112] input_4 = __VERIFIER_nondet_uchar() [L113] input_6 = __VERIFIER_nondet_uchar() [L114] input_7 = __VERIFIER_nondet_uchar() [L115] input_8 = __VERIFIER_nondet_uchar() [L116] input_8 = input_8 & mask_SORT_5 [L117] input_35 = __VERIFIER_nondet_uchar() [L118] input_37 = __VERIFIER_nondet_uchar() [L119] input_39 = __VERIFIER_nondet_uchar() [L120] input_51 = __VERIFIER_nondet_uchar() [L123] SORT_1 var_16_arg_0 = state_10; [L124] SORT_5 var_16 = var_16_arg_0 >> 0; [L125] var_16 = var_16 & mask_SORT_5 [L126] SORT_1 var_15_arg_0 = state_10; [L127] SORT_1 var_15_arg_1 = state_12; [L128] SORT_1 var_15 = var_15_arg_0 + var_15_arg_1; [L129] SORT_1 var_14_arg_0 = state_10; [L130] SORT_1 var_14_arg_1 = state_12; [L131] SORT_1 var_14 = var_14_arg_0 - var_14_arg_1; [L132] SORT_5 var_17_arg_0 = var_16; [L133] SORT_1 var_17_arg_1 = var_15; [L134] SORT_1 var_17_arg_2 = var_14; [L135] EXPR var_17_arg_0 ? var_17_arg_1 : var_17_arg_2 [L135] SORT_1 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L136] SORT_1 var_21_arg_0 = var_17; [L137] SORT_1 var_21_arg_1 = state_18; [L138] SORT_1 var_21 = var_21_arg_0 + var_21_arg_1; [L139] SORT_1 var_20_arg_0 = var_17; [L140] SORT_1 var_20_arg_1 = state_18; [L141] SORT_1 var_20 = var_20_arg_0 - var_20_arg_1; [L142] SORT_5 var_25_arg_0 = state_23; [L143] SORT_1 var_25_arg_1 = var_21; [L144] SORT_1 var_25_arg_2 = var_20; [L145] EXPR var_25_arg_0 ? var_25_arg_1 : var_25_arg_2 [L145] SORT_1 var_25 = var_25_arg_0 ? var_25_arg_1 : var_25_arg_2; [L146] var_25 = var_25 & mask_SORT_1 [L147] SORT_1 var_28_arg_0 = var_25; [L148] SORT_1 var_28_arg_1 = state_26; [L149] SORT_5 var_28 = var_28_arg_0 == var_28_arg_1; [L150] SORT_5 var_32_arg_0 = var_28; [L151] SORT_5 var_32 = ~var_32_arg_0; [L152] SORT_5 var_33_arg_0 = var_31; [L153] SORT_5 var_33_arg_1 = var_32; [L154] SORT_5 var_33 = var_33_arg_0 & var_33_arg_1; [L155] var_33 = var_33 & mask_SORT_5 [L156] SORT_5 bad_34_arg_0 = var_33; [L157] CALL __VERIFIER_assert(!(bad_34_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 0.8s, OverallIterations: 1, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 0.0s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: , PredicateUnifierStatistics: No data available, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=7occurred in iteration=0, InterpolantAutomatonStates: 0, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: No data available, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 0.0s InterpolantComputationTime, 4 NumberOfCodeBlocks, 4 NumberOfCodeBlocksAsserted, 1 NumberOfCheckSat, 0 ConstructedInterpolants, 0 QuantifiedInterpolants, 0 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 0 InterpolantComputations, 0 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:24:39,768 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 4a0901411443e2369cdef97e7f5c792ca60bb368bf9c988b6ac394cdcdf4c250 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:24:42,134 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:24:42,137 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:24:42,182 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:24:42,182 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:24:42,186 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:24:42,189 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:24:42,193 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:24:42,198 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:24:42,206 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:24:42,207 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:24:42,208 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:24:42,208 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:24:42,209 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:24:42,210 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:24:42,211 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:24:42,214 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:24:42,216 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:24:42,218 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:24:42,225 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:24:42,227 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:24:42,230 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:24:42,232 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:24:42,235 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:24:42,241 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:24:42,243 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:24:42,244 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:24:42,245 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:24:42,246 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:24:42,247 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:24:42,247 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:24:42,248 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:24:42,250 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:24:42,251 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:24:42,252 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:24:42,252 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:24:42,253 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:24:42,253 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:24:42,253 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:24:42,255 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:24:42,256 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:24:42,257 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:24:42,307 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:24:42,308 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:24:42,309 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:24:42,309 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:24:42,310 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:24:42,311 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:24:42,311 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:24:42,311 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:24:42,311 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:24:42,312 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:24:42,312 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:24:42,313 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:24:42,314 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:24:42,314 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:24:42,315 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:24:42,315 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:24:42,315 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:24:42,315 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:24:42,315 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:24:42,316 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:24:42,316 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:24:42,316 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:24:42,316 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:24:42,316 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:24:42,317 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:24:42,317 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:24:42,317 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:24:42,317 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:24:42,318 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:24:42,318 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:24:42,318 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:24:42,318 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:24:42,319 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:24:42,319 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:24:42,319 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:24:42,319 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4a0901411443e2369cdef97e7f5c792ca60bb368bf9c988b6ac394cdcdf4c250 [2022-11-03 02:24:42,639 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:24:42,662 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:24:42,666 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:24:42,668 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:24:42,668 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:24:42,670 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:42,748 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/cf7b12653/227d2371bc8941df8cbb2a458a8a1148/FLAG7c755cb67 [2022-11-03 02:24:43,357 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:24:43,367 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:43,380 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/cf7b12653/227d2371bc8941df8cbb2a458a8a1148/FLAG7c755cb67 [2022-11-03 02:24:43,676 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/data/cf7b12653/227d2371bc8941df8cbb2a458a8a1148 [2022-11-03 02:24:43,678 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:24:43,679 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:24:43,681 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:24:43,681 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:24:43,685 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:24:43,686 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:24:43" (1/1) ... [2022-11-03 02:24:43,687 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2074da4f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:43, skipping insertion in model container [2022-11-03 02:24:43,687 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:24:43" (1/1) ... [2022-11-03 02:24:43,697 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:24:43,722 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:24:43,866 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c[1107,1120] [2022-11-03 02:24:44,011 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:24:44,014 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:24:44,024 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.eq_sdp_v7.c[1107,1120] [2022-11-03 02:24:44,073 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:24:44,090 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:24:44,091 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44 WrapperNode [2022-11-03 02:24:44,091 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:24:44,092 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:24:44,092 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:24:44,092 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:24:44,099 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,121 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,169 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 419 [2022-11-03 02:24:44,176 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:24:44,177 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:24:44,178 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:24:44,178 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:24:44,187 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,187 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,207 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,207 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,216 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,235 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,237 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,248 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,258 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:24:44,259 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:24:44,260 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:24:44,263 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:24:44,264 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (1/1) ... [2022-11-03 02:24:44,272 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:24:44,285 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:24:44,299 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:24:44,312 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:24:44,350 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:24:44,350 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:24:44,525 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:24:44,527 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:24:44,978 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:24:44,985 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:24:44,986 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:24:44,987 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:44 BoogieIcfgContainer [2022-11-03 02:24:44,988 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:24:45,000 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:24:45,001 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:24:45,004 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:24:45,004 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:24:43" (1/3) ... [2022-11-03 02:24:45,005 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@17dd9fe8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:24:45, skipping insertion in model container [2022-11-03 02:24:45,005 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:24:44" (2/3) ... [2022-11-03 02:24:45,006 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@17dd9fe8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:24:45, skipping insertion in model container [2022-11-03 02:24:45,006 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:44" (3/3) ... [2022-11-03 02:24:45,007 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.eq_sdp_v7.c [2022-11-03 02:24:45,025 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:24:45,025 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:24:45,095 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:24:45,102 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@66e69973, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:24:45,102 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:24:45,115 INFO L276 IsEmpty]: Start isEmpty. Operand has 59 states, 57 states have (on average 1.4912280701754386) internal successors, (85), 58 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:45,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-03 02:24:45,122 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:45,122 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:45,123 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:45,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:45,130 INFO L85 PathProgramCache]: Analyzing trace with hash -332259343, now seen corresponding path program 1 times [2022-11-03 02:24:45,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:45,147 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1032171311] [2022-11-03 02:24:45,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:45,148 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:45,148 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:45,155 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:45,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:24:45,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:45,332 INFO L263 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-03 02:24:45,339 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:45,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:45,410 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:45,410 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:45,411 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1032171311] [2022-11-03 02:24:45,411 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1032171311] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:45,411 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:45,412 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:24:45,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1549978056] [2022-11-03 02:24:45,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:45,418 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:24:45,418 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:45,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:24:45,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:24:45,448 INFO L87 Difference]: Start difference. First operand has 59 states, 57 states have (on average 1.4912280701754386) internal successors, (85), 58 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:45,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:45,551 INFO L93 Difference]: Finished difference Result 217 states and 323 transitions. [2022-11-03 02:24:45,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:24:45,554 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-03 02:24:45,554 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:45,563 INFO L225 Difference]: With dead ends: 217 [2022-11-03 02:24:45,563 INFO L226 Difference]: Without dead ends: 160 [2022-11-03 02:24:45,566 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:24:45,570 INFO L413 NwaCegarLoop]: 75 mSDtfsCounter, 224 mSDsluCounter, 218 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 224 SdHoareTripleChecker+Valid, 293 SdHoareTripleChecker+Invalid, 17 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:45,571 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [224 Valid, 293 Invalid, 17 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:24:45,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2022-11-03 02:24:45,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 57. [2022-11-03 02:24:45,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 56 states have (on average 1.4464285714285714) internal successors, (81), 56 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:45,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 81 transitions. [2022-11-03 02:24:45,615 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 81 transitions. Word has length 9 [2022-11-03 02:24:45,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:45,616 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 81 transitions. [2022-11-03 02:24:45,616 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:45,616 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 81 transitions. [2022-11-03 02:24:45,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-03 02:24:45,617 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:45,617 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:45,631 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:45,831 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:45,832 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:45,833 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:45,834 INFO L85 PathProgramCache]: Analyzing trace with hash -275001041, now seen corresponding path program 1 times [2022-11-03 02:24:45,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:45,834 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [698180971] [2022-11-03 02:24:45,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:45,835 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:45,835 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:45,836 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:45,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:24:45,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:45,967 INFO L263 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:24:45,975 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:46,001 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:46,002 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:46,002 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:46,002 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [698180971] [2022-11-03 02:24:46,002 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [698180971] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:46,003 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:46,003 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:24:46,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [674783048] [2022-11-03 02:24:46,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:46,004 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:24:46,005 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:46,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:24:46,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:24:46,005 INFO L87 Difference]: Start difference. First operand 57 states and 81 transitions. Second operand has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:46,067 INFO L93 Difference]: Finished difference Result 213 states and 307 transitions. [2022-11-03 02:24:46,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:24:46,069 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-03 02:24:46,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:46,071 INFO L225 Difference]: With dead ends: 213 [2022-11-03 02:24:46,071 INFO L226 Difference]: Without dead ends: 160 [2022-11-03 02:24:46,072 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:24:46,073 INFO L413 NwaCegarLoop]: 80 mSDtfsCounter, 218 mSDsluCounter, 221 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 218 SdHoareTripleChecker+Valid, 301 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:46,073 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [218 Valid, 301 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:24:46,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2022-11-03 02:24:46,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 59. [2022-11-03 02:24:46,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 58 states have (on average 1.4310344827586208) internal successors, (83), 58 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 83 transitions. [2022-11-03 02:24:46,081 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 83 transitions. Word has length 9 [2022-11-03 02:24:46,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:46,082 INFO L495 AbstractCegarLoop]: Abstraction has 59 states and 83 transitions. [2022-11-03 02:24:46,082 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.25) internal successors, (9), 4 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,082 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 83 transitions. [2022-11-03 02:24:46,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2022-11-03 02:24:46,088 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:46,088 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:46,106 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:46,306 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:46,306 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:46,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:46,309 INFO L85 PathProgramCache]: Analyzing trace with hash -274941459, now seen corresponding path program 1 times [2022-11-03 02:24:46,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:46,310 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [646560951] [2022-11-03 02:24:46,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:46,311 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:46,311 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:46,313 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:46,319 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:24:46,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:46,447 INFO L263 TraceCheckSpWp]: Trace formula consists of 100 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 02:24:46,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:46,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:46,654 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:46,654 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:46,654 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [646560951] [2022-11-03 02:24:46,654 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [646560951] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:46,655 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:46,655 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:24:46,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1807202757] [2022-11-03 02:24:46,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:46,655 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:24:46,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:46,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:24:46,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:24:46,656 INFO L87 Difference]: Start difference. First operand 59 states and 83 transitions. Second operand has 8 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:46,961 INFO L93 Difference]: Finished difference Result 113 states and 161 transitions. [2022-11-03 02:24:46,962 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:24:46,962 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 9 [2022-11-03 02:24:46,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:46,963 INFO L225 Difference]: With dead ends: 113 [2022-11-03 02:24:46,963 INFO L226 Difference]: Without dead ends: 111 [2022-11-03 02:24:46,963 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=111, Unknown=0, NotChecked=0, Total=156 [2022-11-03 02:24:46,965 INFO L413 NwaCegarLoop]: 76 mSDtfsCounter, 281 mSDsluCounter, 425 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 281 SdHoareTripleChecker+Valid, 501 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:46,965 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [281 Valid, 501 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:24:46,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2022-11-03 02:24:46,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 61. [2022-11-03 02:24:46,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 60 states have (on average 1.4166666666666667) internal successors, (85), 60 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 85 transitions. [2022-11-03 02:24:46,972 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 85 transitions. Word has length 9 [2022-11-03 02:24:46,972 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:46,972 INFO L495 AbstractCegarLoop]: Abstraction has 61 states and 85 transitions. [2022-11-03 02:24:46,973 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:46,973 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 85 transitions. [2022-11-03 02:24:46,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:46,987 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:46,987 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:47,007 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:47,199 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:47,199 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:47,200 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:47,200 INFO L85 PathProgramCache]: Analyzing trace with hash 1420143283, now seen corresponding path program 1 times [2022-11-03 02:24:47,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:47,201 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [511330304] [2022-11-03 02:24:47,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:47,201 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:47,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:47,207 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:47,210 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 02:24:47,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:47,419 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:24:47,423 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:47,467 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:47,467 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:47,468 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:47,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [511330304] [2022-11-03 02:24:47,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [511330304] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:47,468 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:47,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:24:47,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416266140] [2022-11-03 02:24:47,469 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:47,469 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:24:47,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:47,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:24:47,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:24:47,471 INFO L87 Difference]: Start difference. First operand 61 states and 85 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:47,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:47,499 INFO L93 Difference]: Finished difference Result 211 states and 304 transitions. [2022-11-03 02:24:47,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:24:47,500 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:24:47,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:47,501 INFO L225 Difference]: With dead ends: 211 [2022-11-03 02:24:47,501 INFO L226 Difference]: Without dead ends: 158 [2022-11-03 02:24:47,502 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:24:47,503 INFO L413 NwaCegarLoop]: 96 mSDtfsCounter, 184 mSDsluCounter, 202 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 184 SdHoareTripleChecker+Valid, 298 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:47,503 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [184 Valid, 298 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:24:47,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states. [2022-11-03 02:24:47,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 71. [2022-11-03 02:24:47,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 70 states have (on average 1.4142857142857144) internal successors, (99), 70 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:47,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 99 transitions. [2022-11-03 02:24:47,527 INFO L78 Accepts]: Start accepts. Automaton has 71 states and 99 transitions. Word has length 60 [2022-11-03 02:24:47,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:47,528 INFO L495 AbstractCegarLoop]: Abstraction has 71 states and 99 transitions. [2022-11-03 02:24:47,528 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:47,528 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 99 transitions. [2022-11-03 02:24:47,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:47,529 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:47,530 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:47,561 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:47,747 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:47,747 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:47,748 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:47,748 INFO L85 PathProgramCache]: Analyzing trace with hash 522750005, now seen corresponding path program 1 times [2022-11-03 02:24:47,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:47,749 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1684746630] [2022-11-03 02:24:47,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:47,749 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:47,750 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:47,751 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:47,754 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 02:24:47,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:47,939 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:24:47,942 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:48,034 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:48,034 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:48,035 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:48,038 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1684746630] [2022-11-03 02:24:48,038 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1684746630] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:48,039 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:48,039 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:24:48,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442293624] [2022-11-03 02:24:48,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:48,047 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:24:48,047 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:48,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:24:48,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:24:48,049 INFO L87 Difference]: Start difference. First operand 71 states and 99 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:48,158 INFO L93 Difference]: Finished difference Result 207 states and 296 transitions. [2022-11-03 02:24:48,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:24:48,159 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:24:48,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:48,162 INFO L225 Difference]: With dead ends: 207 [2022-11-03 02:24:48,162 INFO L226 Difference]: Without dead ends: 154 [2022-11-03 02:24:48,163 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:24:48,167 INFO L413 NwaCegarLoop]: 83 mSDtfsCounter, 305 mSDsluCounter, 158 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 305 SdHoareTripleChecker+Valid, 241 SdHoareTripleChecker+Invalid, 58 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:48,168 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [305 Valid, 241 Invalid, 58 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:24:48,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2022-11-03 02:24:48,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 91. [2022-11-03 02:24:48,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 90 states have (on average 1.4111111111111112) internal successors, (127), 90 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 127 transitions. [2022-11-03 02:24:48,193 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 127 transitions. Word has length 60 [2022-11-03 02:24:48,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:48,196 INFO L495 AbstractCegarLoop]: Abstraction has 91 states and 127 transitions. [2022-11-03 02:24:48,197 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,197 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 127 transitions. [2022-11-03 02:24:48,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:48,201 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:48,201 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:48,215 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:48,402 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:48,402 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:48,402 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:48,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1926850125, now seen corresponding path program 1 times [2022-11-03 02:24:48,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:48,403 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1660385692] [2022-11-03 02:24:48,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:48,404 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:48,404 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:48,405 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:48,407 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 02:24:48,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:48,594 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:24:48,597 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:48,822 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:48,822 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:48,823 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:48,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1660385692] [2022-11-03 02:24:48,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1660385692] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:48,825 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:48,826 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:24:48,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18802874] [2022-11-03 02:24:48,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:48,826 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:24:48,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:48,827 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:24:48,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:24:48,827 INFO L87 Difference]: Start difference. First operand 91 states and 127 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:48,859 INFO L93 Difference]: Finished difference Result 259 states and 370 transitions. [2022-11-03 02:24:48,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:24:48,859 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:24:48,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:48,860 INFO L225 Difference]: With dead ends: 259 [2022-11-03 02:24:48,862 INFO L226 Difference]: Without dead ends: 194 [2022-11-03 02:24:48,865 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:24:48,870 INFO L413 NwaCegarLoop]: 125 mSDtfsCounter, 133 mSDsluCounter, 172 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 133 SdHoareTripleChecker+Valid, 297 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:48,871 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [133 Valid, 297 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 02:24:48,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2022-11-03 02:24:48,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 115. [2022-11-03 02:24:48,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 114 states have (on average 1.412280701754386) internal successors, (161), 114 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 161 transitions. [2022-11-03 02:24:48,882 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 161 transitions. Word has length 60 [2022-11-03 02:24:48,883 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:48,883 INFO L495 AbstractCegarLoop]: Abstraction has 115 states and 161 transitions. [2022-11-03 02:24:48,883 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:48,883 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 161 transitions. [2022-11-03 02:24:48,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:48,884 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:48,884 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:48,901 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:49,096 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:49,097 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:49,097 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:49,097 INFO L85 PathProgramCache]: Analyzing trace with hash 562678837, now seen corresponding path program 1 times [2022-11-03 02:24:49,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:49,098 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1796005329] [2022-11-03 02:24:49,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:49,098 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:49,098 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:49,102 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:49,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 02:24:49,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:49,291 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:24:49,294 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:49,571 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:49,571 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:24:49,571 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:49,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1796005329] [2022-11-03 02:24:49,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1796005329] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:24:49,572 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:24:49,572 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:24:49,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1804867341] [2022-11-03 02:24:49,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:24:49,573 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:24:49,573 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:49,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:24:49,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:24:49,574 INFO L87 Difference]: Start difference. First operand 115 states and 161 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:49,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:49,739 INFO L93 Difference]: Finished difference Result 262 states and 373 transitions. [2022-11-03 02:24:49,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:24:49,740 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:24:49,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:49,741 INFO L225 Difference]: With dead ends: 262 [2022-11-03 02:24:49,741 INFO L226 Difference]: Without dead ends: 197 [2022-11-03 02:24:49,741 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:24:49,742 INFO L413 NwaCegarLoop]: 114 mSDtfsCounter, 190 mSDsluCounter, 607 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 190 SdHoareTripleChecker+Valid, 721 SdHoareTripleChecker+Invalid, 95 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 27 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:49,742 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [190 Valid, 721 Invalid, 95 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 68 Invalid, 0 Unknown, 27 Unchecked, 0.1s Time] [2022-11-03 02:24:49,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2022-11-03 02:24:49,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 133. [2022-11-03 02:24:49,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 132 states have (on average 1.4090909090909092) internal successors, (186), 132 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:49,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 186 transitions. [2022-11-03 02:24:49,749 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 186 transitions. Word has length 60 [2022-11-03 02:24:49,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:49,749 INFO L495 AbstractCegarLoop]: Abstraction has 133 states and 186 transitions. [2022-11-03 02:24:49,750 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:49,750 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 186 transitions. [2022-11-03 02:24:49,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:49,750 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:49,751 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:49,770 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:49,963 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:24:49,963 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:49,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:49,964 INFO L85 PathProgramCache]: Analyzing trace with hash 139977011, now seen corresponding path program 1 times [2022-11-03 02:24:49,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:49,964 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [924884553] [2022-11-03 02:24:49,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:49,965 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:49,965 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:49,966 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:49,969 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 02:24:50,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:50,136 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:24:50,139 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:50,420 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:50,420 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:24:50,639 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:50,639 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:24:50,639 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [924884553] [2022-11-03 02:24:50,640 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [924884553] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:24:50,640 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [494773556] [2022-11-03 02:24:50,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:50,640 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:24:50,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:24:50,647 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:24:50,651 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2022-11-03 02:24:50,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:50,932 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:24:50,934 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:51,150 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:51,150 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:24:51,293 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:51,294 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [494773556] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:24:51,294 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [707049323] [2022-11-03 02:24:51,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:51,294 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:24:51,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:24:51,299 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:24:51,318 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-03 02:24:51,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:51,464 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:24:51,467 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:51,700 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:51,700 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:24:51,909 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:51,909 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [707049323] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:24:51,909 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:24:51,909 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 22 [2022-11-03 02:24:51,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1844665509] [2022-11-03 02:24:51,909 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:24:51,910 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-11-03 02:24:51,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:24:51,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-11-03 02:24:51,911 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=413, Unknown=0, NotChecked=0, Total=462 [2022-11-03 02:24:51,911 INFO L87 Difference]: Start difference. First operand 133 states and 186 transitions. Second operand has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:55,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:24:55,068 INFO L93 Difference]: Finished difference Result 1715 states and 2492 transitions. [2022-11-03 02:24:55,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2022-11-03 02:24:55,069 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:24:55,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:24:55,077 INFO L225 Difference]: With dead ends: 1715 [2022-11-03 02:24:55,077 INFO L226 Difference]: Without dead ends: 1650 [2022-11-03 02:24:55,081 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 432 GetRequests, 334 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3076 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2045, Invalid=7855, Unknown=0, NotChecked=0, Total=9900 [2022-11-03 02:24:55,082 INFO L413 NwaCegarLoop]: 57 mSDtfsCounter, 8616 mSDsluCounter, 591 mSDsCounter, 0 mSdLazyCounter, 464 mSolverCounterSat, 340 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8616 SdHoareTripleChecker+Valid, 648 SdHoareTripleChecker+Invalid, 804 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 340 IncrementalHoareTripleChecker+Valid, 464 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-03 02:24:55,083 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [8616 Valid, 648 Invalid, 804 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [340 Valid, 464 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-11-03 02:24:55,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1650 states. [2022-11-03 02:24:55,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1650 to 292. [2022-11-03 02:24:55,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 292 states, 291 states have (on average 1.4192439862542956) internal successors, (413), 291 states have internal predecessors, (413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:55,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 292 states to 292 states and 413 transitions. [2022-11-03 02:24:55,114 INFO L78 Accepts]: Start accepts. Automaton has 292 states and 413 transitions. Word has length 60 [2022-11-03 02:24:55,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:24:55,115 INFO L495 AbstractCegarLoop]: Abstraction has 292 states and 413 transitions. [2022-11-03 02:24:55,116 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:24:55,116 INFO L276 IsEmpty]: Start isEmpty. Operand 292 states and 413 transitions. [2022-11-03 02:24:55,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:24:55,123 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:24:55,123 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:24:55,142 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:55,345 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:55,563 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-03 02:24:55,742 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:24:55,743 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:24:55,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:24:55,743 INFO L85 PathProgramCache]: Analyzing trace with hash 197294895, now seen corresponding path program 1 times [2022-11-03 02:24:55,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:24:55,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [598444565] [2022-11-03 02:24:55,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:24:55,744 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:24:55,744 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:24:55,745 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:24:55,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 02:24:55,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:24:55,912 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-03 02:24:55,916 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:24:56,831 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:24:56,831 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:00,117 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:00,117 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:00,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [598444565] [2022-11-03 02:25:00,118 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [598444565] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:00,118 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1513098923] [2022-11-03 02:25:00,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:00,118 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:00,119 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:00,123 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:00,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Waiting until timeout for monitored process [2022-11-03 02:25:00,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:00,390 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-03 02:25:00,393 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:01,013 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:01,014 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:01,784 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:01,785 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1513098923] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:01,785 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [651580005] [2022-11-03 02:25:01,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:01,785 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:01,785 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:25:01,786 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:25:01,787 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-03 02:25:01,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:01,942 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 48 conjunts are in the unsatisfiable core [2022-11-03 02:25:01,945 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:02,604 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:02,605 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:03,529 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:03,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [651580005] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:03,530 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:25:03,530 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 20, 20] total 38 [2022-11-03 02:25:03,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75149289] [2022-11-03 02:25:03,531 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:25:03,531 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-11-03 02:25:03,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:03,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-03 02:25:03,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=1290, Unknown=0, NotChecked=0, Total=1406 [2022-11-03 02:25:03,533 INFO L87 Difference]: Start difference. First operand 292 states and 413 transitions. Second operand has 38 states, 38 states have (on average 3.210526315789474) internal successors, (122), 38 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:07,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:07,590 INFO L93 Difference]: Finished difference Result 973 states and 1362 transitions. [2022-11-03 02:25:07,590 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2022-11-03 02:25:07,591 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 3.210526315789474) internal successors, (122), 38 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:07,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:07,594 INFO L225 Difference]: With dead ends: 973 [2022-11-03 02:25:07,594 INFO L226 Difference]: Without dead ends: 971 [2022-11-03 02:25:07,597 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 320 SyntacticMatches, 2 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1042 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=1193, Invalid=4969, Unknown=0, NotChecked=0, Total=6162 [2022-11-03 02:25:07,597 INFO L413 NwaCegarLoop]: 174 mSDtfsCounter, 2079 mSDsluCounter, 3102 mSDsCounter, 0 mSdLazyCounter, 696 mSolverCounterSat, 49 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2079 SdHoareTripleChecker+Valid, 3276 SdHoareTripleChecker+Invalid, 2371 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 49 IncrementalHoareTripleChecker+Valid, 696 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1626 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:07,598 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2079 Valid, 3276 Invalid, 2371 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [49 Valid, 696 Invalid, 0 Unknown, 1626 Unchecked, 0.8s Time] [2022-11-03 02:25:07,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 971 states. [2022-11-03 02:25:07,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 971 to 432. [2022-11-03 02:25:07,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 431 states have (on average 1.4106728538283062) internal successors, (608), 431 states have internal predecessors, (608), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:07,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 608 transitions. [2022-11-03 02:25:07,616 INFO L78 Accepts]: Start accepts. Automaton has 432 states and 608 transitions. Word has length 60 [2022-11-03 02:25:07,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:07,617 INFO L495 AbstractCegarLoop]: Abstraction has 432 states and 608 transitions. [2022-11-03 02:25:07,617 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 3.210526315789474) internal successors, (122), 38 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:07,617 INFO L276 IsEmpty]: Start isEmpty. Operand 432 states and 608 transitions. [2022-11-03 02:25:07,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:07,619 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:07,619 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:07,627 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Ended with exit code 0 [2022-11-03 02:25:07,843 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:08,030 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Ended with exit code 0 [2022-11-03 02:25:08,222 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:08,222 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:08,223 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:08,223 INFO L85 PathProgramCache]: Analyzing trace with hash 620941617, now seen corresponding path program 1 times [2022-11-03 02:25:08,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:08,224 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [50546773] [2022-11-03 02:25:08,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:08,224 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:08,224 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:08,225 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:08,235 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 02:25:08,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:08,392 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:08,395 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:08,557 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:08,558 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:08,558 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:08,558 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [50546773] [2022-11-03 02:25:08,558 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [50546773] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:08,558 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:08,559 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:08,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852752813] [2022-11-03 02:25:08,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:08,559 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:08,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:08,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:08,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:08,560 INFO L87 Difference]: Start difference. First operand 432 states and 608 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:08,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:08,684 INFO L93 Difference]: Finished difference Result 848 states and 1196 transitions. [2022-11-03 02:25:08,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:25:08,684 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:08,687 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:08,688 INFO L225 Difference]: With dead ends: 848 [2022-11-03 02:25:08,689 INFO L226 Difference]: Without dead ends: 542 [2022-11-03 02:25:08,689 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:25:08,690 INFO L413 NwaCegarLoop]: 85 mSDtfsCounter, 203 mSDsluCounter, 445 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 203 SdHoareTripleChecker+Valid, 530 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:08,691 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [203 Valid, 530 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 53 Invalid, 0 Unknown, 23 Unchecked, 0.1s Time] [2022-11-03 02:25:08,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 542 states. [2022-11-03 02:25:08,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 542 to 432. [2022-11-03 02:25:08,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 431 states have (on average 1.4013921113689096) internal successors, (604), 431 states have internal predecessors, (604), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:08,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 604 transitions. [2022-11-03 02:25:08,707 INFO L78 Accepts]: Start accepts. Automaton has 432 states and 604 transitions. Word has length 60 [2022-11-03 02:25:08,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:08,708 INFO L495 AbstractCegarLoop]: Abstraction has 432 states and 604 transitions. [2022-11-03 02:25:08,708 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:08,709 INFO L276 IsEmpty]: Start isEmpty. Operand 432 states and 604 transitions. [2022-11-03 02:25:08,709 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:08,709 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:08,710 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:08,727 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:08,922 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:08,922 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:08,922 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:08,923 INFO L85 PathProgramCache]: Analyzing trace with hash 1090721651, now seen corresponding path program 1 times [2022-11-03 02:25:08,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:08,923 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [290549952] [2022-11-03 02:25:08,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:08,923 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:08,923 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:08,924 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:08,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 02:25:09,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:09,077 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:25:09,079 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:09,117 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:09,117 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:09,117 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:09,117 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [290549952] [2022-11-03 02:25:09,117 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [290549952] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:09,118 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:09,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:09,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1939148538] [2022-11-03 02:25:09,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:09,118 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:09,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:09,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:09,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:09,120 INFO L87 Difference]: Start difference. First operand 432 states and 604 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:09,222 INFO L93 Difference]: Finished difference Result 639 states and 899 transitions. [2022-11-03 02:25:09,226 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:09,226 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:09,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:09,227 INFO L225 Difference]: With dead ends: 639 [2022-11-03 02:25:09,228 INFO L226 Difference]: Without dead ends: 325 [2022-11-03 02:25:09,228 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:09,229 INFO L413 NwaCegarLoop]: 78 mSDtfsCounter, 288 mSDsluCounter, 151 mSDsCounter, 0 mSdLazyCounter, 56 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 288 SdHoareTripleChecker+Valid, 229 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 56 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:09,229 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [288 Valid, 229 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 56 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:09,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2022-11-03 02:25:09,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 304. [2022-11-03 02:25:09,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 304 states, 303 states have (on average 1.396039603960396) internal successors, (423), 303 states have internal predecessors, (423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 304 states to 304 states and 423 transitions. [2022-11-03 02:25:09,240 INFO L78 Accepts]: Start accepts. Automaton has 304 states and 423 transitions. Word has length 60 [2022-11-03 02:25:09,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:09,240 INFO L495 AbstractCegarLoop]: Abstraction has 304 states and 423 transitions. [2022-11-03 02:25:09,240 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,241 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 423 transitions. [2022-11-03 02:25:09,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:09,241 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:09,241 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:09,255 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:09,454 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:09,454 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:09,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:09,454 INFO L85 PathProgramCache]: Analyzing trace with hash -155793487, now seen corresponding path program 1 times [2022-11-03 02:25:09,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:09,455 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [796693737] [2022-11-03 02:25:09,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:09,455 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:09,455 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:09,456 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:09,458 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Waiting until timeout for monitored process [2022-11-03 02:25:09,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:09,611 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:25:09,612 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:09,646 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:09,646 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:09,646 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:09,646 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [796693737] [2022-11-03 02:25:09,647 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [796693737] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:09,647 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:09,647 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:09,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778006011] [2022-11-03 02:25:09,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:09,647 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:09,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:09,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:09,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:09,648 INFO L87 Difference]: Start difference. First operand 304 states and 423 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:09,746 INFO L93 Difference]: Finished difference Result 531 states and 740 transitions. [2022-11-03 02:25:09,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:09,751 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:09,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:09,752 INFO L225 Difference]: With dead ends: 531 [2022-11-03 02:25:09,752 INFO L226 Difference]: Without dead ends: 319 [2022-11-03 02:25:09,753 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:09,754 INFO L413 NwaCegarLoop]: 76 mSDtfsCounter, 284 mSDsluCounter, 149 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 284 SdHoareTripleChecker+Valid, 225 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:09,754 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [284 Valid, 225 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 54 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:09,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2022-11-03 02:25:09,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 304. [2022-11-03 02:25:09,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 304 states, 303 states have (on average 1.3828382838283828) internal successors, (419), 303 states have internal predecessors, (419), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 304 states to 304 states and 419 transitions. [2022-11-03 02:25:09,765 INFO L78 Accepts]: Start accepts. Automaton has 304 states and 419 transitions. Word has length 60 [2022-11-03 02:25:09,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:09,765 INFO L495 AbstractCegarLoop]: Abstraction has 304 states and 419 transitions. [2022-11-03 02:25:09,765 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:09,765 INFO L276 IsEmpty]: Start isEmpty. Operand 304 states and 419 transitions. [2022-11-03 02:25:09,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:09,766 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:09,766 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:09,783 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:09,978 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:09,978 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:09,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:09,979 INFO L85 PathProgramCache]: Analyzing trace with hash 181776177, now seen corresponding path program 1 times [2022-11-03 02:25:09,979 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:09,979 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [841465611] [2022-11-03 02:25:09,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:09,980 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:09,980 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:09,980 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:09,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Waiting until timeout for monitored process [2022-11-03 02:25:10,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:10,113 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:25:10,115 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:10,152 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:10,152 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:10,152 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:10,152 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [841465611] [2022-11-03 02:25:10,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [841465611] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:10,152 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:10,152 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:10,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586582868] [2022-11-03 02:25:10,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:10,153 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:10,153 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:10,153 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:10,154 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:10,154 INFO L87 Difference]: Start difference. First operand 304 states and 419 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:10,251 INFO L93 Difference]: Finished difference Result 492 states and 684 transitions. [2022-11-03 02:25:10,251 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:10,251 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:10,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:10,253 INFO L225 Difference]: With dead ends: 492 [2022-11-03 02:25:10,253 INFO L226 Difference]: Without dead ends: 278 [2022-11-03 02:25:10,253 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:10,254 INFO L413 NwaCegarLoop]: 76 mSDtfsCounter, 278 mSDsluCounter, 147 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 278 SdHoareTripleChecker+Valid, 223 SdHoareTripleChecker+Invalid, 52 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:10,254 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [278 Valid, 223 Invalid, 52 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 52 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:10,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2022-11-03 02:25:10,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 268. [2022-11-03 02:25:10,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 267 states have (on average 1.3932584269662922) internal successors, (372), 267 states have internal predecessors, (372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 372 transitions. [2022-11-03 02:25:10,264 INFO L78 Accepts]: Start accepts. Automaton has 268 states and 372 transitions. Word has length 60 [2022-11-03 02:25:10,264 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:10,265 INFO L495 AbstractCegarLoop]: Abstraction has 268 states and 372 transitions. [2022-11-03 02:25:10,265 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,265 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 372 transitions. [2022-11-03 02:25:10,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:10,266 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:10,266 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:10,283 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:10,483 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:10,484 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:10,484 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:10,484 INFO L85 PathProgramCache]: Analyzing trace with hash 983752439, now seen corresponding path program 1 times [2022-11-03 02:25:10,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:10,484 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1264182358] [2022-11-03 02:25:10,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:10,485 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:10,485 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:10,486 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:10,487 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-03 02:25:10,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:10,627 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:10,628 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:10,644 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:10,644 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:10,644 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:10,645 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1264182358] [2022-11-03 02:25:10,645 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1264182358] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:10,645 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:10,645 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:10,648 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [273860228] [2022-11-03 02:25:10,648 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:10,649 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:10,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:10,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:10,649 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:10,650 INFO L87 Difference]: Start difference. First operand 268 states and 372 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:10,742 INFO L93 Difference]: Finished difference Result 504 states and 704 transitions. [2022-11-03 02:25:10,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:10,743 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:10,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:10,744 INFO L225 Difference]: With dead ends: 504 [2022-11-03 02:25:10,744 INFO L226 Difference]: Without dead ends: 278 [2022-11-03 02:25:10,745 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:10,745 INFO L413 NwaCegarLoop]: 125 mSDtfsCounter, 228 mSDsluCounter, 136 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 228 SdHoareTripleChecker+Valid, 261 SdHoareTripleChecker+Invalid, 64 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:10,745 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [228 Valid, 261 Invalid, 64 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 64 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:10,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states. [2022-11-03 02:25:10,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 268. [2022-11-03 02:25:10,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 267 states have (on average 1.3857677902621723) internal successors, (370), 267 states have internal predecessors, (370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 370 transitions. [2022-11-03 02:25:10,755 INFO L78 Accepts]: Start accepts. Automaton has 268 states and 370 transitions. Word has length 60 [2022-11-03 02:25:10,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:10,756 INFO L495 AbstractCegarLoop]: Abstraction has 268 states and 370 transitions. [2022-11-03 02:25:10,756 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:10,756 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 370 transitions. [2022-11-03 02:25:10,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:10,757 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:10,757 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:10,774 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:10,974 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:10,974 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:10,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:10,975 INFO L85 PathProgramCache]: Analyzing trace with hash 968233721, now seen corresponding path program 1 times [2022-11-03 02:25:10,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:10,975 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [52339047] [2022-11-03 02:25:10,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:10,975 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:10,976 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:10,976 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:10,983 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (20)] Waiting until timeout for monitored process [2022-11-03 02:25:11,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:11,114 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:11,115 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:11,133 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:11,133 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:11,133 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:11,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [52339047] [2022-11-03 02:25:11,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [52339047] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:11,133 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:11,133 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:11,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184174866] [2022-11-03 02:25:11,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:11,134 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:11,136 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:11,136 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:11,136 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:11,137 INFO L87 Difference]: Start difference. First operand 268 states and 370 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:11,231 INFO L93 Difference]: Finished difference Result 506 states and 702 transitions. [2022-11-03 02:25:11,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:11,232 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:11,232 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:11,234 INFO L225 Difference]: With dead ends: 506 [2022-11-03 02:25:11,234 INFO L226 Difference]: Without dead ends: 282 [2022-11-03 02:25:11,237 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:11,238 INFO L413 NwaCegarLoop]: 126 mSDtfsCounter, 225 mSDsluCounter, 138 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 225 SdHoareTripleChecker+Valid, 264 SdHoareTripleChecker+Invalid, 68 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:11,238 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [225 Valid, 264 Invalid, 68 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 68 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:11,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2022-11-03 02:25:11,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 268. [2022-11-03 02:25:11,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 267 states have (on average 1.3782771535580525) internal successors, (368), 267 states have internal predecessors, (368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 368 transitions. [2022-11-03 02:25:11,255 INFO L78 Accepts]: Start accepts. Automaton has 268 states and 368 transitions. Word has length 60 [2022-11-03 02:25:11,255 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:11,255 INFO L495 AbstractCegarLoop]: Abstraction has 268 states and 368 transitions. [2022-11-03 02:25:11,255 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,256 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 368 transitions. [2022-11-03 02:25:11,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:11,256 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:11,256 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:11,271 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (20)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:11,466 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:11,467 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:11,467 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:11,467 INFO L85 PathProgramCache]: Analyzing trace with hash 615145339, now seen corresponding path program 1 times [2022-11-03 02:25:11,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:11,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [497187229] [2022-11-03 02:25:11,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:11,468 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:11,468 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:11,469 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:11,474 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Waiting until timeout for monitored process [2022-11-03 02:25:11,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:11,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:11,630 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:11,650 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:11,650 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:11,651 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:11,651 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [497187229] [2022-11-03 02:25:11,651 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [497187229] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:11,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:11,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:11,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747499207] [2022-11-03 02:25:11,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:11,651 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:11,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:11,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:11,654 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:11,654 INFO L87 Difference]: Start difference. First operand 268 states and 368 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:11,739 INFO L93 Difference]: Finished difference Result 423 states and 578 transitions. [2022-11-03 02:25:11,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:11,740 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:11,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:11,741 INFO L225 Difference]: With dead ends: 423 [2022-11-03 02:25:11,741 INFO L226 Difference]: Without dead ends: 223 [2022-11-03 02:25:11,742 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 57 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:11,742 INFO L413 NwaCegarLoop]: 127 mSDtfsCounter, 222 mSDsluCounter, 140 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 222 SdHoareTripleChecker+Valid, 267 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:11,743 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [222 Valid, 267 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:11,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2022-11-03 02:25:11,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 207. [2022-11-03 02:25:11,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3446601941747574) internal successors, (277), 206 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 277 transitions. [2022-11-03 02:25:11,751 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 277 transitions. Word has length 60 [2022-11-03 02:25:11,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:11,752 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 277 transitions. [2022-11-03 02:25:11,752 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:11,752 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 277 transitions. [2022-11-03 02:25:11,752 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:11,753 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:11,753 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:11,770 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:11,965 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:11,966 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:11,966 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:11,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1508572095, now seen corresponding path program 1 times [2022-11-03 02:25:11,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:11,966 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1146027474] [2022-11-03 02:25:11,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:11,966 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:11,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:11,967 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:11,969 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Waiting until timeout for monitored process [2022-11-03 02:25:12,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:12,119 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:12,121 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:12,289 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:12,289 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:12,289 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:12,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1146027474] [2022-11-03 02:25:12,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1146027474] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:12,290 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:12,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:12,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [285191247] [2022-11-03 02:25:12,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:12,290 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:12,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:12,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:12,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:12,291 INFO L87 Difference]: Start difference. First operand 207 states and 277 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:12,380 INFO L93 Difference]: Finished difference Result 422 states and 580 transitions. [2022-11-03 02:25:12,381 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:12,381 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:12,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:12,382 INFO L225 Difference]: With dead ends: 422 [2022-11-03 02:25:12,382 INFO L226 Difference]: Without dead ends: 265 [2022-11-03 02:25:12,383 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:12,384 INFO L413 NwaCegarLoop]: 121 mSDtfsCounter, 176 mSDsluCounter, 677 mSDsCounter, 0 mSdLazyCounter, 46 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 176 SdHoareTripleChecker+Valid, 798 SdHoareTripleChecker+Invalid, 80 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 46 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 33 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:12,384 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [176 Valid, 798 Invalid, 80 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 46 Invalid, 0 Unknown, 33 Unchecked, 0.1s Time] [2022-11-03 02:25:12,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2022-11-03 02:25:12,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 207. [2022-11-03 02:25:12,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3398058252427185) internal successors, (276), 206 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 276 transitions. [2022-11-03 02:25:12,396 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 276 transitions. Word has length 60 [2022-11-03 02:25:12,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:12,396 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 276 transitions. [2022-11-03 02:25:12,397 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,397 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 276 transitions. [2022-11-03 02:25:12,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:12,397 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:12,398 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:12,410 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Ended with exit code 0 [2022-11-03 02:25:12,610 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:12,610 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:12,610 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:12,610 INFO L85 PathProgramCache]: Analyzing trace with hash 1932218817, now seen corresponding path program 1 times [2022-11-03 02:25:12,611 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:12,611 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [392576738] [2022-11-03 02:25:12,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:12,611 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:12,611 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:12,612 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:12,649 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (23)] Waiting until timeout for monitored process [2022-11-03 02:25:12,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:12,775 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:12,776 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:12,812 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:12,812 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:12,812 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:12,812 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [392576738] [2022-11-03 02:25:12,813 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [392576738] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:12,813 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:12,813 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:12,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1057876625] [2022-11-03 02:25:12,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:12,814 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:12,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:12,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:12,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:12,815 INFO L87 Difference]: Start difference. First operand 207 states and 276 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:12,928 INFO L93 Difference]: Finished difference Result 484 states and 652 transitions. [2022-11-03 02:25:12,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:12,929 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:12,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:12,930 INFO L225 Difference]: With dead ends: 484 [2022-11-03 02:25:12,930 INFO L226 Difference]: Without dead ends: 331 [2022-11-03 02:25:12,931 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:12,931 INFO L413 NwaCegarLoop]: 186 mSDtfsCounter, 215 mSDsluCounter, 200 mSDsCounter, 0 mSdLazyCounter, 93 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 215 SdHoareTripleChecker+Valid, 386 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 93 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:12,932 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [215 Valid, 386 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 93 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:12,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2022-11-03 02:25:12,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 207. [2022-11-03 02:25:12,940 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3300970873786409) internal successors, (274), 206 states have internal predecessors, (274), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 274 transitions. [2022-11-03 02:25:12,941 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 274 transitions. Word has length 60 [2022-11-03 02:25:12,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:12,942 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 274 transitions. [2022-11-03 02:25:12,942 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:12,942 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 274 transitions. [2022-11-03 02:25:12,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:12,943 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:12,943 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:12,958 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (23)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:13,155 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:13,155 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:13,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:13,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1703216957, now seen corresponding path program 1 times [2022-11-03 02:25:13,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:13,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [73285343] [2022-11-03 02:25:13,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:13,156 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:13,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:13,157 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:13,158 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Waiting until timeout for monitored process [2022-11-03 02:25:13,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:13,307 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:13,309 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:13,493 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:13,494 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:13,494 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:13,494 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [73285343] [2022-11-03 02:25:13,494 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [73285343] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:13,495 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:13,495 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:13,495 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1414726895] [2022-11-03 02:25:13,495 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:13,497 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:13,497 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:13,497 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:13,497 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:13,497 INFO L87 Difference]: Start difference. First operand 207 states and 274 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:13,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:13,584 INFO L93 Difference]: Finished difference Result 487 states and 666 transitions. [2022-11-03 02:25:13,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:13,585 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:13,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:13,586 INFO L225 Difference]: With dead ends: 487 [2022-11-03 02:25:13,586 INFO L226 Difference]: Without dead ends: 336 [2022-11-03 02:25:13,587 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:13,587 INFO L413 NwaCegarLoop]: 161 mSDtfsCounter, 107 mSDsluCounter, 507 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 107 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 21 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:13,588 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [107 Valid, 668 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 48 Invalid, 0 Unknown, 21 Unchecked, 0.1s Time] [2022-11-03 02:25:13,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 336 states. [2022-11-03 02:25:13,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 336 to 207. [2022-11-03 02:25:13,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.325242718446602) internal successors, (273), 206 states have internal predecessors, (273), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:13,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 273 transitions. [2022-11-03 02:25:13,599 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 273 transitions. Word has length 60 [2022-11-03 02:25:13,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:13,600 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 273 transitions. [2022-11-03 02:25:13,600 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:13,600 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 273 transitions. [2022-11-03 02:25:13,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:13,601 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:13,601 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:13,618 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:13,813 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:13,813 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:13,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:13,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1747744837, now seen corresponding path program 1 times [2022-11-03 02:25:13,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:13,814 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1932276386] [2022-11-03 02:25:13,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:13,814 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:13,814 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:13,815 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:13,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Waiting until timeout for monitored process [2022-11-03 02:25:13,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:13,960 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:13,962 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:14,133 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:14,133 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:14,134 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:14,134 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1932276386] [2022-11-03 02:25:14,134 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1932276386] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:14,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:14,134 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:14,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966649138] [2022-11-03 02:25:14,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:14,134 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:14,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:14,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:14,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:14,135 INFO L87 Difference]: Start difference. First operand 207 states and 273 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:14,211 INFO L93 Difference]: Finished difference Result 477 states and 650 transitions. [2022-11-03 02:25:14,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:14,212 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:14,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:14,213 INFO L225 Difference]: With dead ends: 477 [2022-11-03 02:25:14,214 INFO L226 Difference]: Without dead ends: 328 [2022-11-03 02:25:14,214 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:14,214 INFO L413 NwaCegarLoop]: 157 mSDtfsCounter, 101 mSDsluCounter, 787 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 101 SdHoareTripleChecker+Valid, 944 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 36 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:14,215 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [101 Valid, 944 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 48 Invalid, 0 Unknown, 36 Unchecked, 0.0s Time] [2022-11-03 02:25:14,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states. [2022-11-03 02:25:14,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 207. [2022-11-03 02:25:14,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3203883495145632) internal successors, (272), 206 states have internal predecessors, (272), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 272 transitions. [2022-11-03 02:25:14,225 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 272 transitions. Word has length 60 [2022-11-03 02:25:14,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:14,225 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 272 transitions. [2022-11-03 02:25:14,225 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,225 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 272 transitions. [2022-11-03 02:25:14,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:14,226 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:14,226 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:14,236 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:14,433 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:14,434 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:14,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:14,434 INFO L85 PathProgramCache]: Analyzing trace with hash 1675358279, now seen corresponding path program 1 times [2022-11-03 02:25:14,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:14,434 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1110068034] [2022-11-03 02:25:14,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:14,434 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:14,435 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:14,436 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:14,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (26)] Waiting until timeout for monitored process [2022-11-03 02:25:14,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:14,579 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:14,586 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:14,759 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:14,759 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:14,759 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:14,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1110068034] [2022-11-03 02:25:14,760 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1110068034] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:14,760 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:14,760 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:14,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299921283] [2022-11-03 02:25:14,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:14,760 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:14,760 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:14,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:14,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:14,761 INFO L87 Difference]: Start difference. First operand 207 states and 272 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:14,836 INFO L93 Difference]: Finished difference Result 467 states and 634 transitions. [2022-11-03 02:25:14,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:14,837 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:14,837 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:14,839 INFO L225 Difference]: With dead ends: 467 [2022-11-03 02:25:14,839 INFO L226 Difference]: Without dead ends: 320 [2022-11-03 02:25:14,839 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:14,840 INFO L413 NwaCegarLoop]: 153 mSDtfsCounter, 95 mSDsluCounter, 489 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 95 SdHoareTripleChecker+Valid, 642 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:14,840 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [95 Valid, 642 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 48 Invalid, 0 Unknown, 22 Unchecked, 0.0s Time] [2022-11-03 02:25:14,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states. [2022-11-03 02:25:14,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 207. [2022-11-03 02:25:14,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3155339805825244) internal successors, (271), 206 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 271 transitions. [2022-11-03 02:25:14,849 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 271 transitions. Word has length 60 [2022-11-03 02:25:14,849 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:14,849 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 271 transitions. [2022-11-03 02:25:14,850 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:14,850 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 271 transitions. [2022-11-03 02:25:14,850 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:14,850 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:14,851 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:14,863 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (26)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:15,063 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:15,063 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:15,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:15,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1918009143, now seen corresponding path program 1 times [2022-11-03 02:25:15,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:15,064 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [919990227] [2022-11-03 02:25:15,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:15,064 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:15,065 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:15,065 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:15,066 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-03 02:25:15,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:15,195 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:15,198 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:15,365 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:15,366 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:15,366 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:15,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [919990227] [2022-11-03 02:25:15,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [919990227] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:15,366 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:15,366 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:15,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638443416] [2022-11-03 02:25:15,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:15,367 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:15,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:15,367 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:15,367 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:15,368 INFO L87 Difference]: Start difference. First operand 207 states and 271 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:15,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:15,471 INFO L93 Difference]: Finished difference Result 457 states and 618 transitions. [2022-11-03 02:25:15,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:25:15,471 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:15,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:15,473 INFO L225 Difference]: With dead ends: 457 [2022-11-03 02:25:15,473 INFO L226 Difference]: Without dead ends: 312 [2022-11-03 02:25:15,473 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:25:15,474 INFO L413 NwaCegarLoop]: 149 mSDtfsCounter, 136 mSDsluCounter, 589 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 136 SdHoareTripleChecker+Valid, 738 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:15,474 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [136 Valid, 738 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 24 Invalid, 0 Unknown, 50 Unchecked, 0.0s Time] [2022-11-03 02:25:15,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2022-11-03 02:25:15,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 207. [2022-11-03 02:25:15,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3106796116504855) internal successors, (270), 206 states have internal predecessors, (270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:15,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 270 transitions. [2022-11-03 02:25:15,484 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 270 transitions. Word has length 60 [2022-11-03 02:25:15,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:15,485 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 270 transitions. [2022-11-03 02:25:15,485 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:15,485 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 270 transitions. [2022-11-03 02:25:15,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:15,486 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:15,486 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:15,497 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:15,695 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:15,695 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:15,695 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:15,695 INFO L85 PathProgramCache]: Analyzing trace with hash -531805749, now seen corresponding path program 1 times [2022-11-03 02:25:15,696 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:15,696 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [953948653] [2022-11-03 02:25:15,696 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:15,696 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:15,696 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:15,697 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:15,710 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (28)] Waiting until timeout for monitored process [2022-11-03 02:25:15,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:15,832 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:15,833 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:16,029 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:16,029 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:16,029 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:16,029 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [953948653] [2022-11-03 02:25:16,030 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [953948653] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:16,030 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:16,030 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:16,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [121661716] [2022-11-03 02:25:16,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:16,031 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:16,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:16,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:16,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:16,032 INFO L87 Difference]: Start difference. First operand 207 states and 270 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:16,108 INFO L93 Difference]: Finished difference Result 447 states and 602 transitions. [2022-11-03 02:25:16,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:16,109 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:16,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:16,110 INFO L225 Difference]: With dead ends: 447 [2022-11-03 02:25:16,110 INFO L226 Difference]: Without dead ends: 304 [2022-11-03 02:25:16,110 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:16,111 INFO L413 NwaCegarLoop]: 145 mSDtfsCounter, 83 mSDsluCounter, 471 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 83 SdHoareTripleChecker+Valid, 616 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 21 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:16,111 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [83 Valid, 616 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 48 Invalid, 0 Unknown, 21 Unchecked, 0.0s Time] [2022-11-03 02:25:16,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 304 states. [2022-11-03 02:25:16,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 304 to 207. [2022-11-03 02:25:16,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3058252427184467) internal successors, (269), 206 states have internal predecessors, (269), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 269 transitions. [2022-11-03 02:25:16,121 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 269 transitions. Word has length 60 [2022-11-03 02:25:16,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:16,122 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 269 transitions. [2022-11-03 02:25:16,122 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,122 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 269 transitions. [2022-11-03 02:25:16,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:16,123 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:16,123 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:16,135 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (28)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:16,335 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:16,335 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:16,335 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:16,335 INFO L85 PathProgramCache]: Analyzing trace with hash 1391422285, now seen corresponding path program 1 times [2022-11-03 02:25:16,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:16,336 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1088128813] [2022-11-03 02:25:16,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:16,336 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:16,336 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:16,337 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:16,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (29)] Waiting until timeout for monitored process [2022-11-03 02:25:16,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:16,467 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:16,468 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:16,649 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:16,649 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:16,649 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:16,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1088128813] [2022-11-03 02:25:16,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1088128813] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:16,650 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:16,650 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:25:16,650 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085528163] [2022-11-03 02:25:16,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:16,650 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:25:16,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:16,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:25:16,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:16,651 INFO L87 Difference]: Start difference. First operand 207 states and 269 transitions. Second operand has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:16,728 INFO L93 Difference]: Finished difference Result 417 states and 557 transitions. [2022-11-03 02:25:16,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 02:25:16,728 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:16,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:16,730 INFO L225 Difference]: With dead ends: 417 [2022-11-03 02:25:16,730 INFO L226 Difference]: Without dead ends: 276 [2022-11-03 02:25:16,731 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2022-11-03 02:25:16,731 INFO L413 NwaCegarLoop]: 115 mSDtfsCounter, 63 mSDsluCounter, 597 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 63 SdHoareTripleChecker+Valid, 712 SdHoareTripleChecker+Invalid, 73 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:16,732 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [63 Valid, 712 Invalid, 73 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 22 Invalid, 0 Unknown, 50 Unchecked, 0.0s Time] [2022-11-03 02:25:16,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2022-11-03 02:25:16,740 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 207. [2022-11-03 02:25:16,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.3009708737864079) internal successors, (268), 206 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 268 transitions. [2022-11-03 02:25:16,742 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 268 transitions. Word has length 60 [2022-11-03 02:25:16,742 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:16,742 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 268 transitions. [2022-11-03 02:25:16,742 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 7.5) internal successors, (60), 8 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:16,743 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 268 transitions. [2022-11-03 02:25:16,743 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:16,743 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:16,743 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:16,759 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (29)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:16,956 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:16,956 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:16,957 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:16,957 INFO L85 PathProgramCache]: Analyzing trace with hash 1531970895, now seen corresponding path program 1 times [2022-11-03 02:25:16,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:16,957 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1266453766] [2022-11-03 02:25:16,958 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:16,958 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:16,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:16,959 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:17,002 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Waiting until timeout for monitored process [2022-11-03 02:25:17,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:17,113 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:17,114 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:17,166 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:17,167 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:17,167 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:17,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1266453766] [2022-11-03 02:25:17,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1266453766] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:17,167 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:17,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:17,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946886496] [2022-11-03 02:25:17,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:17,168 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:17,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:17,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:17,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:17,168 INFO L87 Difference]: Start difference. First operand 207 states and 268 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:17,291 INFO L93 Difference]: Finished difference Result 472 states and 627 transitions. [2022-11-03 02:25:17,292 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:17,292 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:17,292 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:17,293 INFO L225 Difference]: With dead ends: 472 [2022-11-03 02:25:17,294 INFO L226 Difference]: Without dead ends: 333 [2022-11-03 02:25:17,294 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:17,295 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 195 mSDsluCounter, 224 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 195 SdHoareTripleChecker+Valid, 435 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:17,297 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [195 Valid, 435 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:17,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states. [2022-11-03 02:25:17,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 207. [2022-11-03 02:25:17,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.296116504854369) internal successors, (267), 206 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 267 transitions. [2022-11-03 02:25:17,315 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 267 transitions. Word has length 60 [2022-11-03 02:25:17,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:17,315 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 267 transitions. [2022-11-03 02:25:17,316 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,316 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 267 transitions. [2022-11-03 02:25:17,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:17,318 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:17,318 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:17,331 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:17,530 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:17,531 INFO L420 AbstractCegarLoop]: === Iteration 26 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:17,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:17,531 INFO L85 PathProgramCache]: Analyzing trace with hash -156972847, now seen corresponding path program 1 times [2022-11-03 02:25:17,532 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:17,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [127406985] [2022-11-03 02:25:17,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:17,532 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:17,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:17,533 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:17,553 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (31)] Waiting until timeout for monitored process [2022-11-03 02:25:17,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:17,670 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:17,672 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:17,748 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:17,748 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:17,748 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:17,748 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [127406985] [2022-11-03 02:25:17,748 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [127406985] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:17,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:17,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:17,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724685380] [2022-11-03 02:25:17,749 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:17,749 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:17,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:17,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:17,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:17,751 INFO L87 Difference]: Start difference. First operand 207 states and 267 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:17,857 INFO L93 Difference]: Finished difference Result 474 states and 627 transitions. [2022-11-03 02:25:17,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:17,857 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:17,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:17,859 INFO L225 Difference]: With dead ends: 474 [2022-11-03 02:25:17,859 INFO L226 Difference]: Without dead ends: 335 [2022-11-03 02:25:17,859 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:17,860 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 192 mSDsluCounter, 225 mSDsCounter, 0 mSdLazyCounter, 97 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 436 SdHoareTripleChecker+Invalid, 98 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 97 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:17,860 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 436 Invalid, 98 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 97 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:17,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 335 states. [2022-11-03 02:25:17,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 335 to 207. [2022-11-03 02:25:17,869 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.2912621359223302) internal successors, (266), 206 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 266 transitions. [2022-11-03 02:25:17,870 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 266 transitions. Word has length 60 [2022-11-03 02:25:17,870 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:17,871 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 266 transitions. [2022-11-03 02:25:17,871 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:17,871 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 266 transitions. [2022-11-03 02:25:17,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:17,872 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:17,872 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:17,884 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (31)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:18,084 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:18,084 INFO L420 AbstractCegarLoop]: === Iteration 27 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:18,085 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:18,085 INFO L85 PathProgramCache]: Analyzing trace with hash -1745320749, now seen corresponding path program 1 times [2022-11-03 02:25:18,085 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:18,085 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1165473790] [2022-11-03 02:25:18,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:18,085 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:18,086 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:18,086 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:18,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (32)] Waiting until timeout for monitored process [2022-11-03 02:25:18,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:18,215 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:18,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:18,269 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:18,269 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:18,269 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:18,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1165473790] [2022-11-03 02:25:18,269 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1165473790] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:18,269 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:18,270 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:18,270 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132859037] [2022-11-03 02:25:18,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:18,270 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:18,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:18,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:18,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:18,271 INFO L87 Difference]: Start difference. First operand 207 states and 266 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:18,382 INFO L93 Difference]: Finished difference Result 476 states and 627 transitions. [2022-11-03 02:25:18,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:18,383 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:18,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:18,384 INFO L225 Difference]: With dead ends: 476 [2022-11-03 02:25:18,384 INFO L226 Difference]: Without dead ends: 337 [2022-11-03 02:25:18,384 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:18,385 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 189 mSDsluCounter, 226 mSDsCounter, 0 mSdLazyCounter, 99 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 189 SdHoareTripleChecker+Valid, 437 SdHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 99 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:18,385 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [189 Valid, 437 Invalid, 100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 99 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:18,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2022-11-03 02:25:18,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 207. [2022-11-03 02:25:18,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.2864077669902914) internal successors, (265), 206 states have internal predecessors, (265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 265 transitions. [2022-11-03 02:25:18,395 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 265 transitions. Word has length 60 [2022-11-03 02:25:18,395 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:18,395 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 265 transitions. [2022-11-03 02:25:18,395 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,396 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 265 transitions. [2022-11-03 02:25:18,396 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:18,396 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:18,396 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:18,409 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (32)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:18,609 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:18,609 INFO L420 AbstractCegarLoop]: === Iteration 28 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:18,609 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:18,609 INFO L85 PathProgramCache]: Analyzing trace with hash 1269782869, now seen corresponding path program 1 times [2022-11-03 02:25:18,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:18,610 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [146360417] [2022-11-03 02:25:18,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:18,610 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:18,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:18,611 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:18,612 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Waiting until timeout for monitored process [2022-11-03 02:25:18,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:18,739 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:18,740 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:18,808 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:18,808 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:18,809 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:18,809 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [146360417] [2022-11-03 02:25:18,809 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [146360417] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:18,809 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:18,809 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:18,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917798086] [2022-11-03 02:25:18,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:18,810 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:18,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:18,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:18,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:18,811 INFO L87 Difference]: Start difference. First operand 207 states and 265 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:18,935 INFO L93 Difference]: Finished difference Result 478 states and 627 transitions. [2022-11-03 02:25:18,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:18,936 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:18,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:18,938 INFO L225 Difference]: With dead ends: 478 [2022-11-03 02:25:18,938 INFO L226 Difference]: Without dead ends: 339 [2022-11-03 02:25:18,938 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:18,938 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 186 mSDsluCounter, 227 mSDsCounter, 0 mSdLazyCounter, 101 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 186 SdHoareTripleChecker+Valid, 438 SdHoareTripleChecker+Invalid, 102 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 101 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:18,939 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [186 Valid, 438 Invalid, 102 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 101 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:18,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2022-11-03 02:25:18,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 207. [2022-11-03 02:25:18,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.2815533980582525) internal successors, (264), 206 states have internal predecessors, (264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 264 transitions. [2022-11-03 02:25:18,947 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 264 transitions. Word has length 60 [2022-11-03 02:25:18,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:18,947 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 264 transitions. [2022-11-03 02:25:18,947 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:18,947 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 264 transitions. [2022-11-03 02:25:18,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:18,947 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:18,948 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:18,961 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Ended with exit code 0 [2022-11-03 02:25:19,148 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:19,148 INFO L420 AbstractCegarLoop]: === Iteration 29 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:19,148 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:19,149 INFO L85 PathProgramCache]: Analyzing trace with hash 682976855, now seen corresponding path program 1 times [2022-11-03 02:25:19,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:19,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1162448498] [2022-11-03 02:25:19,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:19,149 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:19,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:19,150 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:19,151 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (34)] Waiting until timeout for monitored process [2022-11-03 02:25:19,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:19,279 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:19,281 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:19,336 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:19,337 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:19,337 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:19,337 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1162448498] [2022-11-03 02:25:19,337 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1162448498] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:19,337 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:19,338 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:19,338 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2131934802] [2022-11-03 02:25:19,338 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:19,338 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:19,338 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:19,339 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:19,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:19,339 INFO L87 Difference]: Start difference. First operand 207 states and 264 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:19,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:19,454 INFO L93 Difference]: Finished difference Result 480 states and 627 transitions. [2022-11-03 02:25:19,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:19,454 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:19,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:19,455 INFO L225 Difference]: With dead ends: 480 [2022-11-03 02:25:19,456 INFO L226 Difference]: Without dead ends: 341 [2022-11-03 02:25:19,456 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:19,457 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 183 mSDsluCounter, 228 mSDsCounter, 0 mSdLazyCounter, 103 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 183 SdHoareTripleChecker+Valid, 439 SdHoareTripleChecker+Invalid, 104 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 103 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:19,457 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [183 Valid, 439 Invalid, 104 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 103 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:19,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states. [2022-11-03 02:25:19,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 207. [2022-11-03 02:25:19,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.2766990291262137) internal successors, (263), 206 states have internal predecessors, (263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:19,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 263 transitions. [2022-11-03 02:25:19,467 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 263 transitions. Word has length 60 [2022-11-03 02:25:19,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:19,467 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 263 transitions. [2022-11-03 02:25:19,468 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:19,468 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 263 transitions. [2022-11-03 02:25:19,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:19,468 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:19,469 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:19,481 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (34)] Ended with exit code 0 [2022-11-03 02:25:19,681 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:19,681 INFO L420 AbstractCegarLoop]: === Iteration 30 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:19,681 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:19,682 INFO L85 PathProgramCache]: Analyzing trace with hash 1384041433, now seen corresponding path program 1 times [2022-11-03 02:25:19,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:19,682 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [815073242] [2022-11-03 02:25:19,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:19,682 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:19,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:19,683 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:19,684 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (35)] Waiting until timeout for monitored process [2022-11-03 02:25:19,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:19,813 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:19,815 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:19,888 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:19,889 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:19,889 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:19,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [815073242] [2022-11-03 02:25:19,889 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [815073242] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:19,889 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:25:19,889 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:25:19,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158426675] [2022-11-03 02:25:19,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:19,890 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:19,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:19,890 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:19,890 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:25:19,891 INFO L87 Difference]: Start difference. First operand 207 states and 263 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:20,001 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:20,002 INFO L93 Difference]: Finished difference Result 482 states and 627 transitions. [2022-11-03 02:25:20,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:25:20,003 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:20,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:20,004 INFO L225 Difference]: With dead ends: 482 [2022-11-03 02:25:20,004 INFO L226 Difference]: Without dead ends: 343 [2022-11-03 02:25:20,005 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 58 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:25:20,006 INFO L413 NwaCegarLoop]: 211 mSDtfsCounter, 180 mSDsluCounter, 229 mSDsCounter, 0 mSdLazyCounter, 105 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 180 SdHoareTripleChecker+Valid, 440 SdHoareTripleChecker+Invalid, 106 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 105 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:20,006 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [180 Valid, 440 Invalid, 106 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 105 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:20,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343 states. [2022-11-03 02:25:20,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343 to 207. [2022-11-03 02:25:20,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 207 states, 206 states have (on average 1.2718446601941749) internal successors, (262), 206 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:20,016 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 262 transitions. [2022-11-03 02:25:20,016 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 262 transitions. Word has length 60 [2022-11-03 02:25:20,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:20,017 INFO L495 AbstractCegarLoop]: Abstraction has 207 states and 262 transitions. [2022-11-03 02:25:20,017 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:20,017 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 262 transitions. [2022-11-03 02:25:20,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:20,018 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:20,018 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:20,035 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (35)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:20,230 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:20,231 INFO L420 AbstractCegarLoop]: === Iteration 31 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:20,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:20,231 INFO L85 PathProgramCache]: Analyzing trace with hash 2064099803, now seen corresponding path program 1 times [2022-11-03 02:25:20,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:20,231 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [978546626] [2022-11-03 02:25:20,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:20,232 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:20,232 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:20,232 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:20,233 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (36)] Waiting until timeout for monitored process [2022-11-03 02:25:20,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:20,365 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:20,366 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:20,553 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:20,553 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:20,709 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:20,710 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:20,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [978546626] [2022-11-03 02:25:20,710 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [978546626] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:20,710 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [835470] [2022-11-03 02:25:20,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:20,710 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:20,710 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:20,711 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:20,713 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (37)] Waiting until timeout for monitored process [2022-11-03 02:25:20,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:20,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:20,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:21,141 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:21,141 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:21,238 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:21,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [835470] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:21,238 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [152863679] [2022-11-03 02:25:21,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:21,238 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:21,239 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:25:21,239 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:25:21,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2022-11-03 02:25:21,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:21,371 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:25:21,373 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:21,556 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:21,556 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:21,699 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:21,699 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [152863679] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:21,699 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:25:21,700 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 22 [2022-11-03 02:25:21,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066486890] [2022-11-03 02:25:21,700 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:25:21,700 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-11-03 02:25:21,701 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:21,701 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-11-03 02:25:21,701 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=413, Unknown=0, NotChecked=0, Total=462 [2022-11-03 02:25:21,702 INFO L87 Difference]: Start difference. First operand 207 states and 262 transitions. Second operand has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:22,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:22,452 INFO L93 Difference]: Finished difference Result 914 states and 1203 transitions. [2022-11-03 02:25:22,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-03 02:25:22,453 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:22,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:22,455 INFO L225 Difference]: With dead ends: 914 [2022-11-03 02:25:22,455 INFO L226 Difference]: Without dead ends: 775 [2022-11-03 02:25:22,457 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 374 GetRequests, 334 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=374, Invalid=1348, Unknown=0, NotChecked=0, Total=1722 [2022-11-03 02:25:22,457 INFO L413 NwaCegarLoop]: 132 mSDtfsCounter, 1230 mSDsluCounter, 1821 mSDsCounter, 0 mSdLazyCounter, 270 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1230 SdHoareTripleChecker+Valid, 1953 SdHoareTripleChecker+Invalid, 293 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 270 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:22,458 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1230 Valid, 1953 Invalid, 293 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 270 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 02:25:22,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 775 states. [2022-11-03 02:25:22,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 775 to 221. [2022-11-03 02:25:22,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 220 states have (on average 1.259090909090909) internal successors, (277), 220 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:22,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 277 transitions. [2022-11-03 02:25:22,471 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 277 transitions. Word has length 60 [2022-11-03 02:25:22,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:22,471 INFO L495 AbstractCegarLoop]: Abstraction has 221 states and 277 transitions. [2022-11-03 02:25:22,471 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 8.409090909090908) internal successors, (185), 22 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:22,471 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 277 transitions. [2022-11-03 02:25:22,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2022-11-03 02:25:22,472 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:22,472 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:22,486 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (37)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:22,696 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Ended with exit code 0 [2022-11-03 02:25:22,883 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (36)] Ended with exit code 0 [2022-11-03 02:25:23,076 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:23,076 INFO L420 AbstractCegarLoop]: === Iteration 32 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:23,076 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:23,076 INFO L85 PathProgramCache]: Analyzing trace with hash 2121417687, now seen corresponding path program 1 times [2022-11-03 02:25:23,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:23,077 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2114190810] [2022-11-03 02:25:23,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:23,077 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:23,077 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:23,078 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:23,079 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (39)] Waiting until timeout for monitored process [2022-11-03 02:25:23,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:23,210 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-03 02:25:23,214 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:24,227 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:24,227 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:27,845 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:27,845 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:27,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2114190810] [2022-11-03 02:25:27,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2114190810] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:27,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1371412733] [2022-11-03 02:25:27,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:27,845 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:27,845 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:27,846 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:27,852 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (40)] Waiting until timeout for monitored process [2022-11-03 02:25:28,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:28,092 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 61 conjunts are in the unsatisfiable core [2022-11-03 02:25:28,095 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:28,654 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:28,654 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:29,365 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:29,366 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1371412733] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:29,366 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [566385842] [2022-11-03 02:25:29,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:29,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:29,366 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:25:29,367 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:25:29,368 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2022-11-03 02:25:29,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:29,491 INFO L263 TraceCheckSpWp]: Trace formula consists of 344 conjuncts, 64 conjunts are in the unsatisfiable core [2022-11-03 02:25:29,493 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:30,154 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:30,154 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:31,050 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:31,050 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [566385842] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:31,050 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:25:31,050 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 22, 22] total 42 [2022-11-03 02:25:31,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690316212] [2022-11-03 02:25:31,050 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:25:31,051 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-11-03 02:25:31,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:31,051 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-11-03 02:25:31,052 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=1617, Unknown=0, NotChecked=0, Total=1722 [2022-11-03 02:25:31,052 INFO L87 Difference]: Start difference. First operand 221 states and 277 transitions. Second operand has 42 states, 42 states have (on average 2.9047619047619047) internal successors, (122), 42 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:33,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:33,162 INFO L93 Difference]: Finished difference Result 378 states and 486 transitions. [2022-11-03 02:25:33,163 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-03 02:25:33,163 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 42 states have (on average 2.9047619047619047) internal successors, (122), 42 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 60 [2022-11-03 02:25:33,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:33,165 INFO L225 Difference]: With dead ends: 378 [2022-11-03 02:25:33,165 INFO L226 Difference]: Without dead ends: 376 [2022-11-03 02:25:33,166 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 312 SyntacticMatches, 2 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 376 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=407, Invalid=3253, Unknown=0, NotChecked=0, Total=3660 [2022-11-03 02:25:33,166 INFO L413 NwaCegarLoop]: 169 mSDtfsCounter, 641 mSDsluCounter, 4503 mSDsCounter, 0 mSdLazyCounter, 440 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 641 SdHoareTripleChecker+Valid, 4672 SdHoareTripleChecker+Invalid, 1054 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 440 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 598 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:33,167 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [641 Valid, 4672 Invalid, 1054 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 440 Invalid, 0 Unknown, 598 Unchecked, 0.4s Time] [2022-11-03 02:25:33,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2022-11-03 02:25:33,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 221. [2022-11-03 02:25:33,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 221 states, 220 states have (on average 1.259090909090909) internal successors, (277), 220 states have internal predecessors, (277), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:33,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 277 transitions. [2022-11-03 02:25:33,179 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 277 transitions. Word has length 60 [2022-11-03 02:25:33,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:33,180 INFO L495 AbstractCegarLoop]: Abstraction has 221 states and 277 transitions. [2022-11-03 02:25:33,180 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 42 states have (on average 2.9047619047619047) internal successors, (122), 42 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:33,180 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 277 transitions. [2022-11-03 02:25:33,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:33,181 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:33,181 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:33,195 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (39)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:33,395 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (40)] Ended with exit code 0 [2022-11-03 02:25:33,614 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:33,793 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:33,794 INFO L420 AbstractCegarLoop]: === Iteration 33 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:33,794 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:33,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1321003091, now seen corresponding path program 1 times [2022-11-03 02:25:33,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:33,795 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [707942335] [2022-11-03 02:25:33,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:33,795 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:33,795 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:33,796 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:33,798 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (42)] Waiting until timeout for monitored process [2022-11-03 02:25:33,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:33,993 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:33,995 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:34,167 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:34,167 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:34,299 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:34,299 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:34,299 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [707942335] [2022-11-03 02:25:34,300 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [707942335] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:34,300 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1100038012] [2022-11-03 02:25:34,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:34,300 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:34,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:34,301 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:34,302 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (43)] Waiting until timeout for monitored process [2022-11-03 02:25:34,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:34,604 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:34,606 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:34,648 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:34,649 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:34,649 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1100038012] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:34,649 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:34,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:34,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124925924] [2022-11-03 02:25:34,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:34,650 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:34,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:34,650 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:34,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:34,651 INFO L87 Difference]: Start difference. First operand 221 states and 277 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:34,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:34,762 INFO L93 Difference]: Finished difference Result 548 states and 698 transitions. [2022-11-03 02:25:34,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:34,763 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:34,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:34,765 INFO L225 Difference]: With dead ends: 548 [2022-11-03 02:25:34,765 INFO L226 Difference]: Without dead ends: 409 [2022-11-03 02:25:34,765 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:34,766 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 220 mSDsluCounter, 263 mSDsCounter, 0 mSdLazyCounter, 67 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 220 SdHoareTripleChecker+Valid, 480 SdHoareTripleChecker+Invalid, 68 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 67 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:34,766 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [220 Valid, 480 Invalid, 68 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 67 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:34,767 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 409 states. [2022-11-03 02:25:34,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 409 to 227. [2022-11-03 02:25:34,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 227 states, 226 states have (on average 1.252212389380531) internal successors, (283), 226 states have internal predecessors, (283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:34,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 283 transitions. [2022-11-03 02:25:34,779 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 283 transitions. Word has length 111 [2022-11-03 02:25:34,779 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:34,780 INFO L495 AbstractCegarLoop]: Abstraction has 227 states and 283 transitions. [2022-11-03 02:25:34,780 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:34,780 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 283 transitions. [2022-11-03 02:25:34,781 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:34,781 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:34,781 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:34,784 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (43)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:34,993 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (42)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:35,184 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 43 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:35,185 INFO L420 AbstractCegarLoop]: === Iteration 34 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:35,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:35,185 INFO L85 PathProgramCache]: Analyzing trace with hash 2129958703, now seen corresponding path program 1 times [2022-11-03 02:25:35,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:35,186 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [581583775] [2022-11-03 02:25:35,186 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:35,186 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:35,186 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:35,187 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:35,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (44)] Waiting until timeout for monitored process [2022-11-03 02:25:35,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:35,373 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:35,376 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:35,545 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:35,545 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:35,699 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:35,699 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:35,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [581583775] [2022-11-03 02:25:35,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [581583775] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:35,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [808277163] [2022-11-03 02:25:35,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:35,700 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:35,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:35,701 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:35,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (45)] Waiting until timeout for monitored process [2022-11-03 02:25:35,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:35,995 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:35,996 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:36,041 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:36,041 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:36,041 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [808277163] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:36,041 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:36,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:36,042 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816885481] [2022-11-03 02:25:36,042 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:36,042 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:36,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:36,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:36,043 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:36,043 INFO L87 Difference]: Start difference. First operand 227 states and 283 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:36,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:36,146 INFO L93 Difference]: Finished difference Result 556 states and 703 transitions. [2022-11-03 02:25:36,146 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:36,147 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:36,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:36,149 INFO L225 Difference]: With dead ends: 556 [2022-11-03 02:25:36,149 INFO L226 Difference]: Without dead ends: 411 [2022-11-03 02:25:36,149 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:36,150 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 217 mSDsluCounter, 264 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 217 SdHoareTripleChecker+Valid, 481 SdHoareTripleChecker+Invalid, 70 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:36,150 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [217 Valid, 481 Invalid, 70 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:36,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 411 states. [2022-11-03 02:25:36,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 411 to 229. [2022-11-03 02:25:36,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229 states, 228 states have (on average 1.2456140350877194) internal successors, (284), 228 states have internal predecessors, (284), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:36,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 284 transitions. [2022-11-03 02:25:36,161 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 284 transitions. Word has length 111 [2022-11-03 02:25:36,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:36,161 INFO L495 AbstractCegarLoop]: Abstraction has 229 states and 284 transitions. [2022-11-03 02:25:36,161 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:36,161 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 284 transitions. [2022-11-03 02:25:36,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:36,162 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:36,162 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:36,176 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (44)] Ended with exit code 0 [2022-11-03 02:25:36,377 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (45)] Ended with exit code 0 [2022-11-03 02:25:36,576 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,45 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:36,576 INFO L420 AbstractCegarLoop]: === Iteration 35 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:36,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:36,576 INFO L85 PathProgramCache]: Analyzing trace with hash 2057572145, now seen corresponding path program 1 times [2022-11-03 02:25:36,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:36,577 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [557766932] [2022-11-03 02:25:36,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:36,577 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:36,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:36,583 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:36,586 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (46)] Waiting until timeout for monitored process [2022-11-03 02:25:36,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:36,772 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:36,774 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:36,959 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:36,959 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:37,132 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:37,133 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:37,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [557766932] [2022-11-03 02:25:37,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [557766932] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:37,133 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1496427715] [2022-11-03 02:25:37,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:37,133 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:37,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:37,135 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:37,162 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (47)] Waiting until timeout for monitored process [2022-11-03 02:25:37,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:37,443 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:37,445 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:37,491 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:37,491 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:37,492 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1496427715] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:37,492 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:37,492 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:37,492 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623052391] [2022-11-03 02:25:37,492 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:37,492 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:37,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:37,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:37,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:37,493 INFO L87 Difference]: Start difference. First operand 229 states and 284 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:37,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:37,600 INFO L93 Difference]: Finished difference Result 560 states and 703 transitions. [2022-11-03 02:25:37,600 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:37,600 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:37,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:37,602 INFO L225 Difference]: With dead ends: 560 [2022-11-03 02:25:37,602 INFO L226 Difference]: Without dead ends: 413 [2022-11-03 02:25:37,603 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:37,603 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 214 mSDsluCounter, 265 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 214 SdHoareTripleChecker+Valid, 482 SdHoareTripleChecker+Invalid, 72 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:37,603 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [214 Valid, 482 Invalid, 72 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:37,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states. [2022-11-03 02:25:37,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 231. [2022-11-03 02:25:37,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 231 states, 230 states have (on average 1.2391304347826086) internal successors, (285), 230 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:37,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 285 transitions. [2022-11-03 02:25:37,617 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 285 transitions. Word has length 111 [2022-11-03 02:25:37,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:37,618 INFO L495 AbstractCegarLoop]: Abstraction has 231 states and 285 transitions. [2022-11-03 02:25:37,618 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:37,618 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 285 transitions. [2022-11-03 02:25:37,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:37,619 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:37,619 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:37,622 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (47)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:37,830 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (46)] Ended with exit code 0 [2022-11-03 02:25:38,022 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 47 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,46 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:38,022 INFO L420 AbstractCegarLoop]: === Iteration 36 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:38,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:38,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1535795277, now seen corresponding path program 1 times [2022-11-03 02:25:38,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:38,023 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1319994322] [2022-11-03 02:25:38,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:38,023 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:38,023 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:38,024 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:38,037 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (48)] Waiting until timeout for monitored process [2022-11-03 02:25:38,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:38,213 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:38,215 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:38,385 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:38,385 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:38,523 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:38,523 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:38,523 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1319994322] [2022-11-03 02:25:38,524 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1319994322] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:38,524 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [835281884] [2022-11-03 02:25:38,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:38,524 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:38,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:38,525 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:38,532 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (49)] Waiting until timeout for monitored process [2022-11-03 02:25:38,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:38,818 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:38,820 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:38,890 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:38,890 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:38,890 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [835281884] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:38,890 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:38,890 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:38,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2132309369] [2022-11-03 02:25:38,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:38,891 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:38,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:38,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:38,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:38,892 INFO L87 Difference]: Start difference. First operand 231 states and 285 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:39,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:39,017 INFO L93 Difference]: Finished difference Result 564 states and 703 transitions. [2022-11-03 02:25:39,018 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:39,018 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:39,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:39,020 INFO L225 Difference]: With dead ends: 564 [2022-11-03 02:25:39,020 INFO L226 Difference]: Without dead ends: 415 [2022-11-03 02:25:39,020 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:39,021 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 211 mSDsluCounter, 266 mSDsCounter, 0 mSdLazyCounter, 73 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 211 SdHoareTripleChecker+Valid, 483 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 73 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:39,021 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [211 Valid, 483 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 73 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:39,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 415 states. [2022-11-03 02:25:39,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 415 to 233. [2022-11-03 02:25:39,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233 states, 232 states have (on average 1.2327586206896552) internal successors, (286), 232 states have internal predecessors, (286), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:39,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 286 transitions. [2022-11-03 02:25:39,034 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 286 transitions. Word has length 111 [2022-11-03 02:25:39,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:39,034 INFO L495 AbstractCegarLoop]: Abstraction has 233 states and 286 transitions. [2022-11-03 02:25:39,034 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:39,034 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 286 transitions. [2022-11-03 02:25:39,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:39,035 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:39,036 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:39,048 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (48)] Ended with exit code 0 [2022-11-03 02:25:39,249 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (49)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:39,447 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 48 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,49 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:39,448 INFO L420 AbstractCegarLoop]: === Iteration 37 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:39,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:39,448 INFO L85 PathProgramCache]: Analyzing trace with hash -149591883, now seen corresponding path program 1 times [2022-11-03 02:25:39,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:39,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [780924932] [2022-11-03 02:25:39,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:39,449 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:39,449 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:39,450 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:39,453 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (50)] Waiting until timeout for monitored process [2022-11-03 02:25:39,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:39,640 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:39,642 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:39,812 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:39,812 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:39,951 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:39,951 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:39,952 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [780924932] [2022-11-03 02:25:39,953 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [780924932] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:39,953 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1825550374] [2022-11-03 02:25:39,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:39,953 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:39,953 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:39,954 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:39,961 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (51)] Waiting until timeout for monitored process [2022-11-03 02:25:40,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:40,247 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:40,250 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:40,318 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:40,318 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:40,318 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1825550374] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:40,319 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:40,319 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:40,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37679452] [2022-11-03 02:25:40,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:40,320 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:40,320 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:40,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:40,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:40,323 INFO L87 Difference]: Start difference. First operand 233 states and 286 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:40,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:40,450 INFO L93 Difference]: Finished difference Result 568 states and 703 transitions. [2022-11-03 02:25:40,450 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:40,451 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:40,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:40,452 INFO L225 Difference]: With dead ends: 568 [2022-11-03 02:25:40,452 INFO L226 Difference]: Without dead ends: 417 [2022-11-03 02:25:40,453 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:40,458 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 208 mSDsluCounter, 267 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 208 SdHoareTripleChecker+Valid, 484 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:40,458 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [208 Valid, 484 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 75 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:40,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417 states. [2022-11-03 02:25:40,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417 to 235. [2022-11-03 02:25:40,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235 states, 234 states have (on average 1.2264957264957266) internal successors, (287), 234 states have internal predecessors, (287), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:40,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 287 transitions. [2022-11-03 02:25:40,470 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 287 transitions. Word has length 111 [2022-11-03 02:25:40,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:40,471 INFO L495 AbstractCegarLoop]: Abstraction has 235 states and 287 transitions. [2022-11-03 02:25:40,471 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:40,471 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 287 transitions. [2022-11-03 02:25:40,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:40,472 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:40,472 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:40,475 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (51)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:40,687 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (50)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:40,875 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 51 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,50 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:40,875 INFO L420 AbstractCegarLoop]: === Iteration 38 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:40,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:40,875 INFO L85 PathProgramCache]: Analyzing trace with hash 1773636151, now seen corresponding path program 1 times [2022-11-03 02:25:40,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:40,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [872808635] [2022-11-03 02:25:40,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:40,876 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:40,876 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:40,877 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:40,878 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (52)] Waiting until timeout for monitored process [2022-11-03 02:25:41,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:41,071 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:41,073 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:41,243 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:41,244 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:41,382 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:41,382 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:41,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [872808635] [2022-11-03 02:25:41,382 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [872808635] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:41,382 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1753077341] [2022-11-03 02:25:41,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:41,382 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:41,382 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:41,383 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:41,385 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (53)] Waiting until timeout for monitored process [2022-11-03 02:25:41,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:41,673 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 4 conjunts are in the unsatisfiable core [2022-11-03 02:25:41,675 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:41,737 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 46 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2022-11-03 02:25:41,737 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:25:41,738 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1753077341] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:25:41,738 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-03 02:25:41,738 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 8] total 14 [2022-11-03 02:25:41,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194463174] [2022-11-03 02:25:41,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:41,739 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:25:41,740 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:41,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:25:41,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2022-11-03 02:25:41,741 INFO L87 Difference]: Start difference. First operand 235 states and 287 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:41,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:41,858 INFO L93 Difference]: Finished difference Result 572 states and 703 transitions. [2022-11-03 02:25:41,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:25:41,859 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:41,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:41,859 INFO L225 Difference]: With dead ends: 572 [2022-11-03 02:25:41,860 INFO L226 Difference]: Without dead ends: 419 [2022-11-03 02:25:41,860 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 321 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=229, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:25:41,860 INFO L413 NwaCegarLoop]: 217 mSDtfsCounter, 205 mSDsluCounter, 268 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 205 SdHoareTripleChecker+Valid, 485 SdHoareTripleChecker+Invalid, 78 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:41,861 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [205 Valid, 485 Invalid, 78 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 77 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:41,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states. [2022-11-03 02:25:41,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 237. [2022-11-03 02:25:41,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 237 states, 236 states have (on average 1.2203389830508475) internal successors, (288), 236 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:41,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 288 transitions. [2022-11-03 02:25:41,872 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 288 transitions. Word has length 111 [2022-11-03 02:25:41,872 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:41,872 INFO L495 AbstractCegarLoop]: Abstraction has 237 states and 288 transitions. [2022-11-03 02:25:41,873 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:41,873 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 288 transitions. [2022-11-03 02:25:41,873 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:41,874 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:41,874 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:41,876 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (53)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:42,084 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (52)] Ended with exit code 0 [2022-11-03 02:25:42,276 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 53 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,52 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:42,276 INFO L420 AbstractCegarLoop]: === Iteration 39 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:42,277 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:42,277 INFO L85 PathProgramCache]: Analyzing trace with hash 1914184761, now seen corresponding path program 1 times [2022-11-03 02:25:42,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:42,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1842551344] [2022-11-03 02:25:42,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:42,278 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:42,278 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:42,279 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:42,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (54)] Waiting until timeout for monitored process [2022-11-03 02:25:42,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:42,469 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:42,471 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:42,698 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:42,698 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:42,859 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:42,860 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:42,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1842551344] [2022-11-03 02:25:42,860 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1842551344] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:42,860 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [198400930] [2022-11-03 02:25:42,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:42,860 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:42,860 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:42,863 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:42,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (55)] Waiting until timeout for monitored process [2022-11-03 02:25:43,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:43,239 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:43,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:43,395 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:43,395 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:43,496 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:43,496 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [198400930] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:43,496 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [458904876] [2022-11-03 02:25:43,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:43,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:43,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:25:43,497 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:25:43,498 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2022-11-03 02:25:43,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:43,674 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 02:25:43,675 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:43,834 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:43,834 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:43,941 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:43,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [458904876] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:43,941 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:25:43,942 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 11 [2022-11-03 02:25:43,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755823181] [2022-11-03 02:25:43,942 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:25:43,943 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-11-03 02:25:43,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:43,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-03 02:25:43,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2022-11-03 02:25:43,944 INFO L87 Difference]: Start difference. First operand 237 states and 288 transitions. Second operand has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:44,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:44,270 INFO L93 Difference]: Finished difference Result 832 states and 1037 transitions. [2022-11-03 02:25:44,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-03 02:25:44,271 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:44,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:44,275 INFO L225 Difference]: With dead ends: 832 [2022-11-03 02:25:44,275 INFO L226 Difference]: Without dead ends: 677 [2022-11-03 02:25:44,275 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 673 GetRequests, 651 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 67 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=168, Invalid=384, Unknown=0, NotChecked=0, Total=552 [2022-11-03 02:25:44,276 INFO L413 NwaCegarLoop]: 107 mSDtfsCounter, 1126 mSDsluCounter, 564 mSDsCounter, 0 mSdLazyCounter, 139 mSolverCounterSat, 28 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1126 SdHoareTripleChecker+Valid, 671 SdHoareTripleChecker+Invalid, 167 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 28 IncrementalHoareTripleChecker+Valid, 139 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:44,276 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1126 Valid, 671 Invalid, 167 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [28 Valid, 139 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:44,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 677 states. [2022-11-03 02:25:44,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 677 to 305. [2022-11-03 02:25:44,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 305 states, 304 states have (on average 1.2171052631578947) internal successors, (370), 304 states have internal predecessors, (370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:44,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 305 states to 305 states and 370 transitions. [2022-11-03 02:25:44,297 INFO L78 Accepts]: Start accepts. Automaton has 305 states and 370 transitions. Word has length 111 [2022-11-03 02:25:44,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:44,297 INFO L495 AbstractCegarLoop]: Abstraction has 305 states and 370 transitions. [2022-11-03 02:25:44,297 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:44,297 INFO L276 IsEmpty]: Start isEmpty. Operand 305 states and 370 transitions. [2022-11-03 02:25:44,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:44,298 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:44,299 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:44,315 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (54)] Forceful destruction successful, exit code 0 [2022-11-03 02:25:44,514 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (55)] Ended with exit code 0 [2022-11-03 02:25:44,732 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Ended with exit code 0 [2022-11-03 02:25:44,912 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 54 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,55 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,56 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:44,912 INFO L420 AbstractCegarLoop]: === Iteration 40 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:44,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:44,912 INFO L85 PathProgramCache]: Analyzing trace with hash 1016791483, now seen corresponding path program 1 times [2022-11-03 02:25:44,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:44,913 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [448744493] [2022-11-03 02:25:44,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:44,913 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:44,913 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:44,914 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:44,915 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (57)] Waiting until timeout for monitored process [2022-11-03 02:25:45,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:45,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:45,104 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:45,407 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 45 proven. 17 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:25:45,407 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:45,464 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:25:45,464 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:45,464 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [448744493] [2022-11-03 02:25:45,465 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [448744493] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:25:45,465 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:25:45,465 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2022-11-03 02:25:45,465 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1223465821] [2022-11-03 02:25:45,465 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:45,465 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:25:45,465 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:45,466 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:25:45,466 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:25:45,466 INFO L87 Difference]: Start difference. First operand 305 states and 370 transitions. Second operand has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:45,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:45,614 INFO L93 Difference]: Finished difference Result 571 states and 691 transitions. [2022-11-03 02:25:45,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:25:45,614 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:45,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:45,616 INFO L225 Difference]: With dead ends: 571 [2022-11-03 02:25:45,616 INFO L226 Difference]: Without dead ends: 352 [2022-11-03 02:25:45,617 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 230 GetRequests, 214 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2022-11-03 02:25:45,617 INFO L413 NwaCegarLoop]: 86 mSDtfsCounter, 387 mSDsluCounter, 275 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 387 SdHoareTripleChecker+Valid, 361 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:45,617 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [387 Valid, 361 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:45,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 352 states. [2022-11-03 02:25:45,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 352 to 268. [2022-11-03 02:25:45,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 267 states have (on average 1.2097378277153559) internal successors, (323), 267 states have internal predecessors, (323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:45,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 323 transitions. [2022-11-03 02:25:45,633 INFO L78 Accepts]: Start accepts. Automaton has 268 states and 323 transitions. Word has length 111 [2022-11-03 02:25:45,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:45,633 INFO L495 AbstractCegarLoop]: Abstraction has 268 states and 323 transitions. [2022-11-03 02:25:45,634 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:45,634 INFO L276 IsEmpty]: Start isEmpty. Operand 268 states and 323 transitions. [2022-11-03 02:25:45,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:45,635 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:45,635 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:45,648 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (57)] Ended with exit code 0 [2022-11-03 02:25:45,848 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 57 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:45,848 INFO L420 AbstractCegarLoop]: === Iteration 41 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:45,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:45,849 INFO L85 PathProgramCache]: Analyzing trace with hash -561807287, now seen corresponding path program 1 times [2022-11-03 02:25:45,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:45,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [102216914] [2022-11-03 02:25:45,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:45,849 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:45,849 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:45,850 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:45,851 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (58)] Waiting until timeout for monitored process [2022-11-03 02:25:46,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:46,040 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:25:46,042 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:46,344 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 45 proven. 17 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 02:25:46,344 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:46,386 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:25:46,386 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:46,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [102216914] [2022-11-03 02:25:46,386 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [102216914] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:25:46,386 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:25:46,386 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 10 [2022-11-03 02:25:46,387 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [64752456] [2022-11-03 02:25:46,387 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:25:46,387 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:25:46,387 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:46,390 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:25:46,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:25:46,391 INFO L87 Difference]: Start difference. First operand 268 states and 323 transitions. Second operand has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:46,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:25:46,512 INFO L93 Difference]: Finished difference Result 438 states and 529 transitions. [2022-11-03 02:25:46,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:25:46,512 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:25:46,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:25:46,514 INFO L225 Difference]: With dead ends: 438 [2022-11-03 02:25:46,514 INFO L226 Difference]: Without dead ends: 256 [2022-11-03 02:25:46,514 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 229 GetRequests, 216 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2022-11-03 02:25:46,514 INFO L413 NwaCegarLoop]: 132 mSDtfsCounter, 230 mSDsluCounter, 220 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 230 SdHoareTripleChecker+Valid, 352 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:25:46,515 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [230 Valid, 352 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 52 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:25:46,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2022-11-03 02:25:46,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 229. [2022-11-03 02:25:46,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229 states, 228 states have (on average 1.1885964912280702) internal successors, (271), 228 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:46,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 271 transitions. [2022-11-03 02:25:46,528 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 271 transitions. Word has length 111 [2022-11-03 02:25:46,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:25:46,528 INFO L495 AbstractCegarLoop]: Abstraction has 229 states and 271 transitions. [2022-11-03 02:25:46,529 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 17.5) internal successors, (105), 6 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:25:46,529 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 271 transitions. [2022-11-03 02:25:46,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:25:46,530 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:25:46,530 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:25:46,543 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (58)] Ended with exit code 0 [2022-11-03 02:25:46,743 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 58 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:25:46,743 INFO L420 AbstractCegarLoop]: === Iteration 42 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:25:46,743 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:25:46,743 INFO L85 PathProgramCache]: Analyzing trace with hash -1197940009, now seen corresponding path program 1 times [2022-11-03 02:25:46,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:25:46,744 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2066585934] [2022-11-03 02:25:46,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:46,744 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:25:46,744 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:25:46,745 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:25:46,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (59)] Waiting until timeout for monitored process [2022-11-03 02:25:46,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:46,932 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:25:46,933 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:47,231 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 27 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:47,232 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:47,628 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 27 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:47,629 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:25:47,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2066585934] [2022-11-03 02:25:47,629 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2066585934] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:47,629 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1295899246] [2022-11-03 02:25:47,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:47,629 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:25:47,630 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:25:47,631 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:25:47,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (60)] Waiting until timeout for monitored process [2022-11-03 02:25:47,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:47,997 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:25:47,999 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:48,571 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:48,571 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:49,049 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:49,050 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1295899246] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:49,050 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [643006958] [2022-11-03 02:25:49,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:25:49,050 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:25:49,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:25:49,051 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:25:49,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2022-11-03 02:25:49,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:25:49,220 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:25:49,222 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:25:49,828 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 4 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:49,828 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:25:50,357 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 4 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:25:50,357 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [643006958] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:25:50,357 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:25:50,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 12, 12, 12, 12] total 49 [2022-11-03 02:25:50,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599730908] [2022-11-03 02:25:50,358 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:25:50,359 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 49 states [2022-11-03 02:25:50,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:25:50,360 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2022-11-03 02:25:50,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=2235, Unknown=0, NotChecked=0, Total=2352 [2022-11-03 02:25:50,361 INFO L87 Difference]: Start difference. First operand 229 states and 271 transitions. Second operand has 49 states, 49 states have (on average 11.857142857142858) internal successors, (581), 49 states have internal predecessors, (581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:26:50,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:26:50,362 INFO L93 Difference]: Finished difference Result 11153 states and 14830 transitions. [2022-11-03 02:26:50,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 828 states. [2022-11-03 02:26:50,363 INFO L78 Accepts]: Start accepts. Automaton has has 49 states, 49 states have (on average 11.857142857142858) internal successors, (581), 49 states have internal predecessors, (581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:26:50,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:26:50,388 INFO L225 Difference]: With dead ends: 11153 [2022-11-03 02:26:50,388 INFO L226 Difference]: Without dead ends: 11010 [2022-11-03 02:26:50,431 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1487 GetRequests, 614 SyntacticMatches, 0 SemanticMatches, 873 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 353450 ImplicationChecksByTransitivity, 52.1s TimeCoverageRelationStatistics Valid=52587, Invalid=712163, Unknown=0, NotChecked=0, Total=764750 [2022-11-03 02:26:50,432 INFO L413 NwaCegarLoop]: 253 mSDtfsCounter, 51955 mSDsluCounter, 6878 mSDsCounter, 0 mSdLazyCounter, 4849 mSolverCounterSat, 5322 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 5.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 51955 SdHoareTripleChecker+Valid, 7131 SdHoareTripleChecker+Invalid, 13942 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 5322 IncrementalHoareTripleChecker+Valid, 4849 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 3771 IncrementalHoareTripleChecker+Unchecked, 6.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:26:50,432 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [51955 Valid, 7131 Invalid, 13942 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [5322 Valid, 4849 Invalid, 0 Unknown, 3771 Unchecked, 6.2s Time] [2022-11-03 02:26:50,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11010 states. [2022-11-03 02:26:50,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11010 to 990. [2022-11-03 02:26:50,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 990 states, 989 states have (on average 1.2163801820020221) internal successors, (1203), 989 states have internal predecessors, (1203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:26:50,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 990 states to 990 states and 1203 transitions. [2022-11-03 02:26:50,660 INFO L78 Accepts]: Start accepts. Automaton has 990 states and 1203 transitions. Word has length 111 [2022-11-03 02:26:50,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:26:50,661 INFO L495 AbstractCegarLoop]: Abstraction has 990 states and 1203 transitions. [2022-11-03 02:26:50,661 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 49 states, 49 states have (on average 11.857142857142858) internal successors, (581), 49 states have internal predecessors, (581), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:26:50,661 INFO L276 IsEmpty]: Start isEmpty. Operand 990 states and 1203 transitions. [2022-11-03 02:26:50,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:26:50,663 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:26:50,663 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:26:50,669 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (60)] Forceful destruction successful, exit code 0 [2022-11-03 02:26:50,889 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Ended with exit code 0 [2022-11-03 02:26:51,076 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (59)] Ended with exit code 0 [2022-11-03 02:26:51,268 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 60 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,61 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,59 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:26:51,268 INFO L420 AbstractCegarLoop]: === Iteration 43 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:26:51,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:26:51,269 INFO L85 PathProgramCache]: Analyzing trace with hash 1348906837, now seen corresponding path program 1 times [2022-11-03 02:26:51,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:26:51,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [464850426] [2022-11-03 02:26:51,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:26:51,270 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:26:51,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:26:51,270 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:26:51,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (62)] Waiting until timeout for monitored process [2022-11-03 02:26:51,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:26:51,467 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 76 conjunts are in the unsatisfiable core [2022-11-03 02:26:51,470 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:26:53,229 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:26:53,229 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:03,128 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:03,128 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:03,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [464850426] [2022-11-03 02:27:03,128 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [464850426] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:03,128 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1826368057] [2022-11-03 02:27:03,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:03,129 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:27:03,129 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:27:03,130 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:27:03,131 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (63)] Waiting until timeout for monitored process [2022-11-03 02:27:03,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:03,479 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 76 conjunts are in the unsatisfiable core [2022-11-03 02:27:03,482 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:04,414 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:04,414 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:05,729 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:05,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1826368057] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:05,730 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1890076426] [2022-11-03 02:27:05,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:05,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:27:05,730 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:27:05,733 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:27:05,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2022-11-03 02:27:05,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:05,925 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 79 conjunts are in the unsatisfiable core [2022-11-03 02:27:05,928 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:06,868 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:06,868 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:08,462 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:08,462 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1890076426] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:08,462 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:27:08,462 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 37, 37] total 72 [2022-11-03 02:27:08,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [132545054] [2022-11-03 02:27:08,462 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:27:08,463 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 72 states [2022-11-03 02:27:08,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:08,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2022-11-03 02:27:08,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=252, Invalid=4860, Unknown=0, NotChecked=0, Total=5112 [2022-11-03 02:27:08,464 INFO L87 Difference]: Start difference. First operand 990 states and 1203 transitions. Second operand has 72 states, 72 states have (on average 3.111111111111111) internal successors, (224), 72 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:20,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:20,270 INFO L93 Difference]: Finished difference Result 3005 states and 3862 transitions. [2022-11-03 02:27:20,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2022-11-03 02:27:20,271 INFO L78 Accepts]: Start accepts. Automaton has has 72 states, 72 states have (on average 3.111111111111111) internal successors, (224), 72 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:20,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:20,276 INFO L225 Difference]: With dead ends: 3005 [2022-11-03 02:27:20,276 INFO L226 Difference]: Without dead ends: 3003 [2022-11-03 02:27:20,279 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 744 GetRequests, 594 SyntacticMatches, 7 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4188 ImplicationChecksByTransitivity, 20.4s TimeCoverageRelationStatistics Valid=2141, Invalid=18739, Unknown=0, NotChecked=0, Total=20880 [2022-11-03 02:27:20,279 INFO L413 NwaCegarLoop]: 195 mSDtfsCounter, 1107 mSDsluCounter, 7569 mSDsCounter, 0 mSdLazyCounter, 1518 mSolverCounterSat, 60 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1107 SdHoareTripleChecker+Valid, 7764 SdHoareTripleChecker+Invalid, 4803 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 60 IncrementalHoareTripleChecker+Valid, 1518 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 3225 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:20,280 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1107 Valid, 7764 Invalid, 4803 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [60 Valid, 1518 Invalid, 0 Unknown, 3225 Unchecked, 1.3s Time] [2022-11-03 02:27:20,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3003 states. [2022-11-03 02:27:20,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3003 to 1397. [2022-11-03 02:27:20,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1397 states, 1396 states have (on average 1.2213467048710602) internal successors, (1705), 1396 states have internal predecessors, (1705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:20,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1397 states to 1397 states and 1705 transitions. [2022-11-03 02:27:20,418 INFO L78 Accepts]: Start accepts. Automaton has 1397 states and 1705 transitions. Word has length 111 [2022-11-03 02:27:20,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:20,419 INFO L495 AbstractCegarLoop]: Abstraction has 1397 states and 1705 transitions. [2022-11-03 02:27:20,419 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 72 states, 72 states have (on average 3.111111111111111) internal successors, (224), 72 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:20,419 INFO L276 IsEmpty]: Start isEmpty. Operand 1397 states and 1705 transitions. [2022-11-03 02:27:20,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:20,422 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:20,422 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:20,456 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:20,645 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (63)] Ended with exit code 0 [2022-11-03 02:27:20,851 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (62)] Ended with exit code 0 [2022-11-03 02:27:21,043 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 64 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,63 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,62 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:21,043 INFO L420 AbstractCegarLoop]: === Iteration 44 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:21,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:21,044 INFO L85 PathProgramCache]: Analyzing trace with hash 1550730771, now seen corresponding path program 1 times [2022-11-03 02:27:21,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:21,044 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1237028807] [2022-11-03 02:27:21,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:21,045 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:21,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:21,046 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:21,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (65)] Waiting until timeout for monitored process [2022-11-03 02:27:21,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:21,236 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:27:21,238 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:21,311 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 56 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 02:27:21,311 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:21,311 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:21,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1237028807] [2022-11-03 02:27:21,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1237028807] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:21,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:21,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:27:21,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100098160] [2022-11-03 02:27:21,312 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:21,312 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:27:21,312 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:21,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:27:21,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:27:21,313 INFO L87 Difference]: Start difference. First operand 1397 states and 1705 transitions. Second operand has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:21,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:21,493 INFO L93 Difference]: Finished difference Result 3107 states and 3866 transitions. [2022-11-03 02:27:21,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:27:21,493 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:21,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:21,496 INFO L225 Difference]: With dead ends: 3107 [2022-11-03 02:27:21,497 INFO L226 Difference]: Without dead ends: 1850 [2022-11-03 02:27:21,498 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:21,499 INFO L413 NwaCegarLoop]: 120 mSDtfsCounter, 263 mSDsluCounter, 163 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 263 SdHoareTripleChecker+Valid, 283 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:21,499 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [263 Valid, 283 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:27:21,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states. [2022-11-03 02:27:21,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 1397. [2022-11-03 02:27:21,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1397 states, 1396 states have (on average 1.2041547277936964) internal successors, (1681), 1396 states have internal predecessors, (1681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:21,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1397 states to 1397 states and 1681 transitions. [2022-11-03 02:27:21,601 INFO L78 Accepts]: Start accepts. Automaton has 1397 states and 1681 transitions. Word has length 111 [2022-11-03 02:27:21,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:21,602 INFO L495 AbstractCegarLoop]: Abstraction has 1397 states and 1681 transitions. [2022-11-03 02:27:21,602 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:21,602 INFO L276 IsEmpty]: Start isEmpty. Operand 1397 states and 1681 transitions. [2022-11-03 02:27:21,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:21,605 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:21,605 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:21,618 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (65)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:21,818 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 65 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:21,818 INFO L420 AbstractCegarLoop]: === Iteration 45 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:21,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:21,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1294513939, now seen corresponding path program 1 times [2022-11-03 02:27:21,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:21,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [805694452] [2022-11-03 02:27:21,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:21,820 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:21,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:21,821 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:21,824 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (66)] Waiting until timeout for monitored process [2022-11-03 02:27:22,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:22,014 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:27:22,015 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:22,085 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 52 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2022-11-03 02:27:22,085 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:22,085 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:22,085 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [805694452] [2022-11-03 02:27:22,086 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [805694452] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:22,086 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:22,086 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:27:22,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201570562] [2022-11-03 02:27:22,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:22,086 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:27:22,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:22,087 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:27:22,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:27:22,087 INFO L87 Difference]: Start difference. First operand 1397 states and 1681 transitions. Second operand has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:22,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:22,268 INFO L93 Difference]: Finished difference Result 3003 states and 3666 transitions. [2022-11-03 02:27:22,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:27:22,268 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:22,268 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:22,271 INFO L225 Difference]: With dead ends: 3003 [2022-11-03 02:27:22,271 INFO L226 Difference]: Without dead ends: 1746 [2022-11-03 02:27:22,272 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:22,273 INFO L413 NwaCegarLoop]: 116 mSDtfsCounter, 260 mSDsluCounter, 159 mSDsCounter, 0 mSdLazyCounter, 67 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 260 SdHoareTripleChecker+Valid, 275 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 67 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:22,273 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [260 Valid, 275 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 67 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:27:22,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1746 states. [2022-11-03 02:27:22,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1746 to 1397. [2022-11-03 02:27:22,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1397 states, 1396 states have (on average 1.1869627507163323) internal successors, (1657), 1396 states have internal predecessors, (1657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:22,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1397 states to 1397 states and 1657 transitions. [2022-11-03 02:27:22,441 INFO L78 Accepts]: Start accepts. Automaton has 1397 states and 1657 transitions. Word has length 111 [2022-11-03 02:27:22,441 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:22,441 INFO L495 AbstractCegarLoop]: Abstraction has 1397 states and 1657 transitions. [2022-11-03 02:27:22,442 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:22,442 INFO L276 IsEmpty]: Start isEmpty. Operand 1397 states and 1657 transitions. [2022-11-03 02:27:22,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:22,444 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:22,445 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:22,458 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (66)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:22,657 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 66 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:22,657 INFO L420 AbstractCegarLoop]: === Iteration 46 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:22,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:22,658 INFO L85 PathProgramCache]: Analyzing trace with hash -2049378603, now seen corresponding path program 1 times [2022-11-03 02:27:22,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:22,659 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1943715769] [2022-11-03 02:27:22,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:22,659 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:22,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:22,660 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:22,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (67)] Waiting until timeout for monitored process [2022-11-03 02:27:22,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:22,876 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:27:22,878 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:22,957 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 48 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2022-11-03 02:27:22,957 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:22,957 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:22,957 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1943715769] [2022-11-03 02:27:22,957 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1943715769] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:22,957 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:22,958 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:27:22,958 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [685130400] [2022-11-03 02:27:22,958 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:22,958 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:27:22,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:22,958 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:27:22,959 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:27:22,959 INFO L87 Difference]: Start difference. First operand 1397 states and 1657 transitions. Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:23,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:23,108 INFO L93 Difference]: Finished difference Result 2605 states and 3143 transitions. [2022-11-03 02:27:23,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:27:23,109 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:23,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:23,114 INFO L225 Difference]: With dead ends: 2605 [2022-11-03 02:27:23,114 INFO L226 Difference]: Without dead ends: 1348 [2022-11-03 02:27:23,116 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:23,116 INFO L413 NwaCegarLoop]: 112 mSDtfsCounter, 257 mSDsluCounter, 155 mSDsCounter, 0 mSdLazyCounter, 63 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 257 SdHoareTripleChecker+Valid, 267 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 63 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:23,116 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [257 Valid, 267 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 63 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:27:23,118 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1348 states. [2022-11-03 02:27:23,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1348 to 1137. [2022-11-03 02:27:23,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1137 states, 1136 states have (on average 1.1875) internal successors, (1349), 1136 states have internal predecessors, (1349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:23,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1137 states to 1137 states and 1349 transitions. [2022-11-03 02:27:23,211 INFO L78 Accepts]: Start accepts. Automaton has 1137 states and 1349 transitions. Word has length 111 [2022-11-03 02:27:23,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:23,211 INFO L495 AbstractCegarLoop]: Abstraction has 1137 states and 1349 transitions. [2022-11-03 02:27:23,211 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:23,212 INFO L276 IsEmpty]: Start isEmpty. Operand 1137 states and 1349 transitions. [2022-11-03 02:27:23,214 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:23,214 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:23,214 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:23,228 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (67)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:23,427 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 67 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:23,428 INFO L420 AbstractCegarLoop]: === Iteration 47 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:23,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:23,428 INFO L85 PathProgramCache]: Analyzing trace with hash 168963217, now seen corresponding path program 1 times [2022-11-03 02:27:23,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:23,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [404106503] [2022-11-03 02:27:23,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:23,429 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:23,429 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:23,429 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:23,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (68)] Waiting until timeout for monitored process [2022-11-03 02:27:23,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:23,618 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:27:23,620 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:23,770 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2022-11-03 02:27:23,770 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:23,770 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:23,770 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [404106503] [2022-11-03 02:27:23,770 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [404106503] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:23,770 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:23,770 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:27:23,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117013095] [2022-11-03 02:27:23,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:23,771 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:27:23,771 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:23,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:27:23,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:23,772 INFO L87 Difference]: Start difference. First operand 1137 states and 1349 transitions. Second operand has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:23,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:23,963 INFO L93 Difference]: Finished difference Result 2618 states and 3092 transitions. [2022-11-03 02:27:23,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:27:23,968 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:23,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:23,971 INFO L225 Difference]: With dead ends: 2618 [2022-11-03 02:27:23,971 INFO L226 Difference]: Without dead ends: 1589 [2022-11-03 02:27:23,972 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:27:23,974 INFO L413 NwaCegarLoop]: 109 mSDtfsCounter, 167 mSDsluCounter, 558 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 167 SdHoareTripleChecker+Valid, 667 SdHoareTripleChecker+Invalid, 95 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 30 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:23,974 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [167 Valid, 667 Invalid, 95 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 65 Invalid, 0 Unknown, 30 Unchecked, 0.1s Time] [2022-11-03 02:27:23,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1589 states. [2022-11-03 02:27:24,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1589 to 1105. [2022-11-03 02:27:24,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1105 states, 1104 states have (on average 1.1856884057971016) internal successors, (1309), 1104 states have internal predecessors, (1309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:24,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1105 states to 1105 states and 1309 transitions. [2022-11-03 02:27:24,037 INFO L78 Accepts]: Start accepts. Automaton has 1105 states and 1309 transitions. Word has length 111 [2022-11-03 02:27:24,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:24,038 INFO L495 AbstractCegarLoop]: Abstraction has 1105 states and 1309 transitions. [2022-11-03 02:27:24,038 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:24,038 INFO L276 IsEmpty]: Start isEmpty. Operand 1105 states and 1309 transitions. [2022-11-03 02:27:24,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:24,040 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:24,040 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:24,053 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (68)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:24,253 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 68 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:24,253 INFO L420 AbstractCegarLoop]: === Iteration 48 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:24,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:24,254 INFO L85 PathProgramCache]: Analyzing trace with hash -2107026797, now seen corresponding path program 1 times [2022-11-03 02:27:24,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:24,254 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1172756127] [2022-11-03 02:27:24,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:24,254 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:24,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:24,255 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:24,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (69)] Waiting until timeout for monitored process [2022-11-03 02:27:24,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:24,441 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:27:24,443 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:24,591 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2022-11-03 02:27:24,591 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:24,591 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:24,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1172756127] [2022-11-03 02:27:24,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1172756127] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:24,591 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:24,591 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:27:24,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [348346036] [2022-11-03 02:27:24,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:24,592 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:27:24,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:24,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:27:24,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:24,592 INFO L87 Difference]: Start difference. First operand 1105 states and 1309 transitions. Second operand has 8 states, 8 states have (on average 11.875) internal successors, (95), 8 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:24,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:24,766 INFO L93 Difference]: Finished difference Result 2370 states and 2808 transitions. [2022-11-03 02:27:24,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:27:24,766 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.875) internal successors, (95), 8 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:24,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:24,769 INFO L225 Difference]: With dead ends: 2370 [2022-11-03 02:27:24,769 INFO L226 Difference]: Without dead ends: 1349 [2022-11-03 02:27:24,770 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:27:24,771 INFO L413 NwaCegarLoop]: 106 mSDtfsCounter, 166 mSDsluCounter, 483 mSDsCounter, 0 mSdLazyCounter, 63 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 166 SdHoareTripleChecker+Valid, 589 SdHoareTripleChecker+Invalid, 86 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 63 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:24,771 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [166 Valid, 589 Invalid, 86 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 63 Invalid, 0 Unknown, 23 Unchecked, 0.1s Time] [2022-11-03 02:27:24,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1349 states. [2022-11-03 02:27:24,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1349 to 1081. [2022-11-03 02:27:24,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1081 states, 1080 states have (on average 1.1861111111111111) internal successors, (1281), 1080 states have internal predecessors, (1281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:24,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1081 states to 1081 states and 1281 transitions. [2022-11-03 02:27:24,952 INFO L78 Accepts]: Start accepts. Automaton has 1081 states and 1281 transitions. Word has length 111 [2022-11-03 02:27:24,952 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:24,952 INFO L495 AbstractCegarLoop]: Abstraction has 1081 states and 1281 transitions. [2022-11-03 02:27:24,952 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.875) internal successors, (95), 8 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:24,953 INFO L276 IsEmpty]: Start isEmpty. Operand 1081 states and 1281 transitions. [2022-11-03 02:27:24,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:24,955 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:24,955 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:24,968 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (69)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:25,168 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 69 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:25,168 INFO L420 AbstractCegarLoop]: === Iteration 49 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:25,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:25,169 INFO L85 PathProgramCache]: Analyzing trace with hash 354153557, now seen corresponding path program 1 times [2022-11-03 02:27:25,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:25,170 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2003315415] [2022-11-03 02:27:25,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:25,170 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:25,170 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:25,171 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:25,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (70)] Waiting until timeout for monitored process [2022-11-03 02:27:25,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:25,376 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:27:25,378 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:25,427 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 28 proven. 0 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2022-11-03 02:27:25,427 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:27:25,428 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:25,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2003315415] [2022-11-03 02:27:25,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2003315415] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:27:25,428 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:27:25,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:27:25,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [265100990] [2022-11-03 02:27:25,428 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:27:25,429 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:27:25,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:25,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:27:25,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:27:25,429 INFO L87 Difference]: Start difference. First operand 1081 states and 1281 transitions. Second operand has 5 states, 5 states have (on average 18.2) internal successors, (91), 5 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:25,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:25,573 INFO L93 Difference]: Finished difference Result 1656 states and 1955 transitions. [2022-11-03 02:27:25,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:27:25,573 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 18.2) internal successors, (91), 5 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:25,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:25,574 INFO L225 Difference]: With dead ends: 1656 [2022-11-03 02:27:25,574 INFO L226 Difference]: Without dead ends: 629 [2022-11-03 02:27:25,575 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 108 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:27:25,576 INFO L413 NwaCegarLoop]: 89 mSDtfsCounter, 243 mSDsluCounter, 128 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 243 SdHoareTripleChecker+Valid, 217 SdHoareTripleChecker+Invalid, 59 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:25,576 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [243 Valid, 217 Invalid, 59 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 59 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:27:25,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states. [2022-11-03 02:27:25,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 603. [2022-11-03 02:27:25,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 603 states, 602 states have (on average 1.1727574750830565) internal successors, (706), 602 states have internal predecessors, (706), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:25,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 603 states to 603 states and 706 transitions. [2022-11-03 02:27:25,629 INFO L78 Accepts]: Start accepts. Automaton has 603 states and 706 transitions. Word has length 111 [2022-11-03 02:27:25,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:25,630 INFO L495 AbstractCegarLoop]: Abstraction has 603 states and 706 transitions. [2022-11-03 02:27:25,630 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 18.2) internal successors, (91), 5 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:25,630 INFO L276 IsEmpty]: Start isEmpty. Operand 603 states and 706 transitions. [2022-11-03 02:27:25,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:25,631 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:25,631 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:25,645 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (70)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:25,845 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 70 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:25,845 INFO L420 AbstractCegarLoop]: === Iteration 50 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:25,845 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:25,845 INFO L85 PathProgramCache]: Analyzing trace with hash 298224557, now seen corresponding path program 1 times [2022-11-03 02:27:25,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:25,846 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [144447555] [2022-11-03 02:27:25,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:25,846 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:25,847 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:25,848 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:25,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (71)] Waiting until timeout for monitored process [2022-11-03 02:27:26,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:26,048 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:27:26,051 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:26,249 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:26,249 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:26,398 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:26,399 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:26,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [144447555] [2022-11-03 02:27:26,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [144447555] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:26,399 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [440805901] [2022-11-03 02:27:26,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:26,399 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:27:26,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:27:26,400 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:27:26,402 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (72)] Waiting until timeout for monitored process [2022-11-03 02:27:26,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:26,763 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:27:26,765 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:26,950 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:26,950 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:27,063 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:27,064 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [440805901] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:27,064 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1465797052] [2022-11-03 02:27:27,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:27,064 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:27:27,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:27:27,065 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:27:27,066 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2022-11-03 02:27:27,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:27,240 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:27:27,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:27,393 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:27,393 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:27,501 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 47 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:27,501 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1465797052] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:27,501 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:27:27,502 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 11 [2022-11-03 02:27:27,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047700056] [2022-11-03 02:27:27,502 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:27:27,503 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-11-03 02:27:27,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:27,503 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-11-03 02:27:27,503 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2022-11-03 02:27:27,504 INFO L87 Difference]: Start difference. First operand 603 states and 706 transitions. Second operand has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:27,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:27,825 INFO L93 Difference]: Finished difference Result 2061 states and 2432 transitions. [2022-11-03 02:27:27,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-03 02:27:27,825 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:27,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:27,827 INFO L225 Difference]: With dead ends: 2061 [2022-11-03 02:27:27,827 INFO L226 Difference]: Without dead ends: 1512 [2022-11-03 02:27:27,828 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 669 GetRequests, 651 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2022-11-03 02:27:27,828 INFO L413 NwaCegarLoop]: 171 mSDtfsCounter, 473 mSDsluCounter, 957 mSDsCounter, 0 mSdLazyCounter, 121 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 473 SdHoareTripleChecker+Valid, 1128 SdHoareTripleChecker+Invalid, 128 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:27,828 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [473 Valid, 1128 Invalid, 128 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 121 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:27:27,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1512 states. [2022-11-03 02:27:27,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1512 to 662. [2022-11-03 02:27:27,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 662 states, 661 states have (on average 1.161875945537065) internal successors, (768), 661 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:27,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 768 transitions. [2022-11-03 02:27:27,867 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 768 transitions. Word has length 111 [2022-11-03 02:27:27,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:27,867 INFO L495 AbstractCegarLoop]: Abstraction has 662 states and 768 transitions. [2022-11-03 02:27:27,867 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 13.363636363636363) internal successors, (147), 11 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:27,867 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 768 transitions. [2022-11-03 02:27:27,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:27,868 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:27,868 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:27,871 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (72)] Ended with exit code 0 [2022-11-03 02:27:28,077 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (71)] Ended with exit code 0 [2022-11-03 02:27:28,290 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Ended with exit code 0 [2022-11-03 02:27:28,468 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 72 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,71 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,73 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:27:28,469 INFO L420 AbstractCegarLoop]: === Iteration 51 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:28,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:28,469 INFO L85 PathProgramCache]: Analyzing trace with hash -599168721, now seen corresponding path program 1 times [2022-11-03 02:27:28,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:28,470 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1069501238] [2022-11-03 02:27:28,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:28,470 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:28,470 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:28,471 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:28,472 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (74)] Waiting until timeout for monitored process [2022-11-03 02:27:28,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:28,657 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-03 02:27:28,659 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:29,082 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:29,082 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:29,458 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:29,459 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:29,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1069501238] [2022-11-03 02:27:29,459 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1069501238] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:29,459 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1362388987] [2022-11-03 02:27:29,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:29,459 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:27:29,459 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:27:29,460 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:27:29,462 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (75)] Waiting until timeout for monitored process [2022-11-03 02:27:29,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:29,825 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 18 conjunts are in the unsatisfiable core [2022-11-03 02:27:29,826 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:30,183 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:30,184 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:30,393 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 8 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:30,394 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1362388987] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:30,394 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2120431805] [2022-11-03 02:27:30,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:30,394 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:27:30,394 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:27:30,395 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:27:30,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2022-11-03 02:27:30,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:30,631 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:27:30,633 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:31,140 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 4 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:31,140 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:31,575 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 4 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:31,578 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2120431805] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:31,579 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:27:31,579 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12, 12] total 38 [2022-11-03 02:27:31,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256495876] [2022-11-03 02:27:31,579 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:27:31,580 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-11-03 02:27:31,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:31,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-03 02:27:31,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=1317, Unknown=0, NotChecked=0, Total=1406 [2022-11-03 02:27:31,581 INFO L87 Difference]: Start difference. First operand 662 states and 768 transitions. Second operand has 38 states, 38 states have (on average 10.236842105263158) internal successors, (389), 38 states have internal predecessors, (389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:34,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:27:34,328 INFO L93 Difference]: Finished difference Result 2753 states and 3320 transitions. [2022-11-03 02:27:34,328 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2022-11-03 02:27:34,328 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 10.236842105263158) internal successors, (389), 38 states have internal predecessors, (389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:27:34,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:27:34,331 INFO L225 Difference]: With dead ends: 2753 [2022-11-03 02:27:34,331 INFO L226 Difference]: Without dead ends: 2204 [2022-11-03 02:27:34,332 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 707 GetRequests, 624 SyntacticMatches, 0 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1377 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1431, Invalid=5709, Unknown=0, NotChecked=0, Total=7140 [2022-11-03 02:27:34,333 INFO L413 NwaCegarLoop]: 218 mSDtfsCounter, 2399 mSDsluCounter, 4002 mSDsCounter, 0 mSdLazyCounter, 718 mSolverCounterSat, 91 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2399 SdHoareTripleChecker+Valid, 4220 SdHoareTripleChecker+Invalid, 809 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 91 IncrementalHoareTripleChecker+Valid, 718 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 02:27:34,333 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2399 Valid, 4220 Invalid, 809 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [91 Valid, 718 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-03 02:27:34,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2204 states. [2022-11-03 02:27:34,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2204 to 645. [2022-11-03 02:27:34,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 645 states, 644 states have (on average 1.1645962732919255) internal successors, (750), 644 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:34,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 645 states and 750 transitions. [2022-11-03 02:27:34,373 INFO L78 Accepts]: Start accepts. Automaton has 645 states and 750 transitions. Word has length 111 [2022-11-03 02:27:34,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:27:34,373 INFO L495 AbstractCegarLoop]: Abstraction has 645 states and 750 transitions. [2022-11-03 02:27:34,373 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 10.236842105263158) internal successors, (389), 38 states have internal predecessors, (389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:27:34,373 INFO L276 IsEmpty]: Start isEmpty. Operand 645 states and 750 transitions. [2022-11-03 02:27:34,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:27:34,374 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:27:34,375 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 02:27:34,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:34,594 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (75)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:34,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (74)] Forceful destruction successful, exit code 0 [2022-11-03 02:27:34,991 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 76 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,75 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,74 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:27:34,991 INFO L420 AbstractCegarLoop]: === Iteration 52 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:27:34,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:27:34,991 INFO L85 PathProgramCache]: Analyzing trace with hash -541850837, now seen corresponding path program 1 times [2022-11-03 02:27:34,992 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:27:34,992 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1630980615] [2022-11-03 02:27:34,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:34,992 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:27:34,992 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:27:34,999 INFO L229 MonitoredProcess]: Starting monitored process 77 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:27:35,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (77)] Waiting until timeout for monitored process [2022-11-03 02:27:35,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:35,232 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 94 conjunts are in the unsatisfiable core [2022-11-03 02:27:35,237 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:38,197 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:38,198 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:50,576 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:50,577 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:27:50,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1630980615] [2022-11-03 02:27:50,577 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1630980615] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:50,577 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2043128378] [2022-11-03 02:27:50,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:50,577 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:27:50,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:27:50,578 INFO L229 MonitoredProcess]: Starting monitored process 78 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:27:50,579 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (78)] Waiting until timeout for monitored process [2022-11-03 02:27:50,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:50,939 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 94 conjunts are in the unsatisfiable core [2022-11-03 02:27:50,942 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:52,281 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:52,281 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:53,713 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:53,713 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [2043128378] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:53,713 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [498429613] [2022-11-03 02:27:53,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:27:53,714 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:27:53,714 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:27:53,715 INFO L229 MonitoredProcess]: Starting monitored process 79 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:27:53,716 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Waiting until timeout for monitored process [2022-11-03 02:27:53,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:27:53,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 97 conjunts are in the unsatisfiable core [2022-11-03 02:27:53,957 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:27:55,470 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:55,470 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:27:57,270 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:27:57,271 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [498429613] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:27:57,271 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:27:57,271 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 39, 39] total 76 [2022-11-03 02:27:57,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [571048509] [2022-11-03 02:27:57,271 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:27:57,272 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 76 states [2022-11-03 02:27:57,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:27:57,272 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2022-11-03 02:27:57,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=5510, Unknown=0, NotChecked=0, Total=5700 [2022-11-03 02:27:57,273 INFO L87 Difference]: Start difference. First operand 645 states and 750 transitions. Second operand has 76 states, 76 states have (on average 2.9473684210526314) internal successors, (224), 76 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:10,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:10,647 INFO L93 Difference]: Finished difference Result 1249 states and 1482 transitions. [2022-11-03 02:28:10,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2022-11-03 02:28:10,647 INFO L78 Accepts]: Start accepts. Automaton has has 76 states, 76 states have (on average 2.9473684210526314) internal successors, (224), 76 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:28:10,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:10,648 INFO L225 Difference]: With dead ends: 1249 [2022-11-03 02:28:10,648 INFO L226 Difference]: Without dead ends: 1247 [2022-11-03 02:28:10,650 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 717 GetRequests, 586 SyntacticMatches, 4 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2021 ImplicationChecksByTransitivity, 25.4s TimeCoverageRelationStatistics Valid=1879, Invalid=14633, Unknown=0, NotChecked=0, Total=16512 [2022-11-03 02:28:10,651 INFO L413 NwaCegarLoop]: 81 mSDtfsCounter, 1524 mSDsluCounter, 5473 mSDsCounter, 0 mSdLazyCounter, 1231 mSolverCounterSat, 97 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1524 SdHoareTripleChecker+Valid, 5554 SdHoareTripleChecker+Invalid, 3528 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 97 IncrementalHoareTripleChecker+Valid, 1231 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 2200 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:10,651 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1524 Valid, 5554 Invalid, 3528 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [97 Valid, 1231 Invalid, 0 Unknown, 2200 Unchecked, 1.1s Time] [2022-11-03 02:28:10,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1247 states. [2022-11-03 02:28:10,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1247 to 657. [2022-11-03 02:28:10,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 657 states, 656 states have (on average 1.1615853658536586) internal successors, (762), 656 states have internal predecessors, (762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:10,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 657 states to 657 states and 762 transitions. [2022-11-03 02:28:10,705 INFO L78 Accepts]: Start accepts. Automaton has 657 states and 762 transitions. Word has length 111 [2022-11-03 02:28:10,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:10,705 INFO L495 AbstractCegarLoop]: Abstraction has 657 states and 762 transitions. [2022-11-03 02:28:10,705 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 76 states, 76 states have (on average 2.9473684210526314) internal successors, (224), 76 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:10,705 INFO L276 IsEmpty]: Start isEmpty. Operand 657 states and 762 transitions. [2022-11-03 02:28:10,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-11-03 02:28:10,706 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:10,706 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:10,709 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (78)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:10,928 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Ended with exit code 0 [2022-11-03 02:28:11,119 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (77)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:11,307 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 78 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,79 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,77 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:11,307 INFO L420 AbstractCegarLoop]: === Iteration 53 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:11,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:11,308 INFO L85 PathProgramCache]: Analyzing trace with hash -618751635, now seen corresponding path program 1 times [2022-11-03 02:28:11,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:11,308 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1679528914] [2022-11-03 02:28:11,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:11,308 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:11,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:11,309 INFO L229 MonitoredProcess]: Starting monitored process 80 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:11,310 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (80)] Waiting until timeout for monitored process [2022-11-03 02:28:11,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:11,496 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:28:11,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:11,660 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 44 proven. 0 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2022-11-03 02:28:11,660 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:28:11,660 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:11,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1679528914] [2022-11-03 02:28:11,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1679528914] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:28:11,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:28:11,661 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:28:11,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262274304] [2022-11-03 02:28:11,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:11,661 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:28:11,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:11,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:28:11,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:28:11,662 INFO L87 Difference]: Start difference. First operand 657 states and 762 transitions. Second operand has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:11,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:11,795 INFO L93 Difference]: Finished difference Result 1337 states and 1551 transitions. [2022-11-03 02:28:11,796 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:28:11,796 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 111 [2022-11-03 02:28:11,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:11,797 INFO L225 Difference]: With dead ends: 1337 [2022-11-03 02:28:11,797 INFO L226 Difference]: Without dead ends: 776 [2022-11-03 02:28:11,797 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 113 GetRequests, 104 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=82, Unknown=0, NotChecked=0, Total=110 [2022-11-03 02:28:11,798 INFO L413 NwaCegarLoop]: 106 mSDtfsCounter, 75 mSDsluCounter, 575 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 75 SdHoareTripleChecker+Valid, 681 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:11,798 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [75 Valid, 681 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 43 Invalid, 0 Unknown, 50 Unchecked, 0.0s Time] [2022-11-03 02:28:11,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states. [2022-11-03 02:28:11,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 645. [2022-11-03 02:28:11,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 645 states, 644 states have (on average 1.1630434782608696) internal successors, (749), 644 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:11,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 645 states to 645 states and 749 transitions. [2022-11-03 02:28:11,833 INFO L78 Accepts]: Start accepts. Automaton has 645 states and 749 transitions. Word has length 111 [2022-11-03 02:28:11,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:11,834 INFO L495 AbstractCegarLoop]: Abstraction has 645 states and 749 transitions. [2022-11-03 02:28:11,834 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:11,834 INFO L276 IsEmpty]: Start isEmpty. Operand 645 states and 749 transitions. [2022-11-03 02:28:11,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:11,835 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:11,835 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:11,850 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (80)] Ended with exit code 0 [2022-11-03 02:28:12,035 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 80 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:12,036 INFO L420 AbstractCegarLoop]: === Iteration 54 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:12,036 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:12,036 INFO L85 PathProgramCache]: Analyzing trace with hash 531220693, now seen corresponding path program 2 times [2022-11-03 02:28:12,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:12,036 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [880254158] [2022-11-03 02:28:12,036 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:28:12,036 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:12,037 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:12,037 INFO L229 MonitoredProcess]: Starting monitored process 81 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:12,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (81)] Waiting until timeout for monitored process [2022-11-03 02:28:12,275 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:28:12,275 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:28:12,286 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:28:12,288 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:12,589 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 114 proven. 37 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2022-11-03 02:28:12,589 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:12,671 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 145 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2022-11-03 02:28:12,672 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:12,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [880254158] [2022-11-03 02:28:12,672 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [880254158] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:28:12,672 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:28:12,672 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2022-11-03 02:28:12,672 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610431482] [2022-11-03 02:28:12,672 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:12,672 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:28:12,673 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:12,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:28:12,673 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:28:12,673 INFO L87 Difference]: Start difference. First operand 645 states and 749 transitions. Second operand has 6 states, 6 states have (on average 24.0) internal successors, (144), 6 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:12,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:12,869 INFO L93 Difference]: Finished difference Result 1399 states and 1629 transitions. [2022-11-03 02:28:12,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:28:12,870 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 24.0) internal successors, (144), 6 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:12,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:12,871 INFO L225 Difference]: With dead ends: 1399 [2022-11-03 02:28:12,871 INFO L226 Difference]: Without dead ends: 850 [2022-11-03 02:28:12,872 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2022-11-03 02:28:12,872 INFO L413 NwaCegarLoop]: 113 mSDtfsCounter, 339 mSDsluCounter, 269 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 339 SdHoareTripleChecker+Valid, 382 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:12,873 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [339 Valid, 382 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 71 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:28:12,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 850 states. [2022-11-03 02:28:12,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 850 to 637. [2022-11-03 02:28:12,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 637 states, 636 states have (on average 1.1525157232704402) internal successors, (733), 636 states have internal predecessors, (733), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:12,932 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 637 states to 637 states and 733 transitions. [2022-11-03 02:28:12,932 INFO L78 Accepts]: Start accepts. Automaton has 637 states and 733 transitions. Word has length 162 [2022-11-03 02:28:12,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:12,933 INFO L495 AbstractCegarLoop]: Abstraction has 637 states and 733 transitions. [2022-11-03 02:28:12,933 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 24.0) internal successors, (144), 6 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:12,933 INFO L276 IsEmpty]: Start isEmpty. Operand 637 states and 733 transitions. [2022-11-03 02:28:12,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:12,934 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:12,935 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:12,951 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (81)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:13,148 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 81 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:13,148 INFO L420 AbstractCegarLoop]: === Iteration 55 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:13,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:13,149 INFO L85 PathProgramCache]: Analyzing trace with hash -725623725, now seen corresponding path program 1 times [2022-11-03 02:28:13,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:13,149 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [713711637] [2022-11-03 02:28:13,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:13,149 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:13,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:13,150 INFO L229 MonitoredProcess]: Starting monitored process 82 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:13,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (82)] Waiting until timeout for monitored process [2022-11-03 02:28:13,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:13,404 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:28:13,406 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:13,723 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 114 proven. 33 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2022-11-03 02:28:13,723 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:13,799 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 141 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2022-11-03 02:28:13,799 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:13,799 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [713711637] [2022-11-03 02:28:13,799 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [713711637] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:28:13,799 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:28:13,800 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 12 [2022-11-03 02:28:13,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336817548] [2022-11-03 02:28:13,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:13,800 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:28:13,800 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:13,800 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:28:13,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=103, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:28:13,801 INFO L87 Difference]: Start difference. First operand 637 states and 733 transitions. Second operand has 6 states, 6 states have (on average 23.5) internal successors, (141), 6 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:13,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:13,960 INFO L93 Difference]: Finished difference Result 1108 states and 1277 transitions. [2022-11-03 02:28:13,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:28:13,960 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 23.5) internal successors, (141), 6 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:13,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:13,961 INFO L225 Difference]: With dead ends: 1108 [2022-11-03 02:28:13,961 INFO L226 Difference]: Without dead ends: 559 [2022-11-03 02:28:13,961 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 316 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=59, Invalid=213, Unknown=0, NotChecked=0, Total=272 [2022-11-03 02:28:13,962 INFO L413 NwaCegarLoop]: 102 mSDtfsCounter, 283 mSDsluCounter, 212 mSDsCounter, 0 mSdLazyCounter, 66 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 283 SdHoareTripleChecker+Valid, 314 SdHoareTripleChecker+Invalid, 68 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 66 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:13,962 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [283 Valid, 314 Invalid, 68 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 66 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:28:13,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states. [2022-11-03 02:28:13,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 485. [2022-11-03 02:28:13,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 484 states have (on average 1.1322314049586777) internal successors, (548), 484 states have internal predecessors, (548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:13,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 548 transitions. [2022-11-03 02:28:13,986 INFO L78 Accepts]: Start accepts. Automaton has 485 states and 548 transitions. Word has length 162 [2022-11-03 02:28:13,986 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:13,986 INFO L495 AbstractCegarLoop]: Abstraction has 485 states and 548 transitions. [2022-11-03 02:28:13,987 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 23.5) internal successors, (141), 6 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:13,987 INFO L276 IsEmpty]: Start isEmpty. Operand 485 states and 548 transitions. [2022-11-03 02:28:13,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:13,987 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:13,987 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:14,004 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (82)] Ended with exit code 0 [2022-11-03 02:28:14,188 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 82 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:14,188 INFO L420 AbstractCegarLoop]: === Iteration 56 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:14,188 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:14,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1293353557, now seen corresponding path program 3 times [2022-11-03 02:28:14,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:14,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [795055424] [2022-11-03 02:28:14,189 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-03 02:28:14,189 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:14,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:14,190 INFO L229 MonitoredProcess]: Starting monitored process 83 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:14,191 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (83)] Waiting until timeout for monitored process [2022-11-03 02:28:14,396 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-11-03 02:28:14,396 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:28:14,405 INFO L263 TraceCheckSpWp]: Trace formula consists of 588 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 02:28:14,408 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:14,565 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 122 proven. 17 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2022-11-03 02:28:14,566 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:14,635 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 139 proven. 0 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2022-11-03 02:28:14,635 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:14,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [795055424] [2022-11-03 02:28:14,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [795055424] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:28:14,635 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:28:14,635 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [7] total 11 [2022-11-03 02:28:14,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [197999602] [2022-11-03 02:28:14,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:28:14,636 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:28:14,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:14,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:28:14,636 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2022-11-03 02:28:14,637 INFO L87 Difference]: Start difference. First operand 485 states and 548 transitions. Second operand has 6 states, 6 states have (on average 23.333333333333332) internal successors, (140), 6 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:14,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:14,810 INFO L93 Difference]: Finished difference Result 811 states and 923 transitions. [2022-11-03 02:28:14,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:28:14,811 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 23.333333333333332) internal successors, (140), 6 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:14,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:14,811 INFO L225 Difference]: With dead ends: 811 [2022-11-03 02:28:14,812 INFO L226 Difference]: Without dead ends: 410 [2022-11-03 02:28:14,812 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 317 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=183, Unknown=0, NotChecked=0, Total=240 [2022-11-03 02:28:14,813 INFO L413 NwaCegarLoop]: 100 mSDtfsCounter, 278 mSDsluCounter, 208 mSDsCounter, 0 mSdLazyCounter, 63 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 278 SdHoareTripleChecker+Valid, 308 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 63 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:14,813 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [278 Valid, 308 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 63 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:28:14,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states. [2022-11-03 02:28:14,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 316. [2022-11-03 02:28:14,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 316 states, 315 states have (on average 1.1238095238095238) internal successors, (354), 315 states have internal predecessors, (354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:14,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 316 states to 316 states and 354 transitions. [2022-11-03 02:28:14,837 INFO L78 Accepts]: Start accepts. Automaton has 316 states and 354 transitions. Word has length 162 [2022-11-03 02:28:14,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:14,837 INFO L495 AbstractCegarLoop]: Abstraction has 316 states and 354 transitions. [2022-11-03 02:28:14,837 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 23.333333333333332) internal successors, (140), 6 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:14,837 INFO L276 IsEmpty]: Start isEmpty. Operand 316 states and 354 transitions. [2022-11-03 02:28:14,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:14,838 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:14,838 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:14,852 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (83)] Ended with exit code 0 [2022-11-03 02:28:15,049 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 83 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:28:15,049 INFO L420 AbstractCegarLoop]: === Iteration 57 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:15,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:15,049 INFO L85 PathProgramCache]: Analyzing trace with hash -596362385, now seen corresponding path program 1 times [2022-11-03 02:28:15,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:15,050 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1363813170] [2022-11-03 02:28:15,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:15,050 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:15,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:15,052 INFO L229 MonitoredProcess]: Starting monitored process 84 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:15,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (84)] Waiting until timeout for monitored process [2022-11-03 02:28:15,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:15,349 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:28:15,353 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:15,736 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:15,737 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:16,069 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:16,069 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:16,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1363813170] [2022-11-03 02:28:16,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1363813170] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:16,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [211122949] [2022-11-03 02:28:16,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:16,070 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:28:16,070 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:28:16,070 INFO L229 MonitoredProcess]: Starting monitored process 85 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:28:16,072 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (85)] Waiting until timeout for monitored process [2022-11-03 02:28:16,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:16,582 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:28:16,584 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:16,904 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:16,905 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:17,100 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:17,100 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [211122949] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:17,101 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1342582251] [2022-11-03 02:28:17,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:28:17,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:28:17,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:28:17,103 INFO L229 MonitoredProcess]: Starting monitored process 86 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:28:17,104 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (86)] Waiting until timeout for monitored process [2022-11-03 02:28:17,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:28:17,327 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 02:28:17,329 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:17,641 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:17,641 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:17,844 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 88 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:17,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1342582251] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:17,844 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:28:17,844 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12, 12] total 19 [2022-11-03 02:28:17,844 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1629758716] [2022-11-03 02:28:17,845 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:28:17,845 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-11-03 02:28:17,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:17,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-11-03 02:28:17,846 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=300, Unknown=0, NotChecked=0, Total=342 [2022-11-03 02:28:17,846 INFO L87 Difference]: Start difference. First operand 316 states and 354 transitions. Second operand has 19 states, 19 states have (on average 13.105263157894736) internal successors, (249), 19 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:19,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:28:19,008 INFO L93 Difference]: Finished difference Result 1763 states and 2002 transitions. [2022-11-03 02:28:19,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-11-03 02:28:19,009 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 13.105263157894736) internal successors, (249), 19 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:28:19,009 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:28:19,010 INFO L225 Difference]: With dead ends: 1763 [2022-11-03 02:28:19,011 INFO L226 Difference]: Without dead ends: 1499 [2022-11-03 02:28:19,011 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1002 GetRequests, 949 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 680 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=647, Invalid=2323, Unknown=0, NotChecked=0, Total=2970 [2022-11-03 02:28:19,012 INFO L413 NwaCegarLoop]: 150 mSDtfsCounter, 1878 mSDsluCounter, 1430 mSDsCounter, 0 mSdLazyCounter, 393 mSolverCounterSat, 88 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1878 SdHoareTripleChecker+Valid, 1580 SdHoareTripleChecker+Invalid, 481 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 88 IncrementalHoareTripleChecker+Valid, 393 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:28:19,012 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1878 Valid, 1580 Invalid, 481 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [88 Valid, 393 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 02:28:19,014 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1499 states. [2022-11-03 02:28:19,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1499 to 473. [2022-11-03 02:28:19,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 473 states, 472 states have (on average 1.1144067796610169) internal successors, (526), 472 states have internal predecessors, (526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:19,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 526 transitions. [2022-11-03 02:28:19,040 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 526 transitions. Word has length 162 [2022-11-03 02:28:19,040 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:28:19,041 INFO L495 AbstractCegarLoop]: Abstraction has 473 states and 526 transitions. [2022-11-03 02:28:19,041 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 13.105263157894736) internal successors, (249), 19 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:28:19,041 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 526 transitions. [2022-11-03 02:28:19,042 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:28:19,042 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:28:19,042 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:28:19,068 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (86)] Forceful destruction successful, exit code 0 [2022-11-03 02:28:19,252 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (84)] Ended with exit code 0 [2022-11-03 02:28:19,446 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (85)] Ended with exit code 0 [2022-11-03 02:28:19,643 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 86 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,84 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,85 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:28:19,643 INFO L420 AbstractCegarLoop]: === Iteration 58 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:28:19,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:28:19,643 INFO L85 PathProgramCache]: Analyzing trace with hash -1493755663, now seen corresponding path program 2 times [2022-11-03 02:28:19,644 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:28:19,644 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1706528367] [2022-11-03 02:28:19,644 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:28:19,644 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:28:19,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:28:19,645 INFO L229 MonitoredProcess]: Starting monitored process 87 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:28:19,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (87)] Waiting until timeout for monitored process [2022-11-03 02:28:19,886 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:28:19,886 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:28:19,898 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-03 02:28:19,900 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:20,575 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 12 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:20,575 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:21,243 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 12 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:21,244 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:28:21,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1706528367] [2022-11-03 02:28:21,244 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1706528367] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:21,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [788256124] [2022-11-03 02:28:21,244 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:28:21,244 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:28:21,244 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:28:21,245 INFO L229 MonitoredProcess]: Starting monitored process 88 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:28:21,248 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (88)] Waiting until timeout for monitored process [2022-11-03 02:28:21,733 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:28:21,733 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:28:21,759 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-03 02:28:21,761 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:22,210 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 12 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:22,211 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:22,506 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 12 proven. 159 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:22,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [788256124] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:22,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [556606147] [2022-11-03 02:28:22,506 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:28:22,507 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:28:22,507 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:28:22,508 INFO L229 MonitoredProcess]: Starting monitored process 89 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:28:22,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (89)] Waiting until timeout for monitored process [2022-11-03 02:28:22,725 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:28:22,725 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:28:22,730 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-03 02:28:22,732 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:28:23,607 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 6 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:23,607 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:28:24,454 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 6 proven. 165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:28:24,454 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [556606147] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:28:24,454 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:28:24,455 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16, 16] total 54 [2022-11-03 02:28:24,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046765347] [2022-11-03 02:28:24,455 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:28:24,455 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 54 states [2022-11-03 02:28:24,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:28:24,456 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2022-11-03 02:28:24,456 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=2733, Unknown=0, NotChecked=0, Total=2862 [2022-11-03 02:28:24,456 INFO L87 Difference]: Start difference. First operand 473 states and 526 transitions. Second operand has 54 states, 54 states have (on average 10.981481481481481) internal successors, (593), 54 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:29:08,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:29:08,364 INFO L93 Difference]: Finished difference Result 10853 states and 12414 transitions. [2022-11-03 02:29:08,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 518 states. [2022-11-03 02:29:08,365 INFO L78 Accepts]: Start accepts. Automaton has has 54 states, 54 states have (on average 10.981481481481481) internal successors, (593), 54 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:29:08,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:29:08,376 INFO L225 Difference]: With dead ends: 10853 [2022-11-03 02:29:08,376 INFO L226 Difference]: Without dead ends: 10432 [2022-11-03 02:29:08,395 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1482 GetRequests, 914 SyntacticMatches, 0 SemanticMatches, 568 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 141055 ImplicationChecksByTransitivity, 34.9s TimeCoverageRelationStatistics Valid=31370, Invalid=292960, Unknown=0, NotChecked=0, Total=324330 [2022-11-03 02:29:08,395 INFO L413 NwaCegarLoop]: 250 mSDtfsCounter, 15291 mSDsluCounter, 10556 mSDsCounter, 0 mSdLazyCounter, 9536 mSolverCounterSat, 1992 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15291 SdHoareTripleChecker+Valid, 10806 SdHoareTripleChecker+Invalid, 11528 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.1s SdHoareTripleChecker+Time, 1992 IncrementalHoareTripleChecker+Valid, 9536 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 8.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:29:08,396 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15291 Valid, 10806 Invalid, 11528 Unknown, 0 Unchecked, 0.1s Time], IncrementalHoareTripleChecker [1992 Valid, 9536 Invalid, 0 Unknown, 0 Unchecked, 8.3s Time] [2022-11-03 02:29:08,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10432 states. [2022-11-03 02:29:08,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10432 to 1523. [2022-11-03 02:29:08,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1523 states, 1522 states have (on average 1.092641261498029) internal successors, (1663), 1522 states have internal predecessors, (1663), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:29:08,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1523 states to 1523 states and 1663 transitions. [2022-11-03 02:29:08,590 INFO L78 Accepts]: Start accepts. Automaton has 1523 states and 1663 transitions. Word has length 162 [2022-11-03 02:29:08,590 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:29:08,590 INFO L495 AbstractCegarLoop]: Abstraction has 1523 states and 1663 transitions. [2022-11-03 02:29:08,590 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 54 states, 54 states have (on average 10.981481481481481) internal successors, (593), 54 states have internal predecessors, (593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:29:08,590 INFO L276 IsEmpty]: Start isEmpty. Operand 1523 states and 1663 transitions. [2022-11-03 02:29:08,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:29:08,593 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:29:08,593 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:29:08,610 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (87)] Ended with exit code 0 [2022-11-03 02:29:08,829 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (89)] Ended with exit code 0 [2022-11-03 02:29:09,010 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (88)] Forceful destruction successful, exit code 0 [2022-11-03 02:29:09,207 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 87 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,89 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,88 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:29:09,207 INFO L420 AbstractCegarLoop]: === Iteration 59 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:29:09,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:29:09,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1436437779, now seen corresponding path program 1 times [2022-11-03 02:29:09,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:29:09,208 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [590293060] [2022-11-03 02:29:09,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:29:09,208 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:29:09,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:29:09,209 INFO L229 MonitoredProcess]: Starting monitored process 90 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:29:09,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (90)] Waiting until timeout for monitored process [2022-11-03 02:29:09,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:29:09,464 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 112 conjunts are in the unsatisfiable core [2022-11-03 02:29:09,467 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:29:13,666 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:13,666 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:29:38,876 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 51 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:38,876 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:29:38,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [590293060] [2022-11-03 02:29:38,876 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [590293060] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:29:38,876 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1249408847] [2022-11-03 02:29:38,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:29:38,876 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:29:38,876 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:29:38,877 INFO L229 MonitoredProcess]: Starting monitored process 91 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:29:38,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (91)] Waiting until timeout for monitored process [2022-11-03 02:29:39,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:29:39,395 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 112 conjunts are in the unsatisfiable core [2022-11-03 02:29:39,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:29:41,190 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:41,191 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:29:43,035 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 51 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:43,036 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1249408847] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:29:43,036 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1668733357] [2022-11-03 02:29:43,036 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:29:43,036 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:29:43,036 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:29:43,043 INFO L229 MonitoredProcess]: Starting monitored process 92 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:29:43,044 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (92)] Waiting until timeout for monitored process [2022-11-03 02:29:43,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:29:43,264 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 115 conjunts are in the unsatisfiable core [2022-11-03 02:29:43,269 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:29:45,326 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:45,326 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:29:47,535 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 51 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:29:47,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1668733357] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:29:47,535 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:29:47,535 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 56, 56] total 110 [2022-11-03 02:29:47,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260035458] [2022-11-03 02:29:47,535 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:29:47,536 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 110 states [2022-11-03 02:29:47,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:29:47,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2022-11-03 02:29:47,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=510, Invalid=11480, Unknown=0, NotChecked=0, Total=11990 [2022-11-03 02:29:47,537 INFO L87 Difference]: Start difference. First operand 1523 states and 1663 transitions. Second operand has 110 states, 110 states have (on average 2.963636363636364) internal successors, (326), 110 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:24,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:24,322 INFO L93 Difference]: Finished difference Result 4479 states and 4931 transitions. [2022-11-03 02:31:24,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 201 states. [2022-11-03 02:31:24,323 INFO L78 Accepts]: Start accepts. Automaton has has 110 states, 110 states have (on average 2.963636363636364) internal successors, (326), 110 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:24,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:24,326 INFO L225 Difference]: With dead ends: 4479 [2022-11-03 02:31:24,326 INFO L226 Difference]: Without dead ends: 4477 [2022-11-03 02:31:24,329 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1196 GetRequests, 894 SyntacticMatches, 7 SemanticMatches, 295 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22695 ImplicationChecksByTransitivity, 120.5s TimeCoverageRelationStatistics Valid=4041, Invalid=83871, Unknown=0, NotChecked=0, Total=87912 [2022-11-03 02:31:24,330 INFO L413 NwaCegarLoop]: 179 mSDtfsCounter, 2079 mSDsluCounter, 13268 mSDsCounter, 0 mSdLazyCounter, 2770 mSolverCounterSat, 58 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2079 SdHoareTripleChecker+Valid, 13447 SdHoareTripleChecker+Invalid, 15119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 58 IncrementalHoareTripleChecker+Valid, 2770 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 12291 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:24,330 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2079 Valid, 13447 Invalid, 15119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [58 Valid, 2770 Invalid, 0 Unknown, 12291 Unchecked, 2.3s Time] [2022-11-03 02:31:24,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4477 states. [2022-11-03 02:31:24,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4477 to 2422. [2022-11-03 02:31:24,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2422 states, 2421 states have (on average 1.10119785212722) internal successors, (2666), 2421 states have internal predecessors, (2666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:24,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2422 states to 2422 states and 2666 transitions. [2022-11-03 02:31:24,605 INFO L78 Accepts]: Start accepts. Automaton has 2422 states and 2666 transitions. Word has length 162 [2022-11-03 02:31:24,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:24,605 INFO L495 AbstractCegarLoop]: Abstraction has 2422 states and 2666 transitions. [2022-11-03 02:31:24,605 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 110 states, 110 states have (on average 2.963636363636364) internal successors, (326), 110 states have internal predecessors, (326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:24,606 INFO L276 IsEmpty]: Start isEmpty. Operand 2422 states and 2666 transitions. [2022-11-03 02:31:24,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:24,610 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:24,610 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:24,626 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (90)] Ended with exit code 0 [2022-11-03 02:31:24,832 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (92)] Ended with exit code 0 [2022-11-03 02:31:25,014 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (91)] Forceful destruction successful, exit code 0 [2022-11-03 02:31:25,211 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 90 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,92 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,91 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 02:31:25,211 INFO L420 AbstractCegarLoop]: === Iteration 60 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:25,211 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:25,212 INFO L85 PathProgramCache]: Analyzing trace with hash -1513338577, now seen corresponding path program 2 times [2022-11-03 02:31:25,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:25,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [623597172] [2022-11-03 02:31:25,212 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:31:25,212 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:25,212 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:25,213 INFO L229 MonitoredProcess]: Starting monitored process 93 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:25,214 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (93)] Waiting until timeout for monitored process [2022-11-03 02:31:25,449 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:31:25,449 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-03 02:31:25,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:31:25,462 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:25,794 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 114 proven. 37 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2022-11-03 02:31:25,795 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:31:25,869 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 145 proven. 0 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2022-11-03 02:31:25,869 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:25,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [623597172] [2022-11-03 02:31:25,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [623597172] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 02:31:25,869 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 02:31:25,869 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [8] total 10 [2022-11-03 02:31:25,869 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1819096260] [2022-11-03 02:31:25,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:25,870 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:31:25,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:25,870 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:31:25,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:31:25,871 INFO L87 Difference]: Start difference. First operand 2422 states and 2666 transitions. Second operand has 6 states, 6 states have (on average 23.0) internal successors, (138), 6 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:26,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:26,202 INFO L93 Difference]: Finished difference Result 4388 states and 4830 transitions. [2022-11-03 02:31:26,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:31:26,202 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 23.0) internal successors, (138), 6 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:26,203 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:26,205 INFO L225 Difference]: With dead ends: 4388 [2022-11-03 02:31:26,205 INFO L226 Difference]: Without dead ends: 2430 [2022-11-03 02:31:26,207 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2022-11-03 02:31:26,207 INFO L413 NwaCegarLoop]: 163 mSDtfsCounter, 214 mSDsluCounter, 253 mSDsCounter, 0 mSdLazyCounter, 73 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 214 SdHoareTripleChecker+Valid, 416 SdHoareTripleChecker+Invalid, 74 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 73 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:26,207 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [214 Valid, 416 Invalid, 74 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 73 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:31:26,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2430 states. [2022-11-03 02:31:26,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2430 to 2194. [2022-11-03 02:31:26,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2194 states, 2193 states have (on average 1.0939352485180118) internal successors, (2399), 2193 states have internal predecessors, (2399), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:26,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2194 states to 2194 states and 2399 transitions. [2022-11-03 02:31:26,420 INFO L78 Accepts]: Start accepts. Automaton has 2194 states and 2399 transitions. Word has length 162 [2022-11-03 02:31:26,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:26,420 INFO L495 AbstractCegarLoop]: Abstraction has 2194 states and 2399 transitions. [2022-11-03 02:31:26,421 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 23.0) internal successors, (138), 6 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:26,421 INFO L276 IsEmpty]: Start isEmpty. Operand 2194 states and 2399 transitions. [2022-11-03 02:31:26,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:26,424 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:26,424 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:26,439 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (93)] Forceful destruction successful, exit code 0 [2022-11-03 02:31:26,639 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 93 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:26,639 INFO L420 AbstractCegarLoop]: === Iteration 61 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:26,639 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:26,639 INFO L85 PathProgramCache]: Analyzing trace with hash 290707183, now seen corresponding path program 1 times [2022-11-03 02:31:26,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:26,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [843704848] [2022-11-03 02:31:26,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:26,640 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:26,640 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:26,641 INFO L229 MonitoredProcess]: Starting monitored process 94 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:26,642 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (94)] Waiting until timeout for monitored process [2022-11-03 02:31:26,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:26,885 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:31:26,887 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:26,958 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 102 proven. 0 refuted. 0 times theorem prover too weak. 69 trivial. 0 not checked. [2022-11-03 02:31:26,958 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:26,958 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:26,958 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [843704848] [2022-11-03 02:31:26,959 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [843704848] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:26,959 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:26,959 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:31:26,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1186664842] [2022-11-03 02:31:26,959 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:26,959 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:31:26,959 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:26,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:31:26,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:31:26,960 INFO L87 Difference]: Start difference. First operand 2194 states and 2399 transitions. Second operand has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:27,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:27,217 INFO L93 Difference]: Finished difference Result 4420 states and 4823 transitions. [2022-11-03 02:31:27,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:31:27,218 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:27,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:27,220 INFO L225 Difference]: With dead ends: 4420 [2022-11-03 02:31:27,220 INFO L226 Difference]: Without dead ends: 2480 [2022-11-03 02:31:27,221 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:27,221 INFO L413 NwaCegarLoop]: 118 mSDtfsCounter, 235 mSDsluCounter, 158 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 235 SdHoareTripleChecker+Valid, 276 SdHoareTripleChecker+Invalid, 69 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:27,221 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [235 Valid, 276 Invalid, 69 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 69 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:31:27,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2480 states. [2022-11-03 02:31:27,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2480 to 2186. [2022-11-03 02:31:27,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2186 states, 2185 states have (on average 1.0842105263157895) internal successors, (2369), 2185 states have internal predecessors, (2369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:27,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2186 states to 2186 states and 2369 transitions. [2022-11-03 02:31:27,412 INFO L78 Accepts]: Start accepts. Automaton has 2186 states and 2369 transitions. Word has length 162 [2022-11-03 02:31:27,412 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:27,412 INFO L495 AbstractCegarLoop]: Abstraction has 2186 states and 2369 transitions. [2022-11-03 02:31:27,413 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 21.0) internal successors, (105), 5 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:27,413 INFO L276 IsEmpty]: Start isEmpty. Operand 2186 states and 2369 transitions. [2022-11-03 02:31:27,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:27,414 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:27,415 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:27,427 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (94)] Forceful destruction successful, exit code 0 [2022-11-03 02:31:27,615 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 94 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:27,615 INFO L420 AbstractCegarLoop]: === Iteration 62 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:27,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:27,616 INFO L85 PathProgramCache]: Analyzing trace with hash 1136526831, now seen corresponding path program 1 times [2022-11-03 02:31:27,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:27,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1915764673] [2022-11-03 02:31:27,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:27,616 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:27,616 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:27,617 INFO L229 MonitoredProcess]: Starting monitored process 95 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:27,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (95)] Waiting until timeout for monitored process [2022-11-03 02:31:27,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:27,861 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:31:27,863 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:27,929 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 94 proven. 0 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2022-11-03 02:31:27,930 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:27,930 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:27,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1915764673] [2022-11-03 02:31:27,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1915764673] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:27,930 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:27,930 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:31:27,930 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1514942527] [2022-11-03 02:31:27,930 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:27,931 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:31:27,931 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:27,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:31:27,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:31:27,931 INFO L87 Difference]: Start difference. First operand 2186 states and 2369 transitions. Second operand has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:28,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:28,180 INFO L93 Difference]: Finished difference Result 4382 states and 4741 transitions. [2022-11-03 02:31:28,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:31:28,181 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:28,181 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:28,182 INFO L225 Difference]: With dead ends: 4382 [2022-11-03 02:31:28,182 INFO L226 Difference]: Without dead ends: 2418 [2022-11-03 02:31:28,183 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:28,184 INFO L413 NwaCegarLoop]: 114 mSDtfsCounter, 232 mSDsluCounter, 154 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 232 SdHoareTripleChecker+Valid, 268 SdHoareTripleChecker+Invalid, 65 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:28,184 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [232 Valid, 268 Invalid, 65 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:31:28,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2418 states. [2022-11-03 02:31:28,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2418 to 2154. [2022-11-03 02:31:28,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2154 states, 2153 states have (on average 1.0733859730608453) internal successors, (2311), 2153 states have internal predecessors, (2311), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:28,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2154 states to 2154 states and 2311 transitions. [2022-11-03 02:31:28,391 INFO L78 Accepts]: Start accepts. Automaton has 2154 states and 2311 transitions. Word has length 162 [2022-11-03 02:31:28,391 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:28,391 INFO L495 AbstractCegarLoop]: Abstraction has 2154 states and 2311 transitions. [2022-11-03 02:31:28,391 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:28,391 INFO L276 IsEmpty]: Start isEmpty. Operand 2154 states and 2311 transitions. [2022-11-03 02:31:28,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:28,394 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:28,394 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:28,408 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (95)] Ended with exit code 0 [2022-11-03 02:31:28,594 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 95 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:28,595 INFO L420 AbstractCegarLoop]: === Iteration 63 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:28,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:28,595 INFO L85 PathProgramCache]: Analyzing trace with hash -1005648975, now seen corresponding path program 1 times [2022-11-03 02:31:28,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:28,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [733505654] [2022-11-03 02:31:28,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:28,596 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:28,596 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:28,596 INFO L229 MonitoredProcess]: Starting monitored process 96 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:28,597 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (96)] Waiting until timeout for monitored process [2022-11-03 02:31:28,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:28,841 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 02:31:28,842 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:28,912 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2022-11-03 02:31:28,913 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:28,913 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:28,913 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [733505654] [2022-11-03 02:31:28,913 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [733505654] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:28,913 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:28,913 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:31:28,913 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242534278] [2022-11-03 02:31:28,913 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:28,914 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:31:28,914 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:28,914 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:31:28,914 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:31:28,914 INFO L87 Difference]: Start difference. First operand 2154 states and 2311 transitions. Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:29,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:29,122 INFO L93 Difference]: Finished difference Result 3830 states and 4125 transitions. [2022-11-03 02:31:29,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 02:31:29,122 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:29,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:29,124 INFO L225 Difference]: With dead ends: 3830 [2022-11-03 02:31:29,124 INFO L226 Difference]: Without dead ends: 1910 [2022-11-03 02:31:29,125 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 159 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:29,125 INFO L413 NwaCegarLoop]: 110 mSDtfsCounter, 229 mSDsluCounter, 150 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 229 SdHoareTripleChecker+Valid, 260 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:29,126 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [229 Valid, 260 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-03 02:31:29,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1910 states. [2022-11-03 02:31:29,241 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1910 to 1722. [2022-11-03 02:31:29,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1722 states, 1721 states have (on average 1.074375363160953) internal successors, (1849), 1721 states have internal predecessors, (1849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:29,243 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1722 states to 1722 states and 1849 transitions. [2022-11-03 02:31:29,243 INFO L78 Accepts]: Start accepts. Automaton has 1722 states and 1849 transitions. Word has length 162 [2022-11-03 02:31:29,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:29,244 INFO L495 AbstractCegarLoop]: Abstraction has 1722 states and 1849 transitions. [2022-11-03 02:31:29,244 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:29,244 INFO L276 IsEmpty]: Start isEmpty. Operand 1722 states and 1849 transitions. [2022-11-03 02:31:29,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:29,247 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:29,247 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:29,258 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (96)] Ended with exit code 0 [2022-11-03 02:31:29,448 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 96 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:29,448 INFO L420 AbstractCegarLoop]: === Iteration 64 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:29,448 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:29,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1083917075, now seen corresponding path program 1 times [2022-11-03 02:31:29,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:29,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [544467859] [2022-11-03 02:31:29,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:29,450 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:29,450 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:29,451 INFO L229 MonitoredProcess]: Starting monitored process 97 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:29,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (97)] Waiting until timeout for monitored process [2022-11-03 02:31:29,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:29,703 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:31:29,707 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:29,852 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 66 proven. 0 refuted. 0 times theorem prover too weak. 105 trivial. 0 not checked. [2022-11-03 02:31:29,853 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:29,853 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:29,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [544467859] [2022-11-03 02:31:29,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [544467859] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:29,853 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:29,853 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:31:29,854 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1779514710] [2022-11-03 02:31:29,854 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:29,854 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:31:29,855 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:29,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:31:29,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:29,855 INFO L87 Difference]: Start difference. First operand 1722 states and 1849 transitions. Second operand has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:30,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:30,110 INFO L93 Difference]: Finished difference Result 3567 states and 3835 transitions. [2022-11-03 02:31:30,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:31:30,111 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:30,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:30,113 INFO L225 Difference]: With dead ends: 3567 [2022-11-03 02:31:30,113 INFO L226 Difference]: Without dead ends: 1906 [2022-11-03 02:31:30,114 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:31:30,115 INFO L413 NwaCegarLoop]: 103 mSDtfsCounter, 154 mSDsluCounter, 471 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 154 SdHoareTripleChecker+Valid, 574 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:30,115 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [154 Valid, 574 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 61 Invalid, 0 Unknown, 22 Unchecked, 0.1s Time] [2022-11-03 02:31:30,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1906 states. [2022-11-03 02:31:30,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1906 to 1703. [2022-11-03 02:31:30,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1702 states have (on average 1.0757931844888367) internal successors, (1831), 1702 states have internal predecessors, (1831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:30,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 1831 transitions. [2022-11-03 02:31:30,233 INFO L78 Accepts]: Start accepts. Automaton has 1703 states and 1831 transitions. Word has length 162 [2022-11-03 02:31:30,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:30,233 INFO L495 AbstractCegarLoop]: Abstraction has 1703 states and 1831 transitions. [2022-11-03 02:31:30,233 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 12.0) internal successors, (96), 8 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:30,233 INFO L276 IsEmpty]: Start isEmpty. Operand 1703 states and 1831 transitions. [2022-11-03 02:31:30,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:30,235 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:30,235 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:30,245 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (97)] Ended with exit code 0 [2022-11-03 02:31:30,435 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 97 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:30,436 INFO L420 AbstractCegarLoop]: === Iteration 65 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:30,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:30,436 INFO L85 PathProgramCache]: Analyzing trace with hash -1072971281, now seen corresponding path program 1 times [2022-11-03 02:31:30,436 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:30,436 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [727834747] [2022-11-03 02:31:30,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:30,437 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:30,437 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:30,438 INFO L229 MonitoredProcess]: Starting monitored process 98 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:30,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (98)] Waiting until timeout for monitored process [2022-11-03 02:31:30,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:30,679 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:31:30,681 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:30,824 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 62 proven. 0 refuted. 0 times theorem prover too weak. 109 trivial. 0 not checked. [2022-11-03 02:31:30,825 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:30,825 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:30,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [727834747] [2022-11-03 02:31:30,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [727834747] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:30,825 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:30,825 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:31:30,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283296109] [2022-11-03 02:31:30,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:30,826 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:31:30,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:30,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:31:30,826 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:30,826 INFO L87 Difference]: Start difference. First operand 1703 states and 1831 transitions. Second operand has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:31,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:31,041 INFO L93 Difference]: Finished difference Result 2878 states and 3095 transitions. [2022-11-03 02:31:31,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:31:31,041 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:31,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:31,043 INFO L225 Difference]: With dead ends: 2878 [2022-11-03 02:31:31,043 INFO L226 Difference]: Without dead ends: 1884 [2022-11-03 02:31:31,044 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:31:31,044 INFO L413 NwaCegarLoop]: 100 mSDtfsCounter, 192 mSDsluCounter, 370 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 470 SdHoareTripleChecker+Invalid, 76 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 22 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:31,045 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 470 Invalid, 76 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 54 Invalid, 0 Unknown, 22 Unchecked, 0.1s Time] [2022-11-03 02:31:31,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1884 states. [2022-11-03 02:31:31,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1884 to 1703. [2022-11-03 02:31:31,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1702 states have (on average 1.0740305522914217) internal successors, (1828), 1702 states have internal predecessors, (1828), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:31,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 1828 transitions. [2022-11-03 02:31:31,178 INFO L78 Accepts]: Start accepts. Automaton has 1703 states and 1828 transitions. Word has length 162 [2022-11-03 02:31:31,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:31,178 INFO L495 AbstractCegarLoop]: Abstraction has 1703 states and 1828 transitions. [2022-11-03 02:31:31,178 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:31,178 INFO L276 IsEmpty]: Start isEmpty. Operand 1703 states and 1828 transitions. [2022-11-03 02:31:31,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:31,180 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:31,180 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:31,190 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (98)] Ended with exit code 0 [2022-11-03 02:31:31,380 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 98 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:31,381 INFO L420 AbstractCegarLoop]: === Iteration 66 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:31,381 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:31,381 INFO L85 PathProgramCache]: Analyzing trace with hash -37484177, now seen corresponding path program 1 times [2022-11-03 02:31:31,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:31,381 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1512888971] [2022-11-03 02:31:31,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:31,382 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:31,382 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:31,382 INFO L229 MonitoredProcess]: Starting monitored process 99 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:31,383 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (99)] Waiting until timeout for monitored process [2022-11-03 02:31:31,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:31,624 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:31:31,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:31,768 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 58 proven. 0 refuted. 0 times theorem prover too weak. 113 trivial. 0 not checked. [2022-11-03 02:31:31,768 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:31,768 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:31,768 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1512888971] [2022-11-03 02:31:31,768 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1512888971] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:31,768 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:31,769 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:31:31,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032532532] [2022-11-03 02:31:31,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:31,769 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:31:31,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:31,769 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:31:31,769 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:31,770 INFO L87 Difference]: Start difference. First operand 1703 states and 1828 transitions. Second operand has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:31,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:31,985 INFO L93 Difference]: Finished difference Result 2788 states and 2995 transitions. [2022-11-03 02:31:31,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:31:31,985 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:31,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:31,986 INFO L225 Difference]: With dead ends: 2788 [2022-11-03 02:31:31,987 INFO L226 Difference]: Without dead ends: 1790 [2022-11-03 02:31:31,987 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:31:31,988 INFO L413 NwaCegarLoop]: 97 mSDtfsCounter, 152 mSDsluCounter, 459 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 152 SdHoareTripleChecker+Valid, 556 SdHoareTripleChecker+Invalid, 81 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:31,988 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [152 Valid, 556 Invalid, 81 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 57 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-11-03 02:31:31,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1790 states. [2022-11-03 02:31:32,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1790 to 1699. [2022-11-03 02:31:32,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1699 states, 1698 states have (on average 1.0730270906949353) internal successors, (1822), 1698 states have internal predecessors, (1822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:32,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1699 states to 1699 states and 1822 transitions. [2022-11-03 02:31:32,132 INFO L78 Accepts]: Start accepts. Automaton has 1699 states and 1822 transitions. Word has length 162 [2022-11-03 02:31:32,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:32,132 INFO L495 AbstractCegarLoop]: Abstraction has 1699 states and 1822 transitions. [2022-11-03 02:31:32,133 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.625) internal successors, (93), 8 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:32,133 INFO L276 IsEmpty]: Start isEmpty. Operand 1699 states and 1822 transitions. [2022-11-03 02:31:32,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:32,135 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:32,135 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:32,153 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (99)] Ended with exit code 0 [2022-11-03 02:31:32,336 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 99 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:32,336 INFO L420 AbstractCegarLoop]: === Iteration 67 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:32,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:32,336 INFO L85 PathProgramCache]: Analyzing trace with hash 2040954545, now seen corresponding path program 1 times [2022-11-03 02:31:32,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:32,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [203462742] [2022-11-03 02:31:32,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:31:32,337 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:32,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:32,338 INFO L229 MonitoredProcess]: Starting monitored process 100 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:32,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (100)] Waiting until timeout for monitored process [2022-11-03 02:31:32,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:31:32,603 INFO L263 TraceCheckSpWp]: Trace formula consists of 832 conjuncts, 13 conjunts are in the unsatisfiable core [2022-11-03 02:31:32,605 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:31:32,744 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2022-11-03 02:31:32,744 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:31:32,744 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:31:32,744 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [203462742] [2022-11-03 02:31:32,744 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [203462742] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:31:32,745 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:31:32,745 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:31:32,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [946778352] [2022-11-03 02:31:32,745 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:31:32,745 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:31:32,745 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:31:32,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:31:32,746 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:31:32,746 INFO L87 Difference]: Start difference. First operand 1699 states and 1822 transitions. Second operand has 8 states, 8 states have (on average 11.5) internal successors, (92), 8 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:32,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:31:32,949 INFO L93 Difference]: Finished difference Result 2707 states and 2909 transitions. [2022-11-03 02:31:32,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 02:31:32,950 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.5) internal successors, (92), 8 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 162 [2022-11-03 02:31:32,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:31:32,951 INFO L225 Difference]: With dead ends: 2707 [2022-11-03 02:31:32,951 INFO L226 Difference]: Without dead ends: 1711 [2022-11-03 02:31:32,952 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 165 GetRequests, 155 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:31:32,952 INFO L413 NwaCegarLoop]: 94 mSDtfsCounter, 188 mSDsluCounter, 421 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 188 SdHoareTripleChecker+Valid, 515 SdHoareTripleChecker+Invalid, 79 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 29 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 02:31:32,953 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [188 Valid, 515 Invalid, 79 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 50 Invalid, 0 Unknown, 29 Unchecked, 0.1s Time] [2022-11-03 02:31:32,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1711 states. [2022-11-03 02:31:33,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1711 to 1693. [2022-11-03 02:31:33,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1693 states, 1692 states have (on average 1.072695035460993) internal successors, (1815), 1692 states have internal predecessors, (1815), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:33,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1693 states to 1693 states and 1815 transitions. [2022-11-03 02:31:33,070 INFO L78 Accepts]: Start accepts. Automaton has 1693 states and 1815 transitions. Word has length 162 [2022-11-03 02:31:33,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:31:33,070 INFO L495 AbstractCegarLoop]: Abstraction has 1693 states and 1815 transitions. [2022-11-03 02:31:33,070 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.5) internal successors, (92), 8 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:31:33,071 INFO L276 IsEmpty]: Start isEmpty. Operand 1693 states and 1815 transitions. [2022-11-03 02:31:33,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 163 [2022-11-03 02:31:33,073 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:31:33,074 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:33,090 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (100)] Ended with exit code 0 [2022-11-03 02:31:33,274 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 100 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:33,274 INFO L420 AbstractCegarLoop]: === Iteration 68 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:31:33,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:31:33,275 INFO L85 PathProgramCache]: Analyzing trace with hash -383446055, now seen corresponding path program 2 times [2022-11-03 02:31:33,275 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:31:33,275 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2091985617] [2022-11-03 02:31:33,275 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-11-03 02:31:33,275 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:31:33,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:31:33,276 INFO L229 MonitoredProcess]: Starting monitored process 101 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:31:33,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (101)] Waiting until timeout for monitored process [2022-11-03 02:31:33,517 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-11-03 02:31:33,517 INFO L229 tOrderPrioritization]: Conjunction of SSA is sat [2022-11-03 02:31:33,517 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:31:33,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:31:34,040 INFO L130 FreeRefinementEngine]: Strategy WALRUS found a feasible trace [2022-11-03 02:31:34,041 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:31:34,042 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:31:34,059 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (101)] Ended with exit code 0 [2022-11-03 02:31:34,250 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 101 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:31:34,253 INFO L444 BasicCegarLoop]: Path program histogram: [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:31:34,257 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:31:34,552 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,553 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,553 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,553 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,648 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:31:34 BoogieIcfgContainer [2022-11-03 02:31:34,648 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:31:34,649 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:31:34,649 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:31:34,650 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:31:34,650 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:24:44" (3/4) ... [2022-11-03 02:31:34,652 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-03 02:31:34,851 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,852 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,852 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:34,852 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:31:35,047 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/witness.graphml [2022-11-03 02:31:35,047 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:31:35,048 INFO L158 Benchmark]: Toolchain (without parser) took 411368.70ms. Allocated memory was 62.9MB in the beginning and 1.5GB in the end (delta: 1.5GB). Free memory was 40.7MB in the beginning and 816.1MB in the end (delta: -775.3MB). Peak memory consumption was 697.3MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,048 INFO L158 Benchmark]: CDTParser took 0.25ms. Allocated memory is still 62.9MB. Free memory is still 42.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:31:35,048 INFO L158 Benchmark]: CACSL2BoogieTranslator took 410.51ms. Allocated memory is still 62.9MB. Free memory was 40.5MB in the beginning and 39.4MB in the end (delta: 1.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,048 INFO L158 Benchmark]: Boogie Procedure Inliner took 84.76ms. Allocated memory is still 62.9MB. Free memory was 39.4MB in the beginning and 35.9MB in the end (delta: 3.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,049 INFO L158 Benchmark]: Boogie Preprocessor took 81.19ms. Allocated memory is still 62.9MB. Free memory was 35.9MB in the beginning and 33.6MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,049 INFO L158 Benchmark]: RCFGBuilder took 728.40ms. Allocated memory is still 62.9MB. Free memory was 33.6MB in the beginning and 24.6MB in the end (delta: 9.0MB). Peak memory consumption was 17.8MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,049 INFO L158 Benchmark]: TraceAbstraction took 409648.86ms. Allocated memory was 62.9MB in the beginning and 1.5GB in the end (delta: 1.5GB). Free memory was 24.0MB in the beginning and 903.0MB in the end (delta: -879.0MB). Peak memory consumption was 594.4MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,049 INFO L158 Benchmark]: Witness Printer took 398.31ms. Allocated memory is still 1.5GB. Free memory was 903.0MB in the beginning and 816.1MB in the end (delta: 86.9MB). Peak memory consumption was 86.0MB. Max. memory is 16.1GB. [2022-11-03 02:31:35,050 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.25ms. Allocated memory is still 62.9MB. Free memory is still 42.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 410.51ms. Allocated memory is still 62.9MB. Free memory was 40.5MB in the beginning and 39.4MB in the end (delta: 1.1MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 84.76ms. Allocated memory is still 62.9MB. Free memory was 39.4MB in the beginning and 35.9MB in the end (delta: 3.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 81.19ms. Allocated memory is still 62.9MB. Free memory was 35.9MB in the beginning and 33.6MB in the end (delta: 2.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 728.40ms. Allocated memory is still 62.9MB. Free memory was 33.6MB in the beginning and 24.6MB in the end (delta: 9.0MB). Peak memory consumption was 17.8MB. Max. memory is 16.1GB. * TraceAbstraction took 409648.86ms. Allocated memory was 62.9MB in the beginning and 1.5GB in the end (delta: 1.5GB). Free memory was 24.0MB in the beginning and 903.0MB in the end (delta: -879.0MB). Peak memory consumption was 594.4MB. Max. memory is 16.1GB. * Witness Printer took 398.31ms. Allocated memory is still 1.5GB. Free memory was 903.0MB in the beginning and 816.1MB in the end (delta: 86.9MB). Peak memory consumption was 86.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 20]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 8); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (8 - 1); [L28] const SORT_5 mask_SORT_5 = (SORT_5)-1 >> (sizeof(SORT_5) * 8 - 1); [L29] const SORT_5 msb_SORT_5 = (SORT_5)1 << (1 - 1); [L31] const SORT_1 var_9 = 0; [L32] const SORT_5 var_22 = 0; [L33] const SORT_5 var_31 = 1; [L34] const SORT_1 var_109 = 1; [L36] SORT_1 input_2; [L37] SORT_1 input_3; [L38] SORT_1 input_4; [L39] SORT_5 input_6; [L40] SORT_5 input_7; [L41] SORT_5 input_8; [L42] SORT_5 input_35; [L43] SORT_5 input_37; [L44] SORT_5 input_39; [L45] SORT_5 input_51; [L47] SORT_1 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L48] SORT_1 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L49] SORT_1 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L50] SORT_5 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L51] SORT_1 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L52] SORT_5 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L53] SORT_5 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L54] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L55] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L56] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L57] SORT_5 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L58] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L59] SORT_5 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_5; [L60] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L61] SORT_1 state_62 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L62] SORT_1 state_64 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L63] SORT_1 state_66 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L64] SORT_1 state_68 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L65] SORT_1 state_70 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L66] SORT_1 state_72 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L68] SORT_1 init_11_arg_1 = var_9; [L69] state_10 = init_11_arg_1 [L70] SORT_1 init_13_arg_1 = var_9; [L71] state_12 = init_13_arg_1 [L72] SORT_1 init_19_arg_1 = var_9; [L73] state_18 = init_19_arg_1 [L74] SORT_5 init_24_arg_1 = var_22; [L75] state_23 = init_24_arg_1 [L76] SORT_1 init_27_arg_1 = var_9; [L77] state_26 = init_27_arg_1 [L78] SORT_5 init_42_arg_1 = var_22; [L79] state_41 = init_42_arg_1 [L80] SORT_5 init_44_arg_1 = var_22; [L81] state_43 = init_44_arg_1 [L82] SORT_1 init_46_arg_1 = var_9; [L83] state_45 = init_46_arg_1 [L84] SORT_1 init_48_arg_1 = var_9; [L85] state_47 = init_48_arg_1 [L86] SORT_1 init_50_arg_1 = var_9; [L87] state_49 = init_50_arg_1 [L88] SORT_5 init_54_arg_1 = var_22; [L89] state_53 = init_54_arg_1 [L90] SORT_1 init_56_arg_1 = var_9; [L91] state_55 = init_56_arg_1 [L92] SORT_5 init_58_arg_1 = var_22; [L93] state_57 = init_58_arg_1 [L94] SORT_1 init_60_arg_1 = var_9; [L95] state_59 = init_60_arg_1 [L96] SORT_1 init_63_arg_1 = var_9; [L97] state_62 = init_63_arg_1 [L98] SORT_1 init_65_arg_1 = var_9; [L99] state_64 = init_65_arg_1 [L100] SORT_1 init_67_arg_1 = var_9; [L101] state_66 = init_67_arg_1 [L102] SORT_1 init_69_arg_1 = var_9; [L103] state_68 = init_69_arg_1 [L104] SORT_1 init_71_arg_1 = var_9; [L105] state_70 = init_71_arg_1 [L106] SORT_1 init_73_arg_1 = var_9; [L107] state_72 = init_73_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_22=0, var_31=1, var_9=0] [L110] input_2 = __VERIFIER_nondet_uchar() [L111] input_3 = __VERIFIER_nondet_uchar() [L112] input_4 = __VERIFIER_nondet_uchar() [L113] input_6 = __VERIFIER_nondet_uchar() [L114] input_7 = __VERIFIER_nondet_uchar() [L115] input_8 = __VERIFIER_nondet_uchar() [L116] input_8 = input_8 & mask_SORT_5 [L117] input_35 = __VERIFIER_nondet_uchar() [L118] input_37 = __VERIFIER_nondet_uchar() [L119] input_39 = __VERIFIER_nondet_uchar() [L120] input_51 = __VERIFIER_nondet_uchar() [L123] SORT_1 var_16_arg_0 = state_10; [L124] SORT_5 var_16 = var_16_arg_0 >> 0; [L125] var_16 = var_16 & mask_SORT_5 [L126] SORT_1 var_15_arg_0 = state_10; [L127] SORT_1 var_15_arg_1 = state_12; [L128] SORT_1 var_15 = var_15_arg_0 + var_15_arg_1; [L129] SORT_1 var_14_arg_0 = state_10; [L130] SORT_1 var_14_arg_1 = state_12; [L131] SORT_1 var_14 = var_14_arg_0 - var_14_arg_1; [L132] SORT_5 var_17_arg_0 = var_16; [L133] SORT_1 var_17_arg_1 = var_15; [L134] SORT_1 var_17_arg_2 = var_14; VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_22=0, var_31=1, var_9=0] [L135] EXPR var_17_arg_0 ? var_17_arg_1 : var_17_arg_2 VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17_arg_0=0, var_17_arg_0 ? var_17_arg_1 : var_17_arg_2=0, var_17_arg_1=0, var_17_arg_2=0, var_22=0, var_31=1, var_9=0] [L135] SORT_1 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L136] SORT_1 var_21_arg_0 = var_17; [L137] SORT_1 var_21_arg_1 = state_18; [L138] SORT_1 var_21 = var_21_arg_0 + var_21_arg_1; [L139] SORT_1 var_20_arg_0 = var_17; [L140] SORT_1 var_20_arg_1 = state_18; [L141] SORT_1 var_20 = var_20_arg_0 - var_20_arg_1; [L142] SORT_5 var_25_arg_0 = state_23; [L143] SORT_1 var_25_arg_1 = var_21; [L144] SORT_1 var_25_arg_2 = var_20; VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_31=1, var_9=0] [L145] EXPR var_25_arg_0 ? var_25_arg_1 : var_25_arg_2 VAL [init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25_arg_0=0, var_25_arg_0 ? var_25_arg_1 : var_25_arg_2=0, var_25_arg_1=0, var_25_arg_2=0, var_31=1, var_9=0] [L145] SORT_1 var_25 = var_25_arg_0 ? var_25_arg_1 : var_25_arg_2; [L146] var_25 = var_25 & mask_SORT_1 [L147] SORT_1 var_28_arg_0 = var_25; [L148] SORT_1 var_28_arg_1 = state_26; [L149] SORT_5 var_28 = var_28_arg_0 == var_28_arg_1; [L150] SORT_5 var_32_arg_0 = var_28; [L151] SORT_5 var_32 = ~var_32_arg_0; [L152] SORT_5 var_33_arg_0 = var_31; [L153] SORT_5 var_33_arg_1 = var_32; [L154] SORT_5 var_33 = var_33_arg_0 & var_33_arg_1; [L155] var_33 = var_33 & mask_SORT_5 [L156] SORT_5 bad_34_arg_0 = var_33; [L157] CALL __VERIFIER_assert(!(bad_34_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L157] RET __VERIFIER_assert(!(bad_34_arg_0)) [L159] SORT_5 var_76_arg_0 = input_8; [L160] SORT_5 var_76_arg_1 = var_31; [L161] SORT_5 var_76 = var_76_arg_0 == var_76_arg_1; [L162] SORT_5 var_77_arg_0 = var_76; [L163] SORT_1 var_77_arg_1 = var_9; [L164] SORT_1 var_77_arg_2 = state_64; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_9=0] [L165] EXPR var_77_arg_0 ? var_77_arg_1 : var_77_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77_arg_0=0, var_77_arg_0 ? var_77_arg_1 : var_77_arg_2=0, var_77_arg_1=0, var_77_arg_2=0, var_9=0] [L165] SORT_1 var_77 = var_77_arg_0 ? var_77_arg_1 : var_77_arg_2; [L166] SORT_1 next_78_arg_1 = var_77; [L167] SORT_5 var_79_arg_0 = var_76; [L168] SORT_1 var_79_arg_1 = var_9; [L169] SORT_1 var_79_arg_2 = state_68; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_9=0] [L170] EXPR var_79_arg_0 ? var_79_arg_1 : var_79_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79_arg_0=0, var_79_arg_0 ? var_79_arg_1 : var_79_arg_2=0, var_79_arg_1=0, var_79_arg_2=0, var_9=0] [L170] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L171] SORT_1 next_80_arg_1 = var_79; [L172] SORT_5 var_81_arg_0 = var_76; [L173] SORT_1 var_81_arg_1 = var_9; [L174] SORT_1 var_81_arg_2 = state_72; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_9=0] [L175] EXPR var_81_arg_0 ? var_81_arg_1 : var_81_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81_arg_0=0, var_81_arg_0 ? var_81_arg_1 : var_81_arg_2=0, var_81_arg_1=0, var_81_arg_2=0, var_9=0] [L175] SORT_1 var_81 = var_81_arg_0 ? var_81_arg_1 : var_81_arg_2; [L176] SORT_1 next_82_arg_1 = var_81; [L177] SORT_5 var_83_arg_0 = var_76; [L178] SORT_5 var_83_arg_1 = var_22; [L179] SORT_5 var_83_arg_2 = state_43; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_9=0] [L180] EXPR var_83_arg_0 ? var_83_arg_1 : var_83_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83_arg_0=0, var_83_arg_0 ? var_83_arg_1 : var_83_arg_2=0, var_83_arg_1=0, var_83_arg_2=0, var_9=0] [L180] SORT_5 var_83 = var_83_arg_0 ? var_83_arg_1 : var_83_arg_2; [L181] var_83 = var_83 & mask_SORT_5 [L182] SORT_5 next_84_arg_1 = var_83; [L183] SORT_5 var_88_arg_0 = input_8; [L184] SORT_5 var_88_arg_1 = var_31; [L185] SORT_5 var_88 = var_88_arg_0 == var_88_arg_1; [L186] SORT_1 var_86_arg_0 = state_59; [L187] SORT_1 var_86_arg_1 = state_55; [L188] SORT_1 var_86 = var_86_arg_0 - var_86_arg_1; [L189] SORT_1 var_85_arg_0 = state_59; [L190] SORT_1 var_85_arg_1 = state_55; [L191] SORT_1 var_85 = var_85_arg_0 - var_85_arg_1; [L192] SORT_5 var_87_arg_0 = state_57; [L193] SORT_1 var_87_arg_1 = var_86; [L194] SORT_1 var_87_arg_2 = var_85; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_9=0] [L195] EXPR var_87_arg_0 ? var_87_arg_1 : var_87_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87_arg_0=0, var_87_arg_0 ? var_87_arg_1 : var_87_arg_2=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_9=0] [L195] SORT_1 var_87 = var_87_arg_0 ? var_87_arg_1 : var_87_arg_2; [L196] SORT_5 var_89_arg_0 = var_88; [L197] SORT_1 var_89_arg_1 = var_9; [L198] SORT_1 var_89_arg_2 = var_87; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0] [L199] EXPR var_89_arg_0 ? var_89_arg_1 : var_89_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89_arg_0=0, var_89_arg_0 ? var_89_arg_1 : var_89_arg_2=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0] [L199] SORT_1 var_89 = var_89_arg_0 ? var_89_arg_1 : var_89_arg_2; [L200] var_89 = var_89 & mask_SORT_1 [L201] SORT_1 next_90_arg_1 = var_89; [L202] SORT_5 var_91_arg_0 = var_76; [L203] SORT_5 var_91_arg_1 = var_22; [L204] SORT_5 var_91_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1] [L205] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91_arg_0=0, var_91_arg_0 ? var_91_arg_1 : var_91_arg_2=1, var_91_arg_1=0, var_91_arg_2=1] [L205] SORT_5 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L206] SORT_5 next_92_arg_1 = var_91; [L207] SORT_5 var_93_arg_0 = var_76; [L208] SORT_5 var_93_arg_1 = var_22; [L209] SORT_5 var_93_arg_2 = state_41; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0] [L210] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93_arg_0=0, var_93_arg_0 ? var_93_arg_1 : var_93_arg_2=0, var_93_arg_1=0, var_93_arg_2=0] [L210] SORT_5 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L211] SORT_5 next_94_arg_1 = var_93; [L212] SORT_5 var_95_arg_0 = var_88; [L213] SORT_1 var_95_arg_1 = var_9; [L214] SORT_1 var_95_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1] [L215] EXPR var_95_arg_0 ? var_95_arg_1 : var_95_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95_arg_0=0, var_95_arg_0 ? var_95_arg_1 : var_95_arg_2=1, var_95_arg_1=0, var_95_arg_2=1] [L215] SORT_1 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L216] SORT_1 next_96_arg_1 = var_95; [L217] SORT_5 var_97_arg_0 = var_88; [L218] SORT_1 var_97_arg_1 = var_9; [L219] SORT_1 var_97_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65] [L220] EXPR var_97_arg_0 ? var_97_arg_1 : var_97_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97_arg_0=0, var_97_arg_0 ? var_97_arg_1 : var_97_arg_2=65, var_97_arg_1=0, var_97_arg_2=65] [L220] SORT_1 var_97 = var_97_arg_0 ? var_97_arg_1 : var_97_arg_2; [L221] SORT_1 next_98_arg_1 = var_97; [L222] SORT_5 var_99_arg_0 = var_88; [L223] SORT_1 var_99_arg_1 = var_9; [L224] SORT_1 var_99_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L225] EXPR var_99_arg_0 ? var_99_arg_1 : var_99_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99_arg_0=0, var_99_arg_0 ? var_99_arg_1 : var_99_arg_2=32, var_99_arg_1=0, var_99_arg_2=32] [L225] SORT_1 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; [L226] SORT_1 next_100_arg_1 = var_99; [L227] SORT_5 var_101_arg_0 = var_88; [L228] SORT_5 var_101_arg_1 = var_22; [L229] SORT_5 var_101_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L230] EXPR var_101_arg_0 ? var_101_arg_1 : var_101_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101_arg_0=0, var_101_arg_0 ? var_101_arg_1 : var_101_arg_2=1, var_101_arg_1=0, var_101_arg_2=1, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L230] SORT_5 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L231] SORT_5 next_102_arg_1 = var_101; [L232] SORT_5 var_103_arg_0 = var_88; [L233] SORT_1 var_103_arg_1 = var_9; [L234] SORT_1 var_103_arg_2 = state_49; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L235] EXPR var_103_arg_0 ? var_103_arg_1 : var_103_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103_arg_0=0, var_103_arg_0 ? var_103_arg_1 : var_103_arg_2=0, var_103_arg_1=0, var_103_arg_2=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L235] SORT_1 var_103 = var_103_arg_0 ? var_103_arg_1 : var_103_arg_2; [L236] SORT_1 next_104_arg_1 = var_103; [L237] SORT_5 var_105_arg_0 = var_88; [L238] SORT_5 var_105_arg_1 = var_22; [L239] SORT_5 var_105_arg_2 = state_53; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L240] EXPR var_105_arg_0 ? var_105_arg_1 : var_105_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105_arg_0=0, var_105_arg_0 ? var_105_arg_1 : var_105_arg_2=0, var_105_arg_1=0, var_105_arg_2=0, var_109=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L240] SORT_5 var_105 = var_105_arg_0 ? var_105_arg_1 : var_105_arg_2; [L241] var_105 = var_105 & mask_SORT_5 [L242] SORT_5 next_106_arg_1 = var_105; [L243] SORT_1 var_110_arg_0 = state_45; [L244] SORT_1 var_110_arg_1 = var_109; [L245] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L246] var_110 = var_110 & mask_SORT_1 [L247] SORT_1 var_111_arg_0 = var_110; [L248] SORT_1 var_111_arg_1 = var_109; [L249] SORT_5 var_111 = var_111_arg_0 == var_111_arg_1; [L250] SORT_1 var_108_arg_0 = state_45; [L251] SORT_1 var_108_arg_1 = state_47; [L252] SORT_1 var_108 = var_108_arg_0 + var_108_arg_1; [L253] SORT_1 var_107_arg_0 = state_45; [L254] SORT_1 var_107_arg_1 = state_47; [L255] SORT_1 var_107 = var_107_arg_0 - var_107_arg_1; [L256] SORT_5 var_112_arg_0 = var_111; [L257] SORT_1 var_112_arg_1 = var_108; [L258] SORT_1 var_112_arg_2 = var_107; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L259] EXPR var_112_arg_0 ? var_112_arg_1 : var_112_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112_arg_0=0, var_112_arg_0 ? var_112_arg_1 : var_112_arg_2=0, var_112_arg_1=0, var_112_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L259] SORT_1 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L260] SORT_5 var_113_arg_0 = var_88; [L261] SORT_1 var_113_arg_1 = var_9; [L262] SORT_1 var_113_arg_2 = var_112; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L263] EXPR var_113_arg_0 ? var_113_arg_1 : var_113_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113_arg_0=0, var_113_arg_0 ? var_113_arg_1 : var_113_arg_2=0, var_113_arg_1=0, var_113_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L263] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L264] SORT_1 next_114_arg_1 = var_113; [L265] SORT_5 var_115_arg_0 = var_76; [L266] SORT_1 var_115_arg_1 = var_9; [L267] SORT_1 var_115_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L268] EXPR var_115_arg_0 ? var_115_arg_1 : var_115_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115_arg_0=0, var_115_arg_0 ? var_115_arg_1 : var_115_arg_2=1, var_115_arg_1=0, var_115_arg_2=1, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L268] SORT_1 var_115 = var_115_arg_0 ? var_115_arg_1 : var_115_arg_2; [L269] SORT_1 next_116_arg_1 = var_115; [L270] SORT_5 var_117_arg_0 = var_76; [L271] SORT_1 var_117_arg_1 = var_9; [L272] SORT_1 var_117_arg_2 = state_62; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L273] EXPR var_117_arg_0 ? var_117_arg_1 : var_117_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117_arg_0=0, var_117_arg_0 ? var_117_arg_1 : var_117_arg_2=0, var_117_arg_1=0, var_117_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L273] SORT_1 var_117 = var_117_arg_0 ? var_117_arg_1 : var_117_arg_2; [L274] SORT_1 next_118_arg_1 = var_117; [L275] SORT_5 var_119_arg_0 = var_76; [L276] SORT_1 var_119_arg_1 = var_9; [L277] SORT_1 var_119_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L278] EXPR var_119_arg_0 ? var_119_arg_1 : var_119_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119_arg_0=0, var_119_arg_0 ? var_119_arg_1 : var_119_arg_2=65, var_119_arg_1=0, var_119_arg_2=65, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L278] SORT_1 var_119 = var_119_arg_0 ? var_119_arg_1 : var_119_arg_2; [L279] SORT_1 next_120_arg_1 = var_119; [L280] SORT_5 var_121_arg_0 = var_76; [L281] SORT_1 var_121_arg_1 = var_9; [L282] SORT_1 var_121_arg_2 = state_66; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L283] EXPR var_121_arg_0 ? var_121_arg_1 : var_121_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121_arg_0=0, var_121_arg_0 ? var_121_arg_1 : var_121_arg_2=0, var_121_arg_1=0, var_121_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L283] SORT_1 var_121 = var_121_arg_0 ? var_121_arg_1 : var_121_arg_2; [L284] SORT_1 next_122_arg_1 = var_121; [L285] SORT_5 var_123_arg_0 = var_76; [L286] SORT_1 var_123_arg_1 = var_9; [L287] SORT_1 var_123_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L288] EXPR var_123_arg_0 ? var_123_arg_1 : var_123_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123_arg_0=0, var_123_arg_0 ? var_123_arg_1 : var_123_arg_2=32, var_123_arg_1=0, var_123_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L288] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L289] SORT_1 next_124_arg_1 = var_123; [L290] SORT_5 var_125_arg_0 = var_76; [L291] SORT_1 var_125_arg_1 = var_9; [L292] SORT_1 var_125_arg_2 = state_70; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L293] EXPR var_125_arg_0 ? var_125_arg_1 : var_125_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=0, state_62=0, state_64=0, state_66=0, state_68=0, state_70=0, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125_arg_0=0, var_125_arg_0 ? var_125_arg_1 : var_125_arg_2=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L293] SORT_1 var_125 = var_125_arg_0 ? var_125_arg_1 : var_125_arg_2; [L294] SORT_1 next_126_arg_1 = var_125; [L296] state_10 = next_78_arg_1 [L297] state_12 = next_80_arg_1 [L298] state_18 = next_82_arg_1 [L299] state_23 = next_84_arg_1 [L300] state_26 = next_90_arg_1 [L301] state_41 = next_92_arg_1 [L302] state_43 = next_94_arg_1 [L303] state_45 = next_96_arg_1 [L304] state_47 = next_98_arg_1 [L305] state_49 = next_100_arg_1 [L306] state_53 = next_102_arg_1 [L307] state_55 = next_104_arg_1 [L308] state_57 = next_106_arg_1 [L309] state_59 = next_114_arg_1 [L310] state_62 = next_116_arg_1 [L311] state_64 = next_118_arg_1 [L312] state_66 = next_120_arg_1 [L313] state_68 = next_122_arg_1 [L314] state_70 = next_124_arg_1 [L315] state_72 = next_126_arg_1 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=65, input_35=2, input_37=5, input_39=4, input_4=32, input_51=3, input_6=6, input_7=1, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L110] input_2 = __VERIFIER_nondet_uchar() [L111] input_3 = __VERIFIER_nondet_uchar() [L112] input_4 = __VERIFIER_nondet_uchar() [L113] input_6 = __VERIFIER_nondet_uchar() [L114] input_7 = __VERIFIER_nondet_uchar() [L115] input_8 = __VERIFIER_nondet_uchar() [L116] input_8 = input_8 & mask_SORT_5 [L117] input_35 = __VERIFIER_nondet_uchar() [L118] input_37 = __VERIFIER_nondet_uchar() [L119] input_39 = __VERIFIER_nondet_uchar() [L120] input_51 = __VERIFIER_nondet_uchar() [L123] SORT_1 var_16_arg_0 = state_10; [L124] SORT_5 var_16 = var_16_arg_0 >> 0; [L125] var_16 = var_16 & mask_SORT_5 [L126] SORT_1 var_15_arg_0 = state_10; [L127] SORT_1 var_15_arg_1 = state_12; [L128] SORT_1 var_15 = var_15_arg_0 + var_15_arg_1; [L129] SORT_1 var_14_arg_0 = state_10; [L130] SORT_1 var_14_arg_1 = state_12; [L131] SORT_1 var_14 = var_14_arg_0 - var_14_arg_1; [L132] SORT_5 var_17_arg_0 = var_16; [L133] SORT_1 var_17_arg_1 = var_15; [L134] SORT_1 var_17_arg_2 = var_14; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L135] EXPR var_17_arg_0 ? var_17_arg_1 : var_17_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_0 ? var_17_arg_1 : var_17_arg_2=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L135] SORT_1 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L136] SORT_1 var_21_arg_0 = var_17; [L137] SORT_1 var_21_arg_1 = state_18; [L138] SORT_1 var_21 = var_21_arg_0 + var_21_arg_1; [L139] SORT_1 var_20_arg_0 = var_17; [L140] SORT_1 var_20_arg_1 = state_18; [L141] SORT_1 var_20 = var_20_arg_0 - var_20_arg_1; [L142] SORT_5 var_25_arg_0 = state_23; [L143] SORT_1 var_25_arg_1 = var_21; [L144] SORT_1 var_25_arg_2 = var_20; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L145] EXPR var_25_arg_0 ? var_25_arg_1 : var_25_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_0 ? var_25_arg_1 : var_25_arg_2=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L145] SORT_1 var_25 = var_25_arg_0 ? var_25_arg_1 : var_25_arg_2; [L146] var_25 = var_25 & mask_SORT_1 [L147] SORT_1 var_28_arg_0 = var_25; [L148] SORT_1 var_28_arg_1 = state_26; [L149] SORT_5 var_28 = var_28_arg_0 == var_28_arg_1; [L150] SORT_5 var_32_arg_0 = var_28; [L151] SORT_5 var_32 = ~var_32_arg_0; [L152] SORT_5 var_33_arg_0 = var_31; [L153] SORT_5 var_33_arg_1 = var_32; [L154] SORT_5 var_33 = var_33_arg_0 & var_33_arg_1; [L155] var_33 = var_33 & mask_SORT_5 [L156] SORT_5 bad_34_arg_0 = var_33; [L157] CALL __VERIFIER_assert(!(bad_34_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L157] RET __VERIFIER_assert(!(bad_34_arg_0)) [L159] SORT_5 var_76_arg_0 = input_8; [L160] SORT_5 var_76_arg_1 = var_31; [L161] SORT_5 var_76 = var_76_arg_0 == var_76_arg_1; [L162] SORT_5 var_77_arg_0 = var_76; [L163] SORT_1 var_77_arg_1 = var_9; [L164] SORT_1 var_77_arg_2 = state_64; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L165] EXPR var_77_arg_0 ? var_77_arg_1 : var_77_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_0 ? var_77_arg_1 : var_77_arg_2=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L165] SORT_1 var_77 = var_77_arg_0 ? var_77_arg_1 : var_77_arg_2; [L166] SORT_1 next_78_arg_1 = var_77; [L167] SORT_5 var_79_arg_0 = var_76; [L168] SORT_1 var_79_arg_1 = var_9; [L169] SORT_1 var_79_arg_2 = state_68; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L170] EXPR var_79_arg_0 ? var_79_arg_1 : var_79_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_0 ? var_79_arg_1 : var_79_arg_2=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L170] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L171] SORT_1 next_80_arg_1 = var_79; [L172] SORT_5 var_81_arg_0 = var_76; [L173] SORT_1 var_81_arg_1 = var_9; [L174] SORT_1 var_81_arg_2 = state_72; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L175] EXPR var_81_arg_0 ? var_81_arg_1 : var_81_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_0 ? var_81_arg_1 : var_81_arg_2=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L175] SORT_1 var_81 = var_81_arg_0 ? var_81_arg_1 : var_81_arg_2; [L176] SORT_1 next_82_arg_1 = var_81; [L177] SORT_5 var_83_arg_0 = var_76; [L178] SORT_5 var_83_arg_1 = var_22; [L179] SORT_5 var_83_arg_2 = state_43; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L180] EXPR var_83_arg_0 ? var_83_arg_1 : var_83_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_0 ? var_83_arg_1 : var_83_arg_2=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L180] SORT_5 var_83 = var_83_arg_0 ? var_83_arg_1 : var_83_arg_2; [L181] var_83 = var_83 & mask_SORT_5 [L182] SORT_5 next_84_arg_1 = var_83; [L183] SORT_5 var_88_arg_0 = input_8; [L184] SORT_5 var_88_arg_1 = var_31; [L185] SORT_5 var_88 = var_88_arg_0 == var_88_arg_1; [L186] SORT_1 var_86_arg_0 = state_59; [L187] SORT_1 var_86_arg_1 = state_55; [L188] SORT_1 var_86 = var_86_arg_0 - var_86_arg_1; [L189] SORT_1 var_85_arg_0 = state_59; [L190] SORT_1 var_85_arg_1 = state_55; [L191] SORT_1 var_85 = var_85_arg_0 - var_85_arg_1; [L192] SORT_5 var_87_arg_0 = state_57; [L193] SORT_1 var_87_arg_1 = var_86; [L194] SORT_1 var_87_arg_2 = var_85; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L195] EXPR var_87_arg_0 ? var_87_arg_1 : var_87_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_0 ? var_87_arg_1 : var_87_arg_2=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L195] SORT_1 var_87 = var_87_arg_0 ? var_87_arg_1 : var_87_arg_2; [L196] SORT_5 var_89_arg_0 = var_88; [L197] SORT_1 var_89_arg_1 = var_9; [L198] SORT_1 var_89_arg_2 = var_87; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L199] EXPR var_89_arg_0 ? var_89_arg_1 : var_89_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_0 ? var_89_arg_1 : var_89_arg_2=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=1, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L199] SORT_1 var_89 = var_89_arg_0 ? var_89_arg_1 : var_89_arg_2; [L200] var_89 = var_89 & mask_SORT_1 [L201] SORT_1 next_90_arg_1 = var_89; [L202] SORT_5 var_91_arg_0 = var_76; [L203] SORT_5 var_91_arg_1 = var_22; [L204] SORT_5 var_91_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L205] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=1, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=1, var_91_arg_0=0, var_91_arg_0 ? var_91_arg_1 : var_91_arg_2=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L205] SORT_5 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L206] SORT_5 next_92_arg_1 = var_91; [L207] SORT_5 var_93_arg_0 = var_76; [L208] SORT_5 var_93_arg_1 = var_22; [L209] SORT_5 var_93_arg_2 = state_41; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L210] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_0 ? var_93_arg_1 : var_93_arg_2=1, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L210] SORT_5 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L211] SORT_5 next_94_arg_1 = var_93; [L212] SORT_5 var_95_arg_0 = var_88; [L213] SORT_1 var_95_arg_1 = var_9; [L214] SORT_1 var_95_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L215] EXPR var_95_arg_0 ? var_95_arg_1 : var_95_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_0 ? var_95_arg_1 : var_95_arg_2=1, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=65, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L215] SORT_1 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L216] SORT_1 next_96_arg_1 = var_95; [L217] SORT_5 var_97_arg_0 = var_88; [L218] SORT_1 var_97_arg_1 = var_9; [L219] SORT_1 var_97_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L220] EXPR var_97_arg_0 ? var_97_arg_1 : var_97_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=65, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=65, var_97_arg_0=0, var_97_arg_0 ? var_97_arg_1 : var_97_arg_2=0, var_97_arg_1=0, var_97_arg_2=0, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=32] [L220] SORT_1 var_97 = var_97_arg_0 ? var_97_arg_1 : var_97_arg_2; [L221] SORT_1 next_98_arg_1 = var_97; [L222] SORT_5 var_99_arg_0 = var_88; [L223] SORT_1 var_99_arg_1 = var_9; [L224] SORT_1 var_99_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=32, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L225] EXPR var_99_arg_0 ? var_99_arg_1 : var_99_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=32, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=1, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=32, var_99_arg_0=0, var_99_arg_0 ? var_99_arg_1 : var_99_arg_2=0, var_99_arg_1=0, var_99_arg_2=0] [L225] SORT_1 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; [L226] SORT_1 next_100_arg_1 = var_99; [L227] SORT_5 var_101_arg_0 = var_88; [L228] SORT_5 var_101_arg_1 = var_22; [L229] SORT_5 var_101_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L230] EXPR var_101_arg_0 ? var_101_arg_1 : var_101_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=1, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=1, var_101_arg_0=0, var_101_arg_0 ? var_101_arg_1 : var_101_arg_2=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L230] SORT_5 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L231] SORT_5 next_102_arg_1 = var_101; [L232] SORT_5 var_103_arg_0 = var_88; [L233] SORT_1 var_103_arg_1 = var_9; [L234] SORT_1 var_103_arg_2 = state_49; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L235] EXPR var_103_arg_0 ? var_103_arg_1 : var_103_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_0 ? var_103_arg_1 : var_103_arg_2=32, var_103_arg_1=0, var_103_arg_2=32, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L235] SORT_1 var_103 = var_103_arg_0 ? var_103_arg_1 : var_103_arg_2; [L236] SORT_1 next_104_arg_1 = var_103; [L237] SORT_5 var_105_arg_0 = var_88; [L238] SORT_5 var_105_arg_1 = var_22; [L239] SORT_5 var_105_arg_2 = state_53; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L240] EXPR var_105_arg_0 ? var_105_arg_1 : var_105_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=0, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=0, var_105_arg_0=0, var_105_arg_0 ? var_105_arg_1 : var_105_arg_2=1, var_105_arg_1=0, var_105_arg_2=1, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=0, var_108_arg_0=0, var_108_arg_1=0, var_109=1, var_110=0, var_110_arg_0=0, var_110_arg_1=1, var_111=0, var_111_arg_0=0, var_111_arg_1=1, var_112=0, var_112_arg_0=0, var_112_arg_1=0, var_112_arg_2=0, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L240] SORT_5 var_105 = var_105_arg_0 ? var_105_arg_1 : var_105_arg_2; [L241] var_105 = var_105 & mask_SORT_5 [L242] SORT_5 next_106_arg_1 = var_105; [L243] SORT_1 var_110_arg_0 = state_45; [L244] SORT_1 var_110_arg_1 = var_109; [L245] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L246] var_110 = var_110 & mask_SORT_1 [L247] SORT_1 var_111_arg_0 = var_110; [L248] SORT_1 var_111_arg_1 = var_109; [L249] SORT_5 var_111 = var_111_arg_0 == var_111_arg_1; [L250] SORT_1 var_108_arg_0 = state_45; [L251] SORT_1 var_108_arg_1 = state_47; [L252] SORT_1 var_108 = var_108_arg_0 + var_108_arg_1; [L253] SORT_1 var_107_arg_0 = state_45; [L254] SORT_1 var_107_arg_1 = state_47; [L255] SORT_1 var_107 = var_107_arg_0 - var_107_arg_1; [L256] SORT_5 var_112_arg_0 = var_111; [L257] SORT_1 var_112_arg_1 = var_108; [L258] SORT_1 var_112_arg_2 = var_107; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=0, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L259] EXPR var_112_arg_0 ? var_112_arg_1 : var_112_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=0, var_112_arg_0=1, var_112_arg_0 ? var_112_arg_1 : var_112_arg_2=66, var_112_arg_1=66, var_112_arg_2=192, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=0, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L259] SORT_1 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L260] SORT_5 var_113_arg_0 = var_88; [L261] SORT_1 var_113_arg_1 = var_9; [L262] SORT_1 var_113_arg_2 = var_112; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=0, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L263] EXPR var_113_arg_0 ? var_113_arg_1 : var_113_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=0, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=0, var_113_arg_0=0, var_113_arg_0 ? var_113_arg_1 : var_113_arg_2=66, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L263] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L264] SORT_1 next_114_arg_1 = var_113; [L265] SORT_5 var_115_arg_0 = var_76; [L266] SORT_1 var_115_arg_1 = var_9; [L267] SORT_1 var_115_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L268] EXPR var_115_arg_0 ? var_115_arg_1 : var_115_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_0 ? var_115_arg_1 : var_115_arg_2=1, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L268] SORT_1 var_115 = var_115_arg_0 ? var_115_arg_1 : var_115_arg_2; [L269] SORT_1 next_116_arg_1 = var_115; [L270] SORT_5 var_117_arg_0 = var_76; [L271] SORT_1 var_117_arg_1 = var_9; [L272] SORT_1 var_117_arg_2 = state_62; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L273] EXPR var_117_arg_0 ? var_117_arg_1 : var_117_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=0, var_117_arg_0=0, var_117_arg_0 ? var_117_arg_1 : var_117_arg_2=1, var_117_arg_1=0, var_117_arg_2=1, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=65, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L273] SORT_1 var_117 = var_117_arg_0 ? var_117_arg_1 : var_117_arg_2; [L274] SORT_1 next_118_arg_1 = var_117; [L275] SORT_5 var_119_arg_0 = var_76; [L276] SORT_1 var_119_arg_1 = var_9; [L277] SORT_1 var_119_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=65, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L278] EXPR var_119_arg_0 ? var_119_arg_1 : var_119_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=65, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=65, var_119_arg_0=0, var_119_arg_0 ? var_119_arg_1 : var_119_arg_2=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L278] SORT_1 var_119 = var_119_arg_0 ? var_119_arg_1 : var_119_arg_2; [L279] SORT_1 next_120_arg_1 = var_119; [L280] SORT_5 var_121_arg_0 = var_76; [L281] SORT_1 var_121_arg_1 = var_9; [L282] SORT_1 var_121_arg_2 = state_66; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L283] EXPR var_121_arg_0 ? var_121_arg_1 : var_121_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_0 ? var_121_arg_1 : var_121_arg_2=65, var_121_arg_1=0, var_121_arg_2=65, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=32, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L283] SORT_1 var_121 = var_121_arg_0 ? var_121_arg_1 : var_121_arg_2; [L284] SORT_1 next_122_arg_1 = var_121; [L285] SORT_5 var_123_arg_0 = var_76; [L286] SORT_1 var_123_arg_1 = var_9; [L287] SORT_1 var_123_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=32, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L288] EXPR var_123_arg_0 ? var_123_arg_1 : var_123_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=32, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=32, var_123_arg_0=0, var_123_arg_0 ? var_123_arg_1 : var_123_arg_2=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L288] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L289] SORT_1 next_124_arg_1 = var_123; [L290] SORT_5 var_125_arg_0 = var_76; [L291] SORT_1 var_125_arg_1 = var_9; [L292] SORT_1 var_125_arg_2 = state_70; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L293] EXPR var_125_arg_0 ? var_125_arg_1 : var_125_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=1, state_43=0, state_45=1, state_47=65, state_49=32, state_53=1, state_55=0, state_57=0, state_59=0, state_62=1, state_64=0, state_66=65, state_68=0, state_70=32, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_0 ? var_125_arg_1 : var_125_arg_2=32, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L293] SORT_1 var_125 = var_125_arg_0 ? var_125_arg_1 : var_125_arg_2; [L294] SORT_1 next_126_arg_1 = var_125; [L296] state_10 = next_78_arg_1 [L297] state_12 = next_80_arg_1 [L298] state_18 = next_82_arg_1 [L299] state_23 = next_84_arg_1 [L300] state_26 = next_90_arg_1 [L301] state_41 = next_92_arg_1 [L302] state_43 = next_94_arg_1 [L303] state_45 = next_96_arg_1 [L304] state_47 = next_98_arg_1 [L305] state_49 = next_100_arg_1 [L306] state_53 = next_102_arg_1 [L307] state_55 = next_104_arg_1 [L308] state_57 = next_106_arg_1 [L309] state_59 = next_114_arg_1 [L310] state_62 = next_116_arg_1 [L311] state_64 = next_118_arg_1 [L312] state_66 = next_120_arg_1 [L313] state_68 = next_122_arg_1 [L314] state_70 = next_124_arg_1 [L315] state_72 = next_126_arg_1 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=1, input_3=0, input_35=7, input_37=10, input_39=11, input_4=0, input_51=9, input_6=8, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L110] input_2 = __VERIFIER_nondet_uchar() [L111] input_3 = __VERIFIER_nondet_uchar() [L112] input_4 = __VERIFIER_nondet_uchar() [L113] input_6 = __VERIFIER_nondet_uchar() [L114] input_7 = __VERIFIER_nondet_uchar() [L115] input_8 = __VERIFIER_nondet_uchar() [L116] input_8 = input_8 & mask_SORT_5 [L117] input_35 = __VERIFIER_nondet_uchar() [L118] input_37 = __VERIFIER_nondet_uchar() [L119] input_39 = __VERIFIER_nondet_uchar() [L120] input_51 = __VERIFIER_nondet_uchar() [L123] SORT_1 var_16_arg_0 = state_10; [L124] SORT_5 var_16 = var_16_arg_0 >> 0; [L125] var_16 = var_16 & mask_SORT_5 [L126] SORT_1 var_15_arg_0 = state_10; [L127] SORT_1 var_15_arg_1 = state_12; [L128] SORT_1 var_15 = var_15_arg_0 + var_15_arg_1; [L129] SORT_1 var_14_arg_0 = state_10; [L130] SORT_1 var_14_arg_1 = state_12; [L131] SORT_1 var_14 = var_14_arg_0 - var_14_arg_1; [L132] SORT_5 var_17_arg_0 = var_16; [L133] SORT_1 var_17_arg_1 = var_15; [L134] SORT_1 var_17_arg_2 = var_14; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L135] EXPR var_17_arg_0 ? var_17_arg_1 : var_17_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_0 ? var_17_arg_1 : var_17_arg_2=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L135] SORT_1 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L136] SORT_1 var_21_arg_0 = var_17; [L137] SORT_1 var_21_arg_1 = state_18; [L138] SORT_1 var_21 = var_21_arg_0 + var_21_arg_1; [L139] SORT_1 var_20_arg_0 = var_17; [L140] SORT_1 var_20_arg_1 = state_18; [L141] SORT_1 var_20 = var_20_arg_0 - var_20_arg_1; [L142] SORT_5 var_25_arg_0 = state_23; [L143] SORT_1 var_25_arg_1 = var_21; [L144] SORT_1 var_25_arg_2 = var_20; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L145] EXPR var_25_arg_0 ? var_25_arg_1 : var_25_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_0 ? var_25_arg_1 : var_25_arg_2=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L145] SORT_1 var_25 = var_25_arg_0 ? var_25_arg_1 : var_25_arg_2; [L146] var_25 = var_25 & mask_SORT_1 [L147] SORT_1 var_28_arg_0 = var_25; [L148] SORT_1 var_28_arg_1 = state_26; [L149] SORT_5 var_28 = var_28_arg_0 == var_28_arg_1; [L150] SORT_5 var_32_arg_0 = var_28; [L151] SORT_5 var_32 = ~var_32_arg_0; [L152] SORT_5 var_33_arg_0 = var_31; [L153] SORT_5 var_33_arg_1 = var_32; [L154] SORT_5 var_33 = var_33_arg_0 & var_33_arg_1; [L155] var_33 = var_33 & mask_SORT_5 [L156] SORT_5 bad_34_arg_0 = var_33; [L157] CALL __VERIFIER_assert(!(bad_34_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L157] RET __VERIFIER_assert(!(bad_34_arg_0)) [L159] SORT_5 var_76_arg_0 = input_8; [L160] SORT_5 var_76_arg_1 = var_31; [L161] SORT_5 var_76 = var_76_arg_0 == var_76_arg_1; [L162] SORT_5 var_77_arg_0 = var_76; [L163] SORT_1 var_77_arg_1 = var_9; [L164] SORT_1 var_77_arg_2 = state_64; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L165] EXPR var_77_arg_0 ? var_77_arg_1 : var_77_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=0, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_0 ? var_77_arg_1 : var_77_arg_2=1, var_77_arg_1=0, var_77_arg_2=1, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=0, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L165] SORT_1 var_77 = var_77_arg_0 ? var_77_arg_1 : var_77_arg_2; [L166] SORT_1 next_78_arg_1 = var_77; [L167] SORT_5 var_79_arg_0 = var_76; [L168] SORT_1 var_79_arg_1 = var_9; [L169] SORT_1 var_79_arg_2 = state_68; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L170] EXPR var_79_arg_0 ? var_79_arg_1 : var_79_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=0, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=0, var_79_arg_0=0, var_79_arg_0 ? var_79_arg_1 : var_79_arg_2=65, var_79_arg_1=0, var_79_arg_2=65, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L170] SORT_1 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L171] SORT_1 next_80_arg_1 = var_79; [L172] SORT_5 var_81_arg_0 = var_76; [L173] SORT_1 var_81_arg_1 = var_9; [L174] SORT_1 var_81_arg_2 = state_72; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L175] EXPR var_81_arg_0 ? var_81_arg_1 : var_81_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=0, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=0, var_81_arg_0=0, var_81_arg_0 ? var_81_arg_1 : var_81_arg_2=32, var_81_arg_1=0, var_81_arg_2=32, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L175] SORT_1 var_81 = var_81_arg_0 ? var_81_arg_1 : var_81_arg_2; [L176] SORT_1 next_82_arg_1 = var_81; [L177] SORT_5 var_83_arg_0 = var_76; [L178] SORT_5 var_83_arg_1 = var_22; [L179] SORT_5 var_83_arg_2 = state_43; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L180] EXPR var_83_arg_0 ? var_83_arg_1 : var_83_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=0, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=0, var_83_arg_0=0, var_83_arg_0 ? var_83_arg_1 : var_83_arg_2=1, var_83_arg_1=0, var_83_arg_2=1, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L180] SORT_5 var_83 = var_83_arg_0 ? var_83_arg_1 : var_83_arg_2; [L181] var_83 = var_83 & mask_SORT_5 [L182] SORT_5 next_84_arg_1 = var_83; [L183] SORT_5 var_88_arg_0 = input_8; [L184] SORT_5 var_88_arg_1 = var_31; [L185] SORT_5 var_88 = var_88_arg_0 == var_88_arg_1; [L186] SORT_1 var_86_arg_0 = state_59; [L187] SORT_1 var_86_arg_1 = state_55; [L188] SORT_1 var_86 = var_86_arg_0 - var_86_arg_1; [L189] SORT_1 var_85_arg_0 = state_59; [L190] SORT_1 var_85_arg_1 = state_55; [L191] SORT_1 var_85 = var_85_arg_0 - var_85_arg_1; [L192] SORT_5 var_87_arg_0 = state_57; [L193] SORT_1 var_87_arg_1 = var_86; [L194] SORT_1 var_87_arg_2 = var_85; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=0, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L195] EXPR var_87_arg_0 ? var_87_arg_1 : var_87_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=0, var_87_arg_0=1, var_87_arg_0 ? var_87_arg_1 : var_87_arg_2=34, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=0, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L195] SORT_1 var_87 = var_87_arg_0 ? var_87_arg_1 : var_87_arg_2; [L196] SORT_5 var_89_arg_0 = var_88; [L197] SORT_1 var_89_arg_1 = var_9; [L198] SORT_1 var_89_arg_2 = var_87; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L199] EXPR var_89_arg_0 ? var_89_arg_1 : var_89_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_0 ? var_89_arg_1 : var_89_arg_2=34, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L199] SORT_1 var_89 = var_89_arg_0 ? var_89_arg_1 : var_89_arg_2; [L200] var_89 = var_89 & mask_SORT_1 [L201] SORT_1 next_90_arg_1 = var_89; [L202] SORT_5 var_91_arg_0 = var_76; [L203] SORT_5 var_91_arg_1 = var_22; [L204] SORT_5 var_91_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L205] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_0 ? var_91_arg_1 : var_91_arg_2=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=1, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L205] SORT_5 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L206] SORT_5 next_92_arg_1 = var_91; [L207] SORT_5 var_93_arg_0 = var_76; [L208] SORT_5 var_93_arg_1 = var_22; [L209] SORT_5 var_93_arg_2 = state_41; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L210] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=1, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=1, var_93_arg_0=0, var_93_arg_0 ? var_93_arg_1 : var_93_arg_2=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=1, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L210] SORT_5 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L211] SORT_5 next_94_arg_1 = var_93; [L212] SORT_5 var_95_arg_0 = var_88; [L213] SORT_1 var_95_arg_1 = var_9; [L214] SORT_1 var_95_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L215] EXPR var_95_arg_0 ? var_95_arg_1 : var_95_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=1, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=1, var_95_arg_0=0, var_95_arg_0 ? var_95_arg_1 : var_95_arg_2=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L215] SORT_1 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L216] SORT_1 next_96_arg_1 = var_95; [L217] SORT_5 var_97_arg_0 = var_88; [L218] SORT_1 var_97_arg_1 = var_9; [L219] SORT_1 var_97_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L220] EXPR var_97_arg_0 ? var_97_arg_1 : var_97_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_0 ? var_97_arg_1 : var_97_arg_2=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L220] SORT_1 var_97 = var_97_arg_0 ? var_97_arg_1 : var_97_arg_2; [L221] SORT_1 next_98_arg_1 = var_97; [L222] SORT_5 var_99_arg_0 = var_88; [L223] SORT_1 var_99_arg_1 = var_9; [L224] SORT_1 var_99_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L225] EXPR var_99_arg_0 ? var_99_arg_1 : var_99_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_0 ? var_99_arg_1 : var_99_arg_2=0, var_99_arg_1=0, var_99_arg_2=0] [L225] SORT_1 var_99 = var_99_arg_0 ? var_99_arg_1 : var_99_arg_2; [L226] SORT_1 next_100_arg_1 = var_99; [L227] SORT_5 var_101_arg_0 = var_88; [L228] SORT_5 var_101_arg_1 = var_22; [L229] SORT_5 var_101_arg_2 = input_7; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L230] EXPR var_101_arg_0 ? var_101_arg_1 : var_101_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_0 ? var_101_arg_1 : var_101_arg_2=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=32, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L230] SORT_5 var_101 = var_101_arg_0 ? var_101_arg_1 : var_101_arg_2; [L231] SORT_5 next_102_arg_1 = var_101; [L232] SORT_5 var_103_arg_0 = var_88; [L233] SORT_1 var_103_arg_1 = var_9; [L234] SORT_1 var_103_arg_2 = state_49; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L235] EXPR var_103_arg_0 ? var_103_arg_1 : var_103_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=32, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=32, var_103_arg_0=0, var_103_arg_0 ? var_103_arg_1 : var_103_arg_2=0, var_103_arg_1=0, var_103_arg_2=0, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=1, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L235] SORT_1 var_103 = var_103_arg_0 ? var_103_arg_1 : var_103_arg_2; [L236] SORT_1 next_104_arg_1 = var_103; [L237] SORT_5 var_105_arg_0 = var_88; [L238] SORT_5 var_105_arg_1 = var_22; [L239] SORT_5 var_105_arg_2 = state_53; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=1, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L240] EXPR var_105_arg_0 ? var_105_arg_1 : var_105_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=1, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=1, var_105_arg_0=0, var_105_arg_0 ? var_105_arg_1 : var_105_arg_2=0, var_105_arg_1=0, var_105_arg_2=0, var_107=192, var_107_arg_0=1, var_107_arg_1=65, var_108=66, var_108_arg_0=1, var_108_arg_1=65, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=66, var_112_arg_2=192, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L240] SORT_5 var_105 = var_105_arg_0 ? var_105_arg_1 : var_105_arg_2; [L241] var_105 = var_105 & mask_SORT_5 [L242] SORT_5 next_106_arg_1 = var_105; [L243] SORT_1 var_110_arg_0 = state_45; [L244] SORT_1 var_110_arg_1 = var_109; [L245] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L246] var_110 = var_110 & mask_SORT_1 [L247] SORT_1 var_111_arg_0 = var_110; [L248] SORT_1 var_111_arg_1 = var_109; [L249] SORT_5 var_111 = var_111_arg_0 == var_111_arg_1; [L250] SORT_1 var_108_arg_0 = state_45; [L251] SORT_1 var_108_arg_1 = state_47; [L252] SORT_1 var_108 = var_108_arg_0 + var_108_arg_1; [L253] SORT_1 var_107_arg_0 = state_45; [L254] SORT_1 var_107_arg_1 = state_47; [L255] SORT_1 var_107 = var_107_arg_0 - var_107_arg_1; [L256] SORT_5 var_112_arg_0 = var_111; [L257] SORT_1 var_112_arg_1 = var_108; [L258] SORT_1 var_112_arg_2 = var_107; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L259] EXPR var_112_arg_0 ? var_112_arg_1 : var_112_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=66, var_112_arg_0=1, var_112_arg_0 ? var_112_arg_1 : var_112_arg_2=1, var_112_arg_1=1, var_112_arg_2=1, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=66, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L259] SORT_1 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L260] SORT_5 var_113_arg_0 = var_88; [L261] SORT_1 var_113_arg_1 = var_9; [L262] SORT_1 var_113_arg_2 = var_112; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=66, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L263] EXPR var_113_arg_0 ? var_113_arg_1 : var_113_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=66, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=66, var_113_arg_0=0, var_113_arg_0 ? var_113_arg_1 : var_113_arg_2=1, var_113_arg_1=0, var_113_arg_2=1, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=1, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L263] SORT_1 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L264] SORT_1 next_114_arg_1 = var_113; [L265] SORT_5 var_115_arg_0 = var_76; [L266] SORT_1 var_115_arg_1 = var_9; [L267] SORT_1 var_115_arg_2 = input_2; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=1, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L268] EXPR var_115_arg_0 ? var_115_arg_1 : var_115_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=1, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=1, var_115_arg_0=0, var_115_arg_0 ? var_115_arg_1 : var_115_arg_2=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L268] SORT_1 var_115 = var_115_arg_0 ? var_115_arg_1 : var_115_arg_2; [L269] SORT_1 next_116_arg_1 = var_115; [L270] SORT_5 var_117_arg_0 = var_76; [L271] SORT_1 var_117_arg_1 = var_9; [L272] SORT_1 var_117_arg_2 = state_62; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L273] EXPR var_117_arg_0 ? var_117_arg_1 : var_117_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_0 ? var_117_arg_1 : var_117_arg_2=1, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L273] SORT_1 var_117 = var_117_arg_0 ? var_117_arg_1 : var_117_arg_2; [L274] SORT_1 next_118_arg_1 = var_117; [L275] SORT_5 var_119_arg_0 = var_76; [L276] SORT_1 var_119_arg_1 = var_9; [L277] SORT_1 var_119_arg_2 = input_3; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L278] EXPR var_119_arg_0 ? var_119_arg_1 : var_119_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_0 ? var_119_arg_1 : var_119_arg_2=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=65, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L278] SORT_1 var_119 = var_119_arg_0 ? var_119_arg_1 : var_119_arg_2; [L279] SORT_1 next_120_arg_1 = var_119; [L280] SORT_5 var_121_arg_0 = var_76; [L281] SORT_1 var_121_arg_1 = var_9; [L282] SORT_1 var_121_arg_2 = state_66; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L283] EXPR var_121_arg_0 ? var_121_arg_1 : var_121_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=65, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=65, var_121_arg_0=0, var_121_arg_0 ? var_121_arg_1 : var_121_arg_2=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L283] SORT_1 var_121 = var_121_arg_0 ? var_121_arg_1 : var_121_arg_2; [L284] SORT_1 next_122_arg_1 = var_121; [L285] SORT_5 var_123_arg_0 = var_76; [L286] SORT_1 var_123_arg_1 = var_9; [L287] SORT_1 var_123_arg_2 = input_4; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L288] EXPR var_123_arg_0 ? var_123_arg_1 : var_123_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_0 ? var_123_arg_1 : var_123_arg_2=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=32, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L288] SORT_1 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L289] SORT_1 next_124_arg_1 = var_123; [L290] SORT_5 var_125_arg_0 = var_76; [L291] SORT_1 var_125_arg_1 = var_9; [L292] SORT_1 var_125_arg_2 = state_70; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L293] EXPR var_125_arg_0 ? var_125_arg_1 : var_125_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=32, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=0, state_12=0, state_18=0, state_23=0, state_26=0, state_41=0, state_43=1, state_45=1, state_47=0, state_49=0, state_53=0, state_55=32, state_57=1, state_59=66, state_62=1, state_64=1, state_66=0, state_68=65, state_70=0, state_72=32, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=32, var_125_arg_0=0, var_125_arg_0 ? var_125_arg_1 : var_125_arg_2=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L293] SORT_1 var_125 = var_125_arg_0 ? var_125_arg_1 : var_125_arg_2; [L294] SORT_1 next_126_arg_1 = var_125; [L296] state_10 = next_78_arg_1 [L297] state_12 = next_80_arg_1 [L298] state_18 = next_82_arg_1 [L299] state_23 = next_84_arg_1 [L300] state_26 = next_90_arg_1 [L301] state_41 = next_92_arg_1 [L302] state_43 = next_94_arg_1 [L303] state_45 = next_96_arg_1 [L304] state_47 = next_98_arg_1 [L305] state_49 = next_100_arg_1 [L306] state_53 = next_102_arg_1 [L307] state_55 = next_104_arg_1 [L308] state_57 = next_106_arg_1 [L309] state_59 = next_114_arg_1 [L310] state_62 = next_116_arg_1 [L311] state_64 = next_118_arg_1 [L312] state_66 = next_120_arg_1 [L313] state_68 = next_122_arg_1 [L314] state_70 = next_124_arg_1 [L315] state_72 = next_126_arg_1 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=0, input_3=0, input_35=12, input_37=15, input_39=16, input_4=0, input_51=14, input_6=13, input_7=0, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=1, state_12=65, state_18=32, state_23=1, state_26=34, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=1, state_62=0, state_64=1, state_66=0, state_68=0, state_70=0, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=0, var_14_arg_0=0, var_14_arg_1=0, var_15=0, var_15_arg_0=0, var_15_arg_1=0, var_16=0, var_16_arg_0=0, var_17=0, var_17_arg_0=0, var_17_arg_1=0, var_17_arg_2=0, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L110] input_2 = __VERIFIER_nondet_uchar() [L111] input_3 = __VERIFIER_nondet_uchar() [L112] input_4 = __VERIFIER_nondet_uchar() [L113] input_6 = __VERIFIER_nondet_uchar() [L114] input_7 = __VERIFIER_nondet_uchar() [L115] input_8 = __VERIFIER_nondet_uchar() [L116] input_8 = input_8 & mask_SORT_5 [L117] input_35 = __VERIFIER_nondet_uchar() [L118] input_37 = __VERIFIER_nondet_uchar() [L119] input_39 = __VERIFIER_nondet_uchar() [L120] input_51 = __VERIFIER_nondet_uchar() [L123] SORT_1 var_16_arg_0 = state_10; [L124] SORT_5 var_16 = var_16_arg_0 >> 0; [L125] var_16 = var_16 & mask_SORT_5 [L126] SORT_1 var_15_arg_0 = state_10; [L127] SORT_1 var_15_arg_1 = state_12; [L128] SORT_1 var_15 = var_15_arg_0 + var_15_arg_1; [L129] SORT_1 var_14_arg_0 = state_10; [L130] SORT_1 var_14_arg_1 = state_12; [L131] SORT_1 var_14 = var_14_arg_0 - var_14_arg_1; [L132] SORT_5 var_17_arg_0 = var_16; [L133] SORT_1 var_17_arg_1 = var_15; [L134] SORT_1 var_17_arg_2 = var_14; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=23, input_3=17, input_35=19, input_37=22, input_39=25, input_4=18, input_51=21, input_6=20, input_7=24, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=1, state_12=65, state_18=32, state_23=1, state_26=34, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=1, state_62=0, state_64=1, state_66=0, state_68=0, state_70=0, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=192, var_14_arg_0=1, var_14_arg_1=65, var_15=66, var_15_arg_0=1, var_15_arg_1=65, var_16=1, var_16_arg_0=1, var_17=0, var_17_arg_0=1, var_17_arg_1=66, var_17_arg_2=192, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L135] EXPR var_17_arg_0 ? var_17_arg_1 : var_17_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=23, input_3=17, input_35=19, input_37=22, input_39=25, input_4=18, input_51=21, input_6=20, input_7=24, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=1, state_12=65, state_18=32, state_23=1, state_26=34, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=1, state_62=0, state_64=1, state_66=0, state_68=0, state_70=0, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=192, var_14_arg_0=1, var_14_arg_1=65, var_15=66, var_15_arg_0=1, var_15_arg_1=65, var_16=1, var_16_arg_0=1, var_17=0, var_17_arg_0=1, var_17_arg_0 ? var_17_arg_1 : var_17_arg_2=66, var_17_arg_1=66, var_17_arg_2=192, var_20=0, var_20_arg_0=0, var_20_arg_1=0, var_21=0, var_21_arg_0=0, var_21_arg_1=0, var_22=0, var_25=0, var_25_arg_0=0, var_25_arg_1=0, var_25_arg_2=0, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L135] SORT_1 var_17 = var_17_arg_0 ? var_17_arg_1 : var_17_arg_2; [L136] SORT_1 var_21_arg_0 = var_17; [L137] SORT_1 var_21_arg_1 = state_18; [L138] SORT_1 var_21 = var_21_arg_0 + var_21_arg_1; [L139] SORT_1 var_20_arg_0 = var_17; [L140] SORT_1 var_20_arg_1 = state_18; [L141] SORT_1 var_20 = var_20_arg_0 - var_20_arg_1; [L142] SORT_5 var_25_arg_0 = state_23; [L143] SORT_1 var_25_arg_1 = var_21; [L144] SORT_1 var_25_arg_2 = var_20; VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=23, input_3=17, input_35=19, input_37=22, input_39=25, input_4=18, input_51=21, input_6=20, input_7=24, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=1, state_12=65, state_18=32, state_23=1, state_26=34, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=1, state_62=0, state_64=1, state_66=0, state_68=0, state_70=0, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=192, var_14_arg_0=1, var_14_arg_1=65, var_15=66, var_15_arg_0=1, var_15_arg_1=65, var_16=1, var_16_arg_0=1, var_17=66, var_17_arg_0=1, var_17_arg_1=66, var_17_arg_2=192, var_20=34, var_20_arg_0=66, var_20_arg_1=32, var_21=98, var_21_arg_0=66, var_21_arg_1=32, var_22=0, var_25=0, var_25_arg_0=1, var_25_arg_1=98, var_25_arg_2=34, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L145] EXPR var_25_arg_0 ? var_25_arg_1 : var_25_arg_2 VAL [bad_34_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_19_arg_1=0, init_24_arg_1=0, init_27_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_63_arg_1=0, init_65_arg_1=0, init_67_arg_1=0, init_69_arg_1=0, init_71_arg_1=0, init_73_arg_1=0, input_2=23, input_3=17, input_35=19, input_37=22, input_39=25, input_4=18, input_51=21, input_6=20, input_7=24, input_8=0, mask_SORT_1=255, mask_SORT_5=1, msb_SORT_1=128, msb_SORT_5=1, next_100_arg_1=0, next_102_arg_1=0, next_104_arg_1=0, next_106_arg_1=0, next_114_arg_1=1, next_116_arg_1=0, next_118_arg_1=1, next_120_arg_1=0, next_122_arg_1=0, next_124_arg_1=0, next_126_arg_1=0, next_78_arg_1=1, next_80_arg_1=65, next_82_arg_1=32, next_84_arg_1=1, next_90_arg_1=34, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=0, state_10=1, state_12=65, state_18=32, state_23=1, state_26=34, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_53=0, state_55=0, state_57=0, state_59=1, state_62=0, state_64=1, state_66=0, state_68=0, state_70=0, state_72=0, var_101=0, var_101_arg_0=0, var_101_arg_1=0, var_101_arg_2=0, var_103=0, var_103_arg_0=0, var_103_arg_1=0, var_103_arg_2=0, var_105=0, var_105_arg_0=0, var_105_arg_1=0, var_105_arg_2=0, var_107=1, var_107_arg_0=1, var_107_arg_1=0, var_108=1, var_108_arg_0=1, var_108_arg_1=0, var_109=1, var_110=1, var_110_arg_0=1, var_110_arg_1=1, var_111=1, var_111_arg_0=1, var_111_arg_1=1, var_112=1, var_112_arg_0=1, var_112_arg_1=1, var_112_arg_2=1, var_113=1, var_113_arg_0=0, var_113_arg_1=0, var_113_arg_2=1, var_115=0, var_115_arg_0=0, var_115_arg_1=0, var_115_arg_2=0, var_117=1, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=1, var_119=0, var_119_arg_0=0, var_119_arg_1=0, var_119_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_123_arg_2=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_125_arg_2=0, var_14=192, var_14_arg_0=1, var_14_arg_1=65, var_15=66, var_15_arg_0=1, var_15_arg_1=65, var_16=1, var_16_arg_0=1, var_17=66, var_17_arg_0=1, var_17_arg_1=66, var_17_arg_2=192, var_20=34, var_20_arg_0=66, var_20_arg_1=32, var_21=98, var_21_arg_0=66, var_21_arg_1=32, var_22=0, var_25=0, var_25_arg_0=1, var_25_arg_0 ? var_25_arg_1 : var_25_arg_2=98, var_25_arg_1=98, var_25_arg_2=34, var_28=1, var_28_arg_0=0, var_28_arg_1=0, var_31=1, var_32=254, var_32_arg_0=1, var_33=0, var_33_arg_0=1, var_33_arg_1=254, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_79=65, var_79_arg_0=0, var_79_arg_1=0, var_79_arg_2=65, var_81=32, var_81_arg_0=0, var_81_arg_1=0, var_81_arg_2=32, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_83_arg_2=1, var_85=34, var_85_arg_0=66, var_85_arg_1=32, var_86=34, var_86_arg_0=66, var_86_arg_1=32, var_87=34, var_87_arg_0=1, var_87_arg_1=34, var_87_arg_2=34, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=34, var_89_arg_0=0, var_89_arg_1=0, var_89_arg_2=34, var_9=0, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_91_arg_2=0, var_93=0, var_93_arg_0=0, var_93_arg_1=0, var_93_arg_2=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_95_arg_2=0, var_97=0, var_97_arg_0=0, var_97_arg_1=0, var_97_arg_2=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0, var_99_arg_2=0] [L145] SORT_1 var_25 = var_25_arg_0 ? var_25_arg_1 : var_25_arg_2; [L146] var_25 = var_25 & mask_SORT_1 [L147] SORT_1 var_28_arg_0 = var_25; [L148] SORT_1 var_28_arg_1 = state_26; [L149] SORT_5 var_28 = var_28_arg_0 == var_28_arg_1; [L150] SORT_5 var_32_arg_0 = var_28; [L151] SORT_5 var_32 = ~var_32_arg_0; [L152] SORT_5 var_33_arg_0 = var_31; [L153] SORT_5 var_33_arg_1 = var_32; [L154] SORT_5 var_33 = var_33_arg_0 & var_33_arg_1; [L155] var_33 = var_33 & mask_SORT_5 [L156] SORT_5 bad_34_arg_0 = var_33; [L157] CALL __VERIFIER_assert(!(bad_34_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 59 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 409.2s, OverallIterations: 68, TraceHistogramMax: 4, PathProgramHistogramMax: 3, EmptinessCheckTime: 0.1s, AutomataDifference: 248.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 101581 SdHoareTripleChecker+Valid, 26.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 101581 mSDsluCounter, 86556 SdHoareTripleChecker+Invalid, 22.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 24194 IncrementalHoareTripleChecker+Unchecked, 77133 mSDsCounter, 8213 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 26432 IncrementalHoareTripleChecker+Invalid, 58839 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 8213 mSolverCounterUnsat, 9423 mSDtfsCounter, 26432 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 17603 GetRequests, 14651 SyntacticMatches, 22 SemanticMatches, 2930 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 530781 ImplicationChecksByTransitivity, 276.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=2422occurred in iteration=59, InterpolantAutomatonStates: 2397, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 3.5s AutomataMinimizationTime, 67 MinimizatonAttempts, 36919 StatesRemovedByMinimization, 67 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 5.2s SsaConstructionTime, 10.4s SatisfiabilityAnalysisTime, 114.5s InterpolantComputationTime, 9978 NumberOfCodeBlocks, 9927 NumberOfCodeBlocksAsserted, 108 NumberOfCheckSat, 15378 ConstructedInterpolants, 1755 QuantifiedInterpolants, 178137 SizeOfPredicates, 1636 NumberOfNonLiveVariables, 52356 ConjunctsInSsa, 2025 ConjunctsInUnsatCore, 150 InterpolantComputations, 54 PerfectInterpolantSequences, 5655/10032 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-03 02:31:35,143 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0b1f4ae-6531-4c2b-9910-9b9370bded48/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE