./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 976b5e579eb51a9c3b2aa44adf60fda10cd2a5d26988018c09fec4e23c991e41 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:47:46,783 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:47:46,786 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:47:46,849 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:47:46,850 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:47:46,851 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:47:46,853 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:47:46,855 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:47:46,857 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:47:46,858 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:47:46,860 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:47:46,861 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:47:46,862 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:47:46,863 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:47:46,865 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:47:46,867 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:47:46,868 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:47:46,869 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:47:46,872 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:47:46,875 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:47:46,877 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:47:46,891 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:47:46,892 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:47:46,894 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:47:46,898 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:47:46,899 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:47:46,899 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:47:46,900 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:47:46,901 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:47:46,909 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:47:46,909 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:47:46,911 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:47:46,913 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:47:46,915 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:47:46,917 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:47:46,918 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:47:46,919 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:47:46,919 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:47:46,920 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:47:46,924 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:47:46,925 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:47:46,927 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:47:46,976 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:47:46,977 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:47:46,977 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:47:46,977 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:47:46,978 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:47:46,978 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:47:46,979 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:47:46,979 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:47:46,979 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:47:46,979 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:47:46,980 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:47:46,980 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:47:46,980 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:47:46,981 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:47:46,981 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:47:46,981 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:47:46,981 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:47:46,982 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:47:46,982 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:47:46,983 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:47:46,983 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:47:46,983 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:47:46,983 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:47:46,984 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:47:46,984 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:47:46,984 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:47:46,985 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:47:46,985 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:47:46,985 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:47:46,985 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:47:46,986 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:47:46,986 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:47:46,986 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:47:46,987 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:47:46,987 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:47:46,987 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:47:46,987 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:47:46,988 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:47:46,988 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 976b5e579eb51a9c3b2aa44adf60fda10cd2a5d26988018c09fec4e23c991e41 [2022-11-03 02:47:47,334 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:47:47,384 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:47:47,387 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:47:47,389 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:47:47,390 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:47:47,392 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 02:47:47,469 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/ca8d6fa6b/71c487c06191415d892d816b47df67f8/FLAGfd344ef09 [2022-11-03 02:47:48,151 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:47:48,152 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 02:47:48,184 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/ca8d6fa6b/71c487c06191415d892d816b47df67f8/FLAGfd344ef09 [2022-11-03 02:47:48,318 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/ca8d6fa6b/71c487c06191415d892d816b47df67f8 [2022-11-03 02:47:48,321 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:47:48,323 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:47:48,329 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:47:48,329 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:47:48,334 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:47:48,335 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:47:48" (1/1) ... [2022-11-03 02:47:48,337 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@40c6590e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:48, skipping insertion in model container [2022-11-03 02:47:48,338 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:47:48" (1/1) ... [2022-11-03 02:47:48,359 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:47:48,451 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:47:48,767 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c[1014,1027] [2022-11-03 02:47:49,331 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:47:49,337 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:47:49,362 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c[1014,1027] [2022-11-03 02:47:49,588 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:47:49,604 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:47:49,605 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49 WrapperNode [2022-11-03 02:47:49,605 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:47:49,606 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:47:49,607 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:47:49,607 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:47:49,617 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:49,680 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:49,974 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2277 [2022-11-03 02:47:49,975 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:47:49,976 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:47:49,976 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:47:49,985 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:47:49,996 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:49,997 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,083 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,084 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,342 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,366 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,408 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,426 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,490 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:47:50,492 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:47:50,493 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:47:50,493 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:47:50,494 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (1/1) ... [2022-11-03 02:47:50,503 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:47:50,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:47:50,540 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:47:50,577 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:47:50,603 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:47:50,604 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:47:51,264 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:47:51,266 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:48:16,458 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:48:26,126 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:48:26,126 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:48:26,130 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:48:26 BoogieIcfgContainer [2022-11-03 02:48:26,130 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:48:26,132 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:48:26,133 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:48:26,140 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:48:26,141 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:47:48" (1/3) ... [2022-11-03 02:48:26,142 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3bc6a978 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:48:26, skipping insertion in model container [2022-11-03 02:48:26,143 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:47:49" (2/3) ... [2022-11-03 02:48:26,143 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3bc6a978 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:48:26, skipping insertion in model container [2022-11-03 02:48:26,144 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:48:26" (3/3) ... [2022-11-03 02:48:26,145 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 02:48:26,175 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:48:26,175 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:48:26,242 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:48:26,250 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3aa6725e, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:48:26,251 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:48:26,266 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:48:26,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:48:26,275 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:48:26,276 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:48:26,277 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:48:26,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:48:26,286 INFO L85 PathProgramCache]: Analyzing trace with hash 11419981, now seen corresponding path program 1 times [2022-11-03 02:48:26,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:48:26,299 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [554869901] [2022-11-03 02:48:26,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:48:26,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:48:27,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:48:36,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:48:36,131 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 02:48:36,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [554869901] [2022-11-03 02:48:36,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [554869901] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:48:36,132 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:48:36,133 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 02:48:36,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596020855] [2022-11-03 02:48:36,136 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:48:36,140 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:48:36,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 02:48:36,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:48:36,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:48:36,177 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:48:37,926 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.72s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:48:40,242 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.25s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:48:41,548 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.31s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:48:43,578 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.03s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:48:43,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:48:43,628 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 02:48:43,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:48:43,630 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 02:48:43,630 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:48:43,638 INFO L225 Difference]: With dead ends: 15 [2022-11-03 02:48:43,638 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 02:48:43,641 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:48:43,644 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:48:43,646 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 2 Unknown, 0 Unchecked, 7.4s Time] [2022-11-03 02:48:43,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 02:48:43,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 02:48:43,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:48:43,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 02:48:43,680 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 02:48:43,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:48:43,681 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 02:48:43,681 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:48:43,681 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 02:48:43,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 02:48:43,682 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:48:43,682 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 02:48:43,683 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:48:43,683 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:48:43,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:48:43,684 INFO L85 PathProgramCache]: Analyzing trace with hash 929105318, now seen corresponding path program 1 times [2022-11-03 02:48:43,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:48:43,685 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245839264] [2022-11-03 02:48:43,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:48:43,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:54:32,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:54:32,083 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 03:00:08,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 03:00:08,400 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 03:00:08,400 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 03:00:08,405 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 03:00:08,408 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 03:00:08,416 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 03:00:08,420 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 03:00:08,580 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:00:08,593 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:00:08,665 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 03:00:08 BoogieIcfgContainer [2022-11-03 03:00:08,666 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 03:00:08,666 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 03:00:08,666 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 03:00:08,667 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 03:00:08,667 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:48:26" (3/4) ... [2022-11-03 03:00:08,671 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 03:00:08,671 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 03:00:08,672 INFO L158 Benchmark]: Toolchain (without parser) took 740348.74ms. Allocated memory was 102.8MB in the beginning and 4.1GB in the end (delta: 4.0GB). Free memory was 56.4MB in the beginning and 3.8GB in the end (delta: -3.7GB). Peak memory consumption was 286.7MB. Max. memory is 16.1GB. [2022-11-03 03:00:08,672 INFO L158 Benchmark]: CDTParser took 0.37ms. Allocated memory is still 102.8MB. Free memory is still 76.1MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 03:00:08,673 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1276.58ms. Allocated memory was 102.8MB in the beginning and 136.3MB in the end (delta: 33.6MB). Free memory was 56.2MB in the beginning and 80.5MB in the end (delta: -24.3MB). Peak memory consumption was 22.4MB. Max. memory is 16.1GB. [2022-11-03 03:00:08,674 INFO L158 Benchmark]: Boogie Procedure Inliner took 368.49ms. Allocated memory is still 136.3MB. Free memory was 80.5MB in the beginning and 60.5MB in the end (delta: 20.0MB). Peak memory consumption was 33.8MB. Max. memory is 16.1GB. [2022-11-03 03:00:08,674 INFO L158 Benchmark]: Boogie Preprocessor took 515.50ms. Allocated memory was 136.3MB in the beginning and 245.4MB in the end (delta: 109.1MB). Free memory was 60.5MB in the beginning and 167.5MB in the end (delta: -107.0MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. [2022-11-03 03:00:08,675 INFO L158 Benchmark]: RCFGBuilder took 35637.81ms. Allocated memory was 245.4MB in the beginning and 1.4GB in the end (delta: 1.2GB). Free memory was 167.5MB in the beginning and 696.2MB in the end (delta: -528.8MB). Peak memory consumption was 863.7MB. Max. memory is 16.1GB. [2022-11-03 03:00:08,676 INFO L158 Benchmark]: TraceAbstraction took 702533.42ms. Allocated memory was 1.4GB in the beginning and 4.1GB in the end (delta: 2.7GB). Free memory was 695.2MB in the beginning and 3.8GB in the end (delta: -3.1GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2022-11-03 03:00:08,676 INFO L158 Benchmark]: Witness Printer took 4.71ms. Allocated memory is still 4.1GB. Free memory was 3.8GB in the beginning and 3.8GB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 03:00:08,680 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.37ms. Allocated memory is still 102.8MB. Free memory is still 76.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1276.58ms. Allocated memory was 102.8MB in the beginning and 136.3MB in the end (delta: 33.6MB). Free memory was 56.2MB in the beginning and 80.5MB in the end (delta: -24.3MB). Peak memory consumption was 22.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 368.49ms. Allocated memory is still 136.3MB. Free memory was 80.5MB in the beginning and 60.5MB in the end (delta: 20.0MB). Peak memory consumption was 33.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 515.50ms. Allocated memory was 136.3MB in the beginning and 245.4MB in the end (delta: 109.1MB). Free memory was 60.5MB in the beginning and 167.5MB in the end (delta: -107.0MB). Peak memory consumption was 27.3MB. Max. memory is 16.1GB. * RCFGBuilder took 35637.81ms. Allocated memory was 245.4MB in the beginning and 1.4GB in the end (delta: 1.2GB). Free memory was 167.5MB in the beginning and 696.2MB in the end (delta: -528.8MB). Peak memory consumption was 863.7MB. Max. memory is 16.1GB. * TraceAbstraction took 702533.42ms. Allocated memory was 1.4GB in the beginning and 4.1GB in the end (delta: 2.7GB). Free memory was 695.2MB in the beginning and 3.8GB in the end (delta: -3.1GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. * Witness Printer took 4.71ms. Allocated memory is still 4.1GB. Free memory was 3.8GB in the beginning and 3.8GB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 315, overapproximation of bitwiseOr at line 497, overapproximation of bitwiseAnd at line 211. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 8); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (8 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 24); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (24 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_2 var_5 = 0; [L38] const SORT_1 var_30 = 0; [L39] const SORT_2 var_97 = 3; [L40] const SORT_2 var_100 = 4; [L41] const SORT_2 var_105 = 12; [L42] const SORT_2 var_108 = 2; [L43] const SORT_2 var_111 = 0; [L44] const SORT_2 var_116 = 15; [L45] const SORT_2 var_121 = 10; [L46] const SORT_1 var_196 = 1; [L47] const SORT_4 var_199 = 1; [L48] const SORT_3 var_200 = 0; [L49] const SORT_4 var_203 = 2; [L50] const SORT_4 var_678 = 20; [L52] SORT_2 input_130; [L53] SORT_2 input_132; [L54] SORT_2 input_134; [L55] SORT_2 input_136; [L56] SORT_2 input_138; [L57] SORT_2 input_140; [L58] SORT_2 input_142; [L59] SORT_2 input_144; [L60] SORT_2 input_146; [L61] SORT_2 input_148; [L62] SORT_2 input_150; [L63] SORT_2 input_152; [L64] SORT_1 input_154; [L65] SORT_1 input_156; [L66] SORT_1 input_158; [L67] SORT_1 input_160; [L68] SORT_1 input_162; [L69] SORT_1 input_164; [L70] SORT_1 input_166; [L71] SORT_1 input_168; [L72] SORT_1 input_170; [L73] SORT_1 input_172; [L74] SORT_1 input_174; [L75] SORT_1 input_176; [L76] SORT_1 input_178; [L77] SORT_1 input_180; [L78] SORT_1 input_182; [L79] SORT_1 input_184; [L80] SORT_1 input_186; [L81] SORT_1 input_188; [L82] SORT_1 input_190; [L83] SORT_1 input_192; [L84] SORT_1 input_194; [L85] SORT_1 input_198; [L86] SORT_1 input_215; [L87] SORT_1 input_231; [L88] SORT_1 input_249; [L89] SORT_1 input_252; [L90] SORT_1 input_262; [L91] SORT_1 input_272; [L92] SORT_1 input_282; [L93] SORT_1 input_287; [L94] SORT_1 input_303; [L95] SORT_1 input_306; [L96] SORT_1 input_316; [L97] SORT_1 input_326; [L98] SORT_1 input_336; [L99] SORT_1 input_341; [L100] SORT_1 input_350; [L102] SORT_2 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L103] SORT_2 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L104] SORT_2 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L105] SORT_2 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L106] SORT_2 state_14 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L107] SORT_2 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L108] SORT_2 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L109] SORT_2 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L110] SORT_2 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L111] SORT_2 state_24 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L112] SORT_2 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L113] SORT_2 state_28 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L114] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L115] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L116] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L117] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L118] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L119] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L120] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L121] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L122] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L123] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L124] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L125] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L126] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L127] SORT_1 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L128] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L129] SORT_1 state_61 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L130] SORT_1 state_63 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L131] SORT_1 state_65 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L132] SORT_1 state_67 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L133] SORT_1 state_69 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L134] SORT_1 state_71 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L135] SORT_1 state_73 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L136] SORT_1 state_75 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L138] SORT_2 init_7_arg_1 = var_5; [L139] state_6 = init_7_arg_1 [L140] SORT_2 init_9_arg_1 = var_5; [L141] state_8 = init_9_arg_1 [L142] SORT_2 init_11_arg_1 = var_5; [L143] state_10 = init_11_arg_1 [L144] SORT_2 init_13_arg_1 = var_5; [L145] state_12 = init_13_arg_1 [L146] SORT_2 init_15_arg_1 = var_5; [L147] state_14 = init_15_arg_1 [L148] SORT_2 init_17_arg_1 = var_5; [L149] state_16 = init_17_arg_1 [L150] SORT_2 init_19_arg_1 = var_5; [L151] state_18 = init_19_arg_1 [L152] SORT_2 init_21_arg_1 = var_5; [L153] state_20 = init_21_arg_1 [L154] SORT_2 init_23_arg_1 = var_5; [L155] state_22 = init_23_arg_1 [L156] SORT_2 init_25_arg_1 = var_5; [L157] state_24 = init_25_arg_1 [L158] SORT_2 init_27_arg_1 = var_5; [L159] state_26 = init_27_arg_1 [L160] SORT_2 init_29_arg_1 = var_5; [L161] state_28 = init_29_arg_1 [L162] SORT_1 init_32_arg_1 = var_30; [L163] state_31 = init_32_arg_1 [L164] SORT_1 init_34_arg_1 = var_30; [L165] state_33 = init_34_arg_1 [L166] SORT_1 init_36_arg_1 = var_30; [L167] state_35 = init_36_arg_1 [L168] SORT_1 init_38_arg_1 = var_30; [L169] state_37 = init_38_arg_1 [L170] SORT_1 init_40_arg_1 = var_30; [L171] state_39 = init_40_arg_1 [L172] SORT_1 init_42_arg_1 = var_30; [L173] state_41 = init_42_arg_1 [L174] SORT_1 init_44_arg_1 = var_30; [L175] state_43 = init_44_arg_1 [L176] SORT_1 init_46_arg_1 = var_30; [L177] state_45 = init_46_arg_1 [L178] SORT_1 init_48_arg_1 = var_30; [L179] state_47 = init_48_arg_1 [L180] SORT_1 init_50_arg_1 = var_30; [L181] state_49 = init_50_arg_1 [L182] SORT_1 init_52_arg_1 = var_30; [L183] state_51 = init_52_arg_1 [L184] SORT_1 init_54_arg_1 = var_30; [L185] state_53 = init_54_arg_1 [L186] SORT_1 init_56_arg_1 = var_30; [L187] state_55 = init_56_arg_1 [L188] SORT_1 init_58_arg_1 = var_30; [L189] state_57 = init_58_arg_1 [L190] SORT_1 init_60_arg_1 = var_30; [L191] state_59 = init_60_arg_1 [L192] SORT_1 init_62_arg_1 = var_30; [L193] state_61 = init_62_arg_1 [L194] SORT_1 init_64_arg_1 = var_30; [L195] state_63 = init_64_arg_1 [L196] SORT_1 init_66_arg_1 = var_30; [L197] state_65 = init_66_arg_1 [L198] SORT_1 init_68_arg_1 = var_30; [L199] state_67 = init_68_arg_1 [L200] SORT_1 init_70_arg_1 = var_30; [L201] state_69 = init_70_arg_1 [L202] SORT_1 init_72_arg_1 = var_30; [L203] state_71 = init_72_arg_1 [L204] SORT_1 init_74_arg_1 = var_30; [L205] state_73 = init_74_arg_1 [L206] SORT_1 init_76_arg_1 = var_30; [L207] state_75 = init_76_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_76_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_57=0, state_59=0, state_6=0, state_61=0, state_63=0, state_65=0, state_67=0, state_69=0, state_71=0, state_73=0, state_75=0, state_8=0, var_100=4, var_105=12, var_108=2, var_111=0, var_116=15, var_121=10, var_196=1, var_199=1, var_200=0, var_203=2, var_30=0, var_5=0, var_678=20, var_97=3] [L210] input_130 = __VERIFIER_nondet_uchar() [L211] input_130 = input_130 & mask_SORT_2 [L212] input_132 = __VERIFIER_nondet_uchar() [L213] input_132 = input_132 & mask_SORT_2 [L214] input_134 = __VERIFIER_nondet_uchar() [L215] input_134 = input_134 & mask_SORT_2 [L216] input_136 = __VERIFIER_nondet_uchar() [L217] input_136 = input_136 & mask_SORT_2 [L218] input_138 = __VERIFIER_nondet_uchar() [L219] input_138 = input_138 & mask_SORT_2 [L220] input_140 = __VERIFIER_nondet_uchar() [L221] input_140 = input_140 & mask_SORT_2 [L222] input_142 = __VERIFIER_nondet_uchar() [L223] input_142 = input_142 & mask_SORT_2 [L224] input_144 = __VERIFIER_nondet_uchar() [L225] input_144 = input_144 & mask_SORT_2 [L226] input_146 = __VERIFIER_nondet_uchar() [L227] input_146 = input_146 & mask_SORT_2 [L228] input_148 = __VERIFIER_nondet_uchar() [L229] input_148 = input_148 & mask_SORT_2 [L230] input_150 = __VERIFIER_nondet_uchar() [L231] input_150 = input_150 & mask_SORT_2 [L232] input_152 = __VERIFIER_nondet_uchar() [L233] input_152 = input_152 & mask_SORT_2 [L234] input_154 = __VERIFIER_nondet_uchar() [L235] input_154 = input_154 & mask_SORT_1 [L236] input_156 = __VERIFIER_nondet_uchar() [L237] input_156 = input_156 & mask_SORT_1 [L238] input_158 = __VERIFIER_nondet_uchar() [L239] input_158 = input_158 & mask_SORT_1 [L240] input_160 = __VERIFIER_nondet_uchar() [L241] input_160 = input_160 & mask_SORT_1 [L242] input_162 = __VERIFIER_nondet_uchar() [L243] input_162 = input_162 & mask_SORT_1 [L244] input_164 = __VERIFIER_nondet_uchar() [L245] input_164 = input_164 & mask_SORT_1 [L246] input_166 = __VERIFIER_nondet_uchar() [L247] input_166 = input_166 & mask_SORT_1 [L248] input_168 = __VERIFIER_nondet_uchar() [L249] input_168 = input_168 & mask_SORT_1 [L250] input_170 = __VERIFIER_nondet_uchar() [L251] input_170 = input_170 & mask_SORT_1 [L252] input_172 = __VERIFIER_nondet_uchar() [L253] input_172 = input_172 & mask_SORT_1 [L254] input_174 = __VERIFIER_nondet_uchar() [L255] input_174 = input_174 & mask_SORT_1 [L256] input_176 = __VERIFIER_nondet_uchar() [L257] input_176 = input_176 & mask_SORT_1 [L258] input_178 = __VERIFIER_nondet_uchar() [L259] input_178 = input_178 & mask_SORT_1 [L260] input_180 = __VERIFIER_nondet_uchar() [L261] input_180 = input_180 & mask_SORT_1 [L262] input_182 = __VERIFIER_nondet_uchar() [L263] input_182 = input_182 & mask_SORT_1 [L264] input_184 = __VERIFIER_nondet_uchar() [L265] input_184 = input_184 & mask_SORT_1 [L266] input_186 = __VERIFIER_nondet_uchar() [L267] input_186 = input_186 & mask_SORT_1 [L268] input_188 = __VERIFIER_nondet_uchar() [L269] input_188 = input_188 & mask_SORT_1 [L270] input_190 = __VERIFIER_nondet_uchar() [L271] input_190 = input_190 & mask_SORT_1 [L272] input_192 = __VERIFIER_nondet_uchar() [L273] input_192 = input_192 & mask_SORT_1 [L274] input_194 = __VERIFIER_nondet_uchar() [L275] input_194 = input_194 & mask_SORT_1 [L276] input_198 = __VERIFIER_nondet_uchar() [L277] input_198 = input_198 & mask_SORT_1 [L278] input_215 = __VERIFIER_nondet_uchar() [L279] input_215 = input_215 & mask_SORT_1 [L280] input_231 = __VERIFIER_nondet_uchar() [L281] input_231 = input_231 & mask_SORT_1 [L282] input_249 = __VERIFIER_nondet_uchar() [L283] input_252 = __VERIFIER_nondet_uchar() [L284] input_252 = input_252 & mask_SORT_1 [L285] input_262 = __VERIFIER_nondet_uchar() [L286] input_262 = input_262 & mask_SORT_1 [L287] input_272 = __VERIFIER_nondet_uchar() [L288] input_272 = input_272 & mask_SORT_1 [L289] input_282 = __VERIFIER_nondet_uchar() [L290] input_282 = input_282 & mask_SORT_1 [L291] input_287 = __VERIFIER_nondet_uchar() [L292] input_287 = input_287 & mask_SORT_1 [L293] input_303 = __VERIFIER_nondet_uchar() [L294] input_306 = __VERIFIER_nondet_uchar() [L295] input_306 = input_306 & mask_SORT_1 [L296] input_316 = __VERIFIER_nondet_uchar() [L297] input_316 = input_316 & mask_SORT_1 [L298] input_326 = __VERIFIER_nondet_uchar() [L299] input_326 = input_326 & mask_SORT_1 [L300] input_336 = __VERIFIER_nondet_uchar() [L301] input_336 = input_336 & mask_SORT_1 [L302] input_341 = __VERIFIER_nondet_uchar() [L303] input_341 = input_341 & mask_SORT_1 [L304] input_350 = __VERIFIER_nondet_uchar() [L305] input_350 = input_350 & mask_SORT_1 [L308] SORT_1 var_77_arg_0 = state_31; [L309] SORT_1 var_77_arg_1 = state_33; [L310] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L311] SORT_1 var_78_arg_0 = var_77; [L312] SORT_1 var_78_arg_1 = state_35; [L313] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L314] SORT_1 var_79_arg_0 = var_78; [L315] SORT_1 var_79_arg_1 = ~state_37; [L316] var_79_arg_1 = var_79_arg_1 & mask_SORT_1 [L317] SORT_1 var_79 = var_79_arg_0 & var_79_arg_1; [L318] SORT_1 var_80_arg_0 = var_79; [L319] SORT_1 var_80_arg_1 = ~state_39; [L320] var_80_arg_1 = var_80_arg_1 & mask_SORT_1 [L321] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L322] SORT_1 var_81_arg_0 = var_80; [L323] SORT_1 var_81_arg_1 = ~state_41; [L324] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L325] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L326] SORT_1 var_82_arg_0 = var_81; [L327] SORT_1 var_82_arg_1 = ~state_43; [L328] var_82_arg_1 = var_82_arg_1 & mask_SORT_1 [L329] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L330] SORT_1 var_83_arg_0 = var_82; [L331] SORT_1 var_83_arg_1 = ~state_45; [L332] var_83_arg_1 = var_83_arg_1 & mask_SORT_1 [L333] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L334] SORT_1 var_84_arg_0 = var_83; [L335] SORT_1 var_84_arg_1 = ~state_47; [L336] var_84_arg_1 = var_84_arg_1 & mask_SORT_1 [L337] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L338] SORT_1 var_85_arg_0 = var_84; [L339] SORT_1 var_85_arg_1 = ~state_49; [L340] var_85_arg_1 = var_85_arg_1 & mask_SORT_1 [L341] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L342] SORT_1 var_86_arg_0 = var_85; [L343] SORT_1 var_86_arg_1 = state_51; [L344] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L345] SORT_1 var_87_arg_0 = var_86; [L346] SORT_1 var_87_arg_1 = ~state_53; [L347] var_87_arg_1 = var_87_arg_1 & mask_SORT_1 [L348] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L349] SORT_1 var_88_arg_0 = var_87; [L350] SORT_1 var_88_arg_1 = ~state_55; [L351] var_88_arg_1 = var_88_arg_1 & mask_SORT_1 [L352] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L353] SORT_1 var_89_arg_0 = var_88; [L354] SORT_1 var_89_arg_1 = ~state_57; [L355] var_89_arg_1 = var_89_arg_1 & mask_SORT_1 [L356] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L357] SORT_1 var_90_arg_0 = var_89; [L358] SORT_1 var_90_arg_1 = ~state_59; [L359] var_90_arg_1 = var_90_arg_1 & mask_SORT_1 [L360] SORT_1 var_90 = var_90_arg_0 & var_90_arg_1; [L361] SORT_1 var_91_arg_0 = var_90; [L362] SORT_1 var_91_arg_1 = ~state_61; [L363] var_91_arg_1 = var_91_arg_1 & mask_SORT_1 [L364] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L365] SORT_1 var_92_arg_0 = var_91; [L366] SORT_1 var_92_arg_1 = ~state_63; [L367] var_92_arg_1 = var_92_arg_1 & mask_SORT_1 [L368] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L369] SORT_1 var_93_arg_0 = var_92; [L370] SORT_1 var_93_arg_1 = ~state_65; [L371] var_93_arg_1 = var_93_arg_1 & mask_SORT_1 [L372] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L373] SORT_1 var_94_arg_0 = var_93; [L374] SORT_1 var_94_arg_1 = state_67; [L375] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L376] SORT_1 var_95_arg_0 = var_94; [L377] SORT_1 var_95_arg_1 = state_69; [L378] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L379] SORT_1 var_96_arg_0 = var_95; [L380] SORT_1 var_96_arg_1 = state_71; [L381] SORT_1 var_96 = var_96_arg_0 & var_96_arg_1; [L382] SORT_2 var_98_arg_0 = var_97; [L383] SORT_2 var_98_arg_1 = state_6; [L384] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L385] SORT_1 var_99_arg_0 = var_96; [L386] SORT_1 var_99_arg_1 = var_98; [L387] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L388] SORT_2 var_101_arg_0 = var_100; [L389] SORT_2 var_101_arg_1 = state_8; [L390] SORT_1 var_101 = var_101_arg_0 == var_101_arg_1; [L391] SORT_1 var_102_arg_0 = var_99; [L392] SORT_1 var_102_arg_1 = var_101; [L393] SORT_1 var_102 = var_102_arg_0 & var_102_arg_1; [L394] SORT_2 var_103_arg_0 = var_100; [L395] SORT_2 var_103_arg_1 = state_10; [L396] SORT_1 var_103 = var_103_arg_0 == var_103_arg_1; [L397] SORT_1 var_104_arg_0 = var_102; [L398] SORT_1 var_104_arg_1 = var_103; [L399] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L400] SORT_2 var_106_arg_0 = var_105; [L401] SORT_2 var_106_arg_1 = state_12; [L402] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L403] SORT_1 var_107_arg_0 = var_104; [L404] SORT_1 var_107_arg_1 = var_106; [L405] SORT_1 var_107 = var_107_arg_0 & var_107_arg_1; [L406] SORT_2 var_109_arg_0 = var_108; [L407] SORT_2 var_109_arg_1 = state_14; [L408] SORT_1 var_109 = var_109_arg_0 == var_109_arg_1; [L409] SORT_1 var_110_arg_0 = var_107; [L410] SORT_1 var_110_arg_1 = var_109; [L411] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L412] SORT_2 var_112_arg_0 = var_111; [L413] SORT_2 var_112_arg_1 = state_16; [L414] SORT_1 var_112 = var_112_arg_0 == var_112_arg_1; [L415] SORT_1 var_113_arg_0 = var_110; [L416] SORT_1 var_113_arg_1 = var_112; [L417] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L418] SORT_2 var_114_arg_0 = var_111; [L419] SORT_2 var_114_arg_1 = state_18; [L420] SORT_1 var_114 = var_114_arg_0 == var_114_arg_1; [L421] SORT_1 var_115_arg_0 = var_113; [L422] SORT_1 var_115_arg_1 = var_114; [L423] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L424] SORT_2 var_117_arg_0 = var_116; [L425] SORT_2 var_117_arg_1 = state_20; [L426] SORT_1 var_117 = var_117_arg_0 == var_117_arg_1; [L427] SORT_1 var_118_arg_0 = var_115; [L428] SORT_1 var_118_arg_1 = var_117; [L429] SORT_1 var_118 = var_118_arg_0 & var_118_arg_1; [L430] SORT_2 var_119_arg_0 = var_111; [L431] SORT_2 var_119_arg_1 = state_22; [L432] SORT_1 var_119 = var_119_arg_0 == var_119_arg_1; [L433] SORT_1 var_120_arg_0 = var_118; [L434] SORT_1 var_120_arg_1 = var_119; [L435] SORT_1 var_120 = var_120_arg_0 & var_120_arg_1; [L436] SORT_2 var_122_arg_0 = var_121; [L437] SORT_2 var_122_arg_1 = state_24; [L438] SORT_1 var_122 = var_122_arg_0 == var_122_arg_1; [L439] SORT_1 var_123_arg_0 = var_120; [L440] SORT_1 var_123_arg_1 = var_122; [L441] SORT_1 var_123 = var_123_arg_0 & var_123_arg_1; [L442] SORT_2 var_124_arg_0 = var_121; [L443] SORT_2 var_124_arg_1 = state_26; [L444] SORT_1 var_124 = var_124_arg_0 == var_124_arg_1; [L445] SORT_1 var_125_arg_0 = var_123; [L446] SORT_1 var_125_arg_1 = var_124; [L447] SORT_1 var_125 = var_125_arg_0 & var_125_arg_1; [L448] SORT_2 var_126_arg_0 = var_111; [L449] SORT_2 var_126_arg_1 = state_28; [L450] SORT_1 var_126 = var_126_arg_0 == var_126_arg_1; [L451] SORT_1 var_127_arg_0 = var_125; [L452] SORT_1 var_127_arg_1 = var_126; [L453] SORT_1 var_127 = var_127_arg_0 & var_127_arg_1; [L454] SORT_1 var_128_arg_0 = state_75; [L455] SORT_1 var_128_arg_1 = var_127; [L456] SORT_1 var_128 = var_128_arg_0 & var_128_arg_1; [L457] var_128 = var_128 & mask_SORT_1 [L458] SORT_1 bad_129_arg_0 = var_128; [L459] CALL __VERIFIER_assert(!(bad_129_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L459] RET __VERIFIER_assert(!(bad_129_arg_0)) [L461] SORT_2 next_131_arg_1 = input_130; [L462] SORT_2 next_133_arg_1 = input_132; [L463] SORT_2 next_135_arg_1 = input_134; [L464] SORT_2 next_137_arg_1 = input_136; [L465] SORT_2 next_139_arg_1 = input_138; [L466] SORT_2 next_141_arg_1 = input_140; [L467] SORT_2 next_143_arg_1 = input_142; [L468] SORT_2 next_145_arg_1 = input_144; [L469] SORT_2 next_147_arg_1 = input_146; [L470] SORT_2 next_149_arg_1 = input_148; [L471] SORT_2 next_151_arg_1 = input_150; [L472] SORT_2 next_153_arg_1 = input_152; [L473] SORT_1 next_155_arg_1 = input_154; [L474] SORT_1 next_157_arg_1 = input_156; [L475] SORT_1 next_159_arg_1 = input_158; [L476] SORT_1 next_161_arg_1 = input_160; [L477] SORT_1 next_163_arg_1 = input_162; [L478] SORT_1 next_165_arg_1 = input_164; [L479] SORT_1 next_167_arg_1 = input_166; [L480] SORT_1 next_169_arg_1 = input_168; [L481] SORT_1 next_171_arg_1 = input_170; [L482] SORT_1 next_173_arg_1 = input_172; [L483] SORT_1 next_175_arg_1 = input_174; [L484] SORT_1 next_177_arg_1 = input_176; [L485] SORT_1 next_179_arg_1 = input_178; [L486] SORT_1 next_181_arg_1 = input_180; [L487] SORT_1 next_183_arg_1 = input_182; [L488] SORT_1 next_185_arg_1 = input_184; [L489] SORT_1 next_187_arg_1 = input_186; [L490] SORT_1 next_189_arg_1 = input_188; [L491] SORT_1 next_191_arg_1 = input_190; [L492] SORT_1 next_193_arg_1 = input_192; [L493] SORT_1 next_195_arg_1 = input_194; [L494] SORT_1 next_197_arg_1 = var_196; [L495] SORT_3 var_201_arg_0 = var_200; [L496] SORT_2 var_201_arg_1 = input_130; [L497] SORT_4 var_201 = ((SORT_4)var_201_arg_0 << 8) | var_201_arg_1; [L498] var_201 = var_201 & mask_SORT_4 [L499] SORT_4 var_202_arg_0 = var_199; [L500] SORT_4 var_202_arg_1 = var_201; [L501] SORT_1 var_202 = var_202_arg_0 <= var_202_arg_1; [L502] SORT_3 var_204_arg_0 = var_200; [L503] SORT_2 var_204_arg_1 = input_132; [L504] SORT_4 var_204 = ((SORT_4)var_204_arg_0 << 8) | var_204_arg_1; [L505] var_204 = var_204 & mask_SORT_4 [L506] SORT_4 var_205_arg_0 = var_203; [L507] SORT_4 var_205_arg_1 = var_204; [L508] SORT_1 var_205 = var_205_arg_0 <= var_205_arg_1; [L509] SORT_1 var_206_arg_0 = var_202; [L510] SORT_1 var_206_arg_1 = var_205; [L511] SORT_1 var_206 = var_206_arg_0 & var_206_arg_1; [L512] SORT_3 var_207_arg_0 = var_200; [L513] SORT_2 var_207_arg_1 = input_134; [L514] SORT_4 var_207 = ((SORT_4)var_207_arg_0 << 8) | var_207_arg_1; [L515] var_207 = var_207 & mask_SORT_4 [L516] SORT_4 var_208_arg_0 = var_203; [L517] SORT_4 var_208_arg_1 = var_207; [L518] SORT_1 var_208 = var_208_arg_0 <= var_208_arg_1; [L519] SORT_1 var_209_arg_0 = var_206; [L520] SORT_1 var_209_arg_1 = var_208; [L521] SORT_1 var_209 = var_209_arg_0 & var_209_arg_1; [L522] SORT_3 var_210_arg_0 = var_200; [L523] SORT_2 var_210_arg_1 = input_136; [L524] SORT_4 var_210 = ((SORT_4)var_210_arg_0 << 8) | var_210_arg_1; [L525] var_210 = var_210 & mask_SORT_4 [L526] SORT_4 var_211_arg_0 = var_203; [L527] SORT_4 var_211_arg_1 = var_210; [L528] SORT_1 var_211 = var_211_arg_0 <= var_211_arg_1; [L529] SORT_1 var_212_arg_0 = var_209; [L530] SORT_1 var_212_arg_1 = var_211; [L531] SORT_1 var_212 = var_212_arg_0 & var_212_arg_1; [L532] SORT_1 var_213_arg_0 = input_154; [L533] SORT_1 var_213_arg_1 = var_212; [L534] SORT_1 var_213 = var_213_arg_0 & var_213_arg_1; [L535] SORT_1 var_214_arg_0 = ~input_198; [L536] var_214_arg_0 = var_214_arg_0 & mask_SORT_1 [L537] SORT_1 var_214_arg_1 = var_213; [L538] SORT_1 var_214 = var_214_arg_0 | var_214_arg_1; [L539] SORT_3 var_216_arg_0 = var_200; [L540] SORT_2 var_216_arg_1 = input_140; [L541] SORT_4 var_216 = ((SORT_4)var_216_arg_0 << 8) | var_216_arg_1; [L542] SORT_4 var_217_arg_0 = var_203; [L543] SORT_4 var_217_arg_1 = var_216; [L544] SORT_4 var_217 = var_217_arg_0 + var_217_arg_1; [L545] SORT_4 var_218_arg_0 = var_217; [L546] SORT_2 var_218 = var_218_arg_0 >> 0; [L547] SORT_1 var_219_arg_0 = input_198; [L548] SORT_2 var_219_arg_1 = var_218; [L549] SORT_2 var_219_arg_2 = input_140; [L550] EXPR var_219_arg_0 ? var_219_arg_1 : var_219_arg_2 [L550] SORT_2 var_219 = var_219_arg_0 ? var_219_arg_1 : var_219_arg_2; [L551] var_219 = var_219 & mask_SORT_2 [L552] SORT_3 var_220_arg_0 = var_200; [L553] SORT_2 var_220_arg_1 = var_219; [L554] SORT_4 var_220 = ((SORT_4)var_220_arg_0 << 8) | var_220_arg_1; [L555] var_220 = var_220 & mask_SORT_4 [L556] SORT_4 var_221_arg_0 = var_199; [L557] SORT_4 var_221_arg_1 = var_220; [L558] SORT_1 var_221 = var_221_arg_0 <= var_221_arg_1; [L559] SORT_4 var_222_arg_0 = var_210; [L560] SORT_4 var_222_arg_1 = var_203; [L561] SORT_4 var_222 = var_222_arg_0 - var_222_arg_1; [L562] SORT_4 var_223_arg_0 = var_222; [L563] SORT_2 var_223 = var_223_arg_0 >> 0; [L564] SORT_1 var_224_arg_0 = input_198; [L565] SORT_2 var_224_arg_1 = var_223; [L566] SORT_2 var_224_arg_2 = input_136; [L567] EXPR var_224_arg_0 ? var_224_arg_1 : var_224_arg_2 [L567] SORT_2 var_224 = var_224_arg_0 ? var_224_arg_1 : var_224_arg_2; [L568] var_224 = var_224 & mask_SORT_2 [L569] SORT_3 var_225_arg_0 = var_200; [L570] SORT_2 var_225_arg_1 = var_224; [L571] SORT_4 var_225 = ((SORT_4)var_225_arg_0 << 8) | var_225_arg_1; [L572] var_225 = var_225 & mask_SORT_4 [L573] SORT_4 var_226_arg_0 = var_199; [L574] SORT_4 var_226_arg_1 = var_225; [L575] SORT_1 var_226 = var_226_arg_0 <= var_226_arg_1; [L576] SORT_1 var_227_arg_0 = var_221; [L577] SORT_1 var_227_arg_1 = var_226; [L578] SORT_1 var_227 = var_227_arg_0 & var_227_arg_1; [L579] SORT_1 var_228_arg_0 = input_156; [L580] SORT_1 var_228_arg_1 = var_227; [L581] SORT_1 var_228 = var_228_arg_0 & var_228_arg_1; [L582] SORT_1 var_229_arg_0 = ~input_215; [L583] var_229_arg_0 = var_229_arg_0 & mask_SORT_1 [L584] SORT_1 var_229_arg_1 = var_228; [L585] SORT_1 var_229 = var_229_arg_0 | var_229_arg_1; [L586] SORT_1 var_230_arg_0 = var_214; [L587] SORT_1 var_230_arg_1 = var_229; [L588] SORT_1 var_230 = var_230_arg_0 & var_230_arg_1; [L589] SORT_3 var_232_arg_0 = var_200; [L590] SORT_2 var_232_arg_1 = input_142; [L591] SORT_4 var_232 = ((SORT_4)var_232_arg_0 << 8) | var_232_arg_1; [L592] SORT_4 var_233_arg_0 = var_199; [L593] SORT_4 var_233_arg_1 = var_232; [L594] SORT_4 var_233 = var_233_arg_0 + var_233_arg_1; [L595] SORT_4 var_234_arg_0 = var_233; [L596] SORT_2 var_234 = var_234_arg_0 >> 0; [L597] SORT_1 var_235_arg_0 = input_215; [L598] SORT_2 var_235_arg_1 = var_234; [L599] SORT_2 var_235_arg_2 = input_142; [L600] EXPR var_235_arg_0 ? var_235_arg_1 : var_235_arg_2 [L600] SORT_2 var_235 = var_235_arg_0 ? var_235_arg_1 : var_235_arg_2; [L601] var_235 = var_235 & mask_SORT_2 [L602] SORT_3 var_236_arg_0 = var_200; [L603] SORT_2 var_236_arg_1 = var_235; [L604] SORT_4 var_236 = ((SORT_4)var_236_arg_0 << 8) | var_236_arg_1; [L605] var_236 = var_236 & mask_SORT_4 [L606] SORT_4 var_237_arg_0 = var_199; [L607] SORT_4 var_237_arg_1 = var_236; [L608] SORT_1 var_237 = var_237_arg_0 <= var_237_arg_1; [L609] SORT_3 var_238_arg_0 = var_200; [L610] SORT_2 var_238_arg_1 = input_150; [L611] SORT_4 var_238 = ((SORT_4)var_238_arg_0 << 8) | var_238_arg_1; [L612] SORT_4 var_239_arg_0 = var_203; [L613] SORT_4 var_239_arg_1 = var_238; [L614] SORT_4 var_239 = var_239_arg_0 + var_239_arg_1; [L615] SORT_4 var_240_arg_0 = var_239; [L616] SORT_2 var_240 = var_240_arg_0 >> 0; [L617] SORT_1 var_241_arg_0 = input_198; [L618] SORT_2 var_241_arg_1 = var_240; [L619] SORT_2 var_241_arg_2 = input_150; [L620] EXPR var_241_arg_0 ? var_241_arg_1 : var_241_arg_2 [L620] SORT_2 var_241 = var_241_arg_0 ? var_241_arg_1 : var_241_arg_2; [L621] var_241 = var_241 & mask_SORT_2 [L622] SORT_3 var_242_arg_0 = var_200; [L623] SORT_2 var_242_arg_1 = var_241; [L624] SORT_4 var_242 = ((SORT_4)var_242_arg_0 << 8) | var_242_arg_1; [L625] var_242 = var_242 & mask_SORT_4 [L626] SORT_4 var_243_arg_0 = var_199; [L627] SORT_4 var_243_arg_1 = var_242; [L628] SORT_1 var_243 = var_243_arg_0 <= var_243_arg_1; [L629] SORT_1 var_244_arg_0 = var_237; [L630] SORT_1 var_244_arg_1 = var_243; [L631] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L632] SORT_1 var_245_arg_0 = input_158; [L633] SORT_1 var_245_arg_1 = var_244; [L634] SORT_1 var_245 = var_245_arg_0 & var_245_arg_1; [L635] SORT_1 var_246_arg_0 = ~input_231; [L636] var_246_arg_0 = var_246_arg_0 & mask_SORT_1 [L637] SORT_1 var_246_arg_1 = var_245; [L638] SORT_1 var_246 = var_246_arg_0 | var_246_arg_1; [L639] SORT_1 var_247_arg_0 = var_230; [L640] SORT_1 var_247_arg_1 = var_246; [L641] SORT_1 var_247 = var_247_arg_0 & var_247_arg_1; [L642] SORT_1 var_248_arg_0 = input_160; [L643] SORT_1 var_248_arg_1 = input_231; [L644] SORT_1 var_248 = var_248_arg_0 | var_248_arg_1; [L645] SORT_1 var_250_arg_0 = var_248; [L646] SORT_1 var_250_arg_1 = ~input_249; [L647] var_250_arg_1 = var_250_arg_1 & mask_SORT_1 [L648] SORT_1 var_250 = var_250_arg_0 | var_250_arg_1; [L649] SORT_1 var_251_arg_0 = var_247; [L650] SORT_1 var_251_arg_1 = var_250; [L651] SORT_1 var_251 = var_251_arg_0 & var_251_arg_1; [L652] SORT_1 var_253_arg_0 = input_162; [L653] SORT_1 var_253_arg_1 = input_249; [L654] SORT_1 var_253 = var_253_arg_0 | var_253_arg_1; [L655] SORT_4 var_254_arg_0 = var_225; [L656] SORT_4 var_254_arg_1 = var_199; [L657] SORT_4 var_254 = var_254_arg_0 - var_254_arg_1; [L658] SORT_4 var_255_arg_0 = var_254; [L659] SORT_2 var_255 = var_255_arg_0 >> 0; [L660] SORT_1 var_256_arg_0 = input_215; [L661] SORT_2 var_256_arg_1 = var_255; [L662] SORT_2 var_256_arg_2 = var_224; [L663] EXPR var_256_arg_0 ? var_256_arg_1 : var_256_arg_2 [L663] SORT_2 var_256 = var_256_arg_0 ? var_256_arg_1 : var_256_arg_2; [L664] var_256 = var_256 & mask_SORT_2 [L665] SORT_3 var_257_arg_0 = var_200; [L666] SORT_2 var_257_arg_1 = var_256; [L667] SORT_4 var_257 = ((SORT_4)var_257_arg_0 << 8) | var_257_arg_1; [L668] var_257 = var_257 & mask_SORT_4 [L669] SORT_4 var_258_arg_0 = var_199; [L670] SORT_4 var_258_arg_1 = var_257; [L671] SORT_1 var_258 = var_258_arg_0 <= var_258_arg_1; [L672] SORT_1 var_259_arg_0 = var_253; [L673] SORT_1 var_259_arg_1 = var_258; [L674] SORT_1 var_259 = var_259_arg_0 & var_259_arg_1; [L675] SORT_1 var_260_arg_0 = ~input_252; [L676] var_260_arg_0 = var_260_arg_0 & mask_SORT_1 [L677] SORT_1 var_260_arg_1 = var_259; [L678] SORT_1 var_260 = var_260_arg_0 | var_260_arg_1; [L679] SORT_1 var_261_arg_0 = var_251; [L680] SORT_1 var_261_arg_1 = var_260; [L681] SORT_1 var_261 = var_261_arg_0 & var_261_arg_1; [L682] SORT_1 var_263_arg_0 = input_164; [L683] SORT_1 var_263_arg_1 = input_252; [L684] SORT_1 var_263 = var_263_arg_0 | var_263_arg_1; [L685] SORT_4 var_264_arg_0 = var_257; [L686] SORT_4 var_264_arg_1 = var_199; [L687] SORT_4 var_264 = var_264_arg_0 - var_264_arg_1; [L688] SORT_4 var_265_arg_0 = var_264; [L689] SORT_2 var_265 = var_265_arg_0 >> 0; [L690] SORT_1 var_266_arg_0 = input_252; [L691] SORT_2 var_266_arg_1 = var_265; [L692] SORT_2 var_266_arg_2 = var_256; [L693] EXPR var_266_arg_0 ? var_266_arg_1 : var_266_arg_2 [L693] SORT_2 var_266 = var_266_arg_0 ? var_266_arg_1 : var_266_arg_2; [L694] var_266 = var_266 & mask_SORT_2 [L695] SORT_3 var_267_arg_0 = var_200; [L696] SORT_2 var_267_arg_1 = var_266; [L697] SORT_4 var_267 = ((SORT_4)var_267_arg_0 << 8) | var_267_arg_1; [L698] var_267 = var_267 & mask_SORT_4 [L699] SORT_4 var_268_arg_0 = var_199; [L700] SORT_4 var_268_arg_1 = var_267; [L701] SORT_1 var_268 = var_268_arg_0 <= var_268_arg_1; [L702] SORT_1 var_269_arg_0 = var_263; [L703] SORT_1 var_269_arg_1 = var_268; [L704] SORT_1 var_269 = var_269_arg_0 & var_269_arg_1; [L705] SORT_1 var_270_arg_0 = ~input_262; [L706] var_270_arg_0 = var_270_arg_0 & mask_SORT_1 [L707] SORT_1 var_270_arg_1 = var_269; [L708] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L709] SORT_1 var_271_arg_0 = var_261; [L710] SORT_1 var_271_arg_1 = var_270; [L711] SORT_1 var_271 = var_271_arg_0 & var_271_arg_1; [L712] SORT_1 var_273_arg_0 = input_170; [L713] SORT_1 var_273_arg_1 = input_262; [L714] SORT_1 var_273 = var_273_arg_0 | var_273_arg_1; [L715] SORT_4 var_274_arg_0 = var_242; [L716] SORT_4 var_274_arg_1 = var_199; [L717] SORT_4 var_274 = var_274_arg_0 - var_274_arg_1; [L718] SORT_4 var_275_arg_0 = var_274; [L719] SORT_2 var_275 = var_275_arg_0 >> 0; [L720] SORT_1 var_276_arg_0 = input_231; [L721] SORT_2 var_276_arg_1 = var_275; [L722] SORT_2 var_276_arg_2 = var_241; [L723] EXPR var_276_arg_0 ? var_276_arg_1 : var_276_arg_2 [L723] SORT_2 var_276 = var_276_arg_0 ? var_276_arg_1 : var_276_arg_2; [L724] var_276 = var_276 & mask_SORT_2 [L725] SORT_3 var_277_arg_0 = var_200; [L726] SORT_2 var_277_arg_1 = var_276; [L727] SORT_4 var_277 = ((SORT_4)var_277_arg_0 << 8) | var_277_arg_1; [L728] var_277 = var_277 & mask_SORT_4 [L729] SORT_4 var_278_arg_0 = var_199; [L730] SORT_4 var_278_arg_1 = var_277; [L731] SORT_1 var_278 = var_278_arg_0 <= var_278_arg_1; [L732] SORT_1 var_279_arg_0 = var_273; [L733] SORT_1 var_279_arg_1 = var_278; [L734] SORT_1 var_279 = var_279_arg_0 & var_279_arg_1; [L735] SORT_1 var_280_arg_0 = ~input_272; [L736] var_280_arg_0 = var_280_arg_0 & mask_SORT_1 [L737] SORT_1 var_280_arg_1 = var_279; [L738] SORT_1 var_280 = var_280_arg_0 | var_280_arg_1; [L739] SORT_1 var_281_arg_0 = var_271; [L740] SORT_1 var_281_arg_1 = var_280; [L741] SORT_1 var_281 = var_281_arg_0 & var_281_arg_1; [L742] SORT_1 var_283_arg_0 = input_172; [L743] SORT_1 var_283_arg_1 = input_272; [L744] SORT_1 var_283 = var_283_arg_0 | var_283_arg_1; [L745] SORT_1 var_284_arg_0 = var_268; [L746] SORT_1 var_284_arg_1 = var_283; [L747] SORT_1 var_284 = var_284_arg_0 & var_284_arg_1; [L748] SORT_1 var_285_arg_0 = ~input_282; [L749] var_285_arg_0 = var_285_arg_0 & mask_SORT_1 [L750] SORT_1 var_285_arg_1 = var_284; [L751] SORT_1 var_285 = var_285_arg_0 | var_285_arg_1; [L752] SORT_1 var_286_arg_0 = var_281; [L753] SORT_1 var_286_arg_1 = var_285; [L754] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L755] SORT_4 var_288_arg_0 = var_236; [L756] SORT_4 var_288_arg_1 = var_199; [L757] SORT_4 var_288 = var_288_arg_0 - var_288_arg_1; [L758] SORT_4 var_289_arg_0 = var_288; [L759] SORT_2 var_289 = var_289_arg_0 >> 0; [L760] SORT_1 var_290_arg_0 = input_231; [L761] SORT_2 var_290_arg_1 = var_289; [L762] SORT_2 var_290_arg_2 = var_235; [L763] EXPR var_290_arg_0 ? var_290_arg_1 : var_290_arg_2 [L763] SORT_2 var_290 = var_290_arg_0 ? var_290_arg_1 : var_290_arg_2; [L764] var_290 = var_290 & mask_SORT_2 [L765] SORT_3 var_291_arg_0 = var_200; [L766] SORT_2 var_291_arg_1 = var_290; [L767] SORT_4 var_291 = ((SORT_4)var_291_arg_0 << 8) | var_291_arg_1; [L768] var_291 = var_291 & mask_SORT_4 [L769] SORT_4 var_292_arg_0 = var_199; [L770] SORT_4 var_292_arg_1 = var_291; [L771] SORT_1 var_292 = var_292_arg_0 <= var_292_arg_1; [L772] SORT_4 var_293_arg_0 = var_277; [L773] SORT_4 var_293_arg_1 = var_199; [L774] SORT_4 var_293 = var_293_arg_0 - var_293_arg_1; [L775] SORT_4 var_294_arg_0 = var_293; [L776] SORT_2 var_294 = var_294_arg_0 >> 0; [L777] SORT_1 var_295_arg_0 = input_272; [L778] SORT_2 var_295_arg_1 = var_294; [L779] SORT_2 var_295_arg_2 = var_276; [L780] EXPR var_295_arg_0 ? var_295_arg_1 : var_295_arg_2 [L780] SORT_2 var_295 = var_295_arg_0 ? var_295_arg_1 : var_295_arg_2; [L781] var_295 = var_295 & mask_SORT_2 [L782] SORT_3 var_296_arg_0 = var_200; [L783] SORT_2 var_296_arg_1 = var_295; [L784] SORT_4 var_296 = ((SORT_4)var_296_arg_0 << 8) | var_296_arg_1; [L785] var_296 = var_296 & mask_SORT_4 [L786] SORT_4 var_297_arg_0 = var_199; [L787] SORT_4 var_297_arg_1 = var_296; [L788] SORT_1 var_297 = var_297_arg_0 <= var_297_arg_1; [L789] SORT_1 var_298_arg_0 = var_292; [L790] SORT_1 var_298_arg_1 = var_297; [L791] SORT_1 var_298 = var_298_arg_0 & var_298_arg_1; [L792] SORT_1 var_299_arg_0 = input_174; [L793] SORT_1 var_299_arg_1 = var_298; [L794] SORT_1 var_299 = var_299_arg_0 & var_299_arg_1; [L795] SORT_1 var_300_arg_0 = ~input_287; [L796] var_300_arg_0 = var_300_arg_0 & mask_SORT_1 [L797] SORT_1 var_300_arg_1 = var_299; [L798] SORT_1 var_300 = var_300_arg_0 | var_300_arg_1; [L799] SORT_1 var_301_arg_0 = var_286; [L800] SORT_1 var_301_arg_1 = var_300; [L801] SORT_1 var_301 = var_301_arg_0 & var_301_arg_1; [L802] SORT_1 var_302_arg_0 = input_176; [L803] SORT_1 var_302_arg_1 = input_287; [L804] SORT_1 var_302 = var_302_arg_0 | var_302_arg_1; [L805] SORT_1 var_304_arg_0 = var_302; [L806] SORT_1 var_304_arg_1 = ~input_303; [L807] var_304_arg_1 = var_304_arg_1 & mask_SORT_1 [L808] SORT_1 var_304 = var_304_arg_0 | var_304_arg_1; [L809] SORT_1 var_305_arg_0 = var_301; [L810] SORT_1 var_305_arg_1 = var_304; [L811] SORT_1 var_305 = var_305_arg_0 & var_305_arg_1; [L812] SORT_1 var_307_arg_0 = input_178; [L813] SORT_1 var_307_arg_1 = input_303; [L814] SORT_1 var_307 = var_307_arg_0 | var_307_arg_1; [L815] SORT_4 var_308_arg_0 = var_267; [L816] SORT_4 var_308_arg_1 = var_199; [L817] SORT_4 var_308 = var_308_arg_0 - var_308_arg_1; [L818] SORT_4 var_309_arg_0 = var_308; [L819] SORT_2 var_309 = var_309_arg_0 >> 0; [L820] SORT_1 var_310_arg_0 = input_282; [L821] SORT_2 var_310_arg_1 = var_309; [L822] SORT_2 var_310_arg_2 = var_266; [L823] EXPR var_310_arg_0 ? var_310_arg_1 : var_310_arg_2 [L823] SORT_2 var_310 = var_310_arg_0 ? var_310_arg_1 : var_310_arg_2; [L824] var_310 = var_310 & mask_SORT_2 [L825] SORT_3 var_311_arg_0 = var_200; [L826] SORT_2 var_311_arg_1 = var_310; [L827] SORT_4 var_311 = ((SORT_4)var_311_arg_0 << 8) | var_311_arg_1; [L828] var_311 = var_311 & mask_SORT_4 [L829] SORT_4 var_312_arg_0 = var_199; [L830] SORT_4 var_312_arg_1 = var_311; [L831] SORT_1 var_312 = var_312_arg_0 <= var_312_arg_1; [L832] SORT_1 var_313_arg_0 = var_307; [L833] SORT_1 var_313_arg_1 = var_312; [L834] SORT_1 var_313 = var_313_arg_0 & var_313_arg_1; [L835] SORT_1 var_314_arg_0 = ~input_306; [L836] var_314_arg_0 = var_314_arg_0 & mask_SORT_1 [L837] SORT_1 var_314_arg_1 = var_313; [L838] SORT_1 var_314 = var_314_arg_0 | var_314_arg_1; [L839] SORT_1 var_315_arg_0 = var_305; [L840] SORT_1 var_315_arg_1 = var_314; [L841] SORT_1 var_315 = var_315_arg_0 & var_315_arg_1; [L842] SORT_1 var_317_arg_0 = input_180; [L843] SORT_1 var_317_arg_1 = input_306; [L844] SORT_1 var_317 = var_317_arg_0 | var_317_arg_1; [L845] SORT_4 var_318_arg_0 = var_311; [L846] SORT_4 var_318_arg_1 = var_199; [L847] SORT_4 var_318 = var_318_arg_0 - var_318_arg_1; [L848] SORT_4 var_319_arg_0 = var_318; [L849] SORT_2 var_319 = var_319_arg_0 >> 0; [L850] SORT_1 var_320_arg_0 = input_306; [L851] SORT_2 var_320_arg_1 = var_319; [L852] SORT_2 var_320_arg_2 = var_310; [L853] EXPR var_320_arg_0 ? var_320_arg_1 : var_320_arg_2 [L853] SORT_2 var_320 = var_320_arg_0 ? var_320_arg_1 : var_320_arg_2; [L854] var_320 = var_320 & mask_SORT_2 [L855] SORT_3 var_321_arg_0 = var_200; [L856] SORT_2 var_321_arg_1 = var_320; [L857] SORT_4 var_321 = ((SORT_4)var_321_arg_0 << 8) | var_321_arg_1; [L858] var_321 = var_321 & mask_SORT_4 [L859] SORT_4 var_322_arg_0 = var_199; [L860] SORT_4 var_322_arg_1 = var_321; [L861] SORT_1 var_322 = var_322_arg_0 <= var_322_arg_1; [L862] SORT_1 var_323_arg_0 = var_317; [L863] SORT_1 var_323_arg_1 = var_322; [L864] SORT_1 var_323 = var_323_arg_0 & var_323_arg_1; [L865] SORT_1 var_324_arg_0 = ~input_316; [L866] var_324_arg_0 = var_324_arg_0 & mask_SORT_1 [L867] SORT_1 var_324_arg_1 = var_323; [L868] SORT_1 var_324 = var_324_arg_0 | var_324_arg_1; [L869] SORT_1 var_325_arg_0 = var_315; [L870] SORT_1 var_325_arg_1 = var_324; [L871] SORT_1 var_325 = var_325_arg_0 & var_325_arg_1; [L872] SORT_1 var_327_arg_0 = input_186; [L873] SORT_1 var_327_arg_1 = input_316; [L874] SORT_1 var_327 = var_327_arg_0 | var_327_arg_1; [L875] SORT_4 var_328_arg_0 = var_296; [L876] SORT_4 var_328_arg_1 = var_199; [L877] SORT_4 var_328 = var_328_arg_0 - var_328_arg_1; [L878] SORT_4 var_329_arg_0 = var_328; [L879] SORT_2 var_329 = var_329_arg_0 >> 0; [L880] SORT_1 var_330_arg_0 = input_287; [L881] SORT_2 var_330_arg_1 = var_329; [L882] SORT_2 var_330_arg_2 = var_295; [L883] EXPR var_330_arg_0 ? var_330_arg_1 : var_330_arg_2 [L883] SORT_2 var_330 = var_330_arg_0 ? var_330_arg_1 : var_330_arg_2; [L884] var_330 = var_330 & mask_SORT_2 [L885] SORT_3 var_331_arg_0 = var_200; [L886] SORT_2 var_331_arg_1 = var_330; [L887] SORT_4 var_331 = ((SORT_4)var_331_arg_0 << 8) | var_331_arg_1; [L888] var_331 = var_331 & mask_SORT_4 [L889] SORT_4 var_332_arg_0 = var_199; [L890] SORT_4 var_332_arg_1 = var_331; [L891] SORT_1 var_332 = var_332_arg_0 <= var_332_arg_1; [L892] SORT_1 var_333_arg_0 = var_327; [L893] SORT_1 var_333_arg_1 = var_332; [L894] SORT_1 var_333 = var_333_arg_0 & var_333_arg_1; [L895] SORT_1 var_334_arg_0 = ~input_326; [L896] var_334_arg_0 = var_334_arg_0 & mask_SORT_1 [L897] SORT_1 var_334_arg_1 = var_333; [L898] SORT_1 var_334 = var_334_arg_0 | var_334_arg_1; [L899] SORT_1 var_335_arg_0 = var_325; [L900] SORT_1 var_335_arg_1 = var_334; [L901] SORT_1 var_335 = var_335_arg_0 & var_335_arg_1; [L902] SORT_1 var_337_arg_0 = input_188; [L903] SORT_1 var_337_arg_1 = input_326; [L904] SORT_1 var_337 = var_337_arg_0 | var_337_arg_1; [L905] SORT_1 var_338_arg_0 = var_322; [L906] SORT_1 var_338_arg_1 = var_337; [L907] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L908] SORT_1 var_339_arg_0 = ~input_336; [L909] var_339_arg_0 = var_339_arg_0 & mask_SORT_1 [L910] SORT_1 var_339_arg_1 = var_338; [L911] SORT_1 var_339 = var_339_arg_0 | var_339_arg_1; [L912] SORT_1 var_340_arg_0 = var_335; [L913] SORT_1 var_340_arg_1 = var_339; [L914] SORT_1 var_340 = var_340_arg_0 & var_340_arg_1; [L915] SORT_4 var_342_arg_0 = var_203; [L916] SORT_4 var_342_arg_1 = var_204; [L917] SORT_4 var_342 = var_342_arg_0 + var_342_arg_1; [L918] SORT_4 var_343_arg_0 = var_342; [L919] SORT_2 var_343 = var_343_arg_0 >> 0; [L920] SORT_1 var_344_arg_0 = input_198; [L921] SORT_2 var_344_arg_1 = var_343; [L922] SORT_2 var_344_arg_2 = input_132; [L923] EXPR var_344_arg_0 ? var_344_arg_1 : var_344_arg_2 [L923] SORT_2 var_344 = var_344_arg_0 ? var_344_arg_1 : var_344_arg_2; [L924] var_344 = var_344 & mask_SORT_2 [L925] SORT_3 var_345_arg_0 = var_200; [L926] SORT_2 var_345_arg_1 = var_344; [L927] SORT_4 var_345 = ((SORT_4)var_345_arg_0 << 8) | var_345_arg_1; [L928] var_345 = var_345 & mask_SORT_4 [L929] SORT_4 var_346_arg_0 = var_199; [L930] SORT_4 var_346_arg_1 = var_345; [L931] SORT_1 var_346 = var_346_arg_0 <= var_346_arg_1; [L932] SORT_1 var_347_arg_0 = input_194; [L933] SORT_1 var_347_arg_1 = var_346; [L934] SORT_1 var_347 = var_347_arg_0 & var_347_arg_1; [L935] SORT_1 var_348_arg_0 = ~input_341; [L936] var_348_arg_0 = var_348_arg_0 & mask_SORT_1 [L937] SORT_1 var_348_arg_1 = var_347; [L938] SORT_1 var_348 = var_348_arg_0 | var_348_arg_1; [L939] SORT_1 var_349_arg_0 = var_340; [L940] SORT_1 var_349_arg_1 = var_348; [L941] SORT_1 var_349 = var_349_arg_0 & var_349_arg_1; [L942] SORT_1 var_351_arg_0 = input_190; [L943] SORT_1 var_351_arg_1 = input_192; [L944] SORT_1 var_351 = var_351_arg_0 & var_351_arg_1; [L945] SORT_4 var_352_arg_0 = var_207; [L946] SORT_4 var_352_arg_1 = var_203; [L947] SORT_4 var_352 = var_352_arg_0 - var_352_arg_1; [L948] SORT_4 var_353_arg_0 = var_352; [L949] SORT_2 var_353 = var_353_arg_0 >> 0; [L950] SORT_1 var_354_arg_0 = input_198; [L951] SORT_2 var_354_arg_1 = var_353; [L952] SORT_2 var_354_arg_2 = input_134; [L953] EXPR var_354_arg_0 ? var_354_arg_1 : var_354_arg_2 [L953] SORT_2 var_354 = var_354_arg_0 ? var_354_arg_1 : var_354_arg_2; [L954] var_354 = var_354 & mask_SORT_2 [L955] SORT_3 var_355_arg_0 = var_200; [L956] SORT_2 var_355_arg_1 = var_354; [L957] SORT_4 var_355 = ((SORT_4)var_355_arg_0 << 8) | var_355_arg_1; [L958] SORT_4 var_356_arg_0 = var_199; [L959] SORT_4 var_356_arg_1 = var_355; [L960] SORT_4 var_356 = var_356_arg_0 + var_356_arg_1; [L961] SORT_4 var_357_arg_0 = var_356; [L962] SORT_2 var_357 = var_357_arg_0 >> 0; [L963] SORT_1 var_358_arg_0 = input_341; [L964] SORT_2 var_358_arg_1 = var_357; [L965] SORT_2 var_358_arg_2 = var_354; [L966] EXPR var_358_arg_0 ? var_358_arg_1 : var_358_arg_2 [L966] SORT_2 var_358 = var_358_arg_0 ? var_358_arg_1 : var_358_arg_2; [L967] var_358 = var_358 & mask_SORT_2 [L968] SORT_3 var_359_arg_0 = var_200; [L969] SORT_2 var_359_arg_1 = var_358; [L970] SORT_4 var_359 = ((SORT_4)var_359_arg_0 << 8) | var_359_arg_1; [L971] var_359 = var_359 & mask_SORT_4 [L972] SORT_4 var_360_arg_0 = var_203; [L973] SORT_4 var_360_arg_1 = var_359; [L974] SORT_1 var_360 = var_360_arg_0 <= var_360_arg_1; [L975] SORT_1 var_361_arg_0 = var_351; [L976] SORT_1 var_361_arg_1 = var_360; [L977] SORT_1 var_361 = var_361_arg_0 & var_361_arg_1; [L978] SORT_3 var_362_arg_0 = var_200; [L979] SORT_2 var_362_arg_1 = input_138; [L980] SORT_4 var_362 = ((SORT_4)var_362_arg_0 << 8) | var_362_arg_1; [L981] SORT_4 var_363_arg_0 = var_203; [L982] SORT_4 var_363_arg_1 = var_362; [L983] SORT_4 var_363 = var_363_arg_0 + var_363_arg_1; [L984] SORT_4 var_364_arg_0 = var_363; [L985] SORT_2 var_364 = var_364_arg_0 >> 0; [L986] SORT_1 var_365_arg_0 = input_198; [L987] SORT_2 var_365_arg_1 = var_364; [L988] SORT_2 var_365_arg_2 = input_138; [L989] EXPR var_365_arg_0 ? var_365_arg_1 : var_365_arg_2 [L989] SORT_2 var_365 = var_365_arg_0 ? var_365_arg_1 : var_365_arg_2; [L990] var_365 = var_365 & mask_SORT_2 [L991] SORT_3 var_366_arg_0 = var_200; [L992] SORT_2 var_366_arg_1 = var_365; [L993] SORT_4 var_366 = ((SORT_4)var_366_arg_0 << 8) | var_366_arg_1; [L994] SORT_4 var_367_arg_0 = var_199; [L995] SORT_4 var_367_arg_1 = var_366; [L996] SORT_4 var_367 = var_367_arg_0 + var_367_arg_1; [L997] SORT_4 var_368_arg_0 = var_367; [L998] SORT_2 var_368 = var_368_arg_0 >> 0; [L999] SORT_1 var_369_arg_0 = input_215; [L1000] SORT_2 var_369_arg_1 = var_368; [L1001] SORT_2 var_369_arg_2 = var_365; [L1002] EXPR var_369_arg_0 ? var_369_arg_1 : var_369_arg_2 [L1002] SORT_2 var_369 = var_369_arg_0 ? var_369_arg_1 : var_369_arg_2; [L1003] var_369 = var_369 & mask_SORT_2 [L1004] SORT_3 var_370_arg_0 = var_200; [L1005] SORT_2 var_370_arg_1 = var_369; [L1006] SORT_4 var_370 = ((SORT_4)var_370_arg_0 << 8) | var_370_arg_1; [L1007] SORT_4 var_371_arg_0 = var_199; [L1008] SORT_4 var_371_arg_1 = var_370; [L1009] SORT_4 var_371 = var_371_arg_0 + var_371_arg_1; [L1010] SORT_4 var_372_arg_0 = var_371; [L1011] SORT_2 var_372 = var_372_arg_0 >> 0; [L1012] SORT_1 var_373_arg_0 = input_252; [L1013] SORT_2 var_373_arg_1 = var_372; [L1014] SORT_2 var_373_arg_2 = var_369; [L1015] EXPR var_373_arg_0 ? var_373_arg_1 : var_373_arg_2 [L1015] SORT_2 var_373 = var_373_arg_0 ? var_373_arg_1 : var_373_arg_2; [L1016] var_373 = var_373 & mask_SORT_2 [L1017] SORT_3 var_374_arg_0 = var_200; [L1018] SORT_2 var_374_arg_1 = var_373; [L1019] SORT_4 var_374 = ((SORT_4)var_374_arg_0 << 8) | var_374_arg_1; [L1020] SORT_4 var_375_arg_0 = var_199; [L1021] SORT_4 var_375_arg_1 = var_374; [L1022] SORT_4 var_375 = var_375_arg_0 + var_375_arg_1; [L1023] SORT_4 var_376_arg_0 = var_375; [L1024] SORT_2 var_376 = var_376_arg_0 >> 0; [L1025] SORT_1 var_377_arg_0 = input_262; [L1026] SORT_2 var_377_arg_1 = var_376; [L1027] SORT_2 var_377_arg_2 = var_373; [L1028] EXPR var_377_arg_0 ? var_377_arg_1 : var_377_arg_2 [L1028] SORT_2 var_377 = var_377_arg_0 ? var_377_arg_1 : var_377_arg_2; [L1029] var_377 = var_377 & mask_SORT_2 [L1030] SORT_3 var_378_arg_0 = var_200; [L1031] SORT_2 var_378_arg_1 = var_377; [L1032] SORT_4 var_378 = ((SORT_4)var_378_arg_0 << 8) | var_378_arg_1; [L1033] SORT_4 var_379_arg_0 = var_199; [L1034] SORT_4 var_379_arg_1 = var_378; [L1035] SORT_4 var_379 = var_379_arg_0 + var_379_arg_1; [L1036] SORT_4 var_380_arg_0 = var_379; [L1037] SORT_2 var_380 = var_380_arg_0 >> 0; [L1038] SORT_1 var_381_arg_0 = input_282; [L1039] SORT_2 var_381_arg_1 = var_380; [L1040] SORT_2 var_381_arg_2 = var_377; [L1041] EXPR var_381_arg_0 ? var_381_arg_1 : var_381_arg_2 [L1041] SORT_2 var_381 = var_381_arg_0 ? var_381_arg_1 : var_381_arg_2; [L1042] var_381 = var_381 & mask_SORT_2 [L1043] SORT_3 var_382_arg_0 = var_200; [L1044] SORT_2 var_382_arg_1 = var_381; [L1045] SORT_4 var_382 = ((SORT_4)var_382_arg_0 << 8) | var_382_arg_1; [L1046] SORT_4 var_383_arg_0 = var_199; [L1047] SORT_4 var_383_arg_1 = var_382; [L1048] SORT_4 var_383 = var_383_arg_0 + var_383_arg_1; [L1049] SORT_4 var_384_arg_0 = var_383; [L1050] SORT_2 var_384 = var_384_arg_0 >> 0; [L1051] SORT_1 var_385_arg_0 = input_306; [L1052] SORT_2 var_385_arg_1 = var_384; [L1053] SORT_2 var_385_arg_2 = var_381; [L1054] EXPR var_385_arg_0 ? var_385_arg_1 : var_385_arg_2 [L1054] SORT_2 var_385 = var_385_arg_0 ? var_385_arg_1 : var_385_arg_2; [L1055] var_385 = var_385 & mask_SORT_2 [L1056] SORT_3 var_386_arg_0 = var_200; [L1057] SORT_2 var_386_arg_1 = var_385; [L1058] SORT_4 var_386 = ((SORT_4)var_386_arg_0 << 8) | var_386_arg_1; [L1059] SORT_4 var_387_arg_0 = var_199; [L1060] SORT_4 var_387_arg_1 = var_386; [L1061] SORT_4 var_387 = var_387_arg_0 + var_387_arg_1; [L1062] SORT_4 var_388_arg_0 = var_387; [L1063] SORT_2 var_388 = var_388_arg_0 >> 0; [L1064] SORT_1 var_389_arg_0 = input_316; [L1065] SORT_2 var_389_arg_1 = var_388; [L1066] SORT_2 var_389_arg_2 = var_385; [L1067] EXPR var_389_arg_0 ? var_389_arg_1 : var_389_arg_2 [L1067] SORT_2 var_389 = var_389_arg_0 ? var_389_arg_1 : var_389_arg_2; [L1068] var_389 = var_389 & mask_SORT_2 [L1069] SORT_3 var_390_arg_0 = var_200; [L1070] SORT_2 var_390_arg_1 = var_389; [L1071] SORT_4 var_390 = ((SORT_4)var_390_arg_0 << 8) | var_390_arg_1; [L1072] SORT_4 var_391_arg_0 = var_199; [L1073] SORT_4 var_391_arg_1 = var_390; [L1074] SORT_4 var_391 = var_391_arg_0 + var_391_arg_1; [L1075] SORT_4 var_392_arg_0 = var_391; [L1076] SORT_2 var_392 = var_392_arg_0 >> 0; [L1077] SORT_1 var_393_arg_0 = input_336; [L1078] SORT_2 var_393_arg_1 = var_392; [L1079] SORT_2 var_393_arg_2 = var_389; [L1080] EXPR var_393_arg_0 ? var_393_arg_1 : var_393_arg_2 [L1080] SORT_2 var_393 = var_393_arg_0 ? var_393_arg_1 : var_393_arg_2; [L1081] var_393 = var_393 & mask_SORT_2 [L1082] SORT_3 var_394_arg_0 = var_200; [L1083] SORT_2 var_394_arg_1 = var_393; [L1084] SORT_4 var_394 = ((SORT_4)var_394_arg_0 << 8) | var_394_arg_1; [L1085] var_394 = var_394 & mask_SORT_4 [L1086] SORT_4 var_395_arg_0 = var_199; [L1087] SORT_4 var_395_arg_1 = var_394; [L1088] SORT_1 var_395 = var_395_arg_0 <= var_395_arg_1; [L1089] SORT_3 var_396_arg_0 = var_200; [L1090] SORT_2 var_396_arg_1 = input_144; [L1091] SORT_4 var_396 = ((SORT_4)var_396_arg_0 << 8) | var_396_arg_1; [L1092] var_396 = var_396 & mask_SORT_4 [L1093] SORT_4 var_397_arg_0 = var_199; [L1094] SORT_4 var_397_arg_1 = var_396; [L1095] SORT_1 var_397 = var_397_arg_0 <= var_397_arg_1; [L1096] SORT_1 var_398_arg_0 = var_395; [L1097] SORT_1 var_398_arg_1 = var_397; [L1098] SORT_1 var_398 = var_398_arg_0 & var_398_arg_1; [L1099] SORT_3 var_399_arg_0 = var_200; [L1100] SORT_2 var_399_arg_1 = input_148; [L1101] SORT_4 var_399 = ((SORT_4)var_399_arg_0 << 8) | var_399_arg_1; [L1102] SORT_4 var_400_arg_0 = var_203; [L1103] SORT_4 var_400_arg_1 = var_399; [L1104] SORT_4 var_400 = var_400_arg_0 + var_400_arg_1; [L1105] SORT_4 var_401_arg_0 = var_400; [L1106] SORT_2 var_401 = var_401_arg_0 >> 0; [L1107] SORT_1 var_402_arg_0 = input_198; [L1108] SORT_2 var_402_arg_1 = var_401; [L1109] SORT_2 var_402_arg_2 = input_148; [L1110] EXPR var_402_arg_0 ? var_402_arg_1 : var_402_arg_2 [L1110] SORT_2 var_402 = var_402_arg_0 ? var_402_arg_1 : var_402_arg_2; [L1111] var_402 = var_402 & mask_SORT_2 [L1112] SORT_3 var_403_arg_0 = var_200; [L1113] SORT_2 var_403_arg_1 = var_402; [L1114] SORT_4 var_403 = ((SORT_4)var_403_arg_0 << 8) | var_403_arg_1; [L1115] SORT_4 var_404_arg_0 = var_199; [L1116] SORT_4 var_404_arg_1 = var_403; [L1117] SORT_4 var_404 = var_404_arg_0 + var_404_arg_1; [L1118] SORT_4 var_405_arg_0 = var_404; [L1119] SORT_2 var_405 = var_405_arg_0 >> 0; [L1120] SORT_1 var_406_arg_0 = input_252; [L1121] SORT_2 var_406_arg_1 = var_405; [L1122] SORT_2 var_406_arg_2 = var_402; [L1123] EXPR var_406_arg_0 ? var_406_arg_1 : var_406_arg_2 [L1123] SORT_2 var_406 = var_406_arg_0 ? var_406_arg_1 : var_406_arg_2; [L1124] var_406 = var_406 & mask_SORT_2 [L1125] SORT_3 var_407_arg_0 = var_200; [L1126] SORT_2 var_407_arg_1 = var_406; [L1127] SORT_4 var_407 = ((SORT_4)var_407_arg_0 << 8) | var_407_arg_1; [L1128] SORT_4 var_408_arg_0 = var_199; [L1129] SORT_4 var_408_arg_1 = var_407; [L1130] SORT_4 var_408 = var_408_arg_0 + var_408_arg_1; [L1131] SORT_4 var_409_arg_0 = var_408; [L1132] SORT_2 var_409 = var_409_arg_0 >> 0; [L1133] SORT_1 var_410_arg_0 = input_306; [L1134] SORT_2 var_410_arg_1 = var_409; [L1135] SORT_2 var_410_arg_2 = var_406; [L1136] EXPR var_410_arg_0 ? var_410_arg_1 : var_410_arg_2 [L1136] SORT_2 var_410 = var_410_arg_0 ? var_410_arg_1 : var_410_arg_2; [L1137] var_410 = var_410 & mask_SORT_2 [L1138] SORT_3 var_411_arg_0 = var_200; [L1139] SORT_2 var_411_arg_1 = var_410; [L1140] SORT_4 var_411 = ((SORT_4)var_411_arg_0 << 8) | var_411_arg_1; [L1141] var_411 = var_411 & mask_SORT_4 [L1142] SORT_4 var_412_arg_0 = var_203; [L1143] SORT_4 var_412_arg_1 = var_411; [L1144] SORT_1 var_412 = var_412_arg_0 <= var_412_arg_1; [L1145] SORT_1 var_413_arg_0 = var_398; [L1146] SORT_1 var_413_arg_1 = var_412; [L1147] SORT_1 var_413 = var_413_arg_0 & var_413_arg_1; [L1148] SORT_1 var_414_arg_0 = var_361; [L1149] SORT_1 var_414_arg_1 = var_413; [L1150] SORT_1 var_414 = var_414_arg_0 & var_414_arg_1; [L1151] SORT_1 var_415_arg_0 = ~input_350; [L1152] var_415_arg_0 = var_415_arg_0 & mask_SORT_1 [L1153] SORT_1 var_415_arg_1 = var_414; [L1154] SORT_1 var_415 = var_415_arg_0 | var_415_arg_1; [L1155] SORT_1 var_416_arg_0 = var_349; [L1156] SORT_1 var_416_arg_1 = var_415; [L1157] SORT_1 var_416 = var_416_arg_0 & var_416_arg_1; [L1158] SORT_1 var_417_arg_0 = input_198; [L1159] SORT_1 var_417_arg_1 = input_215; [L1160] SORT_1 var_417 = var_417_arg_0 | var_417_arg_1; [L1161] SORT_1 var_418_arg_0 = input_231; [L1162] SORT_1 var_418_arg_1 = var_417; [L1163] SORT_1 var_418 = var_418_arg_0 | var_418_arg_1; [L1164] SORT_1 var_419_arg_0 = input_249; [L1165] SORT_1 var_419_arg_1 = var_418; [L1166] SORT_1 var_419 = var_419_arg_0 | var_419_arg_1; [L1167] SORT_1 var_420_arg_0 = input_252; [L1168] SORT_1 var_420_arg_1 = var_419; [L1169] SORT_1 var_420 = var_420_arg_0 | var_420_arg_1; [L1170] SORT_1 var_421_arg_0 = input_262; [L1171] SORT_1 var_421_arg_1 = var_420; [L1172] SORT_1 var_421 = var_421_arg_0 | var_421_arg_1; [L1173] SORT_1 var_422_arg_0 = input_272; [L1174] SORT_1 var_422_arg_1 = var_421; [L1175] SORT_1 var_422 = var_422_arg_0 | var_422_arg_1; [L1176] SORT_1 var_423_arg_0 = input_282; [L1177] SORT_1 var_423_arg_1 = var_422; [L1178] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1179] SORT_1 var_424_arg_0 = input_287; [L1180] SORT_1 var_424_arg_1 = var_423; [L1181] SORT_1 var_424 = var_424_arg_0 | var_424_arg_1; [L1182] SORT_1 var_425_arg_0 = input_303; [L1183] SORT_1 var_425_arg_1 = var_424; [L1184] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1185] SORT_1 var_426_arg_0 = input_306; [L1186] SORT_1 var_426_arg_1 = var_425; [L1187] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1188] SORT_1 var_427_arg_0 = input_316; [L1189] SORT_1 var_427_arg_1 = var_426; [L1190] SORT_1 var_427 = var_427_arg_0 | var_427_arg_1; [L1191] SORT_1 var_428_arg_0 = input_326; [L1192] SORT_1 var_428_arg_1 = var_427; [L1193] SORT_1 var_428 = var_428_arg_0 | var_428_arg_1; [L1194] SORT_1 var_429_arg_0 = input_336; [L1195] SORT_1 var_429_arg_1 = var_428; [L1196] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1197] SORT_1 var_430_arg_0 = input_341; [L1198] SORT_1 var_430_arg_1 = var_429; [L1199] SORT_1 var_430 = var_430_arg_0 | var_430_arg_1; [L1200] SORT_1 var_431_arg_0 = input_350; [L1201] SORT_1 var_431_arg_1 = var_430; [L1202] SORT_1 var_431 = var_431_arg_0 | var_431_arg_1; [L1203] SORT_1 var_432_arg_0 = var_416; [L1204] SORT_1 var_432_arg_1 = var_431; [L1205] SORT_1 var_432 = var_432_arg_0 & var_432_arg_1; [L1206] SORT_1 var_433_arg_0 = input_154; [L1207] SORT_1 var_433_arg_1 = input_156; [L1208] SORT_1 var_433 = var_433_arg_0 & var_433_arg_1; [L1209] SORT_1 var_434_arg_0 = var_433; [L1210] SORT_1 var_434_arg_1 = input_190; [L1211] SORT_1 var_434 = var_434_arg_0 & var_434_arg_1; [L1212] SORT_1 var_435_arg_0 = var_434; [L1213] SORT_1 var_435_arg_1 = input_192; [L1214] SORT_1 var_435 = var_435_arg_0 & var_435_arg_1; [L1215] SORT_1 var_436_arg_0 = var_435; [L1216] SORT_1 var_436_arg_1 = input_194; [L1217] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1218] SORT_1 var_437_arg_0 = input_158; [L1219] SORT_1 var_437_arg_1 = input_160; [L1220] SORT_1 var_437 = var_437_arg_0 & var_437_arg_1; [L1221] SORT_1 var_438_arg_0 = input_158; [L1222] SORT_1 var_438_arg_1 = input_160; [L1223] SORT_1 var_438 = var_438_arg_0 | var_438_arg_1; [L1224] SORT_1 var_439_arg_0 = input_162; [L1225] SORT_1 var_439_arg_1 = var_438; [L1226] SORT_1 var_439 = var_439_arg_0 & var_439_arg_1; [L1227] SORT_1 var_440_arg_0 = var_437; [L1228] SORT_1 var_440_arg_1 = var_439; [L1229] SORT_1 var_440 = var_440_arg_0 | var_440_arg_1; [L1230] SORT_1 var_441_arg_0 = input_162; [L1231] SORT_1 var_441_arg_1 = var_438; [L1232] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1233] SORT_1 var_442_arg_0 = input_164; [L1234] SORT_1 var_442_arg_1 = var_441; [L1235] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1236] SORT_1 var_443_arg_0 = var_440; [L1237] SORT_1 var_443_arg_1 = var_442; [L1238] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1239] SORT_1 var_444_arg_0 = input_164; [L1240] SORT_1 var_444_arg_1 = var_441; [L1241] SORT_1 var_444 = var_444_arg_0 | var_444_arg_1; [L1242] SORT_1 var_445_arg_0 = input_166; [L1243] SORT_1 var_445_arg_1 = var_444; [L1244] SORT_1 var_445 = var_445_arg_0 & var_445_arg_1; [L1245] SORT_1 var_446_arg_0 = var_443; [L1246] SORT_1 var_446_arg_1 = var_445; [L1247] SORT_1 var_446 = var_446_arg_0 | var_446_arg_1; [L1248] SORT_1 var_447_arg_0 = input_166; [L1249] SORT_1 var_447_arg_1 = var_444; [L1250] SORT_1 var_447 = var_447_arg_0 | var_447_arg_1; [L1251] SORT_1 var_448_arg_0 = input_168; [L1252] SORT_1 var_448_arg_1 = var_447; [L1253] SORT_1 var_448 = var_448_arg_0 & var_448_arg_1; [L1254] SORT_1 var_449_arg_0 = var_446; [L1255] SORT_1 var_449_arg_1 = var_448; [L1256] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1257] SORT_1 var_450_arg_0 = input_168; [L1258] SORT_1 var_450_arg_1 = var_447; [L1259] SORT_1 var_450 = var_450_arg_0 | var_450_arg_1; [L1260] SORT_1 var_451_arg_0 = input_170; [L1261] SORT_1 var_451_arg_1 = var_450; [L1262] SORT_1 var_451 = var_451_arg_0 & var_451_arg_1; [L1263] SORT_1 var_452_arg_0 = var_449; [L1264] SORT_1 var_452_arg_1 = var_451; [L1265] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1266] SORT_1 var_453_arg_0 = input_170; [L1267] SORT_1 var_453_arg_1 = var_450; [L1268] SORT_1 var_453 = var_453_arg_0 | var_453_arg_1; [L1269] SORT_1 var_454_arg_0 = input_172; [L1270] SORT_1 var_454_arg_1 = var_453; [L1271] SORT_1 var_454 = var_454_arg_0 & var_454_arg_1; [L1272] SORT_1 var_455_arg_0 = var_452; [L1273] SORT_1 var_455_arg_1 = var_454; [L1274] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1275] SORT_1 var_456_arg_0 = var_436; [L1276] SORT_1 var_456_arg_1 = ~var_455; [L1277] var_456_arg_1 = var_456_arg_1 & mask_SORT_1 [L1278] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1279] SORT_1 var_457_arg_0 = input_172; [L1280] SORT_1 var_457_arg_1 = var_453; [L1281] SORT_1 var_457 = var_457_arg_0 | var_457_arg_1; [L1282] SORT_1 var_458_arg_0 = var_456; [L1283] SORT_1 var_458_arg_1 = var_457; [L1284] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1285] SORT_1 var_459_arg_0 = input_174; [L1286] SORT_1 var_459_arg_1 = input_176; [L1287] SORT_1 var_459 = var_459_arg_0 & var_459_arg_1; [L1288] SORT_1 var_460_arg_0 = input_174; [L1289] SORT_1 var_460_arg_1 = input_176; [L1290] SORT_1 var_460 = var_460_arg_0 | var_460_arg_1; [L1291] SORT_1 var_461_arg_0 = input_178; [L1292] SORT_1 var_461_arg_1 = var_460; [L1293] SORT_1 var_461 = var_461_arg_0 & var_461_arg_1; [L1294] SORT_1 var_462_arg_0 = var_459; [L1295] SORT_1 var_462_arg_1 = var_461; [L1296] SORT_1 var_462 = var_462_arg_0 | var_462_arg_1; [L1297] SORT_1 var_463_arg_0 = input_178; [L1298] SORT_1 var_463_arg_1 = var_460; [L1299] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1300] SORT_1 var_464_arg_0 = input_180; [L1301] SORT_1 var_464_arg_1 = var_463; [L1302] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1303] SORT_1 var_465_arg_0 = var_462; [L1304] SORT_1 var_465_arg_1 = var_464; [L1305] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1306] SORT_1 var_466_arg_0 = input_180; [L1307] SORT_1 var_466_arg_1 = var_463; [L1308] SORT_1 var_466 = var_466_arg_0 | var_466_arg_1; [L1309] SORT_1 var_467_arg_0 = input_182; [L1310] SORT_1 var_467_arg_1 = var_466; [L1311] SORT_1 var_467 = var_467_arg_0 & var_467_arg_1; [L1312] SORT_1 var_468_arg_0 = var_465; [L1313] SORT_1 var_468_arg_1 = var_467; [L1314] SORT_1 var_468 = var_468_arg_0 | var_468_arg_1; [L1315] SORT_1 var_469_arg_0 = input_182; [L1316] SORT_1 var_469_arg_1 = var_466; [L1317] SORT_1 var_469 = var_469_arg_0 | var_469_arg_1; [L1318] SORT_1 var_470_arg_0 = input_184; [L1319] SORT_1 var_470_arg_1 = var_469; [L1320] SORT_1 var_470 = var_470_arg_0 & var_470_arg_1; [L1321] SORT_1 var_471_arg_0 = var_468; [L1322] SORT_1 var_471_arg_1 = var_470; [L1323] SORT_1 var_471 = var_471_arg_0 | var_471_arg_1; [L1324] SORT_1 var_472_arg_0 = input_184; [L1325] SORT_1 var_472_arg_1 = var_469; [L1326] SORT_1 var_472 = var_472_arg_0 | var_472_arg_1; [L1327] SORT_1 var_473_arg_0 = input_186; [L1328] SORT_1 var_473_arg_1 = var_472; [L1329] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1330] SORT_1 var_474_arg_0 = var_471; [L1331] SORT_1 var_474_arg_1 = var_473; [L1332] SORT_1 var_474 = var_474_arg_0 | var_474_arg_1; [L1333] SORT_1 var_475_arg_0 = input_186; [L1334] SORT_1 var_475_arg_1 = var_472; [L1335] SORT_1 var_475 = var_475_arg_0 | var_475_arg_1; [L1336] SORT_1 var_476_arg_0 = input_188; [L1337] SORT_1 var_476_arg_1 = var_475; [L1338] SORT_1 var_476 = var_476_arg_0 & var_476_arg_1; [L1339] SORT_1 var_477_arg_0 = var_474; [L1340] SORT_1 var_477_arg_1 = var_476; [L1341] SORT_1 var_477 = var_477_arg_0 | var_477_arg_1; [L1342] SORT_1 var_478_arg_0 = var_458; [L1343] SORT_1 var_478_arg_1 = ~var_477; [L1344] var_478_arg_1 = var_478_arg_1 & mask_SORT_1 [L1345] SORT_1 var_478 = var_478_arg_0 & var_478_arg_1; [L1346] SORT_1 var_479_arg_0 = input_188; [L1347] SORT_1 var_479_arg_1 = var_475; [L1348] SORT_1 var_479 = var_479_arg_0 | var_479_arg_1; [L1349] SORT_1 var_480_arg_0 = var_478; [L1350] SORT_1 var_480_arg_1 = var_479; [L1351] SORT_1 var_480 = var_480_arg_0 & var_480_arg_1; [L1352] SORT_1 var_481_arg_0 = var_432; [L1353] SORT_1 var_481_arg_1 = var_480; [L1354] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1355] SORT_1 var_482_arg_0 = input_154; [L1356] SORT_1 var_482_arg_1 = input_156; [L1357] SORT_1 var_482 = var_482_arg_0 & var_482_arg_1; [L1358] SORT_1 var_483_arg_0 = var_482; [L1359] SORT_1 var_483_arg_1 = input_190; [L1360] SORT_1 var_483 = var_483_arg_0 & var_483_arg_1; [L1361] SORT_1 var_484_arg_0 = var_483; [L1362] SORT_1 var_484_arg_1 = input_192; [L1363] SORT_1 var_484 = var_484_arg_0 & var_484_arg_1; [L1364] SORT_1 var_485_arg_0 = var_484; [L1365] SORT_1 var_485_arg_1 = input_194; [L1366] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1367] SORT_1 var_486_arg_0 = var_248; [L1368] SORT_1 var_486_arg_1 = ~input_249; [L1369] var_486_arg_1 = var_486_arg_1 & mask_SORT_1 [L1370] SORT_1 var_486 = var_486_arg_0 & var_486_arg_1; [L1371] var_486 = var_486 & mask_SORT_1 [L1372] SORT_1 var_487_arg_0 = input_158; [L1373] SORT_1 var_487_arg_1 = ~input_231; [L1374] var_487_arg_1 = var_487_arg_1 & mask_SORT_1 [L1375] SORT_1 var_487 = var_487_arg_0 & var_487_arg_1; [L1376] SORT_1 var_488_arg_0 = var_487; [L1377] SORT_1 var_488_arg_1 = input_282; [L1378] SORT_1 var_488 = var_488_arg_0 | var_488_arg_1; [L1379] var_488 = var_488 & mask_SORT_1 [L1380] SORT_1 var_489_arg_0 = var_486; [L1381] SORT_1 var_489_arg_1 = var_488; [L1382] SORT_1 var_489 = var_489_arg_0 & var_489_arg_1; [L1383] SORT_1 var_490_arg_0 = var_253; [L1384] SORT_1 var_490_arg_1 = ~input_252; [L1385] var_490_arg_1 = var_490_arg_1 & mask_SORT_1 [L1386] SORT_1 var_490 = var_490_arg_0 & var_490_arg_1; [L1387] var_490 = var_490 & mask_SORT_1 [L1388] SORT_1 var_491_arg_0 = var_486; [L1389] SORT_1 var_491_arg_1 = var_488; [L1390] SORT_1 var_491 = var_491_arg_0 | var_491_arg_1; [L1391] SORT_1 var_492_arg_0 = var_490; [L1392] SORT_1 var_492_arg_1 = var_491; [L1393] SORT_1 var_492 = var_492_arg_0 & var_492_arg_1; [L1394] SORT_1 var_493_arg_0 = var_489; [L1395] SORT_1 var_493_arg_1 = var_492; [L1396] SORT_1 var_493 = var_493_arg_0 | var_493_arg_1; [L1397] SORT_1 var_494_arg_0 = var_263; [L1398] SORT_1 var_494_arg_1 = ~input_262; [L1399] var_494_arg_1 = var_494_arg_1 & mask_SORT_1 [L1400] SORT_1 var_494 = var_494_arg_0 & var_494_arg_1; [L1401] var_494 = var_494 & mask_SORT_1 [L1402] SORT_1 var_495_arg_0 = var_490; [L1403] SORT_1 var_495_arg_1 = var_491; [L1404] SORT_1 var_495 = var_495_arg_0 | var_495_arg_1; [L1405] SORT_1 var_496_arg_0 = var_494; [L1406] SORT_1 var_496_arg_1 = var_495; [L1407] SORT_1 var_496 = var_496_arg_0 & var_496_arg_1; [L1408] SORT_1 var_497_arg_0 = var_493; [L1409] SORT_1 var_497_arg_1 = var_496; [L1410] SORT_1 var_497 = var_497_arg_0 | var_497_arg_1; [L1411] SORT_1 var_498_arg_0 = var_494; [L1412] SORT_1 var_498_arg_1 = var_495; [L1413] SORT_1 var_498 = var_498_arg_0 | var_498_arg_1; [L1414] SORT_1 var_499_arg_0 = input_166; [L1415] SORT_1 var_499_arg_1 = var_498; [L1416] SORT_1 var_499 = var_499_arg_0 & var_499_arg_1; [L1417] SORT_1 var_500_arg_0 = var_497; [L1418] SORT_1 var_500_arg_1 = var_499; [L1419] SORT_1 var_500 = var_500_arg_0 | var_500_arg_1; [L1420] SORT_1 var_501_arg_0 = input_166; [L1421] SORT_1 var_501_arg_1 = var_498; [L1422] SORT_1 var_501 = var_501_arg_0 | var_501_arg_1; [L1423] SORT_1 var_502_arg_0 = input_168; [L1424] SORT_1 var_502_arg_1 = var_501; [L1425] SORT_1 var_502 = var_502_arg_0 & var_502_arg_1; [L1426] SORT_1 var_503_arg_0 = var_500; [L1427] SORT_1 var_503_arg_1 = var_502; [L1428] SORT_1 var_503 = var_503_arg_0 | var_503_arg_1; [L1429] SORT_1 var_504_arg_0 = var_273; [L1430] SORT_1 var_504_arg_1 = ~input_272; [L1431] var_504_arg_1 = var_504_arg_1 & mask_SORT_1 [L1432] SORT_1 var_504 = var_504_arg_0 & var_504_arg_1; [L1433] var_504 = var_504 & mask_SORT_1 [L1434] SORT_1 var_505_arg_0 = input_168; [L1435] SORT_1 var_505_arg_1 = var_501; [L1436] SORT_1 var_505 = var_505_arg_0 | var_505_arg_1; [L1437] SORT_1 var_506_arg_0 = var_504; [L1438] SORT_1 var_506_arg_1 = var_505; [L1439] SORT_1 var_506 = var_506_arg_0 & var_506_arg_1; [L1440] SORT_1 var_507_arg_0 = var_503; [L1441] SORT_1 var_507_arg_1 = var_506; [L1442] SORT_1 var_507 = var_507_arg_0 | var_507_arg_1; [L1443] SORT_1 var_508_arg_0 = var_283; [L1444] SORT_1 var_508_arg_1 = ~input_282; [L1445] var_508_arg_1 = var_508_arg_1 & mask_SORT_1 [L1446] SORT_1 var_508 = var_508_arg_0 & var_508_arg_1; [L1447] var_508 = var_508 & mask_SORT_1 [L1448] SORT_1 var_509_arg_0 = var_504; [L1449] SORT_1 var_509_arg_1 = var_505; [L1450] SORT_1 var_509 = var_509_arg_0 | var_509_arg_1; [L1451] SORT_1 var_510_arg_0 = var_508; [L1452] SORT_1 var_510_arg_1 = var_509; [L1453] SORT_1 var_510 = var_510_arg_0 & var_510_arg_1; [L1454] SORT_1 var_511_arg_0 = var_507; [L1455] SORT_1 var_511_arg_1 = var_510; [L1456] SORT_1 var_511 = var_511_arg_0 | var_511_arg_1; [L1457] SORT_1 var_512_arg_0 = var_485; [L1458] SORT_1 var_512_arg_1 = ~var_511; [L1459] var_512_arg_1 = var_512_arg_1 & mask_SORT_1 [L1460] SORT_1 var_512 = var_512_arg_0 & var_512_arg_1; [L1461] SORT_1 var_513_arg_0 = var_508; [L1462] SORT_1 var_513_arg_1 = var_509; [L1463] SORT_1 var_513 = var_513_arg_0 | var_513_arg_1; [L1464] SORT_1 var_514_arg_0 = var_512; [L1465] SORT_1 var_514_arg_1 = var_513; [L1466] SORT_1 var_514 = var_514_arg_0 & var_514_arg_1; [L1467] SORT_1 var_515_arg_0 = var_302; [L1468] SORT_1 var_515_arg_1 = ~input_303; [L1469] var_515_arg_1 = var_515_arg_1 & mask_SORT_1 [L1470] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1471] var_515 = var_515 & mask_SORT_1 [L1472] SORT_1 var_516_arg_0 = input_174; [L1473] SORT_1 var_516_arg_1 = ~input_287; [L1474] var_516_arg_1 = var_516_arg_1 & mask_SORT_1 [L1475] SORT_1 var_516 = var_516_arg_0 & var_516_arg_1; [L1476] SORT_1 var_517_arg_0 = var_516; [L1477] SORT_1 var_517_arg_1 = input_336; [L1478] SORT_1 var_517 = var_517_arg_0 | var_517_arg_1; [L1479] var_517 = var_517 & mask_SORT_1 [L1480] SORT_1 var_518_arg_0 = var_515; [L1481] SORT_1 var_518_arg_1 = var_517; [L1482] SORT_1 var_518 = var_518_arg_0 & var_518_arg_1; [L1483] SORT_1 var_519_arg_0 = var_307; [L1484] SORT_1 var_519_arg_1 = ~input_306; [L1485] var_519_arg_1 = var_519_arg_1 & mask_SORT_1 [L1486] SORT_1 var_519 = var_519_arg_0 & var_519_arg_1; [L1487] var_519 = var_519 & mask_SORT_1 [L1488] SORT_1 var_520_arg_0 = var_515; [L1489] SORT_1 var_520_arg_1 = var_517; [L1490] SORT_1 var_520 = var_520_arg_0 | var_520_arg_1; [L1491] SORT_1 var_521_arg_0 = var_519; [L1492] SORT_1 var_521_arg_1 = var_520; [L1493] SORT_1 var_521 = var_521_arg_0 & var_521_arg_1; [L1494] SORT_1 var_522_arg_0 = var_518; [L1495] SORT_1 var_522_arg_1 = var_521; [L1496] SORT_1 var_522 = var_522_arg_0 | var_522_arg_1; [L1497] SORT_1 var_523_arg_0 = var_317; [L1498] SORT_1 var_523_arg_1 = ~input_316; [L1499] var_523_arg_1 = var_523_arg_1 & mask_SORT_1 [L1500] SORT_1 var_523 = var_523_arg_0 & var_523_arg_1; [L1501] var_523 = var_523 & mask_SORT_1 [L1502] SORT_1 var_524_arg_0 = var_519; [L1503] SORT_1 var_524_arg_1 = var_520; [L1504] SORT_1 var_524 = var_524_arg_0 | var_524_arg_1; [L1505] SORT_1 var_525_arg_0 = var_523; [L1506] SORT_1 var_525_arg_1 = var_524; [L1507] SORT_1 var_525 = var_525_arg_0 & var_525_arg_1; [L1508] SORT_1 var_526_arg_0 = var_522; [L1509] SORT_1 var_526_arg_1 = var_525; [L1510] SORT_1 var_526 = var_526_arg_0 | var_526_arg_1; [L1511] SORT_1 var_527_arg_0 = var_523; [L1512] SORT_1 var_527_arg_1 = var_524; [L1513] SORT_1 var_527 = var_527_arg_0 | var_527_arg_1; [L1514] SORT_1 var_528_arg_0 = input_182; [L1515] SORT_1 var_528_arg_1 = var_527; [L1516] SORT_1 var_528 = var_528_arg_0 & var_528_arg_1; [L1517] SORT_1 var_529_arg_0 = var_526; [L1518] SORT_1 var_529_arg_1 = var_528; [L1519] SORT_1 var_529 = var_529_arg_0 | var_529_arg_1; [L1520] SORT_1 var_530_arg_0 = input_182; [L1521] SORT_1 var_530_arg_1 = var_527; [L1522] SORT_1 var_530 = var_530_arg_0 | var_530_arg_1; [L1523] SORT_1 var_531_arg_0 = input_184; [L1524] SORT_1 var_531_arg_1 = var_530; [L1525] SORT_1 var_531 = var_531_arg_0 & var_531_arg_1; [L1526] SORT_1 var_532_arg_0 = var_529; [L1527] SORT_1 var_532_arg_1 = var_531; [L1528] SORT_1 var_532 = var_532_arg_0 | var_532_arg_1; [L1529] SORT_1 var_533_arg_0 = var_327; [L1530] SORT_1 var_533_arg_1 = ~input_326; [L1531] var_533_arg_1 = var_533_arg_1 & mask_SORT_1 [L1532] SORT_1 var_533 = var_533_arg_0 & var_533_arg_1; [L1533] var_533 = var_533 & mask_SORT_1 [L1534] SORT_1 var_534_arg_0 = input_184; [L1535] SORT_1 var_534_arg_1 = var_530; [L1536] SORT_1 var_534 = var_534_arg_0 | var_534_arg_1; [L1537] SORT_1 var_535_arg_0 = var_533; [L1538] SORT_1 var_535_arg_1 = var_534; [L1539] SORT_1 var_535 = var_535_arg_0 & var_535_arg_1; [L1540] SORT_1 var_536_arg_0 = var_532; [L1541] SORT_1 var_536_arg_1 = var_535; [L1542] SORT_1 var_536 = var_536_arg_0 | var_536_arg_1; [L1543] SORT_1 var_537_arg_0 = var_337; [L1544] SORT_1 var_537_arg_1 = ~input_336; [L1545] var_537_arg_1 = var_537_arg_1 & mask_SORT_1 [L1546] SORT_1 var_537 = var_537_arg_0 & var_537_arg_1; [L1547] var_537 = var_537 & mask_SORT_1 [L1548] SORT_1 var_538_arg_0 = var_533; [L1549] SORT_1 var_538_arg_1 = var_534; [L1550] SORT_1 var_538 = var_538_arg_0 | var_538_arg_1; [L1551] SORT_1 var_539_arg_0 = var_537; [L1552] SORT_1 var_539_arg_1 = var_538; [L1553] SORT_1 var_539 = var_539_arg_0 & var_539_arg_1; [L1554] SORT_1 var_540_arg_0 = var_536; [L1555] SORT_1 var_540_arg_1 = var_539; [L1556] SORT_1 var_540 = var_540_arg_0 | var_540_arg_1; [L1557] SORT_1 var_541_arg_0 = var_514; [L1558] SORT_1 var_541_arg_1 = ~var_540; [L1559] var_541_arg_1 = var_541_arg_1 & mask_SORT_1 [L1560] SORT_1 var_541 = var_541_arg_0 & var_541_arg_1; [L1561] SORT_1 var_542_arg_0 = var_537; [L1562] SORT_1 var_542_arg_1 = var_538; [L1563] SORT_1 var_542 = var_542_arg_0 | var_542_arg_1; [L1564] SORT_1 var_543_arg_0 = var_541; [L1565] SORT_1 var_543_arg_1 = var_542; [L1566] SORT_1 var_543 = var_543_arg_0 & var_543_arg_1; [L1567] SORT_1 var_544_arg_0 = var_481; [L1568] SORT_1 var_544_arg_1 = var_543; [L1569] SORT_1 var_544 = var_544_arg_0 & var_544_arg_1; [L1570] SORT_4 var_545_arg_0 = var_201; [L1571] SORT_4 var_545_arg_1 = var_199; [L1572] SORT_4 var_545 = var_545_arg_0 - var_545_arg_1; [L1573] SORT_4 var_546_arg_0 = var_545; [L1574] SORT_2 var_546 = var_546_arg_0 >> 0; [L1575] SORT_1 var_547_arg_0 = input_198; [L1576] SORT_2 var_547_arg_1 = var_546; [L1577] SORT_2 var_547_arg_2 = input_130; [L1578] EXPR var_547_arg_0 ? var_547_arg_1 : var_547_arg_2 [L1578] SORT_2 var_547 = var_547_arg_0 ? var_547_arg_1 : var_547_arg_2; [L1579] var_547 = var_547 & mask_SORT_2 [L1580] SORT_2 var_548_arg_0 = var_547; [L1581] SORT_2 var_548_arg_1 = state_6; [L1582] SORT_1 var_548 = var_548_arg_0 == var_548_arg_1; [L1583] SORT_1 var_549_arg_0 = var_544; [L1584] SORT_1 var_549_arg_1 = var_548; [L1585] SORT_1 var_549 = var_549_arg_0 & var_549_arg_1; [L1586] SORT_4 var_550_arg_0 = var_345; [L1587] SORT_4 var_550_arg_1 = var_199; [L1588] SORT_4 var_550 = var_550_arg_0 - var_550_arg_1; [L1589] SORT_4 var_551_arg_0 = var_550; [L1590] SORT_2 var_551 = var_551_arg_0 >> 0; [L1591] SORT_1 var_552_arg_0 = input_341; [L1592] SORT_2 var_552_arg_1 = var_551; [L1593] SORT_2 var_552_arg_2 = var_344; [L1594] EXPR var_552_arg_0 ? var_552_arg_1 : var_552_arg_2 [L1594] SORT_2 var_552 = var_552_arg_0 ? var_552_arg_1 : var_552_arg_2; [L1595] var_552 = var_552 & mask_SORT_2 [L1596] SORT_3 var_553_arg_0 = var_200; [L1597] SORT_2 var_553_arg_1 = var_552; [L1598] SORT_4 var_553 = ((SORT_4)var_553_arg_0 << 8) | var_553_arg_1; [L1599] SORT_4 var_554_arg_0 = var_203; [L1600] SORT_4 var_554_arg_1 = var_553; [L1601] SORT_4 var_554 = var_554_arg_0 + var_554_arg_1; [L1602] SORT_4 var_555_arg_0 = var_554; [L1603] SORT_2 var_555 = var_555_arg_0 >> 0; [L1604] SORT_1 var_556_arg_0 = input_350; [L1605] SORT_2 var_556_arg_1 = var_555; [L1606] SORT_2 var_556_arg_2 = var_552; [L1607] EXPR var_556_arg_0 ? var_556_arg_1 : var_556_arg_2 [L1607] SORT_2 var_556 = var_556_arg_0 ? var_556_arg_1 : var_556_arg_2; [L1608] var_556 = var_556 & mask_SORT_2 [L1609] SORT_2 var_557_arg_0 = var_556; [L1610] SORT_2 var_557_arg_1 = state_8; [L1611] SORT_1 var_557 = var_557_arg_0 == var_557_arg_1; [L1612] SORT_1 var_558_arg_0 = var_549; [L1613] SORT_1 var_558_arg_1 = var_557; [L1614] SORT_1 var_558 = var_558_arg_0 & var_558_arg_1; [L1615] SORT_4 var_559_arg_0 = var_359; [L1616] SORT_4 var_559_arg_1 = var_203; [L1617] SORT_4 var_559 = var_559_arg_0 - var_559_arg_1; [L1618] SORT_4 var_560_arg_0 = var_559; [L1619] SORT_2 var_560 = var_560_arg_0 >> 0; [L1620] SORT_1 var_561_arg_0 = input_350; [L1621] SORT_2 var_561_arg_1 = var_560; [L1622] SORT_2 var_561_arg_2 = var_358; [L1623] EXPR var_561_arg_0 ? var_561_arg_1 : var_561_arg_2 [L1623] SORT_2 var_561 = var_561_arg_0 ? var_561_arg_1 : var_561_arg_2; [L1624] var_561 = var_561 & mask_SORT_2 [L1625] SORT_2 var_562_arg_0 = var_561; [L1626] SORT_2 var_562_arg_1 = state_10; [L1627] SORT_1 var_562 = var_562_arg_0 == var_562_arg_1; [L1628] SORT_1 var_563_arg_0 = var_558; [L1629] SORT_1 var_563_arg_1 = var_562; [L1630] SORT_1 var_563 = var_563_arg_0 & var_563_arg_1; [L1631] SORT_4 var_564_arg_0 = var_321; [L1632] SORT_4 var_564_arg_1 = var_199; [L1633] SORT_4 var_564 = var_564_arg_0 - var_564_arg_1; [L1634] SORT_4 var_565_arg_0 = var_564; [L1635] SORT_2 var_565 = var_565_arg_0 >> 0; [L1636] SORT_1 var_566_arg_0 = input_336; [L1637] SORT_2 var_566_arg_1 = var_565; [L1638] SORT_2 var_566_arg_2 = var_320; [L1639] EXPR var_566_arg_0 ? var_566_arg_1 : var_566_arg_2 [L1639] SORT_2 var_566 = var_566_arg_0 ? var_566_arg_1 : var_566_arg_2; [L1640] var_566 = var_566 & mask_SORT_2 [L1641] SORT_3 var_567_arg_0 = var_200; [L1642] SORT_2 var_567_arg_1 = var_566; [L1643] SORT_4 var_567 = ((SORT_4)var_567_arg_0 << 8) | var_567_arg_1; [L1644] SORT_4 var_568_arg_0 = var_199; [L1645] SORT_4 var_568_arg_1 = var_567; [L1646] SORT_4 var_568 = var_568_arg_0 + var_568_arg_1; [L1647] SORT_4 var_569_arg_0 = var_568; [L1648] SORT_2 var_569 = var_569_arg_0 >> 0; [L1649] SORT_1 var_570_arg_0 = input_350; [L1650] SORT_2 var_570_arg_1 = var_569; [L1651] SORT_2 var_570_arg_2 = var_566; [L1652] EXPR var_570_arg_0 ? var_570_arg_1 : var_570_arg_2 [L1652] SORT_2 var_570 = var_570_arg_0 ? var_570_arg_1 : var_570_arg_2; [L1653] var_570 = var_570 & mask_SORT_2 [L1654] SORT_2 var_571_arg_0 = var_570; [L1655] SORT_2 var_571_arg_1 = state_12; [L1656] SORT_1 var_571 = var_571_arg_0 == var_571_arg_1; [L1657] SORT_1 var_572_arg_0 = var_563; [L1658] SORT_1 var_572_arg_1 = var_571; [L1659] SORT_1 var_572 = var_572_arg_0 & var_572_arg_1; [L1660] SORT_4 var_573_arg_0 = var_394; [L1661] SORT_4 var_573_arg_1 = var_199; [L1662] SORT_4 var_573 = var_573_arg_0 - var_573_arg_1; [L1663] SORT_4 var_574_arg_0 = var_573; [L1664] SORT_2 var_574 = var_574_arg_0 >> 0; [L1665] SORT_1 var_575_arg_0 = input_350; [L1666] SORT_2 var_575_arg_1 = var_574; [L1667] SORT_2 var_575_arg_2 = var_393; [L1668] EXPR var_575_arg_0 ? var_575_arg_1 : var_575_arg_2 [L1668] SORT_2 var_575 = var_575_arg_0 ? var_575_arg_1 : var_575_arg_2; [L1669] var_575 = var_575 & mask_SORT_2 [L1670] SORT_2 var_576_arg_0 = var_575; [L1671] SORT_2 var_576_arg_1 = state_14; [L1672] SORT_1 var_576 = var_576_arg_0 == var_576_arg_1; [L1673] SORT_1 var_577_arg_0 = var_572; [L1674] SORT_1 var_577_arg_1 = var_576; [L1675] SORT_1 var_577 = var_577_arg_0 & var_577_arg_1; [L1676] SORT_4 var_578_arg_0 = var_220; [L1677] SORT_4 var_578_arg_1 = var_199; [L1678] SORT_4 var_578 = var_578_arg_0 - var_578_arg_1; [L1679] SORT_4 var_579_arg_0 = var_578; [L1680] SORT_2 var_579 = var_579_arg_0 >> 0; [L1681] SORT_1 var_580_arg_0 = input_215; [L1682] SORT_2 var_580_arg_1 = var_579; [L1683] SORT_2 var_580_arg_2 = var_219; [L1684] EXPR var_580_arg_0 ? var_580_arg_1 : var_580_arg_2 [L1684] SORT_2 var_580 = var_580_arg_0 ? var_580_arg_1 : var_580_arg_2; [L1685] var_580 = var_580 & mask_SORT_2 [L1686] SORT_2 var_581_arg_0 = var_580; [L1687] SORT_2 var_581_arg_1 = state_16; [L1688] SORT_1 var_581 = var_581_arg_0 == var_581_arg_1; [L1689] SORT_1 var_582_arg_0 = var_577; [L1690] SORT_1 var_582_arg_1 = var_581; [L1691] SORT_1 var_582 = var_582_arg_0 & var_582_arg_1; [L1692] SORT_4 var_583_arg_0 = var_291; [L1693] SORT_4 var_583_arg_1 = var_199; [L1694] SORT_4 var_583 = var_583_arg_0 - var_583_arg_1; [L1695] SORT_4 var_584_arg_0 = var_583; [L1696] SORT_2 var_584 = var_584_arg_0 >> 0; [L1697] SORT_1 var_585_arg_0 = input_287; [L1698] SORT_2 var_585_arg_1 = var_584; [L1699] SORT_2 var_585_arg_2 = var_290; [L1700] EXPR var_585_arg_0 ? var_585_arg_1 : var_585_arg_2 [L1700] SORT_2 var_585 = var_585_arg_0 ? var_585_arg_1 : var_585_arg_2; [L1701] var_585 = var_585 & mask_SORT_2 [L1702] SORT_2 var_586_arg_0 = var_585; [L1703] SORT_2 var_586_arg_1 = state_18; [L1704] SORT_1 var_586 = var_586_arg_0 == var_586_arg_1; [L1705] SORT_1 var_587_arg_0 = var_582; [L1706] SORT_1 var_587_arg_1 = var_586; [L1707] SORT_1 var_587 = var_587_arg_0 & var_587_arg_1; [L1708] SORT_4 var_588_arg_0 = var_396; [L1709] SORT_4 var_588_arg_1 = var_199; [L1710] SORT_4 var_588 = var_588_arg_0 - var_588_arg_1; [L1711] SORT_4 var_589_arg_0 = var_588; [L1712] SORT_2 var_589 = var_589_arg_0 >> 0; [L1713] SORT_1 var_590_arg_0 = input_350; [L1714] SORT_2 var_590_arg_1 = var_589; [L1715] SORT_2 var_590_arg_2 = input_144; [L1716] EXPR var_590_arg_0 ? var_590_arg_1 : var_590_arg_2 [L1716] SORT_2 var_590 = var_590_arg_0 ? var_590_arg_1 : var_590_arg_2; [L1717] var_590 = var_590 & mask_SORT_2 [L1718] SORT_2 var_591_arg_0 = var_590; [L1719] SORT_2 var_591_arg_1 = state_20; [L1720] SORT_1 var_591 = var_591_arg_0 == var_591_arg_1; [L1721] SORT_1 var_592_arg_0 = var_587; [L1722] SORT_1 var_592_arg_1 = var_591; [L1723] SORT_1 var_592 = var_592_arg_0 & var_592_arg_1; [L1724] SORT_3 var_593_arg_0 = var_200; [L1725] SORT_2 var_593_arg_1 = input_146; [L1726] SORT_4 var_593 = ((SORT_4)var_593_arg_0 << 8) | var_593_arg_1; [L1727] SORT_4 var_594_arg_0 = var_199; [L1728] SORT_4 var_594_arg_1 = var_593; [L1729] SORT_4 var_594 = var_594_arg_0 + var_594_arg_1; [L1730] SORT_4 var_595_arg_0 = var_594; [L1731] SORT_2 var_595 = var_595_arg_0 >> 0; [L1732] SORT_1 var_596_arg_0 = input_215; [L1733] SORT_2 var_596_arg_1 = var_595; [L1734] SORT_2 var_596_arg_2 = input_146; [L1735] EXPR var_596_arg_0 ? var_596_arg_1 : var_596_arg_2 [L1735] SORT_2 var_596 = var_596_arg_0 ? var_596_arg_1 : var_596_arg_2; [L1736] var_596 = var_596 & mask_SORT_2 [L1737] SORT_3 var_597_arg_0 = var_200; [L1738] SORT_2 var_597_arg_1 = var_596; [L1739] SORT_4 var_597 = ((SORT_4)var_597_arg_0 << 8) | var_597_arg_1; [L1740] SORT_4 var_598_arg_0 = var_199; [L1741] SORT_4 var_598_arg_1 = var_597; [L1742] SORT_4 var_598 = var_598_arg_0 + var_598_arg_1; [L1743] SORT_4 var_599_arg_0 = var_598; [L1744] SORT_2 var_599 = var_599_arg_0 >> 0; [L1745] SORT_1 var_600_arg_0 = input_252; [L1746] SORT_2 var_600_arg_1 = var_599; [L1747] SORT_2 var_600_arg_2 = var_596; [L1748] EXPR var_600_arg_0 ? var_600_arg_1 : var_600_arg_2 [L1748] SORT_2 var_600 = var_600_arg_0 ? var_600_arg_1 : var_600_arg_2; [L1749] var_600 = var_600 & mask_SORT_2 [L1750] SORT_3 var_601_arg_0 = var_200; [L1751] SORT_2 var_601_arg_1 = var_600; [L1752] SORT_4 var_601 = ((SORT_4)var_601_arg_0 << 8) | var_601_arg_1; [L1753] SORT_4 var_602_arg_0 = var_199; [L1754] SORT_4 var_602_arg_1 = var_601; [L1755] SORT_4 var_602 = var_602_arg_0 + var_602_arg_1; [L1756] SORT_4 var_603_arg_0 = var_602; [L1757] SORT_2 var_603 = var_603_arg_0 >> 0; [L1758] SORT_1 var_604_arg_0 = input_262; [L1759] SORT_2 var_604_arg_1 = var_603; [L1760] SORT_2 var_604_arg_2 = var_600; [L1761] EXPR var_604_arg_0 ? var_604_arg_1 : var_604_arg_2 [L1761] SORT_2 var_604 = var_604_arg_0 ? var_604_arg_1 : var_604_arg_2; [L1762] var_604 = var_604 & mask_SORT_2 [L1763] SORT_3 var_605_arg_0 = var_200; [L1764] SORT_2 var_605_arg_1 = var_604; [L1765] SORT_4 var_605 = ((SORT_4)var_605_arg_0 << 8) | var_605_arg_1; [L1766] SORT_4 var_606_arg_0 = var_199; [L1767] SORT_4 var_606_arg_1 = var_605; [L1768] SORT_4 var_606 = var_606_arg_0 + var_606_arg_1; [L1769] SORT_4 var_607_arg_0 = var_606; [L1770] SORT_2 var_607 = var_607_arg_0 >> 0; [L1771] SORT_1 var_608_arg_0 = input_306; [L1772] SORT_2 var_608_arg_1 = var_607; [L1773] SORT_2 var_608_arg_2 = var_604; [L1774] EXPR var_608_arg_0 ? var_608_arg_1 : var_608_arg_2 [L1774] SORT_2 var_608 = var_608_arg_0 ? var_608_arg_1 : var_608_arg_2; [L1775] var_608 = var_608 & mask_SORT_2 [L1776] SORT_3 var_609_arg_0 = var_200; [L1777] SORT_2 var_609_arg_1 = var_608; [L1778] SORT_4 var_609 = ((SORT_4)var_609_arg_0 << 8) | var_609_arg_1; [L1779] SORT_4 var_610_arg_0 = var_199; [L1780] SORT_4 var_610_arg_1 = var_609; [L1781] SORT_4 var_610 = var_610_arg_0 + var_610_arg_1; [L1782] SORT_4 var_611_arg_0 = var_610; [L1783] SORT_2 var_611 = var_611_arg_0 >> 0; [L1784] SORT_1 var_612_arg_0 = input_316; [L1785] SORT_2 var_612_arg_1 = var_611; [L1786] SORT_2 var_612_arg_2 = var_608; [L1787] EXPR var_612_arg_0 ? var_612_arg_1 : var_612_arg_2 [L1787] SORT_2 var_612 = var_612_arg_0 ? var_612_arg_1 : var_612_arg_2; [L1788] var_612 = var_612 & mask_SORT_2 [L1789] SORT_2 var_613_arg_0 = var_612; [L1790] SORT_2 var_613_arg_1 = state_22; [L1791] SORT_1 var_613 = var_613_arg_0 == var_613_arg_1; [L1792] SORT_1 var_614_arg_0 = var_592; [L1793] SORT_1 var_614_arg_1 = var_613; [L1794] SORT_1 var_614 = var_614_arg_0 & var_614_arg_1; [L1795] SORT_4 var_615_arg_0 = var_411; [L1796] SORT_4 var_615_arg_1 = var_203; [L1797] SORT_4 var_615 = var_615_arg_0 - var_615_arg_1; [L1798] SORT_4 var_616_arg_0 = var_615; [L1799] SORT_2 var_616 = var_616_arg_0 >> 0; [L1800] SORT_1 var_617_arg_0 = input_350; [L1801] SORT_2 var_617_arg_1 = var_616; [L1802] SORT_2 var_617_arg_2 = var_410; [L1803] EXPR var_617_arg_0 ? var_617_arg_1 : var_617_arg_2 [L1803] SORT_2 var_617 = var_617_arg_0 ? var_617_arg_1 : var_617_arg_2; [L1804] var_617 = var_617 & mask_SORT_2 [L1805] SORT_2 var_618_arg_0 = var_617; [L1806] SORT_2 var_618_arg_1 = state_24; [L1807] SORT_1 var_618 = var_618_arg_0 == var_618_arg_1; [L1808] SORT_1 var_619_arg_0 = var_614; [L1809] SORT_1 var_619_arg_1 = var_618; [L1810] SORT_1 var_619 = var_619_arg_0 & var_619_arg_1; [L1811] SORT_4 var_620_arg_0 = var_331; [L1812] SORT_4 var_620_arg_1 = var_199; [L1813] SORT_4 var_620 = var_620_arg_0 - var_620_arg_1; [L1814] SORT_4 var_621_arg_0 = var_620; [L1815] SORT_2 var_621 = var_621_arg_0 >> 0; [L1816] SORT_1 var_622_arg_0 = input_326; [L1817] SORT_2 var_622_arg_1 = var_621; [L1818] SORT_2 var_622_arg_2 = var_330; [L1819] EXPR var_622_arg_0 ? var_622_arg_1 : var_622_arg_2 [L1819] SORT_2 var_622 = var_622_arg_0 ? var_622_arg_1 : var_622_arg_2; [L1820] var_622 = var_622 & mask_SORT_2 [L1821] SORT_3 var_623_arg_0 = var_200; [L1822] SORT_2 var_623_arg_1 = var_622; [L1823] SORT_4 var_623 = ((SORT_4)var_623_arg_0 << 8) | var_623_arg_1; [L1824] SORT_4 var_624_arg_0 = var_199; [L1825] SORT_4 var_624_arg_1 = var_623; [L1826] SORT_4 var_624 = var_624_arg_0 + var_624_arg_1; [L1827] SORT_4 var_625_arg_0 = var_624; [L1828] SORT_2 var_625 = var_625_arg_0 >> 0; [L1829] SORT_1 var_626_arg_0 = input_350; [L1830] SORT_2 var_626_arg_1 = var_625; [L1831] SORT_2 var_626_arg_2 = var_622; [L1832] EXPR var_626_arg_0 ? var_626_arg_1 : var_626_arg_2 [L1832] SORT_2 var_626 = var_626_arg_0 ? var_626_arg_1 : var_626_arg_2; [L1833] var_626 = var_626 & mask_SORT_2 [L1834] SORT_2 var_627_arg_0 = var_626; [L1835] SORT_2 var_627_arg_1 = state_26; [L1836] SORT_1 var_627 = var_627_arg_0 == var_627_arg_1; [L1837] SORT_1 var_628_arg_0 = var_619; [L1838] SORT_1 var_628_arg_1 = var_627; [L1839] SORT_1 var_628 = var_628_arg_0 & var_628_arg_1; [L1840] SORT_3 var_629_arg_0 = var_200; [L1841] SORT_2 var_629_arg_1 = input_152; [L1842] SORT_4 var_629 = ((SORT_4)var_629_arg_0 << 8) | var_629_arg_1; [L1843] var_629 = var_629 & mask_SORT_4 [L1844] SORT_4 var_630_arg_0 = var_199; [L1845] SORT_4 var_630_arg_1 = var_629; [L1846] SORT_4 var_630 = var_630_arg_0 + var_630_arg_1; [L1847] SORT_4 var_631_arg_0 = var_630; [L1848] SORT_2 var_631 = var_631_arg_0 >> 0; [L1849] SORT_1 var_632_arg_0 = input_341; [L1850] SORT_2 var_632_arg_1 = var_631; [L1851] SORT_2 var_632_arg_2 = input_152; [L1852] EXPR var_632_arg_0 ? var_632_arg_1 : var_632_arg_2 [L1852] SORT_2 var_632 = var_632_arg_0 ? var_632_arg_1 : var_632_arg_2; [L1853] var_632 = var_632 & mask_SORT_2 [L1854] SORT_2 var_633_arg_0 = var_632; [L1855] SORT_2 var_633_arg_1 = state_28; [L1856] SORT_1 var_633 = var_633_arg_0 == var_633_arg_1; [L1857] SORT_1 var_634_arg_0 = var_628; [L1858] SORT_1 var_634_arg_1 = var_633; [L1859] SORT_1 var_634 = var_634_arg_0 & var_634_arg_1; [L1860] SORT_1 var_635_arg_0 = input_154; [L1861] SORT_1 var_635_arg_1 = state_31; [L1862] SORT_1 var_635 = var_635_arg_0 == var_635_arg_1; [L1863] SORT_1 var_636_arg_0 = var_634; [L1864] SORT_1 var_636_arg_1 = var_635; [L1865] SORT_1 var_636 = var_636_arg_0 & var_636_arg_1; [L1866] SORT_1 var_637_arg_0 = input_156; [L1867] SORT_1 var_637_arg_1 = state_33; [L1868] SORT_1 var_637 = var_637_arg_0 == var_637_arg_1; [L1869] SORT_1 var_638_arg_0 = var_636; [L1870] SORT_1 var_638_arg_1 = var_637; [L1871] SORT_1 var_638 = var_638_arg_0 & var_638_arg_1; [L1872] SORT_1 var_639_arg_0 = var_488; [L1873] SORT_1 var_639_arg_1 = state_35; [L1874] SORT_1 var_639 = var_639_arg_0 == var_639_arg_1; [L1875] SORT_1 var_640_arg_0 = var_638; [L1876] SORT_1 var_640_arg_1 = var_639; [L1877] SORT_1 var_640 = var_640_arg_0 & var_640_arg_1; [L1878] SORT_1 var_641_arg_0 = var_486; [L1879] SORT_1 var_641_arg_1 = state_37; [L1880] SORT_1 var_641 = var_641_arg_0 == var_641_arg_1; [L1881] SORT_1 var_642_arg_0 = var_640; [L1882] SORT_1 var_642_arg_1 = var_641; [L1883] SORT_1 var_642 = var_642_arg_0 & var_642_arg_1; [L1884] SORT_1 var_643_arg_0 = var_490; [L1885] SORT_1 var_643_arg_1 = state_39; [L1886] SORT_1 var_643 = var_643_arg_0 == var_643_arg_1; [L1887] SORT_1 var_644_arg_0 = var_642; [L1888] SORT_1 var_644_arg_1 = var_643; [L1889] SORT_1 var_644 = var_644_arg_0 & var_644_arg_1; [L1890] SORT_1 var_645_arg_0 = var_494; [L1891] SORT_1 var_645_arg_1 = state_41; [L1892] SORT_1 var_645 = var_645_arg_0 == var_645_arg_1; [L1893] SORT_1 var_646_arg_0 = var_644; [L1894] SORT_1 var_646_arg_1 = var_645; [L1895] SORT_1 var_646 = var_646_arg_0 & var_646_arg_1; [L1896] SORT_1 var_647_arg_0 = input_166; [L1897] SORT_1 var_647_arg_1 = state_43; [L1898] SORT_1 var_647 = var_647_arg_0 == var_647_arg_1; [L1899] SORT_1 var_648_arg_0 = var_646; [L1900] SORT_1 var_648_arg_1 = var_647; [L1901] SORT_1 var_648 = var_648_arg_0 & var_648_arg_1; [L1902] SORT_1 var_649_arg_0 = input_168; [L1903] SORT_1 var_649_arg_1 = state_45; [L1904] SORT_1 var_649 = var_649_arg_0 == var_649_arg_1; [L1905] SORT_1 var_650_arg_0 = var_648; [L1906] SORT_1 var_650_arg_1 = var_649; [L1907] SORT_1 var_650 = var_650_arg_0 & var_650_arg_1; [L1908] SORT_1 var_651_arg_0 = var_504; [L1909] SORT_1 var_651_arg_1 = state_47; [L1910] SORT_1 var_651 = var_651_arg_0 == var_651_arg_1; [L1911] SORT_1 var_652_arg_0 = var_650; [L1912] SORT_1 var_652_arg_1 = var_651; [L1913] SORT_1 var_652 = var_652_arg_0 & var_652_arg_1; [L1914] SORT_1 var_653_arg_0 = var_508; [L1915] SORT_1 var_653_arg_1 = state_49; [L1916] SORT_1 var_653 = var_653_arg_0 == var_653_arg_1; [L1917] SORT_1 var_654_arg_0 = var_652; [L1918] SORT_1 var_654_arg_1 = var_653; [L1919] SORT_1 var_654 = var_654_arg_0 & var_654_arg_1; [L1920] SORT_1 var_655_arg_0 = var_517; [L1921] SORT_1 var_655_arg_1 = state_51; [L1922] SORT_1 var_655 = var_655_arg_0 == var_655_arg_1; [L1923] SORT_1 var_656_arg_0 = var_654; [L1924] SORT_1 var_656_arg_1 = var_655; [L1925] SORT_1 var_656 = var_656_arg_0 & var_656_arg_1; [L1926] SORT_1 var_657_arg_0 = var_515; [L1927] SORT_1 var_657_arg_1 = state_53; [L1928] SORT_1 var_657 = var_657_arg_0 == var_657_arg_1; [L1929] SORT_1 var_658_arg_0 = var_656; [L1930] SORT_1 var_658_arg_1 = var_657; [L1931] SORT_1 var_658 = var_658_arg_0 & var_658_arg_1; [L1932] SORT_1 var_659_arg_0 = var_519; [L1933] SORT_1 var_659_arg_1 = state_55; [L1934] SORT_1 var_659 = var_659_arg_0 == var_659_arg_1; [L1935] SORT_1 var_660_arg_0 = var_658; [L1936] SORT_1 var_660_arg_1 = var_659; [L1937] SORT_1 var_660 = var_660_arg_0 & var_660_arg_1; [L1938] SORT_1 var_661_arg_0 = var_523; [L1939] SORT_1 var_661_arg_1 = state_57; [L1940] SORT_1 var_661 = var_661_arg_0 == var_661_arg_1; [L1941] SORT_1 var_662_arg_0 = var_660; [L1942] SORT_1 var_662_arg_1 = var_661; [L1943] SORT_1 var_662 = var_662_arg_0 & var_662_arg_1; [L1944] SORT_1 var_663_arg_0 = input_182; [L1945] SORT_1 var_663_arg_1 = state_59; [L1946] SORT_1 var_663 = var_663_arg_0 == var_663_arg_1; [L1947] SORT_1 var_664_arg_0 = var_662; [L1948] SORT_1 var_664_arg_1 = var_663; [L1949] SORT_1 var_664 = var_664_arg_0 & var_664_arg_1; [L1950] SORT_1 var_665_arg_0 = input_184; [L1951] SORT_1 var_665_arg_1 = state_61; [L1952] SORT_1 var_665 = var_665_arg_0 == var_665_arg_1; [L1953] SORT_1 var_666_arg_0 = var_664; [L1954] SORT_1 var_666_arg_1 = var_665; [L1955] SORT_1 var_666 = var_666_arg_0 & var_666_arg_1; [L1956] SORT_1 var_667_arg_0 = var_533; [L1957] SORT_1 var_667_arg_1 = state_63; [L1958] SORT_1 var_667 = var_667_arg_0 == var_667_arg_1; [L1959] SORT_1 var_668_arg_0 = var_666; [L1960] SORT_1 var_668_arg_1 = var_667; [L1961] SORT_1 var_668 = var_668_arg_0 & var_668_arg_1; [L1962] SORT_1 var_669_arg_0 = var_537; [L1963] SORT_1 var_669_arg_1 = state_65; [L1964] SORT_1 var_669 = var_669_arg_0 == var_669_arg_1; [L1965] SORT_1 var_670_arg_0 = var_668; [L1966] SORT_1 var_670_arg_1 = var_669; [L1967] SORT_1 var_670 = var_670_arg_0 & var_670_arg_1; [L1968] SORT_1 var_671_arg_0 = input_190; [L1969] SORT_1 var_671_arg_1 = state_67; [L1970] SORT_1 var_671 = var_671_arg_0 == var_671_arg_1; [L1971] SORT_1 var_672_arg_0 = var_670; [L1972] SORT_1 var_672_arg_1 = var_671; [L1973] SORT_1 var_672 = var_672_arg_0 & var_672_arg_1; [L1974] SORT_1 var_673_arg_0 = input_192; [L1975] SORT_1 var_673_arg_1 = state_69; [L1976] SORT_1 var_673 = var_673_arg_0 == var_673_arg_1; [L1977] SORT_1 var_674_arg_0 = var_672; [L1978] SORT_1 var_674_arg_1 = var_673; [L1979] SORT_1 var_674 = var_674_arg_0 & var_674_arg_1; [L1980] SORT_1 var_675_arg_0 = input_194; [L1981] SORT_1 var_675_arg_1 = state_71; [L1982] SORT_1 var_675 = var_675_arg_0 == var_675_arg_1; [L1983] SORT_1 var_676_arg_0 = var_674; [L1984] SORT_1 var_676_arg_1 = var_675; [L1985] SORT_1 var_676 = var_676_arg_0 & var_676_arg_1; [L1986] SORT_1 var_677_arg_0 = var_676; [L1987] SORT_1 var_677_arg_1 = state_75; [L1988] SORT_1 var_677 = var_677_arg_0 & var_677_arg_1; [L1989] SORT_4 var_679_arg_0 = var_629; [L1990] SORT_4 var_679_arg_1 = var_678; [L1991] SORT_1 var_679 = var_679_arg_0 <= var_679_arg_1; [L1992] SORT_1 var_680_arg_0 = state_73; [L1993] SORT_1 var_680_arg_1 = var_677; [L1994] SORT_1 var_680_arg_2 = ~var_679; [L1995] var_680_arg_2 = var_680_arg_2 & mask_SORT_1 [L1996] EXPR var_680_arg_0 ? var_680_arg_1 : var_680_arg_2 [L1996] SORT_1 var_680 = var_680_arg_0 ? var_680_arg_1 : var_680_arg_2; [L1997] SORT_1 next_681_arg_1 = var_680; [L1999] state_6 = next_131_arg_1 [L2000] state_8 = next_133_arg_1 [L2001] state_10 = next_135_arg_1 [L2002] state_12 = next_137_arg_1 [L2003] state_14 = next_139_arg_1 [L2004] state_16 = next_141_arg_1 [L2005] state_18 = next_143_arg_1 [L2006] state_20 = next_145_arg_1 [L2007] state_22 = next_147_arg_1 [L2008] state_24 = next_149_arg_1 [L2009] state_26 = next_151_arg_1 [L2010] state_28 = next_153_arg_1 [L2011] state_31 = next_155_arg_1 [L2012] state_33 = next_157_arg_1 [L2013] state_35 = next_159_arg_1 [L2014] state_37 = next_161_arg_1 [L2015] state_39 = next_163_arg_1 [L2016] state_41 = next_165_arg_1 [L2017] state_43 = next_167_arg_1 [L2018] state_45 = next_169_arg_1 [L2019] state_47 = next_171_arg_1 [L2020] state_49 = next_173_arg_1 [L2021] state_51 = next_175_arg_1 [L2022] state_53 = next_177_arg_1 [L2023] state_55 = next_179_arg_1 [L2024] state_57 = next_181_arg_1 [L2025] state_59 = next_183_arg_1 [L2026] state_61 = next_185_arg_1 [L2027] state_63 = next_187_arg_1 [L2028] state_65 = next_189_arg_1 [L2029] state_67 = next_191_arg_1 [L2030] state_69 = next_193_arg_1 [L2031] state_71 = next_195_arg_1 [L2032] state_73 = next_197_arg_1 [L2033] state_75 = next_681_arg_1 VAL [bad_129_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_76_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_130=3, input_132=4, input_134=4, input_136=12, input_138=2, input_140=0, input_142=0, input_144=15, input_146=0, input_148=10, input_150=10, input_152=0, input_154=1, input_156=1, input_158=1, input_160=1, input_162=1, input_164=1, input_166=1, input_168=1, input_170=1, input_172=1, input_174=1, input_176=0, input_178=1, input_180=1, input_182=0, input_184=1, input_186=1, input_188=1, input_190=1, input_192=1, input_194=1, input_198=1, input_215=1, input_231=0, input_249=13, input_252=1, input_262=1, input_272=0, input_282=0, input_287=1, input_303=48, input_306=1, input_316=1, input_326=1, input_336=0, input_341=0, input_350=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, next_131_arg_1=3, next_133_arg_1=4, next_135_arg_1=4, next_137_arg_1=12, next_139_arg_1=2, next_141_arg_1=0, next_143_arg_1=0, next_145_arg_1=15, next_147_arg_1=0, next_149_arg_1=10, next_151_arg_1=10, next_153_arg_1=0, next_155_arg_1=1, next_157_arg_1=1, next_159_arg_1=1, next_161_arg_1=1, next_163_arg_1=1, next_165_arg_1=1, next_167_arg_1=1, next_169_arg_1=1, next_171_arg_1=1, next_173_arg_1=1, next_175_arg_1=1, next_177_arg_1=0, next_179_arg_1=1, next_181_arg_1=1, next_183_arg_1=0, next_185_arg_1=1, next_187_arg_1=1, next_189_arg_1=1, next_191_arg_1=1, next_193_arg_1=1, next_195_arg_1=1, next_197_arg_1=1, next_681_arg_1=1, state_10=4, state_12=12, state_14=2, state_16=0, state_18=0, state_20=15, state_22=0, state_24=10, state_26=10, state_28=0, state_31=1, state_33=1, state_35=1, state_37=1, state_39=1, state_41=1, state_43=1, state_45=1, state_47=1, state_49=1, state_51=1, state_53=0, state_55=1, state_57=1, state_59=0, state_6=3, state_61=1, state_63=1, state_65=1, state_67=1, state_69=1, state_71=1, state_73=1, state_75=1, state_8=4, var_100=4, var_101=0, var_101_arg_0=4, var_101_arg_1=0, var_102=0, var_102_arg_0=0, var_102_arg_1=0, var_103=0, var_103_arg_0=4, var_103_arg_1=0, var_104=0, var_104_arg_0=0, var_104_arg_1=0, var_105=12, var_106=0, var_106_arg_0=12, var_106_arg_1=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=2, var_109=0, var_109_arg_0=2, var_109_arg_1=0, var_110=0, var_110_arg_0=0, var_110_arg_1=0, var_111=0, var_112=1, var_112_arg_0=0, var_112_arg_1=0, var_113=0, var_113_arg_0=0, var_113_arg_1=1, var_114=1, var_114_arg_0=0, var_114_arg_1=0, var_115=0, var_115_arg_0=0, var_115_arg_1=1, var_116=15, var_117=0, var_117_arg_0=15, var_117_arg_1=0, var_118=0, var_118_arg_0=0, var_118_arg_1=0, var_119=1, var_119_arg_0=0, var_119_arg_1=0, var_120=0, var_120_arg_0=0, var_120_arg_1=1, var_121=10, var_122=0, var_122_arg_0=10, var_122_arg_1=0, var_123=0, var_123_arg_0=0, var_123_arg_1=0, var_124=0, var_124_arg_0=10, var_124_arg_1=0, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_126=1, var_126_arg_0=0, var_126_arg_1=0, var_127=0, var_127_arg_0=0, var_127_arg_1=1, var_128=0, var_128_arg_0=0, var_128_arg_1=0, var_196=1, var_199=1, var_200=0, var_201=47, var_201_arg_0=0, var_201_arg_1=3, var_202=1, var_202_arg_0=1, var_202_arg_1=47, var_203=2, var_204=258, var_204_arg_0=0, var_204_arg_1=4, var_205=1, var_205_arg_0=2, var_205_arg_1=258, var_206=1, var_206_arg_0=1, var_206_arg_1=1, var_207=4294967046, var_207_arg_0=0, var_207_arg_1=4, var_208=1, var_208_arg_0=2, var_208_arg_1=4294967046, var_209=1, var_209_arg_0=1, var_209_arg_1=1, var_210=14, var_210_arg_0=0, var_210_arg_1=12, var_211=1, var_211_arg_0=2, var_211_arg_1=14, var_212=1, var_212_arg_0=1, var_212_arg_1=1, var_213=1, var_213_arg_0=1, var_213_arg_1=1, var_214=1, var_214_arg_0=1, var_214_arg_1=1, var_216=0, var_216_arg_0=0, var_216_arg_1=0, var_217=2, var_217_arg_0=2, var_217_arg_1=0, var_218=2, var_218_arg_0=2, var_219=66, var_219_arg_0=1, var_219_arg_1=2, var_219_arg_2=0, var_220=323, var_220_arg_0=0, var_220_arg_1=66, var_221=1, var_221_arg_0=1, var_221_arg_1=323, var_222=12, var_222_arg_0=14, var_222_arg_1=2, var_223=12, var_223_arg_0=12, var_224=255, var_224_arg_0=1, var_224_arg_1=12, var_224_arg_2=12, var_225=0, var_225_arg_0=0, var_225_arg_1=255, var_226=0, var_226_arg_0=1, var_226_arg_1=0, var_227=0, var_227_arg_0=1, var_227_arg_1=0, var_228=0, var_228_arg_0=1, var_228_arg_1=0, var_229=1, var_229_arg_0=1, var_229_arg_1=0, var_230=1, var_230_arg_0=1, var_230_arg_1=1, var_232=0, var_232_arg_0=0, var_232_arg_1=0, var_233=1, var_233_arg_0=1, var_233_arg_1=0, var_234=1, var_234_arg_0=1, var_235=1, var_235_arg_0=1, var_235_arg_1=1, var_235_arg_2=0, var_236=0, var_236_arg_0=0, var_236_arg_1=1, var_237=0, var_237_arg_0=1, var_237_arg_1=0, var_238=4294967048, var_238_arg_0=0, var_238_arg_1=10, var_239=4294967050, var_239_arg_0=2, var_239_arg_1=4294967048, var_240=10, var_240_arg_0=4294967050, var_241=10, var_241_arg_0=1, var_241_arg_1=10, var_241_arg_2=10, var_242=9, var_242_arg_0=0, var_242_arg_1=10, var_243=1, var_243_arg_0=1, var_243_arg_1=9, var_244=0, var_244_arg_0=0, var_244_arg_1=1, var_245=0, var_245_arg_0=1, var_245_arg_1=0, var_246=1, var_246_arg_0=1, var_246_arg_1=0, var_247=1, var_247_arg_0=1, var_247_arg_1=1, var_248=1, var_248_arg_0=1, var_248_arg_1=0, var_250=1, var_250_arg_0=1, var_250_arg_1=1, var_251=1, var_251_arg_0=1, var_251_arg_1=1, var_253=3, var_253_arg_0=1, var_253_arg_1=13, var_254=4294967295, var_254_arg_0=0, var_254_arg_1=1, var_255=255, var_255_arg_0=4294967295, var_256=255, var_256_arg_0=1, var_256_arg_1=255, var_256_arg_2=255, var_257=256, var_257_arg_0=0, var_257_arg_1=255, var_258=1, var_258_arg_0=1, var_258_arg_1=256, var_259=1, var_259_arg_0=3, var_259_arg_1=1, var_260=1, var_260_arg_0=1, var_260_arg_1=1, var_261=1, var_261_arg_0=1, var_261_arg_1=1, var_263=1, var_263_arg_0=1, var_263_arg_1=1, var_264=255, var_264_arg_0=256, var_264_arg_1=1, var_265=255, var_265_arg_0=255, var_266=255, var_266_arg_0=1, var_266_arg_1=255, var_266_arg_2=255, var_267=256, var_267_arg_0=0, var_267_arg_1=255, var_268=1, var_268_arg_0=1, var_268_arg_1=256, var_269=1, var_269_arg_0=1, var_269_arg_1=1, var_270=1, var_270_arg_0=0, var_270_arg_1=1, var_271=1, var_271_arg_0=1, var_271_arg_1=1, var_273=1, var_273_arg_0=1, var_273_arg_1=1, var_274=8, var_274_arg_0=9, var_274_arg_1=1, var_275=8, var_275_arg_0=8, var_276=5, var_276_arg_0=0, var_276_arg_1=8, var_276_arg_2=10, var_277=0, var_277_arg_0=0, var_277_arg_1=5, var_278=0, var_278_arg_0=1, var_278_arg_1=0, var_279=0, var_279_arg_0=1, var_279_arg_1=0, var_280=0, var_280_arg_0=0, var_280_arg_1=0, var_281=0, var_281_arg_0=1, var_281_arg_1=0, var_283=1, var_283_arg_0=1, var_283_arg_1=0, var_284=1, var_284_arg_0=1, var_284_arg_1=1, var_285=1, var_285_arg_0=1, var_285_arg_1=1, var_286=0, var_286_arg_0=0, var_286_arg_1=1, var_288=4294967295, var_288_arg_0=0, var_288_arg_1=1, var_289=255, var_289_arg_0=4294967295, var_290=1, var_290_arg_0=0, var_290_arg_1=255, var_290_arg_2=1, var_291=0, var_291_arg_0=0, var_291_arg_1=1, var_292=0, var_292_arg_0=1, var_292_arg_1=0, var_293=4294967295, var_293_arg_0=0, var_293_arg_1=1, var_294=255, var_294_arg_0=4294967295, var_295=34, var_295_arg_0=0, var_295_arg_1=255, var_295_arg_2=5, var_296=4294966307, var_296_arg_0=0, var_296_arg_1=34, var_297=1, var_297_arg_0=1, var_297_arg_1=4294966307, var_298=0, var_298_arg_0=0, var_298_arg_1=1, var_299=0, var_299_arg_0=1, var_299_arg_1=0, var_30=0, var_300=1, var_300_arg_0=1, var_300_arg_1=0, var_301=0, var_301_arg_0=0, var_301_arg_1=1, var_302=1, var_302_arg_0=0, var_302_arg_1=1, var_304=1, var_304_arg_0=1, var_304_arg_1=1, var_305=0, var_305_arg_0=0, var_305_arg_1=1, var_307=1, var_307_arg_0=1, var_307_arg_1=48, var_308=255, var_308_arg_0=256, var_308_arg_1=1, var_309=255, var_309_arg_0=255, var_310=245, var_310_arg_0=0, var_310_arg_1=255, var_310_arg_2=255, var_311=4294967286, var_311_arg_0=0, var_311_arg_1=245, var_312=1, var_312_arg_0=1, var_312_arg_1=4294967286, var_313=1, var_313_arg_0=1, var_313_arg_1=1, var_314=1, var_314_arg_0=1, var_314_arg_1=1, var_315=0, var_315_arg_0=0, var_315_arg_1=1, var_317=1, var_317_arg_0=1, var_317_arg_1=1, var_318=4294967285, var_318_arg_0=4294967286, var_318_arg_1=1, var_319=245, var_319_arg_0=4294967285, var_320=1, var_320_arg_0=1, var_320_arg_1=245, var_320_arg_2=245, var_321=0, var_321_arg_0=0, var_321_arg_1=1, var_322=0, var_322_arg_0=1, var_322_arg_1=0, var_323=0, var_323_arg_0=1, var_323_arg_1=0, var_324=0, var_324_arg_0=0, var_324_arg_1=0, var_325=0, var_325_arg_0=0, var_325_arg_1=0, var_327=1, var_327_arg_0=1, var_327_arg_1=1, var_328=4294966306, var_328_arg_0=4294966307, var_328_arg_1=1, var_329=34, var_329_arg_0=4294966306, var_330=0, var_330_arg_0=1, var_330_arg_1=34, var_330_arg_2=34, var_331=0, var_331_arg_0=0, var_331_arg_1=0, var_332=0, var_332_arg_0=1, var_332_arg_1=0, var_333=0, var_333_arg_0=1, var_333_arg_1=0, var_334=1, var_334_arg_0=1, var_334_arg_1=0, var_335=0, var_335_arg_0=0, var_335_arg_1=1, var_337=1, var_337_arg_0=1, var_337_arg_1=1, var_338=0, var_338_arg_0=0, var_338_arg_1=1, var_339=1, var_339_arg_0=1, var_339_arg_1=0, var_340=0, var_340_arg_0=0, var_340_arg_1=1, var_342=260, var_342_arg_0=2, var_342_arg_1=258, var_343=4, var_343_arg_0=260, var_344=12, var_344_arg_0=1, var_344_arg_1=4, var_344_arg_2=4, var_345=13, var_345_arg_0=0, var_345_arg_1=12, var_346=1, var_346_arg_0=1, var_346_arg_1=13, var_347=1, var_347_arg_0=1, var_347_arg_1=1, var_348=1, var_348_arg_0=1, var_348_arg_1=1, var_349=0, var_349_arg_0=0, var_349_arg_1=1, var_351=1, var_351_arg_0=1, var_351_arg_1=1, var_352=4294967044, var_352_arg_0=4294967046, var_352_arg_1=2, var_353=4, var_353_arg_0=4294967044, var_354=255, var_354_arg_0=1, var_354_arg_1=4, var_354_arg_2=4, var_355=255, var_355_arg_0=0, var_355_arg_1=255, var_356=256, var_356_arg_0=1, var_356_arg_1=255, var_357=0, var_357_arg_0=256, var_358=255, var_358_arg_0=0, var_358_arg_1=0, var_358_arg_2=255, var_359=0, var_359_arg_0=0, var_359_arg_1=255, var_360=0, var_360_arg_0=2, var_360_arg_1=0, var_361=0, var_361_arg_0=1, var_361_arg_1=0, var_362=4294966272, var_362_arg_0=0, var_362_arg_1=2, var_363=4294966274, var_363_arg_0=2, var_363_arg_1=4294966272, var_364=2, var_364_arg_0=4294966274, var_365=73, var_365_arg_0=1, var_365_arg_1=2, var_365_arg_2=2, var_366=4294966599, var_366_arg_0=0, var_366_arg_1=73, var_367=4294966600, var_367_arg_0=1, var_367_arg_1=4294966599, var_368=72, var_368_arg_0=4294966600, var_369=2, var_369_arg_0=1, var_369_arg_1=72, var_369_arg_2=73, var_370=1, var_370_arg_0=0, var_370_arg_1=2, var_371=2, var_371_arg_0=1, var_371_arg_1=1, var_372=2, var_372_arg_0=2, var_373=61, var_373_arg_0=1, var_373_arg_1=2, var_373_arg_2=2, var_374=60, var_374_arg_0=0, var_374_arg_1=61, var_375=61, var_375_arg_0=1, var_375_arg_1=60, var_376=61, var_376_arg_0=61, var_377=0, var_377_arg_0=1, var_377_arg_1=61, var_377_arg_2=61, var_378=0, var_378_arg_0=0, var_378_arg_1=0, var_379=1, var_379_arg_0=1, var_379_arg_1=0, var_380=1, var_380_arg_0=1, var_381=0, var_381_arg_0=0, var_381_arg_1=1, var_381_arg_2=0, var_382=0, var_382_arg_0=0, var_382_arg_1=0, var_383=1, var_383_arg_0=1, var_383_arg_1=0, var_384=1, var_384_arg_0=1, var_385=1, var_385_arg_0=1, var_385_arg_1=1, var_385_arg_2=0, var_386=1, var_386_arg_0=0, var_386_arg_1=1, var_387=2, var_387_arg_0=1, var_387_arg_1=1, var_388=2, var_388_arg_0=2, var_389=0, var_389_arg_0=1, var_389_arg_1=2, var_389_arg_2=1, var_390=0, var_390_arg_0=0, var_390_arg_1=0, var_391=1, var_391_arg_0=1, var_391_arg_1=0, var_392=1, var_392_arg_0=1, var_393=0, var_393_arg_0=0, var_393_arg_1=1, var_393_arg_2=0, var_394=0, var_394_arg_0=0, var_394_arg_1=0, var_395=0, var_395_arg_0=1, var_395_arg_1=0, var_396=4294966800, var_396_arg_0=0, var_396_arg_1=15, var_397=1, var_397_arg_0=1, var_397_arg_1=4294966800, var_398=0, var_398_arg_0=0, var_398_arg_1=1, var_399=4294966536, var_399_arg_0=0, var_399_arg_1=10, var_400=4294966538, var_400_arg_0=2, var_400_arg_1=4294966536, var_401=10, var_401_arg_0=4294966538, var_402=10, var_402_arg_0=1, var_402_arg_1=10, var_402_arg_2=10, var_403=4294966793, var_403_arg_0=0, var_403_arg_1=10, var_404=4294966794, var_404_arg_0=1, var_404_arg_1=4294966793, var_405=10, var_405_arg_0=4294966794, var_406=2, var_406_arg_0=1, var_406_arg_1=10, var_406_arg_2=10, var_407=1, var_407_arg_0=0, var_407_arg_1=2, var_408=2, var_408_arg_0=1, var_408_arg_1=1, var_409=2, var_409_arg_0=2, var_410=1, var_410_arg_0=1, var_410_arg_1=2, var_410_arg_2=2, var_411=3, var_411_arg_0=0, var_411_arg_1=1, var_412=1, var_412_arg_0=2, var_412_arg_1=3, var_413=0, var_413_arg_0=0, var_413_arg_1=1, var_414=0, var_414_arg_0=0, var_414_arg_1=0, var_415=1, var_415_arg_0=1, var_415_arg_1=0, var_416=0, var_416_arg_0=0, var_416_arg_1=1, var_417=1, var_417_arg_0=1, var_417_arg_1=1, var_418=1, var_418_arg_0=0, var_418_arg_1=1, var_419=2, var_419_arg_0=13, var_419_arg_1=1, var_420=2, var_420_arg_0=1, var_420_arg_1=2, var_421=2, var_421_arg_0=1, var_421_arg_1=2, var_422=248, var_422_arg_0=0, var_422_arg_1=2, var_423=30, var_423_arg_0=0, var_423_arg_1=248, var_424=1, var_424_arg_0=1, var_424_arg_1=30, var_425=48, var_425_arg_0=48, var_425_arg_1=1, var_426=48, var_426_arg_0=1, var_426_arg_1=48, var_427=48, var_427_arg_0=1, var_427_arg_1=48, var_428=1, var_428_arg_0=1, var_428_arg_1=48, var_429=1, var_429_arg_0=0, var_429_arg_1=1, var_430=1, var_430_arg_0=0, var_430_arg_1=1, var_431=1, var_431_arg_0=0, var_431_arg_1=1, var_432=0, var_432_arg_0=0, var_432_arg_1=1, var_433=1, var_433_arg_0=1, var_433_arg_1=1, var_434=1, var_434_arg_0=1, var_434_arg_1=1, var_435=1, var_435_arg_0=1, var_435_arg_1=1, var_436=1, var_436_arg_0=1, var_436_arg_1=1, var_437=1, var_437_arg_0=1, var_437_arg_1=1, var_438=1, var_438_arg_0=1, var_438_arg_1=1, var_439=1, var_439_arg_0=1, var_439_arg_1=1, var_440=1, var_440_arg_0=1, var_440_arg_1=1, var_441=1, var_441_arg_0=1, var_441_arg_1=1, var_442=1, var_442_arg_0=1, var_442_arg_1=1, var_443=1, var_443_arg_0=1, var_443_arg_1=1, var_444=1, var_444_arg_0=1, var_444_arg_1=1, var_445=1, var_445_arg_0=1, var_445_arg_1=1, var_446=1, var_446_arg_0=1, var_446_arg_1=1, var_447=1, var_447_arg_0=1, var_447_arg_1=1, var_448=1, var_448_arg_0=1, var_448_arg_1=1, var_449=1, var_449_arg_0=1, var_449_arg_1=1, var_450=1, var_450_arg_0=1, var_450_arg_1=1, var_451=1, var_451_arg_0=1, var_451_arg_1=1, var_452=1, var_452_arg_0=1, var_452_arg_1=1, var_453=1, var_453_arg_0=1, var_453_arg_1=1, var_454=1, var_454_arg_0=1, var_454_arg_1=1, var_455=1, var_455_arg_0=1, var_455_arg_1=1, var_456=1, var_456_arg_0=1, var_456_arg_1=1, var_457=1, var_457_arg_0=1, var_457_arg_1=1, var_458=1, var_458_arg_0=1, var_458_arg_1=1, var_459=0, var_459_arg_0=1, var_459_arg_1=0, var_460=1, var_460_arg_0=1, var_460_arg_1=0, var_461=1, var_461_arg_0=1, var_461_arg_1=1, var_462=1, var_462_arg_0=0, var_462_arg_1=1, var_463=1, var_463_arg_0=1, var_463_arg_1=1, var_464=1, var_464_arg_0=1, var_464_arg_1=1, var_465=1, var_465_arg_0=1, var_465_arg_1=1, var_466=1, var_466_arg_0=1, var_466_arg_1=1, var_467=0, var_467_arg_0=0, var_467_arg_1=1, var_468=1, var_468_arg_0=1, var_468_arg_1=0, var_469=1, var_469_arg_0=0, var_469_arg_1=1, var_470=1, var_470_arg_0=1, var_470_arg_1=1, var_471=1, var_471_arg_0=1, var_471_arg_1=1, var_472=1, var_472_arg_0=1, var_472_arg_1=1, var_473=1, var_473_arg_0=1, var_473_arg_1=1, var_474=1, var_474_arg_0=1, var_474_arg_1=1, var_475=1, var_475_arg_0=1, var_475_arg_1=1, var_476=1, var_476_arg_0=1, var_476_arg_1=1, var_477=1, var_477_arg_0=1, var_477_arg_1=1, var_478=0, var_478_arg_0=1, var_478_arg_1=0, var_479=1, var_479_arg_0=1, var_479_arg_1=1, var_480=0, var_480_arg_0=0, var_480_arg_1=1, var_481=0, var_481_arg_0=0, var_481_arg_1=0, var_482=1, var_482_arg_0=1, var_482_arg_1=1, var_483=1, var_483_arg_0=1, var_483_arg_1=1, var_484=1, var_484_arg_0=1, var_484_arg_1=1, var_485=1, var_485_arg_0=1, var_485_arg_1=1, var_486=0, var_486_arg_0=1, var_486_arg_1=0, var_487=1, var_487_arg_0=1, var_487_arg_1=1, var_488=1, var_488_arg_0=1, var_488_arg_1=0, var_489=0, var_489_arg_0=0, var_489_arg_1=1, var_490=0, var_490_arg_0=3, var_490_arg_1=0, var_491=1, var_491_arg_0=0, var_491_arg_1=1, var_492=0, var_492_arg_0=0, var_492_arg_1=1, var_493=0, var_493_arg_0=0, var_493_arg_1=0, var_494=0, var_494_arg_0=1, var_494_arg_1=0, var_495=1, var_495_arg_0=0, var_495_arg_1=1, var_496=0, var_496_arg_0=0, var_496_arg_1=1, var_497=0, var_497_arg_0=0, var_497_arg_1=0, var_498=1, var_498_arg_0=0, var_498_arg_1=1, var_499=1, var_499_arg_0=1, var_499_arg_1=1, var_5=0, var_500=1, var_500_arg_0=0, var_500_arg_1=1, var_501=1, var_501_arg_0=1, var_501_arg_1=1, var_502=1, var_502_arg_0=1, var_502_arg_1=1, var_503=1, var_503_arg_0=1, var_503_arg_1=1, var_504=1, var_504_arg_0=1, var_504_arg_1=1, var_505=1, var_505_arg_0=1, var_505_arg_1=1, var_506=1, var_506_arg_0=1, var_506_arg_1=1, var_507=1, var_507_arg_0=1, var_507_arg_1=1, var_508=1, var_508_arg_0=1, var_508_arg_1=1, var_509=1, var_509_arg_0=1, var_509_arg_1=1, var_510=1, var_510_arg_0=1, var_510_arg_1=1, var_511=1, var_511_arg_0=1, var_511_arg_1=1, var_512=1, var_512_arg_0=1, var_512_arg_1=1, var_513=1, var_513_arg_0=1, var_513_arg_1=1, var_514=1, var_514_arg_0=1, var_514_arg_1=1, var_515=0, var_515_arg_0=1, var_515_arg_1=0, var_516=1, var_516_arg_0=1, var_516_arg_1=1, var_517=1, var_517_arg_0=1, var_517_arg_1=0, var_518=0, var_518_arg_0=0, var_518_arg_1=1, var_519=0, var_519_arg_0=1, var_519_arg_1=0, var_520=1, var_520_arg_0=0, var_520_arg_1=1, var_521=0, var_521_arg_0=0, var_521_arg_1=1, var_522=0, var_522_arg_0=0, var_522_arg_1=0, var_523=1, var_523_arg_0=1, var_523_arg_1=1, var_524=1, var_524_arg_0=0, var_524_arg_1=1, var_525=1, var_525_arg_0=1, var_525_arg_1=1, var_526=1, var_526_arg_0=0, var_526_arg_1=1, var_527=1, var_527_arg_0=1, var_527_arg_1=1, var_528=0, var_528_arg_0=0, var_528_arg_1=1, var_529=1, var_529_arg_0=1, var_529_arg_1=0, var_530=1, var_530_arg_0=0, var_530_arg_1=1, var_531=1, var_531_arg_0=1, var_531_arg_1=1, var_532=1, var_532_arg_0=1, var_532_arg_1=1, var_533=0, var_533_arg_0=1, var_533_arg_1=0, var_534=1, var_534_arg_0=1, var_534_arg_1=1, var_535=0, var_535_arg_0=0, var_535_arg_1=1, var_536=1, var_536_arg_0=1, var_536_arg_1=0, var_537=1, var_537_arg_0=1, var_537_arg_1=1, var_538=1, var_538_arg_0=0, var_538_arg_1=1, var_539=1, var_539_arg_0=1, var_539_arg_1=1, var_540=1, var_540_arg_0=1, var_540_arg_1=1, var_541=0, var_541_arg_0=1, var_541_arg_1=0, var_542=1, var_542_arg_0=1, var_542_arg_1=1, var_543=0, var_543_arg_0=0, var_543_arg_1=1, var_544=0, var_544_arg_0=0, var_544_arg_1=0, var_545=46, var_545_arg_0=47, var_545_arg_1=1, var_546=46, var_546_arg_0=46, var_547=5, var_547_arg_0=1, var_547_arg_1=46, var_547_arg_2=3, var_548=0, var_548_arg_0=5, var_548_arg_1=0, var_549=0, var_549_arg_0=0, var_549_arg_1=0, var_550=12, var_550_arg_0=13, var_550_arg_1=1, var_551=12, var_551_arg_0=12, var_552=12, var_552_arg_0=0, var_552_arg_1=12, var_552_arg_2=12, var_553=266, var_553_arg_0=0, var_553_arg_1=12, var_554=268, var_554_arg_0=2, var_554_arg_1=266, var_555=12, var_555_arg_0=268, var_556=0, var_556_arg_0=0, var_556_arg_1=12, var_556_arg_2=12, var_557=1, var_557_arg_0=0, var_557_arg_1=0, var_558=0, var_558_arg_0=0, var_558_arg_1=1, var_559=4294967294, var_559_arg_0=0, var_559_arg_1=2, var_560=254, var_560_arg_0=4294967294, var_561=0, var_561_arg_0=0, var_561_arg_1=254, var_561_arg_2=255, var_562=1, var_562_arg_0=0, var_562_arg_1=0, var_563=0, var_563_arg_0=0, var_563_arg_1=1, var_564=4294967295, var_564_arg_0=0, var_564_arg_1=1, var_565=255, var_565_arg_0=4294967295, var_566=1, var_566_arg_0=0, var_566_arg_1=255, var_566_arg_2=1, var_567=1, var_567_arg_0=0, var_567_arg_1=1, var_568=2, var_568_arg_0=1, var_568_arg_1=1, var_569=2, var_569_arg_0=2, var_570=1, var_570_arg_0=0, var_570_arg_1=2, var_570_arg_2=1, var_571=0, var_571_arg_0=1, var_571_arg_1=0, var_572=0, var_572_arg_0=0, var_572_arg_1=0, var_573=4294967295, var_573_arg_0=0, var_573_arg_1=1, var_574=255, var_574_arg_0=4294967295, var_575=0, var_575_arg_0=0, var_575_arg_1=255, var_575_arg_2=0, var_576=1, var_576_arg_0=0, var_576_arg_1=0, var_577=0, var_577_arg_0=0, var_577_arg_1=1, var_578=322, var_578_arg_0=323, var_578_arg_1=1, var_579=66, var_579_arg_0=322, var_580=0, var_580_arg_0=1, var_580_arg_1=66, var_580_arg_2=66, var_581=1, var_581_arg_0=0, var_581_arg_1=0, var_582=0, var_582_arg_0=0, var_582_arg_1=1, var_583=4294967295, var_583_arg_0=0, var_583_arg_1=1, var_584=255, var_584_arg_0=4294967295, var_585=0, var_585_arg_0=1, var_585_arg_1=255, var_585_arg_2=1, var_586=1, var_586_arg_0=0, var_586_arg_1=0, var_587=0, var_587_arg_0=0, var_587_arg_1=1, var_588=4294966799, var_588_arg_0=4294966800, var_588_arg_1=1, var_589=15, var_589_arg_0=4294966799, var_590=3, var_590_arg_0=0, var_590_arg_1=15, var_590_arg_2=15, var_591=0, var_591_arg_0=3, var_591_arg_1=0, var_592=0, var_592_arg_0=0, var_592_arg_1=0, var_593=0, var_593_arg_0=0, var_593_arg_1=0, var_594=1, var_594_arg_0=1, var_594_arg_1=0, var_595=1, var_595_arg_0=1, var_596=1, var_596_arg_0=1, var_596_arg_1=1, var_596_arg_2=0, var_597=1, var_597_arg_0=0, var_597_arg_1=1, var_598=2, var_598_arg_0=1, var_598_arg_1=1, var_599=2, var_599_arg_0=2, var_600=1, var_600_arg_0=1, var_600_arg_1=2, var_600_arg_2=1, var_601=1, var_601_arg_0=0, var_601_arg_1=1, var_602=2, var_602_arg_0=1, var_602_arg_1=1, var_603=2, var_603_arg_0=2, var_604=1, var_604_arg_0=1, var_604_arg_1=2, var_604_arg_2=1, var_605=1, var_605_arg_0=0, var_605_arg_1=1, var_606=2, var_606_arg_0=1, var_606_arg_1=1, var_607=2, var_607_arg_0=2, var_608=0, var_608_arg_0=1, var_608_arg_1=2, var_608_arg_2=1, var_609=0, var_609_arg_0=0, var_609_arg_1=0, var_610=1, var_610_arg_0=1, var_610_arg_1=0, var_611=1, var_611_arg_0=1, var_612=1, var_612_arg_0=1, var_612_arg_1=1, var_612_arg_2=0, var_613=0, var_613_arg_0=1, var_613_arg_1=0, var_614=0, var_614_arg_0=0, var_614_arg_1=0, var_615=1, var_615_arg_0=3, var_615_arg_1=2, var_616=1, var_616_arg_0=1, var_617=1, var_617_arg_0=0, var_617_arg_1=1, var_617_arg_2=1, var_618=0, var_618_arg_0=1, var_618_arg_1=0, var_619=0, var_619_arg_0=0, var_619_arg_1=0, var_620=4294967295, var_620_arg_0=0, var_620_arg_1=1, var_621=255, var_621_arg_0=4294967295, var_622=0, var_622_arg_0=1, var_622_arg_1=255, var_622_arg_2=0, var_623=0, var_623_arg_0=0, var_623_arg_1=0, var_624=1, var_624_arg_0=1, var_624_arg_1=0, var_625=1, var_625_arg_0=1, var_626=0, var_626_arg_0=0, var_626_arg_1=1, var_626_arg_2=0, var_627=1, var_627_arg_0=0, var_627_arg_1=0, var_628=0, var_628_arg_0=0, var_628_arg_1=1, var_629=0, var_629_arg_0=0, var_629_arg_1=0, var_630=1, var_630_arg_0=1, var_630_arg_1=0, var_631=1, var_631_arg_0=1, var_632=0, var_632_arg_0=0, var_632_arg_1=1, var_632_arg_2=0, var_633=1, var_633_arg_0=0, var_633_arg_1=0, var_634=0, var_634_arg_0=0, var_634_arg_1=1, var_635=0, var_635_arg_0=1, var_635_arg_1=0, var_636=0, var_636_arg_0=0, var_636_arg_1=0, var_637=0, var_637_arg_0=1, var_637_arg_1=0, var_638=0, var_638_arg_0=0, var_638_arg_1=0, var_639=0, var_639_arg_0=1, var_639_arg_1=0, var_640=0, var_640_arg_0=0, var_640_arg_1=0, var_641=1, var_641_arg_0=0, var_641_arg_1=0, var_642=0, var_642_arg_0=0, var_642_arg_1=1, var_643=1, var_643_arg_0=0, var_643_arg_1=0, var_644=0, var_644_arg_0=0, var_644_arg_1=1, var_645=1, var_645_arg_0=0, var_645_arg_1=0, var_646=0, var_646_arg_0=0, var_646_arg_1=1, var_647=0, var_647_arg_0=1, var_647_arg_1=0, var_648=0, var_648_arg_0=0, var_648_arg_1=0, var_649=0, var_649_arg_0=1, var_649_arg_1=0, var_650=0, var_650_arg_0=0, var_650_arg_1=0, var_651=0, var_651_arg_0=1, var_651_arg_1=0, var_652=0, var_652_arg_0=0, var_652_arg_1=0, var_653=0, var_653_arg_0=1, var_653_arg_1=0, var_654=0, var_654_arg_0=0, var_654_arg_1=0, var_655=0, var_655_arg_0=1, var_655_arg_1=0, var_656=0, var_656_arg_0=0, var_656_arg_1=0, var_657=1, var_657_arg_0=0, var_657_arg_1=0, var_658=0, var_658_arg_0=0, var_658_arg_1=1, var_659=1, var_659_arg_0=0, var_659_arg_1=0, var_660=0, var_660_arg_0=0, var_660_arg_1=1, var_661=0, var_661_arg_0=1, var_661_arg_1=0, var_662=0, var_662_arg_0=0, var_662_arg_1=0, var_663=1, var_663_arg_0=0, var_663_arg_1=0, var_664=0, var_664_arg_0=0, var_664_arg_1=1, var_665=0, var_665_arg_0=1, var_665_arg_1=0, var_666=0, var_666_arg_0=0, var_666_arg_1=0, var_667=1, var_667_arg_0=0, var_667_arg_1=0, var_668=0, var_668_arg_0=0, var_668_arg_1=1, var_669=0, var_669_arg_0=1, var_669_arg_1=0, var_670=0, var_670_arg_0=0, var_670_arg_1=0, var_671=0, var_671_arg_0=1, var_671_arg_1=0, var_672=0, var_672_arg_0=0, var_672_arg_1=0, var_673=0, var_673_arg_0=1, var_673_arg_1=0, var_674=0, var_674_arg_0=0, var_674_arg_1=0, var_675=0, var_675_arg_0=1, var_675_arg_1=0, var_676=0, var_676_arg_0=0, var_676_arg_1=0, var_677=0, var_677_arg_0=0, var_677_arg_1=0, var_678=20, var_679=1, var_679_arg_0=0, var_679_arg_1=20, var_680=1, var_680_arg_0=0, var_680_arg_1=0, var_680_arg_2=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_78=0, var_78_arg_0=0, var_78_arg_1=0, var_79=0, var_79_arg_0=0, var_79_arg_1=0, var_80=0, var_80_arg_0=0, var_80_arg_1=1, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_82=0, var_82_arg_0=0, var_82_arg_1=0, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_84=0, var_84_arg_0=0, var_84_arg_1=0, var_85=0, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=1, var_90=0, var_90_arg_0=0, var_90_arg_1=0, var_91=0, var_91_arg_0=0, var_91_arg_1=1, var_92=0, var_92_arg_0=0, var_92_arg_1=0, var_93=0, var_93_arg_0=0, var_93_arg_1=1, var_94=0, var_94_arg_0=0, var_94_arg_1=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_96=0, var_96_arg_0=0, var_96_arg_1=0, var_97=3, var_98=0, var_98_arg_0=3, var_98_arg_1=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0] [L210] input_130 = __VERIFIER_nondet_uchar() [L211] input_130 = input_130 & mask_SORT_2 [L212] input_132 = __VERIFIER_nondet_uchar() [L213] input_132 = input_132 & mask_SORT_2 [L214] input_134 = __VERIFIER_nondet_uchar() [L215] input_134 = input_134 & mask_SORT_2 [L216] input_136 = __VERIFIER_nondet_uchar() [L217] input_136 = input_136 & mask_SORT_2 [L218] input_138 = __VERIFIER_nondet_uchar() [L219] input_138 = input_138 & mask_SORT_2 [L220] input_140 = __VERIFIER_nondet_uchar() [L221] input_140 = input_140 & mask_SORT_2 [L222] input_142 = __VERIFIER_nondet_uchar() [L223] input_142 = input_142 & mask_SORT_2 [L224] input_144 = __VERIFIER_nondet_uchar() [L225] input_144 = input_144 & mask_SORT_2 [L226] input_146 = __VERIFIER_nondet_uchar() [L227] input_146 = input_146 & mask_SORT_2 [L228] input_148 = __VERIFIER_nondet_uchar() [L229] input_148 = input_148 & mask_SORT_2 [L230] input_150 = __VERIFIER_nondet_uchar() [L231] input_150 = input_150 & mask_SORT_2 [L232] input_152 = __VERIFIER_nondet_uchar() [L233] input_152 = input_152 & mask_SORT_2 [L234] input_154 = __VERIFIER_nondet_uchar() [L235] input_154 = input_154 & mask_SORT_1 [L236] input_156 = __VERIFIER_nondet_uchar() [L237] input_156 = input_156 & mask_SORT_1 [L238] input_158 = __VERIFIER_nondet_uchar() [L239] input_158 = input_158 & mask_SORT_1 [L240] input_160 = __VERIFIER_nondet_uchar() [L241] input_160 = input_160 & mask_SORT_1 [L242] input_162 = __VERIFIER_nondet_uchar() [L243] input_162 = input_162 & mask_SORT_1 [L244] input_164 = __VERIFIER_nondet_uchar() [L245] input_164 = input_164 & mask_SORT_1 [L246] input_166 = __VERIFIER_nondet_uchar() [L247] input_166 = input_166 & mask_SORT_1 [L248] input_168 = __VERIFIER_nondet_uchar() [L249] input_168 = input_168 & mask_SORT_1 [L250] input_170 = __VERIFIER_nondet_uchar() [L251] input_170 = input_170 & mask_SORT_1 [L252] input_172 = __VERIFIER_nondet_uchar() [L253] input_172 = input_172 & mask_SORT_1 [L254] input_174 = __VERIFIER_nondet_uchar() [L255] input_174 = input_174 & mask_SORT_1 [L256] input_176 = __VERIFIER_nondet_uchar() [L257] input_176 = input_176 & mask_SORT_1 [L258] input_178 = __VERIFIER_nondet_uchar() [L259] input_178 = input_178 & mask_SORT_1 [L260] input_180 = __VERIFIER_nondet_uchar() [L261] input_180 = input_180 & mask_SORT_1 [L262] input_182 = __VERIFIER_nondet_uchar() [L263] input_182 = input_182 & mask_SORT_1 [L264] input_184 = __VERIFIER_nondet_uchar() [L265] input_184 = input_184 & mask_SORT_1 [L266] input_186 = __VERIFIER_nondet_uchar() [L267] input_186 = input_186 & mask_SORT_1 [L268] input_188 = __VERIFIER_nondet_uchar() [L269] input_188 = input_188 & mask_SORT_1 [L270] input_190 = __VERIFIER_nondet_uchar() [L271] input_190 = input_190 & mask_SORT_1 [L272] input_192 = __VERIFIER_nondet_uchar() [L273] input_192 = input_192 & mask_SORT_1 [L274] input_194 = __VERIFIER_nondet_uchar() [L275] input_194 = input_194 & mask_SORT_1 [L276] input_198 = __VERIFIER_nondet_uchar() [L277] input_198 = input_198 & mask_SORT_1 [L278] input_215 = __VERIFIER_nondet_uchar() [L279] input_215 = input_215 & mask_SORT_1 [L280] input_231 = __VERIFIER_nondet_uchar() [L281] input_231 = input_231 & mask_SORT_1 [L282] input_249 = __VERIFIER_nondet_uchar() [L283] input_252 = __VERIFIER_nondet_uchar() [L284] input_252 = input_252 & mask_SORT_1 [L285] input_262 = __VERIFIER_nondet_uchar() [L286] input_262 = input_262 & mask_SORT_1 [L287] input_272 = __VERIFIER_nondet_uchar() [L288] input_272 = input_272 & mask_SORT_1 [L289] input_282 = __VERIFIER_nondet_uchar() [L290] input_282 = input_282 & mask_SORT_1 [L291] input_287 = __VERIFIER_nondet_uchar() [L292] input_287 = input_287 & mask_SORT_1 [L293] input_303 = __VERIFIER_nondet_uchar() [L294] input_306 = __VERIFIER_nondet_uchar() [L295] input_306 = input_306 & mask_SORT_1 [L296] input_316 = __VERIFIER_nondet_uchar() [L297] input_316 = input_316 & mask_SORT_1 [L298] input_326 = __VERIFIER_nondet_uchar() [L299] input_326 = input_326 & mask_SORT_1 [L300] input_336 = __VERIFIER_nondet_uchar() [L301] input_336 = input_336 & mask_SORT_1 [L302] input_341 = __VERIFIER_nondet_uchar() [L303] input_341 = input_341 & mask_SORT_1 [L304] input_350 = __VERIFIER_nondet_uchar() [L305] input_350 = input_350 & mask_SORT_1 [L308] SORT_1 var_77_arg_0 = state_31; [L309] SORT_1 var_77_arg_1 = state_33; [L310] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L311] SORT_1 var_78_arg_0 = var_77; [L312] SORT_1 var_78_arg_1 = state_35; [L313] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L314] SORT_1 var_79_arg_0 = var_78; [L315] SORT_1 var_79_arg_1 = ~state_37; [L316] var_79_arg_1 = var_79_arg_1 & mask_SORT_1 [L317] SORT_1 var_79 = var_79_arg_0 & var_79_arg_1; [L318] SORT_1 var_80_arg_0 = var_79; [L319] SORT_1 var_80_arg_1 = ~state_39; [L320] var_80_arg_1 = var_80_arg_1 & mask_SORT_1 [L321] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L322] SORT_1 var_81_arg_0 = var_80; [L323] SORT_1 var_81_arg_1 = ~state_41; [L324] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L325] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L326] SORT_1 var_82_arg_0 = var_81; [L327] SORT_1 var_82_arg_1 = ~state_43; [L328] var_82_arg_1 = var_82_arg_1 & mask_SORT_1 [L329] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L330] SORT_1 var_83_arg_0 = var_82; [L331] SORT_1 var_83_arg_1 = ~state_45; [L332] var_83_arg_1 = var_83_arg_1 & mask_SORT_1 [L333] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L334] SORT_1 var_84_arg_0 = var_83; [L335] SORT_1 var_84_arg_1 = ~state_47; [L336] var_84_arg_1 = var_84_arg_1 & mask_SORT_1 [L337] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L338] SORT_1 var_85_arg_0 = var_84; [L339] SORT_1 var_85_arg_1 = ~state_49; [L340] var_85_arg_1 = var_85_arg_1 & mask_SORT_1 [L341] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L342] SORT_1 var_86_arg_0 = var_85; [L343] SORT_1 var_86_arg_1 = state_51; [L344] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L345] SORT_1 var_87_arg_0 = var_86; [L346] SORT_1 var_87_arg_1 = ~state_53; [L347] var_87_arg_1 = var_87_arg_1 & mask_SORT_1 [L348] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L349] SORT_1 var_88_arg_0 = var_87; [L350] SORT_1 var_88_arg_1 = ~state_55; [L351] var_88_arg_1 = var_88_arg_1 & mask_SORT_1 [L352] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L353] SORT_1 var_89_arg_0 = var_88; [L354] SORT_1 var_89_arg_1 = ~state_57; [L355] var_89_arg_1 = var_89_arg_1 & mask_SORT_1 [L356] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L357] SORT_1 var_90_arg_0 = var_89; [L358] SORT_1 var_90_arg_1 = ~state_59; [L359] var_90_arg_1 = var_90_arg_1 & mask_SORT_1 [L360] SORT_1 var_90 = var_90_arg_0 & var_90_arg_1; [L361] SORT_1 var_91_arg_0 = var_90; [L362] SORT_1 var_91_arg_1 = ~state_61; [L363] var_91_arg_1 = var_91_arg_1 & mask_SORT_1 [L364] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L365] SORT_1 var_92_arg_0 = var_91; [L366] SORT_1 var_92_arg_1 = ~state_63; [L367] var_92_arg_1 = var_92_arg_1 & mask_SORT_1 [L368] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L369] SORT_1 var_93_arg_0 = var_92; [L370] SORT_1 var_93_arg_1 = ~state_65; [L371] var_93_arg_1 = var_93_arg_1 & mask_SORT_1 [L372] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L373] SORT_1 var_94_arg_0 = var_93; [L374] SORT_1 var_94_arg_1 = state_67; [L375] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L376] SORT_1 var_95_arg_0 = var_94; [L377] SORT_1 var_95_arg_1 = state_69; [L378] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L379] SORT_1 var_96_arg_0 = var_95; [L380] SORT_1 var_96_arg_1 = state_71; [L381] SORT_1 var_96 = var_96_arg_0 & var_96_arg_1; [L382] SORT_2 var_98_arg_0 = var_97; [L383] SORT_2 var_98_arg_1 = state_6; [L384] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L385] SORT_1 var_99_arg_0 = var_96; [L386] SORT_1 var_99_arg_1 = var_98; [L387] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L388] SORT_2 var_101_arg_0 = var_100; [L389] SORT_2 var_101_arg_1 = state_8; [L390] SORT_1 var_101 = var_101_arg_0 == var_101_arg_1; [L391] SORT_1 var_102_arg_0 = var_99; [L392] SORT_1 var_102_arg_1 = var_101; [L393] SORT_1 var_102 = var_102_arg_0 & var_102_arg_1; [L394] SORT_2 var_103_arg_0 = var_100; [L395] SORT_2 var_103_arg_1 = state_10; [L396] SORT_1 var_103 = var_103_arg_0 == var_103_arg_1; [L397] SORT_1 var_104_arg_0 = var_102; [L398] SORT_1 var_104_arg_1 = var_103; [L399] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L400] SORT_2 var_106_arg_0 = var_105; [L401] SORT_2 var_106_arg_1 = state_12; [L402] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L403] SORT_1 var_107_arg_0 = var_104; [L404] SORT_1 var_107_arg_1 = var_106; [L405] SORT_1 var_107 = var_107_arg_0 & var_107_arg_1; [L406] SORT_2 var_109_arg_0 = var_108; [L407] SORT_2 var_109_arg_1 = state_14; [L408] SORT_1 var_109 = var_109_arg_0 == var_109_arg_1; [L409] SORT_1 var_110_arg_0 = var_107; [L410] SORT_1 var_110_arg_1 = var_109; [L411] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L412] SORT_2 var_112_arg_0 = var_111; [L413] SORT_2 var_112_arg_1 = state_16; [L414] SORT_1 var_112 = var_112_arg_0 == var_112_arg_1; [L415] SORT_1 var_113_arg_0 = var_110; [L416] SORT_1 var_113_arg_1 = var_112; [L417] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L418] SORT_2 var_114_arg_0 = var_111; [L419] SORT_2 var_114_arg_1 = state_18; [L420] SORT_1 var_114 = var_114_arg_0 == var_114_arg_1; [L421] SORT_1 var_115_arg_0 = var_113; [L422] SORT_1 var_115_arg_1 = var_114; [L423] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L424] SORT_2 var_117_arg_0 = var_116; [L425] SORT_2 var_117_arg_1 = state_20; [L426] SORT_1 var_117 = var_117_arg_0 == var_117_arg_1; [L427] SORT_1 var_118_arg_0 = var_115; [L428] SORT_1 var_118_arg_1 = var_117; [L429] SORT_1 var_118 = var_118_arg_0 & var_118_arg_1; [L430] SORT_2 var_119_arg_0 = var_111; [L431] SORT_2 var_119_arg_1 = state_22; [L432] SORT_1 var_119 = var_119_arg_0 == var_119_arg_1; [L433] SORT_1 var_120_arg_0 = var_118; [L434] SORT_1 var_120_arg_1 = var_119; [L435] SORT_1 var_120 = var_120_arg_0 & var_120_arg_1; [L436] SORT_2 var_122_arg_0 = var_121; [L437] SORT_2 var_122_arg_1 = state_24; [L438] SORT_1 var_122 = var_122_arg_0 == var_122_arg_1; [L439] SORT_1 var_123_arg_0 = var_120; [L440] SORT_1 var_123_arg_1 = var_122; [L441] SORT_1 var_123 = var_123_arg_0 & var_123_arg_1; [L442] SORT_2 var_124_arg_0 = var_121; [L443] SORT_2 var_124_arg_1 = state_26; [L444] SORT_1 var_124 = var_124_arg_0 == var_124_arg_1; [L445] SORT_1 var_125_arg_0 = var_123; [L446] SORT_1 var_125_arg_1 = var_124; [L447] SORT_1 var_125 = var_125_arg_0 & var_125_arg_1; [L448] SORT_2 var_126_arg_0 = var_111; [L449] SORT_2 var_126_arg_1 = state_28; [L450] SORT_1 var_126 = var_126_arg_0 == var_126_arg_1; [L451] SORT_1 var_127_arg_0 = var_125; [L452] SORT_1 var_127_arg_1 = var_126; [L453] SORT_1 var_127 = var_127_arg_0 & var_127_arg_1; [L454] SORT_1 var_128_arg_0 = state_75; [L455] SORT_1 var_128_arg_1 = var_127; [L456] SORT_1 var_128 = var_128_arg_0 & var_128_arg_1; [L457] var_128 = var_128 & mask_SORT_1 [L458] SORT_1 bad_129_arg_0 = var_128; [L459] CALL __VERIFIER_assert(!(bad_129_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 702.2s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 7.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 2 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 7.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 7.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 6 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 6 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 349.2s SatisfiabilityAnalysisTime, 8.7s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 8 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 03:00:08,753 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 976b5e579eb51a9c3b2aa44adf60fda10cd2a5d26988018c09fec4e23c991e41 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 03:00:11,462 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 03:00:11,464 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 03:00:11,496 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 03:00:11,497 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 03:00:11,498 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 03:00:11,500 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 03:00:11,502 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 03:00:11,504 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 03:00:11,505 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 03:00:11,506 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 03:00:11,507 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 03:00:11,508 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 03:00:11,509 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 03:00:11,510 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 03:00:11,512 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 03:00:11,513 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 03:00:11,514 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 03:00:11,526 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 03:00:11,529 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 03:00:11,531 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 03:00:11,532 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 03:00:11,534 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 03:00:11,536 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 03:00:11,540 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 03:00:11,541 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 03:00:11,541 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 03:00:11,542 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 03:00:11,543 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 03:00:11,544 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 03:00:11,545 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 03:00:11,546 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 03:00:11,547 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 03:00:11,548 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 03:00:11,549 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 03:00:11,550 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 03:00:11,551 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 03:00:11,551 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 03:00:11,551 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 03:00:11,552 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 03:00:11,553 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 03:00:11,559 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 03:00:11,610 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 03:00:11,611 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 03:00:11,613 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 03:00:11,613 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 03:00:11,614 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 03:00:11,615 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 03:00:11,615 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 03:00:11,615 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 03:00:11,615 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 03:00:11,616 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 03:00:11,617 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 03:00:11,617 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 03:00:11,619 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 03:00:11,619 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 03:00:11,619 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 03:00:11,620 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 03:00:11,620 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 03:00:11,620 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 03:00:11,620 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 03:00:11,620 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 03:00:11,621 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 03:00:11,621 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 03:00:11,621 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 03:00:11,622 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 03:00:11,622 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 03:00:11,622 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 03:00:11,622 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:00:11,623 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 03:00:11,623 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 03:00:11,623 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 03:00:11,623 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 03:00:11,624 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 03:00:11,624 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 03:00:11,624 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 03:00:11,625 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 03:00:11,625 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 976b5e579eb51a9c3b2aa44adf60fda10cd2a5d26988018c09fec4e23c991e41 [2022-11-03 03:00:12,048 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 03:00:12,079 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 03:00:12,084 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 03:00:12,085 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 03:00:12,086 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 03:00:12,089 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 03:00:12,162 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/72a957bcc/1eb415f3847e4d74870d80b9389c76f8/FLAG66558bbf2 [2022-11-03 03:00:13,048 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 03:00:13,049 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 03:00:13,065 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/72a957bcc/1eb415f3847e4d74870d80b9389c76f8/FLAG66558bbf2 [2022-11-03 03:00:13,112 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/data/72a957bcc/1eb415f3847e4d74870d80b9389c76f8 [2022-11-03 03:00:13,117 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 03:00:13,119 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 03:00:13,121 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 03:00:13,121 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 03:00:13,130 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 03:00:13,131 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:00:13" (1/1) ... [2022-11-03 03:00:13,132 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1f656358 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:13, skipping insertion in model container [2022-11-03 03:00:13,137 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:00:13" (1/1) ... [2022-11-03 03:00:13,147 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 03:00:13,237 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 03:00:13,500 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c[1014,1027] [2022-11-03 03:00:13,981 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:00:13,985 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 03:00:13,997 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.2.prop1-back-serstep.c[1014,1027] [2022-11-03 03:00:14,159 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:00:14,173 INFO L208 MainTranslator]: Completed translation [2022-11-03 03:00:14,173 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14 WrapperNode [2022-11-03 03:00:14,174 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 03:00:14,175 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 03:00:14,175 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 03:00:14,175 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 03:00:14,184 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,228 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,360 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2277 [2022-11-03 03:00:14,361 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 03:00:14,362 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 03:00:14,362 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 03:00:14,362 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 03:00:14,372 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,373 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,388 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,389 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,443 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,454 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,468 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,496 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,522 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 03:00:14,527 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 03:00:14,527 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 03:00:14,527 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 03:00:14,541 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (1/1) ... [2022-11-03 03:00:14,551 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:00:14,567 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:00:14,587 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 03:00:14,606 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 03:00:14,648 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 03:00:14,648 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 03:00:15,251 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 03:00:15,254 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 03:00:17,121 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 03:00:17,131 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 03:00:17,132 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 03:00:17,135 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:00:17 BoogieIcfgContainer [2022-11-03 03:00:17,135 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 03:00:17,138 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 03:00:17,138 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 03:00:17,146 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 03:00:17,146 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 03:00:13" (1/3) ... [2022-11-03 03:00:17,147 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3c4e26e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:00:17, skipping insertion in model container [2022-11-03 03:00:17,148 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:00:14" (2/3) ... [2022-11-03 03:00:17,148 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3c4e26e8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:00:17, skipping insertion in model container [2022-11-03 03:00:17,148 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:00:17" (3/3) ... [2022-11-03 03:00:17,150 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.krebs.2.prop1-back-serstep.c [2022-11-03 03:00:17,174 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 03:00:17,175 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 03:00:17,251 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 03:00:17,260 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@30b6592a, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 03:00:17,261 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 03:00:17,266 INFO L276 IsEmpty]: Start isEmpty. Operand has 103 states, 101 states have (on average 1.495049504950495) internal successors, (151), 102 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:17,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 03:00:17,274 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:17,275 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 03:00:17,276 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:17,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:17,286 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 03:00:17,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:17,307 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [250116825] [2022-11-03 03:00:17,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:17,308 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:17,308 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:17,313 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:17,315 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 03:00:18,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:18,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 284 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 03:00:18,050 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:18,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:18,171 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:18,172 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:18,172 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [250116825] [2022-11-03 03:00:18,173 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [250116825] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:18,173 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:18,173 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:00:18,175 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1846369353] [2022-11-03 03:00:18,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:18,184 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:00:18,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:18,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:00:18,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:00:18,229 INFO L87 Difference]: Start difference. First operand has 103 states, 101 states have (on average 1.495049504950495) internal successors, (151), 102 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:18,720 INFO L93 Difference]: Finished difference Result 296 states and 444 transitions. [2022-11-03 03:00:18,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:00:18,725 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 03:00:18,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:18,736 INFO L225 Difference]: With dead ends: 296 [2022-11-03 03:00:18,736 INFO L226 Difference]: Without dead ends: 195 [2022-11-03 03:00:18,739 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:00:18,743 INFO L413 NwaCegarLoop]: 131 mSDtfsCounter, 280 mSDsluCounter, 271 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 280 SdHoareTripleChecker+Valid, 402 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:18,745 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [280 Valid, 402 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 03:00:18,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2022-11-03 03:00:18,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 101. [2022-11-03 03:00:18,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 100 states have (on average 1.47) internal successors, (147), 100 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 147 transitions. [2022-11-03 03:00:18,789 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 147 transitions. Word has length 5 [2022-11-03 03:00:18,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:18,790 INFO L495 AbstractCegarLoop]: Abstraction has 101 states and 147 transitions. [2022-11-03 03:00:18,790 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,790 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 147 transitions. [2022-11-03 03:00:18,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:18,794 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:18,794 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:18,815 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:19,015 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:19,015 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:19,016 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:19,016 INFO L85 PathProgramCache]: Analyzing trace with hash -2093197609, now seen corresponding path program 1 times [2022-11-03 03:00:19,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:19,021 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [988701309] [2022-11-03 03:00:19,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:19,021 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:19,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:19,023 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:19,031 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 03:00:20,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:20,374 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:20,392 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:20,595 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:20,596 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:20,596 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:20,596 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [988701309] [2022-11-03 03:00:20,599 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [988701309] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:20,599 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:20,600 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:20,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180152718] [2022-11-03 03:00:20,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:20,602 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:20,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:20,604 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:20,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:20,606 INFO L87 Difference]: Start difference. First operand 101 states and 147 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:20,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:20,858 INFO L93 Difference]: Finished difference Result 202 states and 296 transitions. [2022-11-03 03:00:20,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:00:20,862 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:20,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:20,863 INFO L225 Difference]: With dead ends: 202 [2022-11-03 03:00:20,863 INFO L226 Difference]: Without dead ends: 105 [2022-11-03 03:00:20,864 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:20,865 INFO L413 NwaCegarLoop]: 139 mSDtfsCounter, 2 mSDsluCounter, 529 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 18 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:20,866 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 668 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 18 Unchecked, 0.2s Time] [2022-11-03 03:00:20,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2022-11-03 03:00:20,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2022-11-03 03:00:20,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 104 states have (on average 1.4615384615384615) internal successors, (152), 104 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:20,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 152 transitions. [2022-11-03 03:00:20,889 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 152 transitions. Word has length 100 [2022-11-03 03:00:20,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:20,890 INFO L495 AbstractCegarLoop]: Abstraction has 105 states and 152 transitions. [2022-11-03 03:00:20,890 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:20,890 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 152 transitions. [2022-11-03 03:00:20,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:20,894 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:20,895 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:20,944 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:21,121 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:21,122 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:21,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:21,122 INFO L85 PathProgramCache]: Analyzing trace with hash -1209688619, now seen corresponding path program 1 times [2022-11-03 03:00:21,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:21,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [180743834] [2022-11-03 03:00:21,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:21,125 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:21,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:21,134 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:21,180 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 03:00:22,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:22,545 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:22,563 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:22,885 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:22,885 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:22,886 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:22,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [180743834] [2022-11-03 03:00:22,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [180743834] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:22,891 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:22,892 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:22,892 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [817036882] [2022-11-03 03:00:22,893 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:22,894 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:22,894 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:22,895 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:22,896 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:22,898 INFO L87 Difference]: Start difference. First operand 105 states and 152 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:23,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:23,065 INFO L93 Difference]: Finished difference Result 236 states and 346 transitions. [2022-11-03 03:00:23,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 03:00:23,069 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:23,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:23,070 INFO L225 Difference]: With dead ends: 236 [2022-11-03 03:00:23,070 INFO L226 Difference]: Without dead ends: 139 [2022-11-03 03:00:23,071 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:23,072 INFO L413 NwaCegarLoop]: 138 mSDtfsCounter, 40 mSDsluCounter, 664 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 802 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 28 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:23,072 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 802 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 4 Invalid, 0 Unknown, 28 Unchecked, 0.1s Time] [2022-11-03 03:00:23,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-11-03 03:00:23,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2022-11-03 03:00:23,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 138 states have (on average 1.463768115942029) internal successors, (202), 138 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:23,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 202 transitions. [2022-11-03 03:00:23,096 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 202 transitions. Word has length 100 [2022-11-03 03:00:23,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:23,099 INFO L495 AbstractCegarLoop]: Abstraction has 139 states and 202 transitions. [2022-11-03 03:00:23,099 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:23,099 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 202 transitions. [2022-11-03 03:00:23,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:23,106 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:23,106 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:23,145 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:23,319 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:23,320 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:23,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:23,320 INFO L85 PathProgramCache]: Analyzing trace with hash 1123704019, now seen corresponding path program 1 times [2022-11-03 03:00:23,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:23,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [580544167] [2022-11-03 03:00:23,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:23,323 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:23,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:23,326 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:23,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 03:00:24,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:24,523 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:24,538 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:24,939 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:24,940 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:24,940 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:24,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [580544167] [2022-11-03 03:00:24,941 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [580544167] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:24,941 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:24,941 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:24,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163845619] [2022-11-03 03:00:24,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:24,942 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:24,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:24,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:24,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:24,944 INFO L87 Difference]: Start difference. First operand 139 states and 202 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:25,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:25,090 INFO L93 Difference]: Finished difference Result 250 states and 366 transitions. [2022-11-03 03:00:25,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 03:00:25,092 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:25,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:25,093 INFO L225 Difference]: With dead ends: 250 [2022-11-03 03:00:25,094 INFO L226 Difference]: Without dead ends: 153 [2022-11-03 03:00:25,094 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:25,095 INFO L413 NwaCegarLoop]: 137 mSDtfsCounter, 76 mSDsluCounter, 476 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 76 SdHoareTripleChecker+Valid, 613 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 25 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:25,096 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [76 Valid, 613 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 25 Unchecked, 0.1s Time] [2022-11-03 03:00:25,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2022-11-03 03:00:25,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 153. [2022-11-03 03:00:25,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153 states, 152 states have (on average 1.4605263157894737) internal successors, (222), 152 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:25,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 222 transitions. [2022-11-03 03:00:25,106 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 222 transitions. Word has length 100 [2022-11-03 03:00:25,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:25,107 INFO L495 AbstractCegarLoop]: Abstraction has 153 states and 222 transitions. [2022-11-03 03:00:25,107 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:25,108 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 222 transitions. [2022-11-03 03:00:25,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:25,109 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:25,109 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:25,144 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:25,333 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:25,334 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:25,334 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:25,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1476792401, now seen corresponding path program 1 times [2022-11-03 03:00:25,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:25,337 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [358471268] [2022-11-03 03:00:25,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:25,337 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:25,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:25,339 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:25,378 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 03:00:26,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:26,594 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:26,604 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:27,114 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:27,115 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:27,115 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:27,115 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [358471268] [2022-11-03 03:00:27,115 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [358471268] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:27,116 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:27,116 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:27,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [103554448] [2022-11-03 03:00:27,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:27,117 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:27,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:27,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:27,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:27,118 INFO L87 Difference]: Start difference. First operand 153 states and 222 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:27,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:27,271 INFO L93 Difference]: Finished difference Result 350 states and 513 transitions. [2022-11-03 03:00:27,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 03:00:27,274 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:27,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:27,276 INFO L225 Difference]: With dead ends: 350 [2022-11-03 03:00:27,276 INFO L226 Difference]: Without dead ends: 253 [2022-11-03 03:00:27,277 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:27,278 INFO L413 NwaCegarLoop]: 135 mSDtfsCounter, 121 mSDsluCounter, 491 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 121 SdHoareTripleChecker+Valid, 626 SdHoareTripleChecker+Invalid, 36 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 25 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:27,278 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [121 Valid, 626 Invalid, 36 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 25 Unchecked, 0.1s Time] [2022-11-03 03:00:27,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2022-11-03 03:00:27,288 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 253. [2022-11-03 03:00:27,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253 states, 252 states have (on average 1.4642857142857142) internal successors, (369), 252 states have internal predecessors, (369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:27,289 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253 states to 253 states and 369 transitions. [2022-11-03 03:00:27,290 INFO L78 Accepts]: Start accepts. Automaton has 253 states and 369 transitions. Word has length 100 [2022-11-03 03:00:27,290 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:27,290 INFO L495 AbstractCegarLoop]: Abstraction has 253 states and 369 transitions. [2022-11-03 03:00:27,291 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:27,291 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 369 transitions. [2022-11-03 03:00:27,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:27,293 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:27,293 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:27,337 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:27,517 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:27,518 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:27,518 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:27,518 INFO L85 PathProgramCache]: Analyzing trace with hash 90589007, now seen corresponding path program 1 times [2022-11-03 03:00:27,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:27,520 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [746318879] [2022-11-03 03:00:27,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:27,520 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:27,520 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:27,521 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:27,522 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 03:00:28,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:28,637 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:28,646 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:29,100 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:29,101 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:29,101 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:29,102 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [746318879] [2022-11-03 03:00:29,102 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [746318879] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:29,102 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:29,102 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:29,103 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2989533] [2022-11-03 03:00:29,103 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:29,103 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:29,104 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:29,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:29,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:29,105 INFO L87 Difference]: Start difference. First operand 253 states and 369 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:29,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:29,274 INFO L93 Difference]: Finished difference Result 456 states and 668 transitions. [2022-11-03 03:00:29,275 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 03:00:29,276 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:29,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:29,278 INFO L225 Difference]: With dead ends: 456 [2022-11-03 03:00:29,278 INFO L226 Difference]: Without dead ends: 359 [2022-11-03 03:00:29,279 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:29,280 INFO L413 NwaCegarLoop]: 136 mSDtfsCounter, 94 mSDsluCounter, 572 mSDsCounter, 0 mSdLazyCounter, 12 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 94 SdHoareTripleChecker+Valid, 708 SdHoareTripleChecker+Invalid, 36 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 12 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:29,280 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [94 Valid, 708 Invalid, 36 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 12 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-11-03 03:00:29,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states. [2022-11-03 03:00:29,290 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 359. [2022-11-03 03:00:29,291 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 359 states, 358 states have (on average 1.4636871508379887) internal successors, (524), 358 states have internal predecessors, (524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:29,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 524 transitions. [2022-11-03 03:00:29,293 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 524 transitions. Word has length 100 [2022-11-03 03:00:29,293 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:29,294 INFO L495 AbstractCegarLoop]: Abstraction has 359 states and 524 transitions. [2022-11-03 03:00:29,294 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:29,294 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 524 transitions. [2022-11-03 03:00:29,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:29,297 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:29,297 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:29,339 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:29,521 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:29,522 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:29,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:29,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1370452685, now seen corresponding path program 1 times [2022-11-03 03:00:29,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:29,524 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [247729560] [2022-11-03 03:00:29,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:29,524 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:29,524 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:29,526 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:29,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 03:00:30,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:30,662 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 03:00:30,674 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:30,888 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:30,888 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:30,888 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:30,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [247729560] [2022-11-03 03:00:30,889 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [247729560] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:30,889 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:30,889 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:00:30,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1110824323] [2022-11-03 03:00:30,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:30,890 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:00:30,890 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:30,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:00:30,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:00:30,891 INFO L87 Difference]: Start difference. First operand 359 states and 524 transitions. Second operand has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:30,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:30,957 INFO L93 Difference]: Finished difference Result 601 states and 881 transitions. [2022-11-03 03:00:30,957 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:00:30,957 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:30,958 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:30,959 INFO L225 Difference]: With dead ends: 601 [2022-11-03 03:00:30,959 INFO L226 Difference]: Without dead ends: 504 [2022-11-03 03:00:30,960 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:00:30,961 INFO L413 NwaCegarLoop]: 281 mSDtfsCounter, 189 mSDsluCounter, 283 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 189 SdHoareTripleChecker+Valid, 564 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:30,961 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [189 Valid, 564 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 03:00:30,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2022-11-03 03:00:30,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 407. [2022-11-03 03:00:30,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 406 states have (on average 1.4655172413793103) internal successors, (595), 406 states have internal predecessors, (595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:30,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 595 transitions. [2022-11-03 03:00:30,970 INFO L78 Accepts]: Start accepts. Automaton has 407 states and 595 transitions. Word has length 100 [2022-11-03 03:00:30,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:30,971 INFO L495 AbstractCegarLoop]: Abstraction has 407 states and 595 transitions. [2022-11-03 03:00:30,971 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:30,971 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 595 transitions. [2022-11-03 03:00:30,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 03:00:30,973 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:30,973 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:31,008 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:31,197 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:31,198 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:31,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:31,198 INFO L85 PathProgramCache]: Analyzing trace with hash 1372299727, now seen corresponding path program 1 times [2022-11-03 03:00:31,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:31,200 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1859832393] [2022-11-03 03:00:31,200 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:31,201 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:31,201 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:31,202 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:31,241 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 03:00:32,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:32,416 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-03 03:00:32,425 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:34,397 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:34,397 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:36,105 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:36,106 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:36,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1859832393] [2022-11-03 03:00:36,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1859832393] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:36,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1585924698] [2022-11-03 03:00:36,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:36,107 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:00:36,108 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:00:36,113 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:00:36,134 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2022-11-03 03:00:38,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:38,181 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-03 03:00:38,195 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:39,973 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:39,973 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:41,302 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:41,302 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1585924698] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:41,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1835337440] [2022-11-03 03:00:41,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:41,303 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:00:41,303 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:00:41,306 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:00:41,329 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-03 03:00:42,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:42,210 INFO L263 TraceCheckSpWp]: Trace formula consists of 2024 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 03:00:42,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:44,009 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:44,009 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:45,254 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:45,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1835337440] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:45,255 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:00:45,255 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 10, 10] total 18 [2022-11-03 03:00:45,255 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105119408] [2022-11-03 03:00:45,255 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:00:45,256 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-03 03:00:45,256 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:45,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-03 03:00:45,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2022-11-03 03:00:45,257 INFO L87 Difference]: Start difference. First operand 407 states and 595 transitions. Second operand has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:45,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:45,975 INFO L93 Difference]: Finished difference Result 503 states and 736 transitions. [2022-11-03 03:00:45,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-03 03:00:45,986 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 03:00:45,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:45,990 INFO L225 Difference]: With dead ends: 503 [2022-11-03 03:00:45,991 INFO L226 Difference]: Without dead ends: 501 [2022-11-03 03:00:45,991 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 597 GetRequests, 576 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=81, Invalid=339, Unknown=0, NotChecked=0, Total=420 [2022-11-03 03:00:45,992 INFO L413 NwaCegarLoop]: 104 mSDtfsCounter, 996 mSDsluCounter, 1168 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 996 SdHoareTripleChecker+Valid, 1272 SdHoareTripleChecker+Invalid, 494 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 407 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:45,992 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [996 Valid, 1272 Invalid, 494 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 84 Invalid, 0 Unknown, 407 Unchecked, 0.5s Time] [2022-11-03 03:00:45,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501 states. [2022-11-03 03:00:46,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501 to 410. [2022-11-03 03:00:46,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 410 states, 409 states have (on average 1.4621026894865525) internal successors, (598), 409 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:46,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 410 states to 410 states and 598 transitions. [2022-11-03 03:00:46,016 INFO L78 Accepts]: Start accepts. Automaton has 410 states and 598 transitions. Word has length 100 [2022-11-03 03:00:46,016 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:46,016 INFO L495 AbstractCegarLoop]: Abstraction has 410 states and 598 transitions. [2022-11-03 03:00:46,017 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:46,017 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 598 transitions. [2022-11-03 03:00:46,020 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:00:46,020 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:46,020 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:46,053 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:46,239 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:46,450 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:46,626 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:46,626 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:46,626 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:46,627 INFO L85 PathProgramCache]: Analyzing trace with hash -982244143, now seen corresponding path program 1 times [2022-11-03 03:00:46,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:46,629 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [170779490] [2022-11-03 03:00:46,629 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:46,630 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:46,630 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:46,633 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:46,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 03:00:48,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:48,330 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:48,338 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:48,571 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 93 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:00:48,571 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:48,622 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 96 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 03:00:48,622 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:48,622 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [170779490] [2022-11-03 03:00:48,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [170779490] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 03:00:48,622 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 03:00:48,622 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 03:00:48,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960031206] [2022-11-03 03:00:48,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:48,623 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:00:48,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:48,624 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:00:48,624 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:00:48,625 INFO L87 Difference]: Start difference. First operand 410 states and 598 transitions. Second operand has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:48,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:48,919 INFO L93 Difference]: Finished difference Result 1301 states and 1905 transitions. [2022-11-03 03:00:48,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:00:48,922 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 03:00:48,922 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:48,926 INFO L225 Difference]: With dead ends: 1301 [2022-11-03 03:00:48,926 INFO L226 Difference]: Without dead ends: 1204 [2022-11-03 03:00:48,927 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:00:48,928 INFO L413 NwaCegarLoop]: 138 mSDtfsCounter, 683 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 46 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 683 SdHoareTripleChecker+Valid, 533 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 46 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:48,928 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [683 Valid, 533 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 46 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 03:00:48,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1204 states. [2022-11-03 03:00:48,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1204 to 412. [2022-11-03 03:00:48,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 412 states, 411 states have (on average 1.4598540145985401) internal successors, (600), 411 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:48,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 412 states to 412 states and 600 transitions. [2022-11-03 03:00:48,944 INFO L78 Accepts]: Start accepts. Automaton has 412 states and 600 transitions. Word has length 195 [2022-11-03 03:00:48,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:48,944 INFO L495 AbstractCegarLoop]: Abstraction has 412 states and 600 transitions. [2022-11-03 03:00:48,945 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:48,945 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 600 transitions. [2022-11-03 03:00:48,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:00:48,947 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:48,948 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:48,998 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:49,169 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:49,170 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:49,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:49,170 INFO L85 PathProgramCache]: Analyzing trace with hash -98735153, now seen corresponding path program 1 times [2022-11-03 03:00:49,173 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:49,173 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2120808298] [2022-11-03 03:00:49,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:49,173 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:49,173 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:49,174 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:49,175 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 03:00:50,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:50,790 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:50,798 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:51,150 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 61 proven. 37 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:00:51,150 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:51,235 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 03:00:51,235 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:51,235 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2120808298] [2022-11-03 03:00:51,235 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2120808298] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 03:00:51,235 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 03:00:51,236 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 03:00:51,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499236794] [2022-11-03 03:00:51,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:51,236 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:00:51,236 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:51,237 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:00:51,237 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:00:51,237 INFO L87 Difference]: Start difference. First operand 412 states and 600 transitions. Second operand has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:51,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:51,471 INFO L93 Difference]: Finished difference Result 979 states and 1431 transitions. [2022-11-03 03:00:51,472 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:00:51,472 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 03:00:51,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:51,476 INFO L225 Difference]: With dead ends: 979 [2022-11-03 03:00:51,476 INFO L226 Difference]: Without dead ends: 880 [2022-11-03 03:00:51,477 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:00:51,478 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 599 mSDsluCounter, 404 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 599 SdHoareTripleChecker+Valid, 595 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:51,480 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [599 Valid, 595 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 03:00:51,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 880 states. [2022-11-03 03:00:51,492 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 880 to 436. [2022-11-03 03:00:51,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 435 states have (on average 1.4597701149425288) internal successors, (635), 435 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:51,497 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 635 transitions. [2022-11-03 03:00:51,497 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 635 transitions. Word has length 195 [2022-11-03 03:00:51,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:51,498 INFO L495 AbstractCegarLoop]: Abstraction has 436 states and 635 transitions. [2022-11-03 03:00:51,499 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:51,499 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 635 transitions. [2022-11-03 03:00:51,502 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:00:51,502 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:51,502 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:51,543 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:51,717 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:51,718 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:51,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:51,718 INFO L85 PathProgramCache]: Analyzing trace with hash -2060309811, now seen corresponding path program 1 times [2022-11-03 03:00:51,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:51,720 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1264515354] [2022-11-03 03:00:51,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:51,720 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:51,721 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:51,721 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:51,739 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 03:00:53,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:53,500 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:53,508 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:53,930 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 47 proven. 51 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:00:53,930 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:54,046 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 03:00:54,046 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:54,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1264515354] [2022-11-03 03:00:54,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1264515354] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 03:00:54,047 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 03:00:54,047 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 03:00:54,047 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499692860] [2022-11-03 03:00:54,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:54,048 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:00:54,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:54,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:00:54,048 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:00:54,049 INFO L87 Difference]: Start difference. First operand 436 states and 635 transitions. Second operand has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:54,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:54,318 INFO L93 Difference]: Finished difference Result 977 states and 1425 transitions. [2022-11-03 03:00:54,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:00:54,319 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 03:00:54,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:54,324 INFO L225 Difference]: With dead ends: 977 [2022-11-03 03:00:54,324 INFO L226 Difference]: Without dead ends: 854 [2022-11-03 03:00:54,325 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:00:54,326 INFO L413 NwaCegarLoop]: 209 mSDtfsCounter, 501 mSDsluCounter, 439 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 501 SdHoareTripleChecker+Valid, 648 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:54,327 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [501 Valid, 648 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 03:00:54,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 854 states. [2022-11-03 03:00:54,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 854 to 450. [2022-11-03 03:00:54,340 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 450 states, 449 states have (on average 1.4587973273942094) internal successors, (655), 449 states have internal predecessors, (655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:54,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 655 transitions. [2022-11-03 03:00:54,343 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 655 transitions. Word has length 195 [2022-11-03 03:00:54,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:54,343 INFO L495 AbstractCegarLoop]: Abstraction has 450 states and 655 transitions. [2022-11-03 03:00:54,343 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:54,344 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 655 transitions. [2022-11-03 03:00:54,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:00:54,346 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:54,347 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:54,404 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:54,569 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:54,570 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:54,570 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:54,570 INFO L85 PathProgramCache]: Analyzing trace with hash -1707221429, now seen corresponding path program 1 times [2022-11-03 03:00:54,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:54,573 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [589243111] [2022-11-03 03:00:54,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:54,573 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:54,573 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:54,574 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:54,575 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 03:00:56,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:56,311 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:56,321 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:56,892 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 29 proven. 69 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:00:56,893 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:57,036 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 92 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 03:00:57,037 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:57,037 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [589243111] [2022-11-03 03:00:57,037 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [589243111] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 03:00:57,037 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 03:00:57,037 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 03:00:57,038 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888507652] [2022-11-03 03:00:57,038 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:57,038 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:00:57,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:57,039 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:00:57,039 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:00:57,040 INFO L87 Difference]: Start difference. First operand 450 states and 655 transitions. Second operand has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:57,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:57,423 INFO L93 Difference]: Finished difference Result 1029 states and 1500 transitions. [2022-11-03 03:00:57,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:00:57,424 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 03:00:57,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:57,427 INFO L225 Difference]: With dead ends: 1029 [2022-11-03 03:00:57,427 INFO L226 Difference]: Without dead ends: 892 [2022-11-03 03:00:57,428 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:00:57,428 INFO L413 NwaCegarLoop]: 233 mSDtfsCounter, 530 mSDsluCounter, 418 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 530 SdHoareTripleChecker+Valid, 651 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:57,429 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [530 Valid, 651 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 03:00:57,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 892 states. [2022-11-03 03:00:57,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 892 to 550. [2022-11-03 03:00:57,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 550 states, 549 states have (on average 1.4608378870673953) internal successors, (802), 549 states have internal predecessors, (802), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:57,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 802 transitions. [2022-11-03 03:00:57,447 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 802 transitions. Word has length 195 [2022-11-03 03:00:57,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:57,447 INFO L495 AbstractCegarLoop]: Abstraction has 550 states and 802 transitions. [2022-11-03 03:00:57,448 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:57,448 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 802 transitions. [2022-11-03 03:00:57,451 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:00:57,451 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:57,451 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:57,503 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:57,677 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:57,677 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:57,678 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:57,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1201542473, now seen corresponding path program 1 times [2022-11-03 03:00:57,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:57,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2038531758] [2022-11-03 03:00:57,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:57,680 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:57,680 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:57,681 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:57,685 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 03:00:59,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:59,373 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 03:00:59,383 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:59,942 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 15 proven. 83 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:00:59,942 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:00,064 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2022-11-03 03:01:00,065 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:01:00,065 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2038531758] [2022-11-03 03:01:00,065 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2038531758] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 03:01:00,065 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 03:01:00,065 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 03:01:00,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190704235] [2022-11-03 03:01:00,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:01:00,066 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:01:00,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:01:00,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:01:00,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:01:00,067 INFO L87 Difference]: Start difference. First operand 550 states and 802 transitions. Second operand has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:00,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:01:00,383 INFO L93 Difference]: Finished difference Result 1207 states and 1758 transitions. [2022-11-03 03:01:00,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:01:00,384 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 03:01:00,384 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:01:00,388 INFO L225 Difference]: With dead ends: 1207 [2022-11-03 03:01:00,388 INFO L226 Difference]: Without dead ends: 970 [2022-11-03 03:01:00,389 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:01:00,391 INFO L413 NwaCegarLoop]: 259 mSDtfsCounter, 359 mSDsluCounter, 537 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 359 SdHoareTripleChecker+Valid, 796 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 03:01:00,392 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [359 Valid, 796 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 03:01:00,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 970 states. [2022-11-03 03:01:00,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 970 to 624. [2022-11-03 03:01:00,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 623 states have (on average 1.4590690208667736) internal successors, (909), 623 states have internal predecessors, (909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:00,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 909 transitions. [2022-11-03 03:01:00,413 INFO L78 Accepts]: Start accepts. Automaton has 624 states and 909 transitions. Word has length 195 [2022-11-03 03:01:00,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:01:00,414 INFO L495 AbstractCegarLoop]: Abstraction has 624 states and 909 transitions. [2022-11-03 03:01:00,414 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:00,414 INFO L276 IsEmpty]: Start isEmpty. Operand 624 states and 909 transitions. [2022-11-03 03:01:00,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 03:01:00,418 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:01:00,418 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 03:01:00,470 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:00,640 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:01:00,640 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:01:00,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:01:00,641 INFO L85 PathProgramCache]: Analyzing trace with hash -1813561145, now seen corresponding path program 1 times [2022-11-03 03:01:00,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:01:00,643 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [909737456] [2022-11-03 03:01:00,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:00,643 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:01:00,644 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:01:00,644 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:01:00,646 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d21d9e48-b928-4d2f-a9e7-88c690a5c2de/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Waiting until timeout for monitored process [2022-11-03 03:01:02,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:02,326 INFO L263 TraceCheckSpWp]: Trace formula consists of 3764 conjuncts, 122 conjunts are in the unsatisfiable core [2022-11-03 03:01:02,337 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:20,235 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 96 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:01:20,235 INFO L328 TraceCheckSpWp]: Computing backward predicates...