./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b6819c080be0252472ffbb9d2e5ec70fe87807fca1a5e6b3460972b7b91a9ca6 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 04:01:04,583 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 04:01:04,586 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 04:01:04,620 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 04:01:04,620 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 04:01:04,622 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 04:01:04,623 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 04:01:04,626 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 04:01:04,629 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 04:01:04,631 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 04:01:04,632 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 04:01:04,638 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 04:01:04,640 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 04:01:04,642 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 04:01:04,647 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 04:01:04,648 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 04:01:04,653 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 04:01:04,654 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 04:01:04,656 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 04:01:04,667 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 04:01:04,668 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 04:01:04,670 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 04:01:04,671 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 04:01:04,672 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 04:01:04,676 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 04:01:04,677 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 04:01:04,677 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 04:01:04,678 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 04:01:04,679 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 04:01:04,680 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 04:01:04,680 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 04:01:04,681 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 04:01:04,682 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 04:01:04,683 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 04:01:04,685 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 04:01:04,685 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 04:01:04,686 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 04:01:04,686 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 04:01:04,687 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 04:01:04,688 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 04:01:04,689 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 04:01:04,690 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 04:01:04,719 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 04:01:04,719 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 04:01:04,719 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 04:01:04,720 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 04:01:04,721 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 04:01:04,721 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 04:01:04,721 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 04:01:04,721 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 04:01:04,722 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 04:01:04,722 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 04:01:04,722 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 04:01:04,722 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 04:01:04,723 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 04:01:04,723 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 04:01:04,723 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 04:01:04,723 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 04:01:04,724 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 04:01:04,724 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 04:01:04,725 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 04:01:04,725 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 04:01:04,725 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 04:01:04,726 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 04:01:04,726 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 04:01:04,726 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 04:01:04,727 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 04:01:04,727 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 04:01:04,727 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 04:01:04,727 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 04:01:04,728 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 04:01:04,728 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 04:01:04,728 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 04:01:04,728 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 04:01:04,729 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 04:01:04,729 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 04:01:04,729 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 04:01:04,730 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 04:01:04,730 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 04:01:04,730 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 04:01:04,730 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b6819c080be0252472ffbb9d2e5ec70fe87807fca1a5e6b3460972b7b91a9ca6 [2022-11-03 04:01:05,035 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 04:01:05,068 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 04:01:05,072 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 04:01:05,074 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 04:01:05,075 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 04:01:05,077 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:01:05,168 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/1692dfa62/2d2f6ee620f44e97955205c0997e224a/FLAG4308e8f4f [2022-11-03 04:01:06,114 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 04:01:06,115 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:01:06,140 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/1692dfa62/2d2f6ee620f44e97955205c0997e224a/FLAG4308e8f4f [2022-11-03 04:01:06,250 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/1692dfa62/2d2f6ee620f44e97955205c0997e224a [2022-11-03 04:01:06,255 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 04:01:06,257 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 04:01:06,259 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 04:01:06,262 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 04:01:06,266 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 04:01:06,268 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 04:01:06" (1/1) ... [2022-11-03 04:01:06,271 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3a1b5726 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:06, skipping insertion in model container [2022-11-03 04:01:06,271 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 04:01:06" (1/1) ... [2022-11-03 04:01:06,281 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 04:01:06,392 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 04:01:06,718 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c[1014,1027] [2022-11-03 04:01:07,291 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 04:01:07,302 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 04:01:07,318 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c[1014,1027] [2022-11-03 04:01:07,629 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 04:01:07,645 INFO L208 MainTranslator]: Completed translation [2022-11-03 04:01:07,646 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07 WrapperNode [2022-11-03 04:01:07,646 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 04:01:07,647 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 04:01:07,647 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 04:01:07,647 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 04:01:07,655 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:07,731 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,038 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2276 [2022-11-03 04:01:08,038 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 04:01:08,040 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 04:01:08,040 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 04:01:08,041 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 04:01:08,053 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,053 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,088 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,088 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,293 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,319 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,364 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,383 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,440 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 04:01:08,443 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 04:01:08,443 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 04:01:08,443 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 04:01:08,445 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (1/1) ... [2022-11-03 04:01:08,453 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 04:01:08,467 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 04:01:08,483 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 04:01:08,528 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 04:01:08,585 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 04:01:08,585 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 04:01:09,322 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 04:01:09,325 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 04:01:37,327 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 04:01:48,338 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 04:01:48,338 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 04:01:48,340 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 04:01:48 BoogieIcfgContainer [2022-11-03 04:01:48,341 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 04:01:48,343 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 04:01:48,343 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 04:01:48,347 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 04:01:48,348 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 04:01:06" (1/3) ... [2022-11-03 04:01:48,348 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c026ca3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 04:01:48, skipping insertion in model container [2022-11-03 04:01:48,348 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:01:07" (2/3) ... [2022-11-03 04:01:48,349 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@c026ca3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 04:01:48, skipping insertion in model container [2022-11-03 04:01:48,349 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 04:01:48" (3/3) ... [2022-11-03 04:01:48,350 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:01:48,369 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 04:01:48,369 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 04:01:48,428 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 04:01:48,437 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6cc9b5fa, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 04:01:48,437 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 04:01:48,447 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:01:48,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 04:01:48,455 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:01:48,456 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 04:01:48,457 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:01:48,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:01:48,464 INFO L85 PathProgramCache]: Analyzing trace with hash 11390190, now seen corresponding path program 1 times [2022-11-03 04:01:48,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 04:01:48,477 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080292337] [2022-11-03 04:01:48,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:01:48,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 04:01:50,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:01:59,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:01:59,387 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 04:01:59,388 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080292337] [2022-11-03 04:01:59,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080292337] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:01:59,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:01:59,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 04:01:59,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2099341382] [2022-11-03 04:01:59,393 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:01:59,398 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 04:01:59,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 04:01:59,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 04:01:59,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 04:01:59,445 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:02:02,635 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.29s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 04:02:04,592 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.96s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 04:02:06,649 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.06s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 04:02:06,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:02:06,696 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 04:02:06,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 04:02:06,698 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 04:02:06,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:02:06,707 INFO L225 Difference]: With dead ends: 15 [2022-11-03 04:02:06,707 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 04:02:06,709 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 04:02:06,714 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 1 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:02:06,715 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 6 Invalid, 2 Unknown, 0 Unchecked, 7.2s Time] [2022-11-03 04:02:06,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 04:02:06,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 04:02:06,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:02:06,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 04:02:06,756 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 04:02:06,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:02:06,757 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 04:02:06,757 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:02:06,757 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 04:02:06,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 04:02:06,758 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:02:06,758 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 04:02:06,759 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 04:02:06,759 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:02:06,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:02:06,760 INFO L85 PathProgramCache]: Analyzing trace with hash 41601637, now seen corresponding path program 1 times [2022-11-03 04:02:06,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 04:02:06,761 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892076998] [2022-11-03 04:02:06,761 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:02:06,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 04:08:59,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 04:08:59,814 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 04:14:17,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 04:14:17,819 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 04:14:17,821 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 04:14:17,823 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 04:14:17,825 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 04:14:17,829 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 04:14:17,833 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 04:14:17,939 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 04:14:17,940 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 04:14:18,026 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 04:14:18 BoogieIcfgContainer [2022-11-03 04:14:18,026 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 04:14:18,027 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 04:14:18,027 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 04:14:18,028 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 04:14:18,028 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 04:01:48" (3/4) ... [2022-11-03 04:14:18,032 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 04:14:18,032 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 04:14:18,033 INFO L158 Benchmark]: Toolchain (without parser) took 791775.41ms. Allocated memory was 113.2MB in the beginning and 4.1GB in the end (delta: 4.0GB). Free memory was 81.9MB in the beginning and 2.2GB in the end (delta: -2.1GB). Peak memory consumption was 1.9GB. Max. memory is 16.1GB. [2022-11-03 04:14:18,033 INFO L158 Benchmark]: CDTParser took 0.40ms. Allocated memory is still 113.2MB. Free memory is still 67.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 04:14:18,034 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1387.38ms. Allocated memory was 113.2MB in the beginning and 163.6MB in the end (delta: 50.3MB). Free memory was 81.7MB in the beginning and 120.4MB in the end (delta: -38.6MB). Peak memory consumption was 58.1MB. Max. memory is 16.1GB. [2022-11-03 04:14:18,034 INFO L158 Benchmark]: Boogie Procedure Inliner took 391.79ms. Allocated memory is still 163.6MB. Free memory was 120.4MB in the beginning and 88.1MB in the end (delta: 32.3MB). Peak memory consumption was 37.3MB. Max. memory is 16.1GB. [2022-11-03 04:14:18,035 INFO L158 Benchmark]: Boogie Preprocessor took 401.99ms. Allocated memory is still 163.6MB. Free memory was 88.1MB in the beginning and 86.8MB in the end (delta: 1.3MB). Peak memory consumption was 37.1MB. Max. memory is 16.1GB. [2022-11-03 04:14:18,036 INFO L158 Benchmark]: RCFGBuilder took 39897.89ms. Allocated memory was 163.6MB in the beginning and 1.5GB in the end (delta: 1.3GB). Free memory was 86.8MB in the beginning and 753.3MB in the end (delta: -666.5MB). Peak memory consumption was 889.0MB. Max. memory is 16.1GB. [2022-11-03 04:14:18,036 INFO L158 Benchmark]: TraceAbstraction took 749683.41ms. Allocated memory was 1.5GB in the beginning and 4.1GB in the end (delta: 2.6GB). Free memory was 752.3MB in the beginning and 2.2GB in the end (delta: -1.4GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. [2022-11-03 04:14:18,037 INFO L158 Benchmark]: Witness Printer took 4.80ms. Allocated memory is still 4.1GB. Free memory is still 2.2GB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 04:14:18,040 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.40ms. Allocated memory is still 113.2MB. Free memory is still 67.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1387.38ms. Allocated memory was 113.2MB in the beginning and 163.6MB in the end (delta: 50.3MB). Free memory was 81.7MB in the beginning and 120.4MB in the end (delta: -38.6MB). Peak memory consumption was 58.1MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 391.79ms. Allocated memory is still 163.6MB. Free memory was 120.4MB in the beginning and 88.1MB in the end (delta: 32.3MB). Peak memory consumption was 37.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 401.99ms. Allocated memory is still 163.6MB. Free memory was 88.1MB in the beginning and 86.8MB in the end (delta: 1.3MB). Peak memory consumption was 37.1MB. Max. memory is 16.1GB. * RCFGBuilder took 39897.89ms. Allocated memory was 163.6MB in the beginning and 1.5GB in the end (delta: 1.3GB). Free memory was 86.8MB in the beginning and 753.3MB in the end (delta: -666.5MB). Peak memory consumption was 889.0MB. Max. memory is 16.1GB. * TraceAbstraction took 749683.41ms. Allocated memory was 1.5GB in the beginning and 4.1GB in the end (delta: 2.6GB). Free memory was 752.3MB in the beginning and 2.2GB in the end (delta: -1.4GB). Peak memory consumption was 2.1GB. Max. memory is 16.1GB. * Witness Printer took 4.80ms. Allocated memory is still 4.1GB. Free memory is still 2.2GB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 314, overapproximation of bitwiseOr at line 496, overapproximation of bitwiseAnd at line 210. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 8); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (8 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 24); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (24 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_2 var_5 = 0; [L38] const SORT_1 var_30 = 0; [L39] const SORT_2 var_97 = 10; [L40] const SORT_2 var_100 = 4; [L41] const SORT_2 var_105 = 12; [L42] const SORT_2 var_108 = 2; [L43] const SORT_2 var_111 = 0; [L44] const SORT_2 var_116 = 15; [L45] const SORT_1 var_195 = 1; [L46] const SORT_4 var_198 = 1; [L47] const SORT_3 var_199 = 0; [L48] const SORT_4 var_202 = 2; [L49] const SORT_4 var_677 = 50; [L51] SORT_2 input_129; [L52] SORT_2 input_131; [L53] SORT_2 input_133; [L54] SORT_2 input_135; [L55] SORT_2 input_137; [L56] SORT_2 input_139; [L57] SORT_2 input_141; [L58] SORT_2 input_143; [L59] SORT_2 input_145; [L60] SORT_2 input_147; [L61] SORT_2 input_149; [L62] SORT_2 input_151; [L63] SORT_1 input_153; [L64] SORT_1 input_155; [L65] SORT_1 input_157; [L66] SORT_1 input_159; [L67] SORT_1 input_161; [L68] SORT_1 input_163; [L69] SORT_1 input_165; [L70] SORT_1 input_167; [L71] SORT_1 input_169; [L72] SORT_1 input_171; [L73] SORT_1 input_173; [L74] SORT_1 input_175; [L75] SORT_1 input_177; [L76] SORT_1 input_179; [L77] SORT_1 input_181; [L78] SORT_1 input_183; [L79] SORT_1 input_185; [L80] SORT_1 input_187; [L81] SORT_1 input_189; [L82] SORT_1 input_191; [L83] SORT_1 input_193; [L84] SORT_1 input_197; [L85] SORT_1 input_214; [L86] SORT_1 input_230; [L87] SORT_1 input_248; [L88] SORT_1 input_251; [L89] SORT_1 input_261; [L90] SORT_1 input_271; [L91] SORT_1 input_281; [L92] SORT_1 input_286; [L93] SORT_1 input_302; [L94] SORT_1 input_305; [L95] SORT_1 input_315; [L96] SORT_1 input_325; [L97] SORT_1 input_335; [L98] SORT_1 input_340; [L99] SORT_1 input_349; [L101] SORT_2 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L102] SORT_2 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L103] SORT_2 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L104] SORT_2 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L105] SORT_2 state_14 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L106] SORT_2 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L107] SORT_2 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L108] SORT_2 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L109] SORT_2 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L110] SORT_2 state_24 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L111] SORT_2 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L112] SORT_2 state_28 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L113] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L114] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L115] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L116] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L117] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L118] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L119] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L120] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L121] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L122] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L123] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L124] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L125] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L126] SORT_1 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L127] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L128] SORT_1 state_61 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L129] SORT_1 state_63 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L130] SORT_1 state_65 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L131] SORT_1 state_67 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L132] SORT_1 state_69 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L133] SORT_1 state_71 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L134] SORT_1 state_73 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L135] SORT_1 state_75 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L137] SORT_2 init_7_arg_1 = var_5; [L138] state_6 = init_7_arg_1 [L139] SORT_2 init_9_arg_1 = var_5; [L140] state_8 = init_9_arg_1 [L141] SORT_2 init_11_arg_1 = var_5; [L142] state_10 = init_11_arg_1 [L143] SORT_2 init_13_arg_1 = var_5; [L144] state_12 = init_13_arg_1 [L145] SORT_2 init_15_arg_1 = var_5; [L146] state_14 = init_15_arg_1 [L147] SORT_2 init_17_arg_1 = var_5; [L148] state_16 = init_17_arg_1 [L149] SORT_2 init_19_arg_1 = var_5; [L150] state_18 = init_19_arg_1 [L151] SORT_2 init_21_arg_1 = var_5; [L152] state_20 = init_21_arg_1 [L153] SORT_2 init_23_arg_1 = var_5; [L154] state_22 = init_23_arg_1 [L155] SORT_2 init_25_arg_1 = var_5; [L156] state_24 = init_25_arg_1 [L157] SORT_2 init_27_arg_1 = var_5; [L158] state_26 = init_27_arg_1 [L159] SORT_2 init_29_arg_1 = var_5; [L160] state_28 = init_29_arg_1 [L161] SORT_1 init_32_arg_1 = var_30; [L162] state_31 = init_32_arg_1 [L163] SORT_1 init_34_arg_1 = var_30; [L164] state_33 = init_34_arg_1 [L165] SORT_1 init_36_arg_1 = var_30; [L166] state_35 = init_36_arg_1 [L167] SORT_1 init_38_arg_1 = var_30; [L168] state_37 = init_38_arg_1 [L169] SORT_1 init_40_arg_1 = var_30; [L170] state_39 = init_40_arg_1 [L171] SORT_1 init_42_arg_1 = var_30; [L172] state_41 = init_42_arg_1 [L173] SORT_1 init_44_arg_1 = var_30; [L174] state_43 = init_44_arg_1 [L175] SORT_1 init_46_arg_1 = var_30; [L176] state_45 = init_46_arg_1 [L177] SORT_1 init_48_arg_1 = var_30; [L178] state_47 = init_48_arg_1 [L179] SORT_1 init_50_arg_1 = var_30; [L180] state_49 = init_50_arg_1 [L181] SORT_1 init_52_arg_1 = var_30; [L182] state_51 = init_52_arg_1 [L183] SORT_1 init_54_arg_1 = var_30; [L184] state_53 = init_54_arg_1 [L185] SORT_1 init_56_arg_1 = var_30; [L186] state_55 = init_56_arg_1 [L187] SORT_1 init_58_arg_1 = var_30; [L188] state_57 = init_58_arg_1 [L189] SORT_1 init_60_arg_1 = var_30; [L190] state_59 = init_60_arg_1 [L191] SORT_1 init_62_arg_1 = var_30; [L192] state_61 = init_62_arg_1 [L193] SORT_1 init_64_arg_1 = var_30; [L194] state_63 = init_64_arg_1 [L195] SORT_1 init_66_arg_1 = var_30; [L196] state_65 = init_66_arg_1 [L197] SORT_1 init_68_arg_1 = var_30; [L198] state_67 = init_68_arg_1 [L199] SORT_1 init_70_arg_1 = var_30; [L200] state_69 = init_70_arg_1 [L201] SORT_1 init_72_arg_1 = var_30; [L202] state_71 = init_72_arg_1 [L203] SORT_1 init_74_arg_1 = var_30; [L204] state_73 = init_74_arg_1 [L205] SORT_1 init_76_arg_1 = var_30; [L206] state_75 = init_76_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_76_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_57=0, state_59=0, state_6=0, state_61=0, state_63=0, state_65=0, state_67=0, state_69=0, state_71=0, state_73=0, state_75=0, state_8=0, var_100=4, var_105=12, var_108=2, var_111=0, var_116=15, var_195=1, var_198=1, var_199=0, var_202=2, var_30=0, var_5=0, var_677=50, var_97=10] [L209] input_129 = __VERIFIER_nondet_uchar() [L210] input_129 = input_129 & mask_SORT_2 [L211] input_131 = __VERIFIER_nondet_uchar() [L212] input_131 = input_131 & mask_SORT_2 [L213] input_133 = __VERIFIER_nondet_uchar() [L214] input_133 = input_133 & mask_SORT_2 [L215] input_135 = __VERIFIER_nondet_uchar() [L216] input_135 = input_135 & mask_SORT_2 [L217] input_137 = __VERIFIER_nondet_uchar() [L218] input_137 = input_137 & mask_SORT_2 [L219] input_139 = __VERIFIER_nondet_uchar() [L220] input_139 = input_139 & mask_SORT_2 [L221] input_141 = __VERIFIER_nondet_uchar() [L222] input_141 = input_141 & mask_SORT_2 [L223] input_143 = __VERIFIER_nondet_uchar() [L224] input_143 = input_143 & mask_SORT_2 [L225] input_145 = __VERIFIER_nondet_uchar() [L226] input_145 = input_145 & mask_SORT_2 [L227] input_147 = __VERIFIER_nondet_uchar() [L228] input_147 = input_147 & mask_SORT_2 [L229] input_149 = __VERIFIER_nondet_uchar() [L230] input_149 = input_149 & mask_SORT_2 [L231] input_151 = __VERIFIER_nondet_uchar() [L232] input_151 = input_151 & mask_SORT_2 [L233] input_153 = __VERIFIER_nondet_uchar() [L234] input_153 = input_153 & mask_SORT_1 [L235] input_155 = __VERIFIER_nondet_uchar() [L236] input_155 = input_155 & mask_SORT_1 [L237] input_157 = __VERIFIER_nondet_uchar() [L238] input_157 = input_157 & mask_SORT_1 [L239] input_159 = __VERIFIER_nondet_uchar() [L240] input_159 = input_159 & mask_SORT_1 [L241] input_161 = __VERIFIER_nondet_uchar() [L242] input_161 = input_161 & mask_SORT_1 [L243] input_163 = __VERIFIER_nondet_uchar() [L244] input_163 = input_163 & mask_SORT_1 [L245] input_165 = __VERIFIER_nondet_uchar() [L246] input_165 = input_165 & mask_SORT_1 [L247] input_167 = __VERIFIER_nondet_uchar() [L248] input_167 = input_167 & mask_SORT_1 [L249] input_169 = __VERIFIER_nondet_uchar() [L250] input_169 = input_169 & mask_SORT_1 [L251] input_171 = __VERIFIER_nondet_uchar() [L252] input_171 = input_171 & mask_SORT_1 [L253] input_173 = __VERIFIER_nondet_uchar() [L254] input_173 = input_173 & mask_SORT_1 [L255] input_175 = __VERIFIER_nondet_uchar() [L256] input_175 = input_175 & mask_SORT_1 [L257] input_177 = __VERIFIER_nondet_uchar() [L258] input_177 = input_177 & mask_SORT_1 [L259] input_179 = __VERIFIER_nondet_uchar() [L260] input_179 = input_179 & mask_SORT_1 [L261] input_181 = __VERIFIER_nondet_uchar() [L262] input_181 = input_181 & mask_SORT_1 [L263] input_183 = __VERIFIER_nondet_uchar() [L264] input_183 = input_183 & mask_SORT_1 [L265] input_185 = __VERIFIER_nondet_uchar() [L266] input_185 = input_185 & mask_SORT_1 [L267] input_187 = __VERIFIER_nondet_uchar() [L268] input_187 = input_187 & mask_SORT_1 [L269] input_189 = __VERIFIER_nondet_uchar() [L270] input_189 = input_189 & mask_SORT_1 [L271] input_191 = __VERIFIER_nondet_uchar() [L272] input_191 = input_191 & mask_SORT_1 [L273] input_193 = __VERIFIER_nondet_uchar() [L274] input_193 = input_193 & mask_SORT_1 [L275] input_197 = __VERIFIER_nondet_uchar() [L276] input_197 = input_197 & mask_SORT_1 [L277] input_214 = __VERIFIER_nondet_uchar() [L278] input_214 = input_214 & mask_SORT_1 [L279] input_230 = __VERIFIER_nondet_uchar() [L280] input_230 = input_230 & mask_SORT_1 [L281] input_248 = __VERIFIER_nondet_uchar() [L282] input_251 = __VERIFIER_nondet_uchar() [L283] input_251 = input_251 & mask_SORT_1 [L284] input_261 = __VERIFIER_nondet_uchar() [L285] input_261 = input_261 & mask_SORT_1 [L286] input_271 = __VERIFIER_nondet_uchar() [L287] input_271 = input_271 & mask_SORT_1 [L288] input_281 = __VERIFIER_nondet_uchar() [L289] input_281 = input_281 & mask_SORT_1 [L290] input_286 = __VERIFIER_nondet_uchar() [L291] input_286 = input_286 & mask_SORT_1 [L292] input_302 = __VERIFIER_nondet_uchar() [L293] input_305 = __VERIFIER_nondet_uchar() [L294] input_305 = input_305 & mask_SORT_1 [L295] input_315 = __VERIFIER_nondet_uchar() [L296] input_315 = input_315 & mask_SORT_1 [L297] input_325 = __VERIFIER_nondet_uchar() [L298] input_325 = input_325 & mask_SORT_1 [L299] input_335 = __VERIFIER_nondet_uchar() [L300] input_335 = input_335 & mask_SORT_1 [L301] input_340 = __VERIFIER_nondet_uchar() [L302] input_340 = input_340 & mask_SORT_1 [L303] input_349 = __VERIFIER_nondet_uchar() [L304] input_349 = input_349 & mask_SORT_1 [L307] SORT_1 var_77_arg_0 = state_31; [L308] SORT_1 var_77_arg_1 = state_33; [L309] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L310] SORT_1 var_78_arg_0 = var_77; [L311] SORT_1 var_78_arg_1 = state_35; [L312] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L313] SORT_1 var_79_arg_0 = var_78; [L314] SORT_1 var_79_arg_1 = ~state_37; [L315] var_79_arg_1 = var_79_arg_1 & mask_SORT_1 [L316] SORT_1 var_79 = var_79_arg_0 & var_79_arg_1; [L317] SORT_1 var_80_arg_0 = var_79; [L318] SORT_1 var_80_arg_1 = ~state_39; [L319] var_80_arg_1 = var_80_arg_1 & mask_SORT_1 [L320] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L321] SORT_1 var_81_arg_0 = var_80; [L322] SORT_1 var_81_arg_1 = ~state_41; [L323] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L324] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L325] SORT_1 var_82_arg_0 = var_81; [L326] SORT_1 var_82_arg_1 = ~state_43; [L327] var_82_arg_1 = var_82_arg_1 & mask_SORT_1 [L328] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L329] SORT_1 var_83_arg_0 = var_82; [L330] SORT_1 var_83_arg_1 = ~state_45; [L331] var_83_arg_1 = var_83_arg_1 & mask_SORT_1 [L332] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L333] SORT_1 var_84_arg_0 = var_83; [L334] SORT_1 var_84_arg_1 = ~state_47; [L335] var_84_arg_1 = var_84_arg_1 & mask_SORT_1 [L336] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L337] SORT_1 var_85_arg_0 = var_84; [L338] SORT_1 var_85_arg_1 = ~state_49; [L339] var_85_arg_1 = var_85_arg_1 & mask_SORT_1 [L340] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L341] SORT_1 var_86_arg_0 = var_85; [L342] SORT_1 var_86_arg_1 = state_51; [L343] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L344] SORT_1 var_87_arg_0 = var_86; [L345] SORT_1 var_87_arg_1 = ~state_53; [L346] var_87_arg_1 = var_87_arg_1 & mask_SORT_1 [L347] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L348] SORT_1 var_88_arg_0 = var_87; [L349] SORT_1 var_88_arg_1 = ~state_55; [L350] var_88_arg_1 = var_88_arg_1 & mask_SORT_1 [L351] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L352] SORT_1 var_89_arg_0 = var_88; [L353] SORT_1 var_89_arg_1 = ~state_57; [L354] var_89_arg_1 = var_89_arg_1 & mask_SORT_1 [L355] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L356] SORT_1 var_90_arg_0 = var_89; [L357] SORT_1 var_90_arg_1 = ~state_59; [L358] var_90_arg_1 = var_90_arg_1 & mask_SORT_1 [L359] SORT_1 var_90 = var_90_arg_0 & var_90_arg_1; [L360] SORT_1 var_91_arg_0 = var_90; [L361] SORT_1 var_91_arg_1 = ~state_61; [L362] var_91_arg_1 = var_91_arg_1 & mask_SORT_1 [L363] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L364] SORT_1 var_92_arg_0 = var_91; [L365] SORT_1 var_92_arg_1 = ~state_63; [L366] var_92_arg_1 = var_92_arg_1 & mask_SORT_1 [L367] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L368] SORT_1 var_93_arg_0 = var_92; [L369] SORT_1 var_93_arg_1 = ~state_65; [L370] var_93_arg_1 = var_93_arg_1 & mask_SORT_1 [L371] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L372] SORT_1 var_94_arg_0 = var_93; [L373] SORT_1 var_94_arg_1 = state_67; [L374] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L375] SORT_1 var_95_arg_0 = var_94; [L376] SORT_1 var_95_arg_1 = state_69; [L377] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L378] SORT_1 var_96_arg_0 = var_95; [L379] SORT_1 var_96_arg_1 = state_71; [L380] SORT_1 var_96 = var_96_arg_0 & var_96_arg_1; [L381] SORT_2 var_98_arg_0 = var_97; [L382] SORT_2 var_98_arg_1 = state_6; [L383] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L384] SORT_1 var_99_arg_0 = var_96; [L385] SORT_1 var_99_arg_1 = var_98; [L386] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L387] SORT_2 var_101_arg_0 = var_100; [L388] SORT_2 var_101_arg_1 = state_8; [L389] SORT_1 var_101 = var_101_arg_0 == var_101_arg_1; [L390] SORT_1 var_102_arg_0 = var_99; [L391] SORT_1 var_102_arg_1 = var_101; [L392] SORT_1 var_102 = var_102_arg_0 & var_102_arg_1; [L393] SORT_2 var_103_arg_0 = var_100; [L394] SORT_2 var_103_arg_1 = state_10; [L395] SORT_1 var_103 = var_103_arg_0 == var_103_arg_1; [L396] SORT_1 var_104_arg_0 = var_102; [L397] SORT_1 var_104_arg_1 = var_103; [L398] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L399] SORT_2 var_106_arg_0 = var_105; [L400] SORT_2 var_106_arg_1 = state_12; [L401] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L402] SORT_1 var_107_arg_0 = var_104; [L403] SORT_1 var_107_arg_1 = var_106; [L404] SORT_1 var_107 = var_107_arg_0 & var_107_arg_1; [L405] SORT_2 var_109_arg_0 = var_108; [L406] SORT_2 var_109_arg_1 = state_14; [L407] SORT_1 var_109 = var_109_arg_0 == var_109_arg_1; [L408] SORT_1 var_110_arg_0 = var_107; [L409] SORT_1 var_110_arg_1 = var_109; [L410] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L411] SORT_2 var_112_arg_0 = var_111; [L412] SORT_2 var_112_arg_1 = state_16; [L413] SORT_1 var_112 = var_112_arg_0 == var_112_arg_1; [L414] SORT_1 var_113_arg_0 = var_110; [L415] SORT_1 var_113_arg_1 = var_112; [L416] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L417] SORT_2 var_114_arg_0 = var_111; [L418] SORT_2 var_114_arg_1 = state_18; [L419] SORT_1 var_114 = var_114_arg_0 == var_114_arg_1; [L420] SORT_1 var_115_arg_0 = var_113; [L421] SORT_1 var_115_arg_1 = var_114; [L422] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L423] SORT_2 var_117_arg_0 = var_116; [L424] SORT_2 var_117_arg_1 = state_20; [L425] SORT_1 var_117 = var_117_arg_0 == var_117_arg_1; [L426] SORT_1 var_118_arg_0 = var_115; [L427] SORT_1 var_118_arg_1 = var_117; [L428] SORT_1 var_118 = var_118_arg_0 & var_118_arg_1; [L429] SORT_2 var_119_arg_0 = var_111; [L430] SORT_2 var_119_arg_1 = state_22; [L431] SORT_1 var_119 = var_119_arg_0 == var_119_arg_1; [L432] SORT_1 var_120_arg_0 = var_118; [L433] SORT_1 var_120_arg_1 = var_119; [L434] SORT_1 var_120 = var_120_arg_0 & var_120_arg_1; [L435] SORT_2 var_121_arg_0 = var_97; [L436] SORT_2 var_121_arg_1 = state_24; [L437] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L438] SORT_1 var_122_arg_0 = var_120; [L439] SORT_1 var_122_arg_1 = var_121; [L440] SORT_1 var_122 = var_122_arg_0 & var_122_arg_1; [L441] SORT_2 var_123_arg_0 = var_97; [L442] SORT_2 var_123_arg_1 = state_26; [L443] SORT_1 var_123 = var_123_arg_0 == var_123_arg_1; [L444] SORT_1 var_124_arg_0 = var_122; [L445] SORT_1 var_124_arg_1 = var_123; [L446] SORT_1 var_124 = var_124_arg_0 & var_124_arg_1; [L447] SORT_2 var_125_arg_0 = var_111; [L448] SORT_2 var_125_arg_1 = state_28; [L449] SORT_1 var_125 = var_125_arg_0 == var_125_arg_1; [L450] SORT_1 var_126_arg_0 = var_124; [L451] SORT_1 var_126_arg_1 = var_125; [L452] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L453] SORT_1 var_127_arg_0 = state_75; [L454] SORT_1 var_127_arg_1 = var_126; [L455] SORT_1 var_127 = var_127_arg_0 & var_127_arg_1; [L456] var_127 = var_127 & mask_SORT_1 [L457] SORT_1 bad_128_arg_0 = var_127; [L458] CALL __VERIFIER_assert(!(bad_128_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L458] RET __VERIFIER_assert(!(bad_128_arg_0)) [L460] SORT_2 next_130_arg_1 = input_129; [L461] SORT_2 next_132_arg_1 = input_131; [L462] SORT_2 next_134_arg_1 = input_133; [L463] SORT_2 next_136_arg_1 = input_135; [L464] SORT_2 next_138_arg_1 = input_137; [L465] SORT_2 next_140_arg_1 = input_139; [L466] SORT_2 next_142_arg_1 = input_141; [L467] SORT_2 next_144_arg_1 = input_143; [L468] SORT_2 next_146_arg_1 = input_145; [L469] SORT_2 next_148_arg_1 = input_147; [L470] SORT_2 next_150_arg_1 = input_149; [L471] SORT_2 next_152_arg_1 = input_151; [L472] SORT_1 next_154_arg_1 = input_153; [L473] SORT_1 next_156_arg_1 = input_155; [L474] SORT_1 next_158_arg_1 = input_157; [L475] SORT_1 next_160_arg_1 = input_159; [L476] SORT_1 next_162_arg_1 = input_161; [L477] SORT_1 next_164_arg_1 = input_163; [L478] SORT_1 next_166_arg_1 = input_165; [L479] SORT_1 next_168_arg_1 = input_167; [L480] SORT_1 next_170_arg_1 = input_169; [L481] SORT_1 next_172_arg_1 = input_171; [L482] SORT_1 next_174_arg_1 = input_173; [L483] SORT_1 next_176_arg_1 = input_175; [L484] SORT_1 next_178_arg_1 = input_177; [L485] SORT_1 next_180_arg_1 = input_179; [L486] SORT_1 next_182_arg_1 = input_181; [L487] SORT_1 next_184_arg_1 = input_183; [L488] SORT_1 next_186_arg_1 = input_185; [L489] SORT_1 next_188_arg_1 = input_187; [L490] SORT_1 next_190_arg_1 = input_189; [L491] SORT_1 next_192_arg_1 = input_191; [L492] SORT_1 next_194_arg_1 = input_193; [L493] SORT_1 next_196_arg_1 = var_195; [L494] SORT_3 var_200_arg_0 = var_199; [L495] SORT_2 var_200_arg_1 = input_129; [L496] SORT_4 var_200 = ((SORT_4)var_200_arg_0 << 8) | var_200_arg_1; [L497] var_200 = var_200 & mask_SORT_4 [L498] SORT_4 var_201_arg_0 = var_198; [L499] SORT_4 var_201_arg_1 = var_200; [L500] SORT_1 var_201 = var_201_arg_0 <= var_201_arg_1; [L501] SORT_3 var_203_arg_0 = var_199; [L502] SORT_2 var_203_arg_1 = input_131; [L503] SORT_4 var_203 = ((SORT_4)var_203_arg_0 << 8) | var_203_arg_1; [L504] var_203 = var_203 & mask_SORT_4 [L505] SORT_4 var_204_arg_0 = var_202; [L506] SORT_4 var_204_arg_1 = var_203; [L507] SORT_1 var_204 = var_204_arg_0 <= var_204_arg_1; [L508] SORT_1 var_205_arg_0 = var_201; [L509] SORT_1 var_205_arg_1 = var_204; [L510] SORT_1 var_205 = var_205_arg_0 & var_205_arg_1; [L511] SORT_3 var_206_arg_0 = var_199; [L512] SORT_2 var_206_arg_1 = input_133; [L513] SORT_4 var_206 = ((SORT_4)var_206_arg_0 << 8) | var_206_arg_1; [L514] var_206 = var_206 & mask_SORT_4 [L515] SORT_4 var_207_arg_0 = var_202; [L516] SORT_4 var_207_arg_1 = var_206; [L517] SORT_1 var_207 = var_207_arg_0 <= var_207_arg_1; [L518] SORT_1 var_208_arg_0 = var_205; [L519] SORT_1 var_208_arg_1 = var_207; [L520] SORT_1 var_208 = var_208_arg_0 & var_208_arg_1; [L521] SORT_3 var_209_arg_0 = var_199; [L522] SORT_2 var_209_arg_1 = input_135; [L523] SORT_4 var_209 = ((SORT_4)var_209_arg_0 << 8) | var_209_arg_1; [L524] var_209 = var_209 & mask_SORT_4 [L525] SORT_4 var_210_arg_0 = var_202; [L526] SORT_4 var_210_arg_1 = var_209; [L527] SORT_1 var_210 = var_210_arg_0 <= var_210_arg_1; [L528] SORT_1 var_211_arg_0 = var_208; [L529] SORT_1 var_211_arg_1 = var_210; [L530] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L531] SORT_1 var_212_arg_0 = input_153; [L532] SORT_1 var_212_arg_1 = var_211; [L533] SORT_1 var_212 = var_212_arg_0 & var_212_arg_1; [L534] SORT_1 var_213_arg_0 = ~input_197; [L535] var_213_arg_0 = var_213_arg_0 & mask_SORT_1 [L536] SORT_1 var_213_arg_1 = var_212; [L537] SORT_1 var_213 = var_213_arg_0 | var_213_arg_1; [L538] SORT_3 var_215_arg_0 = var_199; [L539] SORT_2 var_215_arg_1 = input_139; [L540] SORT_4 var_215 = ((SORT_4)var_215_arg_0 << 8) | var_215_arg_1; [L541] SORT_4 var_216_arg_0 = var_202; [L542] SORT_4 var_216_arg_1 = var_215; [L543] SORT_4 var_216 = var_216_arg_0 + var_216_arg_1; [L544] SORT_4 var_217_arg_0 = var_216; [L545] SORT_2 var_217 = var_217_arg_0 >> 0; [L546] SORT_1 var_218_arg_0 = input_197; [L547] SORT_2 var_218_arg_1 = var_217; [L548] SORT_2 var_218_arg_2 = input_139; [L549] EXPR var_218_arg_0 ? var_218_arg_1 : var_218_arg_2 [L549] SORT_2 var_218 = var_218_arg_0 ? var_218_arg_1 : var_218_arg_2; [L550] var_218 = var_218 & mask_SORT_2 [L551] SORT_3 var_219_arg_0 = var_199; [L552] SORT_2 var_219_arg_1 = var_218; [L553] SORT_4 var_219 = ((SORT_4)var_219_arg_0 << 8) | var_219_arg_1; [L554] var_219 = var_219 & mask_SORT_4 [L555] SORT_4 var_220_arg_0 = var_198; [L556] SORT_4 var_220_arg_1 = var_219; [L557] SORT_1 var_220 = var_220_arg_0 <= var_220_arg_1; [L558] SORT_4 var_221_arg_0 = var_209; [L559] SORT_4 var_221_arg_1 = var_202; [L560] SORT_4 var_221 = var_221_arg_0 - var_221_arg_1; [L561] SORT_4 var_222_arg_0 = var_221; [L562] SORT_2 var_222 = var_222_arg_0 >> 0; [L563] SORT_1 var_223_arg_0 = input_197; [L564] SORT_2 var_223_arg_1 = var_222; [L565] SORT_2 var_223_arg_2 = input_135; [L566] EXPR var_223_arg_0 ? var_223_arg_1 : var_223_arg_2 [L566] SORT_2 var_223 = var_223_arg_0 ? var_223_arg_1 : var_223_arg_2; [L567] var_223 = var_223 & mask_SORT_2 [L568] SORT_3 var_224_arg_0 = var_199; [L569] SORT_2 var_224_arg_1 = var_223; [L570] SORT_4 var_224 = ((SORT_4)var_224_arg_0 << 8) | var_224_arg_1; [L571] var_224 = var_224 & mask_SORT_4 [L572] SORT_4 var_225_arg_0 = var_198; [L573] SORT_4 var_225_arg_1 = var_224; [L574] SORT_1 var_225 = var_225_arg_0 <= var_225_arg_1; [L575] SORT_1 var_226_arg_0 = var_220; [L576] SORT_1 var_226_arg_1 = var_225; [L577] SORT_1 var_226 = var_226_arg_0 & var_226_arg_1; [L578] SORT_1 var_227_arg_0 = input_155; [L579] SORT_1 var_227_arg_1 = var_226; [L580] SORT_1 var_227 = var_227_arg_0 & var_227_arg_1; [L581] SORT_1 var_228_arg_0 = ~input_214; [L582] var_228_arg_0 = var_228_arg_0 & mask_SORT_1 [L583] SORT_1 var_228_arg_1 = var_227; [L584] SORT_1 var_228 = var_228_arg_0 | var_228_arg_1; [L585] SORT_1 var_229_arg_0 = var_213; [L586] SORT_1 var_229_arg_1 = var_228; [L587] SORT_1 var_229 = var_229_arg_0 & var_229_arg_1; [L588] SORT_3 var_231_arg_0 = var_199; [L589] SORT_2 var_231_arg_1 = input_141; [L590] SORT_4 var_231 = ((SORT_4)var_231_arg_0 << 8) | var_231_arg_1; [L591] SORT_4 var_232_arg_0 = var_198; [L592] SORT_4 var_232_arg_1 = var_231; [L593] SORT_4 var_232 = var_232_arg_0 + var_232_arg_1; [L594] SORT_4 var_233_arg_0 = var_232; [L595] SORT_2 var_233 = var_233_arg_0 >> 0; [L596] SORT_1 var_234_arg_0 = input_214; [L597] SORT_2 var_234_arg_1 = var_233; [L598] SORT_2 var_234_arg_2 = input_141; [L599] EXPR var_234_arg_0 ? var_234_arg_1 : var_234_arg_2 [L599] SORT_2 var_234 = var_234_arg_0 ? var_234_arg_1 : var_234_arg_2; [L600] var_234 = var_234 & mask_SORT_2 [L601] SORT_3 var_235_arg_0 = var_199; [L602] SORT_2 var_235_arg_1 = var_234; [L603] SORT_4 var_235 = ((SORT_4)var_235_arg_0 << 8) | var_235_arg_1; [L604] var_235 = var_235 & mask_SORT_4 [L605] SORT_4 var_236_arg_0 = var_198; [L606] SORT_4 var_236_arg_1 = var_235; [L607] SORT_1 var_236 = var_236_arg_0 <= var_236_arg_1; [L608] SORT_3 var_237_arg_0 = var_199; [L609] SORT_2 var_237_arg_1 = input_149; [L610] SORT_4 var_237 = ((SORT_4)var_237_arg_0 << 8) | var_237_arg_1; [L611] SORT_4 var_238_arg_0 = var_202; [L612] SORT_4 var_238_arg_1 = var_237; [L613] SORT_4 var_238 = var_238_arg_0 + var_238_arg_1; [L614] SORT_4 var_239_arg_0 = var_238; [L615] SORT_2 var_239 = var_239_arg_0 >> 0; [L616] SORT_1 var_240_arg_0 = input_197; [L617] SORT_2 var_240_arg_1 = var_239; [L618] SORT_2 var_240_arg_2 = input_149; [L619] EXPR var_240_arg_0 ? var_240_arg_1 : var_240_arg_2 [L619] SORT_2 var_240 = var_240_arg_0 ? var_240_arg_1 : var_240_arg_2; [L620] var_240 = var_240 & mask_SORT_2 [L621] SORT_3 var_241_arg_0 = var_199; [L622] SORT_2 var_241_arg_1 = var_240; [L623] SORT_4 var_241 = ((SORT_4)var_241_arg_0 << 8) | var_241_arg_1; [L624] var_241 = var_241 & mask_SORT_4 [L625] SORT_4 var_242_arg_0 = var_198; [L626] SORT_4 var_242_arg_1 = var_241; [L627] SORT_1 var_242 = var_242_arg_0 <= var_242_arg_1; [L628] SORT_1 var_243_arg_0 = var_236; [L629] SORT_1 var_243_arg_1 = var_242; [L630] SORT_1 var_243 = var_243_arg_0 & var_243_arg_1; [L631] SORT_1 var_244_arg_0 = input_157; [L632] SORT_1 var_244_arg_1 = var_243; [L633] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L634] SORT_1 var_245_arg_0 = ~input_230; [L635] var_245_arg_0 = var_245_arg_0 & mask_SORT_1 [L636] SORT_1 var_245_arg_1 = var_244; [L637] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L638] SORT_1 var_246_arg_0 = var_229; [L639] SORT_1 var_246_arg_1 = var_245; [L640] SORT_1 var_246 = var_246_arg_0 & var_246_arg_1; [L641] SORT_1 var_247_arg_0 = input_159; [L642] SORT_1 var_247_arg_1 = input_230; [L643] SORT_1 var_247 = var_247_arg_0 | var_247_arg_1; [L644] SORT_1 var_249_arg_0 = var_247; [L645] SORT_1 var_249_arg_1 = ~input_248; [L646] var_249_arg_1 = var_249_arg_1 & mask_SORT_1 [L647] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L648] SORT_1 var_250_arg_0 = var_246; [L649] SORT_1 var_250_arg_1 = var_249; [L650] SORT_1 var_250 = var_250_arg_0 & var_250_arg_1; [L651] SORT_1 var_252_arg_0 = input_161; [L652] SORT_1 var_252_arg_1 = input_248; [L653] SORT_1 var_252 = var_252_arg_0 | var_252_arg_1; [L654] SORT_4 var_253_arg_0 = var_224; [L655] SORT_4 var_253_arg_1 = var_198; [L656] SORT_4 var_253 = var_253_arg_0 - var_253_arg_1; [L657] SORT_4 var_254_arg_0 = var_253; [L658] SORT_2 var_254 = var_254_arg_0 >> 0; [L659] SORT_1 var_255_arg_0 = input_214; [L660] SORT_2 var_255_arg_1 = var_254; [L661] SORT_2 var_255_arg_2 = var_223; [L662] EXPR var_255_arg_0 ? var_255_arg_1 : var_255_arg_2 [L662] SORT_2 var_255 = var_255_arg_0 ? var_255_arg_1 : var_255_arg_2; [L663] var_255 = var_255 & mask_SORT_2 [L664] SORT_3 var_256_arg_0 = var_199; [L665] SORT_2 var_256_arg_1 = var_255; [L666] SORT_4 var_256 = ((SORT_4)var_256_arg_0 << 8) | var_256_arg_1; [L667] var_256 = var_256 & mask_SORT_4 [L668] SORT_4 var_257_arg_0 = var_198; [L669] SORT_4 var_257_arg_1 = var_256; [L670] SORT_1 var_257 = var_257_arg_0 <= var_257_arg_1; [L671] SORT_1 var_258_arg_0 = var_252; [L672] SORT_1 var_258_arg_1 = var_257; [L673] SORT_1 var_258 = var_258_arg_0 & var_258_arg_1; [L674] SORT_1 var_259_arg_0 = ~input_251; [L675] var_259_arg_0 = var_259_arg_0 & mask_SORT_1 [L676] SORT_1 var_259_arg_1 = var_258; [L677] SORT_1 var_259 = var_259_arg_0 | var_259_arg_1; [L678] SORT_1 var_260_arg_0 = var_250; [L679] SORT_1 var_260_arg_1 = var_259; [L680] SORT_1 var_260 = var_260_arg_0 & var_260_arg_1; [L681] SORT_1 var_262_arg_0 = input_163; [L682] SORT_1 var_262_arg_1 = input_251; [L683] SORT_1 var_262 = var_262_arg_0 | var_262_arg_1; [L684] SORT_4 var_263_arg_0 = var_256; [L685] SORT_4 var_263_arg_1 = var_198; [L686] SORT_4 var_263 = var_263_arg_0 - var_263_arg_1; [L687] SORT_4 var_264_arg_0 = var_263; [L688] SORT_2 var_264 = var_264_arg_0 >> 0; [L689] SORT_1 var_265_arg_0 = input_251; [L690] SORT_2 var_265_arg_1 = var_264; [L691] SORT_2 var_265_arg_2 = var_255; [L692] EXPR var_265_arg_0 ? var_265_arg_1 : var_265_arg_2 [L692] SORT_2 var_265 = var_265_arg_0 ? var_265_arg_1 : var_265_arg_2; [L693] var_265 = var_265 & mask_SORT_2 [L694] SORT_3 var_266_arg_0 = var_199; [L695] SORT_2 var_266_arg_1 = var_265; [L696] SORT_4 var_266 = ((SORT_4)var_266_arg_0 << 8) | var_266_arg_1; [L697] var_266 = var_266 & mask_SORT_4 [L698] SORT_4 var_267_arg_0 = var_198; [L699] SORT_4 var_267_arg_1 = var_266; [L700] SORT_1 var_267 = var_267_arg_0 <= var_267_arg_1; [L701] SORT_1 var_268_arg_0 = var_262; [L702] SORT_1 var_268_arg_1 = var_267; [L703] SORT_1 var_268 = var_268_arg_0 & var_268_arg_1; [L704] SORT_1 var_269_arg_0 = ~input_261; [L705] var_269_arg_0 = var_269_arg_0 & mask_SORT_1 [L706] SORT_1 var_269_arg_1 = var_268; [L707] SORT_1 var_269 = var_269_arg_0 | var_269_arg_1; [L708] SORT_1 var_270_arg_0 = var_260; [L709] SORT_1 var_270_arg_1 = var_269; [L710] SORT_1 var_270 = var_270_arg_0 & var_270_arg_1; [L711] SORT_1 var_272_arg_0 = input_169; [L712] SORT_1 var_272_arg_1 = input_261; [L713] SORT_1 var_272 = var_272_arg_0 | var_272_arg_1; [L714] SORT_4 var_273_arg_0 = var_241; [L715] SORT_4 var_273_arg_1 = var_198; [L716] SORT_4 var_273 = var_273_arg_0 - var_273_arg_1; [L717] SORT_4 var_274_arg_0 = var_273; [L718] SORT_2 var_274 = var_274_arg_0 >> 0; [L719] SORT_1 var_275_arg_0 = input_230; [L720] SORT_2 var_275_arg_1 = var_274; [L721] SORT_2 var_275_arg_2 = var_240; [L722] EXPR var_275_arg_0 ? var_275_arg_1 : var_275_arg_2 [L722] SORT_2 var_275 = var_275_arg_0 ? var_275_arg_1 : var_275_arg_2; [L723] var_275 = var_275 & mask_SORT_2 [L724] SORT_3 var_276_arg_0 = var_199; [L725] SORT_2 var_276_arg_1 = var_275; [L726] SORT_4 var_276 = ((SORT_4)var_276_arg_0 << 8) | var_276_arg_1; [L727] var_276 = var_276 & mask_SORT_4 [L728] SORT_4 var_277_arg_0 = var_198; [L729] SORT_4 var_277_arg_1 = var_276; [L730] SORT_1 var_277 = var_277_arg_0 <= var_277_arg_1; [L731] SORT_1 var_278_arg_0 = var_272; [L732] SORT_1 var_278_arg_1 = var_277; [L733] SORT_1 var_278 = var_278_arg_0 & var_278_arg_1; [L734] SORT_1 var_279_arg_0 = ~input_271; [L735] var_279_arg_0 = var_279_arg_0 & mask_SORT_1 [L736] SORT_1 var_279_arg_1 = var_278; [L737] SORT_1 var_279 = var_279_arg_0 | var_279_arg_1; [L738] SORT_1 var_280_arg_0 = var_270; [L739] SORT_1 var_280_arg_1 = var_279; [L740] SORT_1 var_280 = var_280_arg_0 & var_280_arg_1; [L741] SORT_1 var_282_arg_0 = input_171; [L742] SORT_1 var_282_arg_1 = input_271; [L743] SORT_1 var_282 = var_282_arg_0 | var_282_arg_1; [L744] SORT_1 var_283_arg_0 = var_267; [L745] SORT_1 var_283_arg_1 = var_282; [L746] SORT_1 var_283 = var_283_arg_0 & var_283_arg_1; [L747] SORT_1 var_284_arg_0 = ~input_281; [L748] var_284_arg_0 = var_284_arg_0 & mask_SORT_1 [L749] SORT_1 var_284_arg_1 = var_283; [L750] SORT_1 var_284 = var_284_arg_0 | var_284_arg_1; [L751] SORT_1 var_285_arg_0 = var_280; [L752] SORT_1 var_285_arg_1 = var_284; [L753] SORT_1 var_285 = var_285_arg_0 & var_285_arg_1; [L754] SORT_4 var_287_arg_0 = var_235; [L755] SORT_4 var_287_arg_1 = var_198; [L756] SORT_4 var_287 = var_287_arg_0 - var_287_arg_1; [L757] SORT_4 var_288_arg_0 = var_287; [L758] SORT_2 var_288 = var_288_arg_0 >> 0; [L759] SORT_1 var_289_arg_0 = input_230; [L760] SORT_2 var_289_arg_1 = var_288; [L761] SORT_2 var_289_arg_2 = var_234; [L762] EXPR var_289_arg_0 ? var_289_arg_1 : var_289_arg_2 [L762] SORT_2 var_289 = var_289_arg_0 ? var_289_arg_1 : var_289_arg_2; [L763] var_289 = var_289 & mask_SORT_2 [L764] SORT_3 var_290_arg_0 = var_199; [L765] SORT_2 var_290_arg_1 = var_289; [L766] SORT_4 var_290 = ((SORT_4)var_290_arg_0 << 8) | var_290_arg_1; [L767] var_290 = var_290 & mask_SORT_4 [L768] SORT_4 var_291_arg_0 = var_198; [L769] SORT_4 var_291_arg_1 = var_290; [L770] SORT_1 var_291 = var_291_arg_0 <= var_291_arg_1; [L771] SORT_4 var_292_arg_0 = var_276; [L772] SORT_4 var_292_arg_1 = var_198; [L773] SORT_4 var_292 = var_292_arg_0 - var_292_arg_1; [L774] SORT_4 var_293_arg_0 = var_292; [L775] SORT_2 var_293 = var_293_arg_0 >> 0; [L776] SORT_1 var_294_arg_0 = input_271; [L777] SORT_2 var_294_arg_1 = var_293; [L778] SORT_2 var_294_arg_2 = var_275; [L779] EXPR var_294_arg_0 ? var_294_arg_1 : var_294_arg_2 [L779] SORT_2 var_294 = var_294_arg_0 ? var_294_arg_1 : var_294_arg_2; [L780] var_294 = var_294 & mask_SORT_2 [L781] SORT_3 var_295_arg_0 = var_199; [L782] SORT_2 var_295_arg_1 = var_294; [L783] SORT_4 var_295 = ((SORT_4)var_295_arg_0 << 8) | var_295_arg_1; [L784] var_295 = var_295 & mask_SORT_4 [L785] SORT_4 var_296_arg_0 = var_198; [L786] SORT_4 var_296_arg_1 = var_295; [L787] SORT_1 var_296 = var_296_arg_0 <= var_296_arg_1; [L788] SORT_1 var_297_arg_0 = var_291; [L789] SORT_1 var_297_arg_1 = var_296; [L790] SORT_1 var_297 = var_297_arg_0 & var_297_arg_1; [L791] SORT_1 var_298_arg_0 = input_173; [L792] SORT_1 var_298_arg_1 = var_297; [L793] SORT_1 var_298 = var_298_arg_0 & var_298_arg_1; [L794] SORT_1 var_299_arg_0 = ~input_286; [L795] var_299_arg_0 = var_299_arg_0 & mask_SORT_1 [L796] SORT_1 var_299_arg_1 = var_298; [L797] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L798] SORT_1 var_300_arg_0 = var_285; [L799] SORT_1 var_300_arg_1 = var_299; [L800] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L801] SORT_1 var_301_arg_0 = input_175; [L802] SORT_1 var_301_arg_1 = input_286; [L803] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L804] SORT_1 var_303_arg_0 = var_301; [L805] SORT_1 var_303_arg_1 = ~input_302; [L806] var_303_arg_1 = var_303_arg_1 & mask_SORT_1 [L807] SORT_1 var_303 = var_303_arg_0 | var_303_arg_1; [L808] SORT_1 var_304_arg_0 = var_300; [L809] SORT_1 var_304_arg_1 = var_303; [L810] SORT_1 var_304 = var_304_arg_0 & var_304_arg_1; [L811] SORT_1 var_306_arg_0 = input_177; [L812] SORT_1 var_306_arg_1 = input_302; [L813] SORT_1 var_306 = var_306_arg_0 | var_306_arg_1; [L814] SORT_4 var_307_arg_0 = var_266; [L815] SORT_4 var_307_arg_1 = var_198; [L816] SORT_4 var_307 = var_307_arg_0 - var_307_arg_1; [L817] SORT_4 var_308_arg_0 = var_307; [L818] SORT_2 var_308 = var_308_arg_0 >> 0; [L819] SORT_1 var_309_arg_0 = input_281; [L820] SORT_2 var_309_arg_1 = var_308; [L821] SORT_2 var_309_arg_2 = var_265; [L822] EXPR var_309_arg_0 ? var_309_arg_1 : var_309_arg_2 [L822] SORT_2 var_309 = var_309_arg_0 ? var_309_arg_1 : var_309_arg_2; [L823] var_309 = var_309 & mask_SORT_2 [L824] SORT_3 var_310_arg_0 = var_199; [L825] SORT_2 var_310_arg_1 = var_309; [L826] SORT_4 var_310 = ((SORT_4)var_310_arg_0 << 8) | var_310_arg_1; [L827] var_310 = var_310 & mask_SORT_4 [L828] SORT_4 var_311_arg_0 = var_198; [L829] SORT_4 var_311_arg_1 = var_310; [L830] SORT_1 var_311 = var_311_arg_0 <= var_311_arg_1; [L831] SORT_1 var_312_arg_0 = var_306; [L832] SORT_1 var_312_arg_1 = var_311; [L833] SORT_1 var_312 = var_312_arg_0 & var_312_arg_1; [L834] SORT_1 var_313_arg_0 = ~input_305; [L835] var_313_arg_0 = var_313_arg_0 & mask_SORT_1 [L836] SORT_1 var_313_arg_1 = var_312; [L837] SORT_1 var_313 = var_313_arg_0 | var_313_arg_1; [L838] SORT_1 var_314_arg_0 = var_304; [L839] SORT_1 var_314_arg_1 = var_313; [L840] SORT_1 var_314 = var_314_arg_0 & var_314_arg_1; [L841] SORT_1 var_316_arg_0 = input_179; [L842] SORT_1 var_316_arg_1 = input_305; [L843] SORT_1 var_316 = var_316_arg_0 | var_316_arg_1; [L844] SORT_4 var_317_arg_0 = var_310; [L845] SORT_4 var_317_arg_1 = var_198; [L846] SORT_4 var_317 = var_317_arg_0 - var_317_arg_1; [L847] SORT_4 var_318_arg_0 = var_317; [L848] SORT_2 var_318 = var_318_arg_0 >> 0; [L849] SORT_1 var_319_arg_0 = input_305; [L850] SORT_2 var_319_arg_1 = var_318; [L851] SORT_2 var_319_arg_2 = var_309; [L852] EXPR var_319_arg_0 ? var_319_arg_1 : var_319_arg_2 [L852] SORT_2 var_319 = var_319_arg_0 ? var_319_arg_1 : var_319_arg_2; [L853] var_319 = var_319 & mask_SORT_2 [L854] SORT_3 var_320_arg_0 = var_199; [L855] SORT_2 var_320_arg_1 = var_319; [L856] SORT_4 var_320 = ((SORT_4)var_320_arg_0 << 8) | var_320_arg_1; [L857] var_320 = var_320 & mask_SORT_4 [L858] SORT_4 var_321_arg_0 = var_198; [L859] SORT_4 var_321_arg_1 = var_320; [L860] SORT_1 var_321 = var_321_arg_0 <= var_321_arg_1; [L861] SORT_1 var_322_arg_0 = var_316; [L862] SORT_1 var_322_arg_1 = var_321; [L863] SORT_1 var_322 = var_322_arg_0 & var_322_arg_1; [L864] SORT_1 var_323_arg_0 = ~input_315; [L865] var_323_arg_0 = var_323_arg_0 & mask_SORT_1 [L866] SORT_1 var_323_arg_1 = var_322; [L867] SORT_1 var_323 = var_323_arg_0 | var_323_arg_1; [L868] SORT_1 var_324_arg_0 = var_314; [L869] SORT_1 var_324_arg_1 = var_323; [L870] SORT_1 var_324 = var_324_arg_0 & var_324_arg_1; [L871] SORT_1 var_326_arg_0 = input_185; [L872] SORT_1 var_326_arg_1 = input_315; [L873] SORT_1 var_326 = var_326_arg_0 | var_326_arg_1; [L874] SORT_4 var_327_arg_0 = var_295; [L875] SORT_4 var_327_arg_1 = var_198; [L876] SORT_4 var_327 = var_327_arg_0 - var_327_arg_1; [L877] SORT_4 var_328_arg_0 = var_327; [L878] SORT_2 var_328 = var_328_arg_0 >> 0; [L879] SORT_1 var_329_arg_0 = input_286; [L880] SORT_2 var_329_arg_1 = var_328; [L881] SORT_2 var_329_arg_2 = var_294; [L882] EXPR var_329_arg_0 ? var_329_arg_1 : var_329_arg_2 [L882] SORT_2 var_329 = var_329_arg_0 ? var_329_arg_1 : var_329_arg_2; [L883] var_329 = var_329 & mask_SORT_2 [L884] SORT_3 var_330_arg_0 = var_199; [L885] SORT_2 var_330_arg_1 = var_329; [L886] SORT_4 var_330 = ((SORT_4)var_330_arg_0 << 8) | var_330_arg_1; [L887] var_330 = var_330 & mask_SORT_4 [L888] SORT_4 var_331_arg_0 = var_198; [L889] SORT_4 var_331_arg_1 = var_330; [L890] SORT_1 var_331 = var_331_arg_0 <= var_331_arg_1; [L891] SORT_1 var_332_arg_0 = var_326; [L892] SORT_1 var_332_arg_1 = var_331; [L893] SORT_1 var_332 = var_332_arg_0 & var_332_arg_1; [L894] SORT_1 var_333_arg_0 = ~input_325; [L895] var_333_arg_0 = var_333_arg_0 & mask_SORT_1 [L896] SORT_1 var_333_arg_1 = var_332; [L897] SORT_1 var_333 = var_333_arg_0 | var_333_arg_1; [L898] SORT_1 var_334_arg_0 = var_324; [L899] SORT_1 var_334_arg_1 = var_333; [L900] SORT_1 var_334 = var_334_arg_0 & var_334_arg_1; [L901] SORT_1 var_336_arg_0 = input_187; [L902] SORT_1 var_336_arg_1 = input_325; [L903] SORT_1 var_336 = var_336_arg_0 | var_336_arg_1; [L904] SORT_1 var_337_arg_0 = var_321; [L905] SORT_1 var_337_arg_1 = var_336; [L906] SORT_1 var_337 = var_337_arg_0 & var_337_arg_1; [L907] SORT_1 var_338_arg_0 = ~input_335; [L908] var_338_arg_0 = var_338_arg_0 & mask_SORT_1 [L909] SORT_1 var_338_arg_1 = var_337; [L910] SORT_1 var_338 = var_338_arg_0 | var_338_arg_1; [L911] SORT_1 var_339_arg_0 = var_334; [L912] SORT_1 var_339_arg_1 = var_338; [L913] SORT_1 var_339 = var_339_arg_0 & var_339_arg_1; [L914] SORT_4 var_341_arg_0 = var_202; [L915] SORT_4 var_341_arg_1 = var_203; [L916] SORT_4 var_341 = var_341_arg_0 + var_341_arg_1; [L917] SORT_4 var_342_arg_0 = var_341; [L918] SORT_2 var_342 = var_342_arg_0 >> 0; [L919] SORT_1 var_343_arg_0 = input_197; [L920] SORT_2 var_343_arg_1 = var_342; [L921] SORT_2 var_343_arg_2 = input_131; [L922] EXPR var_343_arg_0 ? var_343_arg_1 : var_343_arg_2 [L922] SORT_2 var_343 = var_343_arg_0 ? var_343_arg_1 : var_343_arg_2; [L923] var_343 = var_343 & mask_SORT_2 [L924] SORT_3 var_344_arg_0 = var_199; [L925] SORT_2 var_344_arg_1 = var_343; [L926] SORT_4 var_344 = ((SORT_4)var_344_arg_0 << 8) | var_344_arg_1; [L927] var_344 = var_344 & mask_SORT_4 [L928] SORT_4 var_345_arg_0 = var_198; [L929] SORT_4 var_345_arg_1 = var_344; [L930] SORT_1 var_345 = var_345_arg_0 <= var_345_arg_1; [L931] SORT_1 var_346_arg_0 = input_193; [L932] SORT_1 var_346_arg_1 = var_345; [L933] SORT_1 var_346 = var_346_arg_0 & var_346_arg_1; [L934] SORT_1 var_347_arg_0 = ~input_340; [L935] var_347_arg_0 = var_347_arg_0 & mask_SORT_1 [L936] SORT_1 var_347_arg_1 = var_346; [L937] SORT_1 var_347 = var_347_arg_0 | var_347_arg_1; [L938] SORT_1 var_348_arg_0 = var_339; [L939] SORT_1 var_348_arg_1 = var_347; [L940] SORT_1 var_348 = var_348_arg_0 & var_348_arg_1; [L941] SORT_1 var_350_arg_0 = input_189; [L942] SORT_1 var_350_arg_1 = input_191; [L943] SORT_1 var_350 = var_350_arg_0 & var_350_arg_1; [L944] SORT_4 var_351_arg_0 = var_206; [L945] SORT_4 var_351_arg_1 = var_202; [L946] SORT_4 var_351 = var_351_arg_0 - var_351_arg_1; [L947] SORT_4 var_352_arg_0 = var_351; [L948] SORT_2 var_352 = var_352_arg_0 >> 0; [L949] SORT_1 var_353_arg_0 = input_197; [L950] SORT_2 var_353_arg_1 = var_352; [L951] SORT_2 var_353_arg_2 = input_133; [L952] EXPR var_353_arg_0 ? var_353_arg_1 : var_353_arg_2 [L952] SORT_2 var_353 = var_353_arg_0 ? var_353_arg_1 : var_353_arg_2; [L953] var_353 = var_353 & mask_SORT_2 [L954] SORT_3 var_354_arg_0 = var_199; [L955] SORT_2 var_354_arg_1 = var_353; [L956] SORT_4 var_354 = ((SORT_4)var_354_arg_0 << 8) | var_354_arg_1; [L957] SORT_4 var_355_arg_0 = var_198; [L958] SORT_4 var_355_arg_1 = var_354; [L959] SORT_4 var_355 = var_355_arg_0 + var_355_arg_1; [L960] SORT_4 var_356_arg_0 = var_355; [L961] SORT_2 var_356 = var_356_arg_0 >> 0; [L962] SORT_1 var_357_arg_0 = input_340; [L963] SORT_2 var_357_arg_1 = var_356; [L964] SORT_2 var_357_arg_2 = var_353; [L965] EXPR var_357_arg_0 ? var_357_arg_1 : var_357_arg_2 [L965] SORT_2 var_357 = var_357_arg_0 ? var_357_arg_1 : var_357_arg_2; [L966] var_357 = var_357 & mask_SORT_2 [L967] SORT_3 var_358_arg_0 = var_199; [L968] SORT_2 var_358_arg_1 = var_357; [L969] SORT_4 var_358 = ((SORT_4)var_358_arg_0 << 8) | var_358_arg_1; [L970] var_358 = var_358 & mask_SORT_4 [L971] SORT_4 var_359_arg_0 = var_202; [L972] SORT_4 var_359_arg_1 = var_358; [L973] SORT_1 var_359 = var_359_arg_0 <= var_359_arg_1; [L974] SORT_1 var_360_arg_0 = var_350; [L975] SORT_1 var_360_arg_1 = var_359; [L976] SORT_1 var_360 = var_360_arg_0 & var_360_arg_1; [L977] SORT_3 var_361_arg_0 = var_199; [L978] SORT_2 var_361_arg_1 = input_137; [L979] SORT_4 var_361 = ((SORT_4)var_361_arg_0 << 8) | var_361_arg_1; [L980] SORT_4 var_362_arg_0 = var_202; [L981] SORT_4 var_362_arg_1 = var_361; [L982] SORT_4 var_362 = var_362_arg_0 + var_362_arg_1; [L983] SORT_4 var_363_arg_0 = var_362; [L984] SORT_2 var_363 = var_363_arg_0 >> 0; [L985] SORT_1 var_364_arg_0 = input_197; [L986] SORT_2 var_364_arg_1 = var_363; [L987] SORT_2 var_364_arg_2 = input_137; [L988] EXPR var_364_arg_0 ? var_364_arg_1 : var_364_arg_2 [L988] SORT_2 var_364 = var_364_arg_0 ? var_364_arg_1 : var_364_arg_2; [L989] var_364 = var_364 & mask_SORT_2 [L990] SORT_3 var_365_arg_0 = var_199; [L991] SORT_2 var_365_arg_1 = var_364; [L992] SORT_4 var_365 = ((SORT_4)var_365_arg_0 << 8) | var_365_arg_1; [L993] SORT_4 var_366_arg_0 = var_198; [L994] SORT_4 var_366_arg_1 = var_365; [L995] SORT_4 var_366 = var_366_arg_0 + var_366_arg_1; [L996] SORT_4 var_367_arg_0 = var_366; [L997] SORT_2 var_367 = var_367_arg_0 >> 0; [L998] SORT_1 var_368_arg_0 = input_214; [L999] SORT_2 var_368_arg_1 = var_367; [L1000] SORT_2 var_368_arg_2 = var_364; [L1001] EXPR var_368_arg_0 ? var_368_arg_1 : var_368_arg_2 [L1001] SORT_2 var_368 = var_368_arg_0 ? var_368_arg_1 : var_368_arg_2; [L1002] var_368 = var_368 & mask_SORT_2 [L1003] SORT_3 var_369_arg_0 = var_199; [L1004] SORT_2 var_369_arg_1 = var_368; [L1005] SORT_4 var_369 = ((SORT_4)var_369_arg_0 << 8) | var_369_arg_1; [L1006] SORT_4 var_370_arg_0 = var_198; [L1007] SORT_4 var_370_arg_1 = var_369; [L1008] SORT_4 var_370 = var_370_arg_0 + var_370_arg_1; [L1009] SORT_4 var_371_arg_0 = var_370; [L1010] SORT_2 var_371 = var_371_arg_0 >> 0; [L1011] SORT_1 var_372_arg_0 = input_251; [L1012] SORT_2 var_372_arg_1 = var_371; [L1013] SORT_2 var_372_arg_2 = var_368; [L1014] EXPR var_372_arg_0 ? var_372_arg_1 : var_372_arg_2 [L1014] SORT_2 var_372 = var_372_arg_0 ? var_372_arg_1 : var_372_arg_2; [L1015] var_372 = var_372 & mask_SORT_2 [L1016] SORT_3 var_373_arg_0 = var_199; [L1017] SORT_2 var_373_arg_1 = var_372; [L1018] SORT_4 var_373 = ((SORT_4)var_373_arg_0 << 8) | var_373_arg_1; [L1019] SORT_4 var_374_arg_0 = var_198; [L1020] SORT_4 var_374_arg_1 = var_373; [L1021] SORT_4 var_374 = var_374_arg_0 + var_374_arg_1; [L1022] SORT_4 var_375_arg_0 = var_374; [L1023] SORT_2 var_375 = var_375_arg_0 >> 0; [L1024] SORT_1 var_376_arg_0 = input_261; [L1025] SORT_2 var_376_arg_1 = var_375; [L1026] SORT_2 var_376_arg_2 = var_372; [L1027] EXPR var_376_arg_0 ? var_376_arg_1 : var_376_arg_2 [L1027] SORT_2 var_376 = var_376_arg_0 ? var_376_arg_1 : var_376_arg_2; [L1028] var_376 = var_376 & mask_SORT_2 [L1029] SORT_3 var_377_arg_0 = var_199; [L1030] SORT_2 var_377_arg_1 = var_376; [L1031] SORT_4 var_377 = ((SORT_4)var_377_arg_0 << 8) | var_377_arg_1; [L1032] SORT_4 var_378_arg_0 = var_198; [L1033] SORT_4 var_378_arg_1 = var_377; [L1034] SORT_4 var_378 = var_378_arg_0 + var_378_arg_1; [L1035] SORT_4 var_379_arg_0 = var_378; [L1036] SORT_2 var_379 = var_379_arg_0 >> 0; [L1037] SORT_1 var_380_arg_0 = input_281; [L1038] SORT_2 var_380_arg_1 = var_379; [L1039] SORT_2 var_380_arg_2 = var_376; [L1040] EXPR var_380_arg_0 ? var_380_arg_1 : var_380_arg_2 [L1040] SORT_2 var_380 = var_380_arg_0 ? var_380_arg_1 : var_380_arg_2; [L1041] var_380 = var_380 & mask_SORT_2 [L1042] SORT_3 var_381_arg_0 = var_199; [L1043] SORT_2 var_381_arg_1 = var_380; [L1044] SORT_4 var_381 = ((SORT_4)var_381_arg_0 << 8) | var_381_arg_1; [L1045] SORT_4 var_382_arg_0 = var_198; [L1046] SORT_4 var_382_arg_1 = var_381; [L1047] SORT_4 var_382 = var_382_arg_0 + var_382_arg_1; [L1048] SORT_4 var_383_arg_0 = var_382; [L1049] SORT_2 var_383 = var_383_arg_0 >> 0; [L1050] SORT_1 var_384_arg_0 = input_305; [L1051] SORT_2 var_384_arg_1 = var_383; [L1052] SORT_2 var_384_arg_2 = var_380; [L1053] EXPR var_384_arg_0 ? var_384_arg_1 : var_384_arg_2 [L1053] SORT_2 var_384 = var_384_arg_0 ? var_384_arg_1 : var_384_arg_2; [L1054] var_384 = var_384 & mask_SORT_2 [L1055] SORT_3 var_385_arg_0 = var_199; [L1056] SORT_2 var_385_arg_1 = var_384; [L1057] SORT_4 var_385 = ((SORT_4)var_385_arg_0 << 8) | var_385_arg_1; [L1058] SORT_4 var_386_arg_0 = var_198; [L1059] SORT_4 var_386_arg_1 = var_385; [L1060] SORT_4 var_386 = var_386_arg_0 + var_386_arg_1; [L1061] SORT_4 var_387_arg_0 = var_386; [L1062] SORT_2 var_387 = var_387_arg_0 >> 0; [L1063] SORT_1 var_388_arg_0 = input_315; [L1064] SORT_2 var_388_arg_1 = var_387; [L1065] SORT_2 var_388_arg_2 = var_384; [L1066] EXPR var_388_arg_0 ? var_388_arg_1 : var_388_arg_2 [L1066] SORT_2 var_388 = var_388_arg_0 ? var_388_arg_1 : var_388_arg_2; [L1067] var_388 = var_388 & mask_SORT_2 [L1068] SORT_3 var_389_arg_0 = var_199; [L1069] SORT_2 var_389_arg_1 = var_388; [L1070] SORT_4 var_389 = ((SORT_4)var_389_arg_0 << 8) | var_389_arg_1; [L1071] SORT_4 var_390_arg_0 = var_198; [L1072] SORT_4 var_390_arg_1 = var_389; [L1073] SORT_4 var_390 = var_390_arg_0 + var_390_arg_1; [L1074] SORT_4 var_391_arg_0 = var_390; [L1075] SORT_2 var_391 = var_391_arg_0 >> 0; [L1076] SORT_1 var_392_arg_0 = input_335; [L1077] SORT_2 var_392_arg_1 = var_391; [L1078] SORT_2 var_392_arg_2 = var_388; [L1079] EXPR var_392_arg_0 ? var_392_arg_1 : var_392_arg_2 [L1079] SORT_2 var_392 = var_392_arg_0 ? var_392_arg_1 : var_392_arg_2; [L1080] var_392 = var_392 & mask_SORT_2 [L1081] SORT_3 var_393_arg_0 = var_199; [L1082] SORT_2 var_393_arg_1 = var_392; [L1083] SORT_4 var_393 = ((SORT_4)var_393_arg_0 << 8) | var_393_arg_1; [L1084] var_393 = var_393 & mask_SORT_4 [L1085] SORT_4 var_394_arg_0 = var_198; [L1086] SORT_4 var_394_arg_1 = var_393; [L1087] SORT_1 var_394 = var_394_arg_0 <= var_394_arg_1; [L1088] SORT_3 var_395_arg_0 = var_199; [L1089] SORT_2 var_395_arg_1 = input_143; [L1090] SORT_4 var_395 = ((SORT_4)var_395_arg_0 << 8) | var_395_arg_1; [L1091] var_395 = var_395 & mask_SORT_4 [L1092] SORT_4 var_396_arg_0 = var_198; [L1093] SORT_4 var_396_arg_1 = var_395; [L1094] SORT_1 var_396 = var_396_arg_0 <= var_396_arg_1; [L1095] SORT_1 var_397_arg_0 = var_394; [L1096] SORT_1 var_397_arg_1 = var_396; [L1097] SORT_1 var_397 = var_397_arg_0 & var_397_arg_1; [L1098] SORT_3 var_398_arg_0 = var_199; [L1099] SORT_2 var_398_arg_1 = input_147; [L1100] SORT_4 var_398 = ((SORT_4)var_398_arg_0 << 8) | var_398_arg_1; [L1101] SORT_4 var_399_arg_0 = var_202; [L1102] SORT_4 var_399_arg_1 = var_398; [L1103] SORT_4 var_399 = var_399_arg_0 + var_399_arg_1; [L1104] SORT_4 var_400_arg_0 = var_399; [L1105] SORT_2 var_400 = var_400_arg_0 >> 0; [L1106] SORT_1 var_401_arg_0 = input_197; [L1107] SORT_2 var_401_arg_1 = var_400; [L1108] SORT_2 var_401_arg_2 = input_147; [L1109] EXPR var_401_arg_0 ? var_401_arg_1 : var_401_arg_2 [L1109] SORT_2 var_401 = var_401_arg_0 ? var_401_arg_1 : var_401_arg_2; [L1110] var_401 = var_401 & mask_SORT_2 [L1111] SORT_3 var_402_arg_0 = var_199; [L1112] SORT_2 var_402_arg_1 = var_401; [L1113] SORT_4 var_402 = ((SORT_4)var_402_arg_0 << 8) | var_402_arg_1; [L1114] SORT_4 var_403_arg_0 = var_198; [L1115] SORT_4 var_403_arg_1 = var_402; [L1116] SORT_4 var_403 = var_403_arg_0 + var_403_arg_1; [L1117] SORT_4 var_404_arg_0 = var_403; [L1118] SORT_2 var_404 = var_404_arg_0 >> 0; [L1119] SORT_1 var_405_arg_0 = input_251; [L1120] SORT_2 var_405_arg_1 = var_404; [L1121] SORT_2 var_405_arg_2 = var_401; [L1122] EXPR var_405_arg_0 ? var_405_arg_1 : var_405_arg_2 [L1122] SORT_2 var_405 = var_405_arg_0 ? var_405_arg_1 : var_405_arg_2; [L1123] var_405 = var_405 & mask_SORT_2 [L1124] SORT_3 var_406_arg_0 = var_199; [L1125] SORT_2 var_406_arg_1 = var_405; [L1126] SORT_4 var_406 = ((SORT_4)var_406_arg_0 << 8) | var_406_arg_1; [L1127] SORT_4 var_407_arg_0 = var_198; [L1128] SORT_4 var_407_arg_1 = var_406; [L1129] SORT_4 var_407 = var_407_arg_0 + var_407_arg_1; [L1130] SORT_4 var_408_arg_0 = var_407; [L1131] SORT_2 var_408 = var_408_arg_0 >> 0; [L1132] SORT_1 var_409_arg_0 = input_305; [L1133] SORT_2 var_409_arg_1 = var_408; [L1134] SORT_2 var_409_arg_2 = var_405; [L1135] EXPR var_409_arg_0 ? var_409_arg_1 : var_409_arg_2 [L1135] SORT_2 var_409 = var_409_arg_0 ? var_409_arg_1 : var_409_arg_2; [L1136] var_409 = var_409 & mask_SORT_2 [L1137] SORT_3 var_410_arg_0 = var_199; [L1138] SORT_2 var_410_arg_1 = var_409; [L1139] SORT_4 var_410 = ((SORT_4)var_410_arg_0 << 8) | var_410_arg_1; [L1140] var_410 = var_410 & mask_SORT_4 [L1141] SORT_4 var_411_arg_0 = var_202; [L1142] SORT_4 var_411_arg_1 = var_410; [L1143] SORT_1 var_411 = var_411_arg_0 <= var_411_arg_1; [L1144] SORT_1 var_412_arg_0 = var_397; [L1145] SORT_1 var_412_arg_1 = var_411; [L1146] SORT_1 var_412 = var_412_arg_0 & var_412_arg_1; [L1147] SORT_1 var_413_arg_0 = var_360; [L1148] SORT_1 var_413_arg_1 = var_412; [L1149] SORT_1 var_413 = var_413_arg_0 & var_413_arg_1; [L1150] SORT_1 var_414_arg_0 = ~input_349; [L1151] var_414_arg_0 = var_414_arg_0 & mask_SORT_1 [L1152] SORT_1 var_414_arg_1 = var_413; [L1153] SORT_1 var_414 = var_414_arg_0 | var_414_arg_1; [L1154] SORT_1 var_415_arg_0 = var_348; [L1155] SORT_1 var_415_arg_1 = var_414; [L1156] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1157] SORT_1 var_416_arg_0 = input_197; [L1158] SORT_1 var_416_arg_1 = input_214; [L1159] SORT_1 var_416 = var_416_arg_0 | var_416_arg_1; [L1160] SORT_1 var_417_arg_0 = input_230; [L1161] SORT_1 var_417_arg_1 = var_416; [L1162] SORT_1 var_417 = var_417_arg_0 | var_417_arg_1; [L1163] SORT_1 var_418_arg_0 = input_248; [L1164] SORT_1 var_418_arg_1 = var_417; [L1165] SORT_1 var_418 = var_418_arg_0 | var_418_arg_1; [L1166] SORT_1 var_419_arg_0 = input_251; [L1167] SORT_1 var_419_arg_1 = var_418; [L1168] SORT_1 var_419 = var_419_arg_0 | var_419_arg_1; [L1169] SORT_1 var_420_arg_0 = input_261; [L1170] SORT_1 var_420_arg_1 = var_419; [L1171] SORT_1 var_420 = var_420_arg_0 | var_420_arg_1; [L1172] SORT_1 var_421_arg_0 = input_271; [L1173] SORT_1 var_421_arg_1 = var_420; [L1174] SORT_1 var_421 = var_421_arg_0 | var_421_arg_1; [L1175] SORT_1 var_422_arg_0 = input_281; [L1176] SORT_1 var_422_arg_1 = var_421; [L1177] SORT_1 var_422 = var_422_arg_0 | var_422_arg_1; [L1178] SORT_1 var_423_arg_0 = input_286; [L1179] SORT_1 var_423_arg_1 = var_422; [L1180] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1181] SORT_1 var_424_arg_0 = input_302; [L1182] SORT_1 var_424_arg_1 = var_423; [L1183] SORT_1 var_424 = var_424_arg_0 | var_424_arg_1; [L1184] SORT_1 var_425_arg_0 = input_305; [L1185] SORT_1 var_425_arg_1 = var_424; [L1186] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1187] SORT_1 var_426_arg_0 = input_315; [L1188] SORT_1 var_426_arg_1 = var_425; [L1189] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1190] SORT_1 var_427_arg_0 = input_325; [L1191] SORT_1 var_427_arg_1 = var_426; [L1192] SORT_1 var_427 = var_427_arg_0 | var_427_arg_1; [L1193] SORT_1 var_428_arg_0 = input_335; [L1194] SORT_1 var_428_arg_1 = var_427; [L1195] SORT_1 var_428 = var_428_arg_0 | var_428_arg_1; [L1196] SORT_1 var_429_arg_0 = input_340; [L1197] SORT_1 var_429_arg_1 = var_428; [L1198] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1199] SORT_1 var_430_arg_0 = input_349; [L1200] SORT_1 var_430_arg_1 = var_429; [L1201] SORT_1 var_430 = var_430_arg_0 | var_430_arg_1; [L1202] SORT_1 var_431_arg_0 = var_415; [L1203] SORT_1 var_431_arg_1 = var_430; [L1204] SORT_1 var_431 = var_431_arg_0 & var_431_arg_1; [L1205] SORT_1 var_432_arg_0 = input_153; [L1206] SORT_1 var_432_arg_1 = input_155; [L1207] SORT_1 var_432 = var_432_arg_0 & var_432_arg_1; [L1208] SORT_1 var_433_arg_0 = var_432; [L1209] SORT_1 var_433_arg_1 = input_189; [L1210] SORT_1 var_433 = var_433_arg_0 & var_433_arg_1; [L1211] SORT_1 var_434_arg_0 = var_433; [L1212] SORT_1 var_434_arg_1 = input_191; [L1213] SORT_1 var_434 = var_434_arg_0 & var_434_arg_1; [L1214] SORT_1 var_435_arg_0 = var_434; [L1215] SORT_1 var_435_arg_1 = input_193; [L1216] SORT_1 var_435 = var_435_arg_0 & var_435_arg_1; [L1217] SORT_1 var_436_arg_0 = input_157; [L1218] SORT_1 var_436_arg_1 = input_159; [L1219] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1220] SORT_1 var_437_arg_0 = input_157; [L1221] SORT_1 var_437_arg_1 = input_159; [L1222] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1223] SORT_1 var_438_arg_0 = input_161; [L1224] SORT_1 var_438_arg_1 = var_437; [L1225] SORT_1 var_438 = var_438_arg_0 & var_438_arg_1; [L1226] SORT_1 var_439_arg_0 = var_436; [L1227] SORT_1 var_439_arg_1 = var_438; [L1228] SORT_1 var_439 = var_439_arg_0 | var_439_arg_1; [L1229] SORT_1 var_440_arg_0 = input_161; [L1230] SORT_1 var_440_arg_1 = var_437; [L1231] SORT_1 var_440 = var_440_arg_0 | var_440_arg_1; [L1232] SORT_1 var_441_arg_0 = input_163; [L1233] SORT_1 var_441_arg_1 = var_440; [L1234] SORT_1 var_441 = var_441_arg_0 & var_441_arg_1; [L1235] SORT_1 var_442_arg_0 = var_439; [L1236] SORT_1 var_442_arg_1 = var_441; [L1237] SORT_1 var_442 = var_442_arg_0 | var_442_arg_1; [L1238] SORT_1 var_443_arg_0 = input_163; [L1239] SORT_1 var_443_arg_1 = var_440; [L1240] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1241] SORT_1 var_444_arg_0 = input_165; [L1242] SORT_1 var_444_arg_1 = var_443; [L1243] SORT_1 var_444 = var_444_arg_0 & var_444_arg_1; [L1244] SORT_1 var_445_arg_0 = var_442; [L1245] SORT_1 var_445_arg_1 = var_444; [L1246] SORT_1 var_445 = var_445_arg_0 | var_445_arg_1; [L1247] SORT_1 var_446_arg_0 = input_165; [L1248] SORT_1 var_446_arg_1 = var_443; [L1249] SORT_1 var_446 = var_446_arg_0 | var_446_arg_1; [L1250] SORT_1 var_447_arg_0 = input_167; [L1251] SORT_1 var_447_arg_1 = var_446; [L1252] SORT_1 var_447 = var_447_arg_0 & var_447_arg_1; [L1253] SORT_1 var_448_arg_0 = var_445; [L1254] SORT_1 var_448_arg_1 = var_447; [L1255] SORT_1 var_448 = var_448_arg_0 | var_448_arg_1; [L1256] SORT_1 var_449_arg_0 = input_167; [L1257] SORT_1 var_449_arg_1 = var_446; [L1258] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1259] SORT_1 var_450_arg_0 = input_169; [L1260] SORT_1 var_450_arg_1 = var_449; [L1261] SORT_1 var_450 = var_450_arg_0 & var_450_arg_1; [L1262] SORT_1 var_451_arg_0 = var_448; [L1263] SORT_1 var_451_arg_1 = var_450; [L1264] SORT_1 var_451 = var_451_arg_0 | var_451_arg_1; [L1265] SORT_1 var_452_arg_0 = input_169; [L1266] SORT_1 var_452_arg_1 = var_449; [L1267] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1268] SORT_1 var_453_arg_0 = input_171; [L1269] SORT_1 var_453_arg_1 = var_452; [L1270] SORT_1 var_453 = var_453_arg_0 & var_453_arg_1; [L1271] SORT_1 var_454_arg_0 = var_451; [L1272] SORT_1 var_454_arg_1 = var_453; [L1273] SORT_1 var_454 = var_454_arg_0 | var_454_arg_1; [L1274] SORT_1 var_455_arg_0 = var_435; [L1275] SORT_1 var_455_arg_1 = ~var_454; [L1276] var_455_arg_1 = var_455_arg_1 & mask_SORT_1 [L1277] SORT_1 var_455 = var_455_arg_0 & var_455_arg_1; [L1278] SORT_1 var_456_arg_0 = input_171; [L1279] SORT_1 var_456_arg_1 = var_452; [L1280] SORT_1 var_456 = var_456_arg_0 | var_456_arg_1; [L1281] SORT_1 var_457_arg_0 = var_455; [L1282] SORT_1 var_457_arg_1 = var_456; [L1283] SORT_1 var_457 = var_457_arg_0 & var_457_arg_1; [L1284] SORT_1 var_458_arg_0 = input_173; [L1285] SORT_1 var_458_arg_1 = input_175; [L1286] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1287] SORT_1 var_459_arg_0 = input_173; [L1288] SORT_1 var_459_arg_1 = input_175; [L1289] SORT_1 var_459 = var_459_arg_0 | var_459_arg_1; [L1290] SORT_1 var_460_arg_0 = input_177; [L1291] SORT_1 var_460_arg_1 = var_459; [L1292] SORT_1 var_460 = var_460_arg_0 & var_460_arg_1; [L1293] SORT_1 var_461_arg_0 = var_458; [L1294] SORT_1 var_461_arg_1 = var_460; [L1295] SORT_1 var_461 = var_461_arg_0 | var_461_arg_1; [L1296] SORT_1 var_462_arg_0 = input_177; [L1297] SORT_1 var_462_arg_1 = var_459; [L1298] SORT_1 var_462 = var_462_arg_0 | var_462_arg_1; [L1299] SORT_1 var_463_arg_0 = input_179; [L1300] SORT_1 var_463_arg_1 = var_462; [L1301] SORT_1 var_463 = var_463_arg_0 & var_463_arg_1; [L1302] SORT_1 var_464_arg_0 = var_461; [L1303] SORT_1 var_464_arg_1 = var_463; [L1304] SORT_1 var_464 = var_464_arg_0 | var_464_arg_1; [L1305] SORT_1 var_465_arg_0 = input_179; [L1306] SORT_1 var_465_arg_1 = var_462; [L1307] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1308] SORT_1 var_466_arg_0 = input_181; [L1309] SORT_1 var_466_arg_1 = var_465; [L1310] SORT_1 var_466 = var_466_arg_0 & var_466_arg_1; [L1311] SORT_1 var_467_arg_0 = var_464; [L1312] SORT_1 var_467_arg_1 = var_466; [L1313] SORT_1 var_467 = var_467_arg_0 | var_467_arg_1; [L1314] SORT_1 var_468_arg_0 = input_181; [L1315] SORT_1 var_468_arg_1 = var_465; [L1316] SORT_1 var_468 = var_468_arg_0 | var_468_arg_1; [L1317] SORT_1 var_469_arg_0 = input_183; [L1318] SORT_1 var_469_arg_1 = var_468; [L1319] SORT_1 var_469 = var_469_arg_0 & var_469_arg_1; [L1320] SORT_1 var_470_arg_0 = var_467; [L1321] SORT_1 var_470_arg_1 = var_469; [L1322] SORT_1 var_470 = var_470_arg_0 | var_470_arg_1; [L1323] SORT_1 var_471_arg_0 = input_183; [L1324] SORT_1 var_471_arg_1 = var_468; [L1325] SORT_1 var_471 = var_471_arg_0 | var_471_arg_1; [L1326] SORT_1 var_472_arg_0 = input_185; [L1327] SORT_1 var_472_arg_1 = var_471; [L1328] SORT_1 var_472 = var_472_arg_0 & var_472_arg_1; [L1329] SORT_1 var_473_arg_0 = var_470; [L1330] SORT_1 var_473_arg_1 = var_472; [L1331] SORT_1 var_473 = var_473_arg_0 | var_473_arg_1; [L1332] SORT_1 var_474_arg_0 = input_185; [L1333] SORT_1 var_474_arg_1 = var_471; [L1334] SORT_1 var_474 = var_474_arg_0 | var_474_arg_1; [L1335] SORT_1 var_475_arg_0 = input_187; [L1336] SORT_1 var_475_arg_1 = var_474; [L1337] SORT_1 var_475 = var_475_arg_0 & var_475_arg_1; [L1338] SORT_1 var_476_arg_0 = var_473; [L1339] SORT_1 var_476_arg_1 = var_475; [L1340] SORT_1 var_476 = var_476_arg_0 | var_476_arg_1; [L1341] SORT_1 var_477_arg_0 = var_457; [L1342] SORT_1 var_477_arg_1 = ~var_476; [L1343] var_477_arg_1 = var_477_arg_1 & mask_SORT_1 [L1344] SORT_1 var_477 = var_477_arg_0 & var_477_arg_1; [L1345] SORT_1 var_478_arg_0 = input_187; [L1346] SORT_1 var_478_arg_1 = var_474; [L1347] SORT_1 var_478 = var_478_arg_0 | var_478_arg_1; [L1348] SORT_1 var_479_arg_0 = var_477; [L1349] SORT_1 var_479_arg_1 = var_478; [L1350] SORT_1 var_479 = var_479_arg_0 & var_479_arg_1; [L1351] SORT_1 var_480_arg_0 = var_431; [L1352] SORT_1 var_480_arg_1 = var_479; [L1353] SORT_1 var_480 = var_480_arg_0 & var_480_arg_1; [L1354] SORT_1 var_481_arg_0 = input_153; [L1355] SORT_1 var_481_arg_1 = input_155; [L1356] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1357] SORT_1 var_482_arg_0 = var_481; [L1358] SORT_1 var_482_arg_1 = input_189; [L1359] SORT_1 var_482 = var_482_arg_0 & var_482_arg_1; [L1360] SORT_1 var_483_arg_0 = var_482; [L1361] SORT_1 var_483_arg_1 = input_191; [L1362] SORT_1 var_483 = var_483_arg_0 & var_483_arg_1; [L1363] SORT_1 var_484_arg_0 = var_483; [L1364] SORT_1 var_484_arg_1 = input_193; [L1365] SORT_1 var_484 = var_484_arg_0 & var_484_arg_1; [L1366] SORT_1 var_485_arg_0 = var_247; [L1367] SORT_1 var_485_arg_1 = ~input_248; [L1368] var_485_arg_1 = var_485_arg_1 & mask_SORT_1 [L1369] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1370] var_485 = var_485 & mask_SORT_1 [L1371] SORT_1 var_486_arg_0 = input_157; [L1372] SORT_1 var_486_arg_1 = ~input_230; [L1373] var_486_arg_1 = var_486_arg_1 & mask_SORT_1 [L1374] SORT_1 var_486 = var_486_arg_0 & var_486_arg_1; [L1375] SORT_1 var_487_arg_0 = var_486; [L1376] SORT_1 var_487_arg_1 = input_281; [L1377] SORT_1 var_487 = var_487_arg_0 | var_487_arg_1; [L1378] var_487 = var_487 & mask_SORT_1 [L1379] SORT_1 var_488_arg_0 = var_485; [L1380] SORT_1 var_488_arg_1 = var_487; [L1381] SORT_1 var_488 = var_488_arg_0 & var_488_arg_1; [L1382] SORT_1 var_489_arg_0 = var_252; [L1383] SORT_1 var_489_arg_1 = ~input_251; [L1384] var_489_arg_1 = var_489_arg_1 & mask_SORT_1 [L1385] SORT_1 var_489 = var_489_arg_0 & var_489_arg_1; [L1386] var_489 = var_489 & mask_SORT_1 [L1387] SORT_1 var_490_arg_0 = var_485; [L1388] SORT_1 var_490_arg_1 = var_487; [L1389] SORT_1 var_490 = var_490_arg_0 | var_490_arg_1; [L1390] SORT_1 var_491_arg_0 = var_489; [L1391] SORT_1 var_491_arg_1 = var_490; [L1392] SORT_1 var_491 = var_491_arg_0 & var_491_arg_1; [L1393] SORT_1 var_492_arg_0 = var_488; [L1394] SORT_1 var_492_arg_1 = var_491; [L1395] SORT_1 var_492 = var_492_arg_0 | var_492_arg_1; [L1396] SORT_1 var_493_arg_0 = var_262; [L1397] SORT_1 var_493_arg_1 = ~input_261; [L1398] var_493_arg_1 = var_493_arg_1 & mask_SORT_1 [L1399] SORT_1 var_493 = var_493_arg_0 & var_493_arg_1; [L1400] var_493 = var_493 & mask_SORT_1 [L1401] SORT_1 var_494_arg_0 = var_489; [L1402] SORT_1 var_494_arg_1 = var_490; [L1403] SORT_1 var_494 = var_494_arg_0 | var_494_arg_1; [L1404] SORT_1 var_495_arg_0 = var_493; [L1405] SORT_1 var_495_arg_1 = var_494; [L1406] SORT_1 var_495 = var_495_arg_0 & var_495_arg_1; [L1407] SORT_1 var_496_arg_0 = var_492; [L1408] SORT_1 var_496_arg_1 = var_495; [L1409] SORT_1 var_496 = var_496_arg_0 | var_496_arg_1; [L1410] SORT_1 var_497_arg_0 = var_493; [L1411] SORT_1 var_497_arg_1 = var_494; [L1412] SORT_1 var_497 = var_497_arg_0 | var_497_arg_1; [L1413] SORT_1 var_498_arg_0 = input_165; [L1414] SORT_1 var_498_arg_1 = var_497; [L1415] SORT_1 var_498 = var_498_arg_0 & var_498_arg_1; [L1416] SORT_1 var_499_arg_0 = var_496; [L1417] SORT_1 var_499_arg_1 = var_498; [L1418] SORT_1 var_499 = var_499_arg_0 | var_499_arg_1; [L1419] SORT_1 var_500_arg_0 = input_165; [L1420] SORT_1 var_500_arg_1 = var_497; [L1421] SORT_1 var_500 = var_500_arg_0 | var_500_arg_1; [L1422] SORT_1 var_501_arg_0 = input_167; [L1423] SORT_1 var_501_arg_1 = var_500; [L1424] SORT_1 var_501 = var_501_arg_0 & var_501_arg_1; [L1425] SORT_1 var_502_arg_0 = var_499; [L1426] SORT_1 var_502_arg_1 = var_501; [L1427] SORT_1 var_502 = var_502_arg_0 | var_502_arg_1; [L1428] SORT_1 var_503_arg_0 = var_272; [L1429] SORT_1 var_503_arg_1 = ~input_271; [L1430] var_503_arg_1 = var_503_arg_1 & mask_SORT_1 [L1431] SORT_1 var_503 = var_503_arg_0 & var_503_arg_1; [L1432] var_503 = var_503 & mask_SORT_1 [L1433] SORT_1 var_504_arg_0 = input_167; [L1434] SORT_1 var_504_arg_1 = var_500; [L1435] SORT_1 var_504 = var_504_arg_0 | var_504_arg_1; [L1436] SORT_1 var_505_arg_0 = var_503; [L1437] SORT_1 var_505_arg_1 = var_504; [L1438] SORT_1 var_505 = var_505_arg_0 & var_505_arg_1; [L1439] SORT_1 var_506_arg_0 = var_502; [L1440] SORT_1 var_506_arg_1 = var_505; [L1441] SORT_1 var_506 = var_506_arg_0 | var_506_arg_1; [L1442] SORT_1 var_507_arg_0 = var_282; [L1443] SORT_1 var_507_arg_1 = ~input_281; [L1444] var_507_arg_1 = var_507_arg_1 & mask_SORT_1 [L1445] SORT_1 var_507 = var_507_arg_0 & var_507_arg_1; [L1446] var_507 = var_507 & mask_SORT_1 [L1447] SORT_1 var_508_arg_0 = var_503; [L1448] SORT_1 var_508_arg_1 = var_504; [L1449] SORT_1 var_508 = var_508_arg_0 | var_508_arg_1; [L1450] SORT_1 var_509_arg_0 = var_507; [L1451] SORT_1 var_509_arg_1 = var_508; [L1452] SORT_1 var_509 = var_509_arg_0 & var_509_arg_1; [L1453] SORT_1 var_510_arg_0 = var_506; [L1454] SORT_1 var_510_arg_1 = var_509; [L1455] SORT_1 var_510 = var_510_arg_0 | var_510_arg_1; [L1456] SORT_1 var_511_arg_0 = var_484; [L1457] SORT_1 var_511_arg_1 = ~var_510; [L1458] var_511_arg_1 = var_511_arg_1 & mask_SORT_1 [L1459] SORT_1 var_511 = var_511_arg_0 & var_511_arg_1; [L1460] SORT_1 var_512_arg_0 = var_507; [L1461] SORT_1 var_512_arg_1 = var_508; [L1462] SORT_1 var_512 = var_512_arg_0 | var_512_arg_1; [L1463] SORT_1 var_513_arg_0 = var_511; [L1464] SORT_1 var_513_arg_1 = var_512; [L1465] SORT_1 var_513 = var_513_arg_0 & var_513_arg_1; [L1466] SORT_1 var_514_arg_0 = var_301; [L1467] SORT_1 var_514_arg_1 = ~input_302; [L1468] var_514_arg_1 = var_514_arg_1 & mask_SORT_1 [L1469] SORT_1 var_514 = var_514_arg_0 & var_514_arg_1; [L1470] var_514 = var_514 & mask_SORT_1 [L1471] SORT_1 var_515_arg_0 = input_173; [L1472] SORT_1 var_515_arg_1 = ~input_286; [L1473] var_515_arg_1 = var_515_arg_1 & mask_SORT_1 [L1474] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1475] SORT_1 var_516_arg_0 = var_515; [L1476] SORT_1 var_516_arg_1 = input_335; [L1477] SORT_1 var_516 = var_516_arg_0 | var_516_arg_1; [L1478] var_516 = var_516 & mask_SORT_1 [L1479] SORT_1 var_517_arg_0 = var_514; [L1480] SORT_1 var_517_arg_1 = var_516; [L1481] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L1482] SORT_1 var_518_arg_0 = var_306; [L1483] SORT_1 var_518_arg_1 = ~input_305; [L1484] var_518_arg_1 = var_518_arg_1 & mask_SORT_1 [L1485] SORT_1 var_518 = var_518_arg_0 & var_518_arg_1; [L1486] var_518 = var_518 & mask_SORT_1 [L1487] SORT_1 var_519_arg_0 = var_514; [L1488] SORT_1 var_519_arg_1 = var_516; [L1489] SORT_1 var_519 = var_519_arg_0 | var_519_arg_1; [L1490] SORT_1 var_520_arg_0 = var_518; [L1491] SORT_1 var_520_arg_1 = var_519; [L1492] SORT_1 var_520 = var_520_arg_0 & var_520_arg_1; [L1493] SORT_1 var_521_arg_0 = var_517; [L1494] SORT_1 var_521_arg_1 = var_520; [L1495] SORT_1 var_521 = var_521_arg_0 | var_521_arg_1; [L1496] SORT_1 var_522_arg_0 = var_316; [L1497] SORT_1 var_522_arg_1 = ~input_315; [L1498] var_522_arg_1 = var_522_arg_1 & mask_SORT_1 [L1499] SORT_1 var_522 = var_522_arg_0 & var_522_arg_1; [L1500] var_522 = var_522 & mask_SORT_1 [L1501] SORT_1 var_523_arg_0 = var_518; [L1502] SORT_1 var_523_arg_1 = var_519; [L1503] SORT_1 var_523 = var_523_arg_0 | var_523_arg_1; [L1504] SORT_1 var_524_arg_0 = var_522; [L1505] SORT_1 var_524_arg_1 = var_523; [L1506] SORT_1 var_524 = var_524_arg_0 & var_524_arg_1; [L1507] SORT_1 var_525_arg_0 = var_521; [L1508] SORT_1 var_525_arg_1 = var_524; [L1509] SORT_1 var_525 = var_525_arg_0 | var_525_arg_1; [L1510] SORT_1 var_526_arg_0 = var_522; [L1511] SORT_1 var_526_arg_1 = var_523; [L1512] SORT_1 var_526 = var_526_arg_0 | var_526_arg_1; [L1513] SORT_1 var_527_arg_0 = input_181; [L1514] SORT_1 var_527_arg_1 = var_526; [L1515] SORT_1 var_527 = var_527_arg_0 & var_527_arg_1; [L1516] SORT_1 var_528_arg_0 = var_525; [L1517] SORT_1 var_528_arg_1 = var_527; [L1518] SORT_1 var_528 = var_528_arg_0 | var_528_arg_1; [L1519] SORT_1 var_529_arg_0 = input_181; [L1520] SORT_1 var_529_arg_1 = var_526; [L1521] SORT_1 var_529 = var_529_arg_0 | var_529_arg_1; [L1522] SORT_1 var_530_arg_0 = input_183; [L1523] SORT_1 var_530_arg_1 = var_529; [L1524] SORT_1 var_530 = var_530_arg_0 & var_530_arg_1; [L1525] SORT_1 var_531_arg_0 = var_528; [L1526] SORT_1 var_531_arg_1 = var_530; [L1527] SORT_1 var_531 = var_531_arg_0 | var_531_arg_1; [L1528] SORT_1 var_532_arg_0 = var_326; [L1529] SORT_1 var_532_arg_1 = ~input_325; [L1530] var_532_arg_1 = var_532_arg_1 & mask_SORT_1 [L1531] SORT_1 var_532 = var_532_arg_0 & var_532_arg_1; [L1532] var_532 = var_532 & mask_SORT_1 [L1533] SORT_1 var_533_arg_0 = input_183; [L1534] SORT_1 var_533_arg_1 = var_529; [L1535] SORT_1 var_533 = var_533_arg_0 | var_533_arg_1; [L1536] SORT_1 var_534_arg_0 = var_532; [L1537] SORT_1 var_534_arg_1 = var_533; [L1538] SORT_1 var_534 = var_534_arg_0 & var_534_arg_1; [L1539] SORT_1 var_535_arg_0 = var_531; [L1540] SORT_1 var_535_arg_1 = var_534; [L1541] SORT_1 var_535 = var_535_arg_0 | var_535_arg_1; [L1542] SORT_1 var_536_arg_0 = var_336; [L1543] SORT_1 var_536_arg_1 = ~input_335; [L1544] var_536_arg_1 = var_536_arg_1 & mask_SORT_1 [L1545] SORT_1 var_536 = var_536_arg_0 & var_536_arg_1; [L1546] var_536 = var_536 & mask_SORT_1 [L1547] SORT_1 var_537_arg_0 = var_532; [L1548] SORT_1 var_537_arg_1 = var_533; [L1549] SORT_1 var_537 = var_537_arg_0 | var_537_arg_1; [L1550] SORT_1 var_538_arg_0 = var_536; [L1551] SORT_1 var_538_arg_1 = var_537; [L1552] SORT_1 var_538 = var_538_arg_0 & var_538_arg_1; [L1553] SORT_1 var_539_arg_0 = var_535; [L1554] SORT_1 var_539_arg_1 = var_538; [L1555] SORT_1 var_539 = var_539_arg_0 | var_539_arg_1; [L1556] SORT_1 var_540_arg_0 = var_513; [L1557] SORT_1 var_540_arg_1 = ~var_539; [L1558] var_540_arg_1 = var_540_arg_1 & mask_SORT_1 [L1559] SORT_1 var_540 = var_540_arg_0 & var_540_arg_1; [L1560] SORT_1 var_541_arg_0 = var_536; [L1561] SORT_1 var_541_arg_1 = var_537; [L1562] SORT_1 var_541 = var_541_arg_0 | var_541_arg_1; [L1563] SORT_1 var_542_arg_0 = var_540; [L1564] SORT_1 var_542_arg_1 = var_541; [L1565] SORT_1 var_542 = var_542_arg_0 & var_542_arg_1; [L1566] SORT_1 var_543_arg_0 = var_480; [L1567] SORT_1 var_543_arg_1 = var_542; [L1568] SORT_1 var_543 = var_543_arg_0 & var_543_arg_1; [L1569] SORT_4 var_544_arg_0 = var_200; [L1570] SORT_4 var_544_arg_1 = var_198; [L1571] SORT_4 var_544 = var_544_arg_0 - var_544_arg_1; [L1572] SORT_4 var_545_arg_0 = var_544; [L1573] SORT_2 var_545 = var_545_arg_0 >> 0; [L1574] SORT_1 var_546_arg_0 = input_197; [L1575] SORT_2 var_546_arg_1 = var_545; [L1576] SORT_2 var_546_arg_2 = input_129; [L1577] EXPR var_546_arg_0 ? var_546_arg_1 : var_546_arg_2 [L1577] SORT_2 var_546 = var_546_arg_0 ? var_546_arg_1 : var_546_arg_2; [L1578] var_546 = var_546 & mask_SORT_2 [L1579] SORT_2 var_547_arg_0 = var_546; [L1580] SORT_2 var_547_arg_1 = state_6; [L1581] SORT_1 var_547 = var_547_arg_0 == var_547_arg_1; [L1582] SORT_1 var_548_arg_0 = var_543; [L1583] SORT_1 var_548_arg_1 = var_547; [L1584] SORT_1 var_548 = var_548_arg_0 & var_548_arg_1; [L1585] SORT_4 var_549_arg_0 = var_344; [L1586] SORT_4 var_549_arg_1 = var_198; [L1587] SORT_4 var_549 = var_549_arg_0 - var_549_arg_1; [L1588] SORT_4 var_550_arg_0 = var_549; [L1589] SORT_2 var_550 = var_550_arg_0 >> 0; [L1590] SORT_1 var_551_arg_0 = input_340; [L1591] SORT_2 var_551_arg_1 = var_550; [L1592] SORT_2 var_551_arg_2 = var_343; [L1593] EXPR var_551_arg_0 ? var_551_arg_1 : var_551_arg_2 [L1593] SORT_2 var_551 = var_551_arg_0 ? var_551_arg_1 : var_551_arg_2; [L1594] var_551 = var_551 & mask_SORT_2 [L1595] SORT_3 var_552_arg_0 = var_199; [L1596] SORT_2 var_552_arg_1 = var_551; [L1597] SORT_4 var_552 = ((SORT_4)var_552_arg_0 << 8) | var_552_arg_1; [L1598] SORT_4 var_553_arg_0 = var_202; [L1599] SORT_4 var_553_arg_1 = var_552; [L1600] SORT_4 var_553 = var_553_arg_0 + var_553_arg_1; [L1601] SORT_4 var_554_arg_0 = var_553; [L1602] SORT_2 var_554 = var_554_arg_0 >> 0; [L1603] SORT_1 var_555_arg_0 = input_349; [L1604] SORT_2 var_555_arg_1 = var_554; [L1605] SORT_2 var_555_arg_2 = var_551; [L1606] EXPR var_555_arg_0 ? var_555_arg_1 : var_555_arg_2 [L1606] SORT_2 var_555 = var_555_arg_0 ? var_555_arg_1 : var_555_arg_2; [L1607] var_555 = var_555 & mask_SORT_2 [L1608] SORT_2 var_556_arg_0 = var_555; [L1609] SORT_2 var_556_arg_1 = state_8; [L1610] SORT_1 var_556 = var_556_arg_0 == var_556_arg_1; [L1611] SORT_1 var_557_arg_0 = var_548; [L1612] SORT_1 var_557_arg_1 = var_556; [L1613] SORT_1 var_557 = var_557_arg_0 & var_557_arg_1; [L1614] SORT_4 var_558_arg_0 = var_358; [L1615] SORT_4 var_558_arg_1 = var_202; [L1616] SORT_4 var_558 = var_558_arg_0 - var_558_arg_1; [L1617] SORT_4 var_559_arg_0 = var_558; [L1618] SORT_2 var_559 = var_559_arg_0 >> 0; [L1619] SORT_1 var_560_arg_0 = input_349; [L1620] SORT_2 var_560_arg_1 = var_559; [L1621] SORT_2 var_560_arg_2 = var_357; [L1622] EXPR var_560_arg_0 ? var_560_arg_1 : var_560_arg_2 [L1622] SORT_2 var_560 = var_560_arg_0 ? var_560_arg_1 : var_560_arg_2; [L1623] var_560 = var_560 & mask_SORT_2 [L1624] SORT_2 var_561_arg_0 = var_560; [L1625] SORT_2 var_561_arg_1 = state_10; [L1626] SORT_1 var_561 = var_561_arg_0 == var_561_arg_1; [L1627] SORT_1 var_562_arg_0 = var_557; [L1628] SORT_1 var_562_arg_1 = var_561; [L1629] SORT_1 var_562 = var_562_arg_0 & var_562_arg_1; [L1630] SORT_4 var_563_arg_0 = var_320; [L1631] SORT_4 var_563_arg_1 = var_198; [L1632] SORT_4 var_563 = var_563_arg_0 - var_563_arg_1; [L1633] SORT_4 var_564_arg_0 = var_563; [L1634] SORT_2 var_564 = var_564_arg_0 >> 0; [L1635] SORT_1 var_565_arg_0 = input_335; [L1636] SORT_2 var_565_arg_1 = var_564; [L1637] SORT_2 var_565_arg_2 = var_319; [L1638] EXPR var_565_arg_0 ? var_565_arg_1 : var_565_arg_2 [L1638] SORT_2 var_565 = var_565_arg_0 ? var_565_arg_1 : var_565_arg_2; [L1639] var_565 = var_565 & mask_SORT_2 [L1640] SORT_3 var_566_arg_0 = var_199; [L1641] SORT_2 var_566_arg_1 = var_565; [L1642] SORT_4 var_566 = ((SORT_4)var_566_arg_0 << 8) | var_566_arg_1; [L1643] SORT_4 var_567_arg_0 = var_198; [L1644] SORT_4 var_567_arg_1 = var_566; [L1645] SORT_4 var_567 = var_567_arg_0 + var_567_arg_1; [L1646] SORT_4 var_568_arg_0 = var_567; [L1647] SORT_2 var_568 = var_568_arg_0 >> 0; [L1648] SORT_1 var_569_arg_0 = input_349; [L1649] SORT_2 var_569_arg_1 = var_568; [L1650] SORT_2 var_569_arg_2 = var_565; [L1651] EXPR var_569_arg_0 ? var_569_arg_1 : var_569_arg_2 [L1651] SORT_2 var_569 = var_569_arg_0 ? var_569_arg_1 : var_569_arg_2; [L1652] var_569 = var_569 & mask_SORT_2 [L1653] SORT_2 var_570_arg_0 = var_569; [L1654] SORT_2 var_570_arg_1 = state_12; [L1655] SORT_1 var_570 = var_570_arg_0 == var_570_arg_1; [L1656] SORT_1 var_571_arg_0 = var_562; [L1657] SORT_1 var_571_arg_1 = var_570; [L1658] SORT_1 var_571 = var_571_arg_0 & var_571_arg_1; [L1659] SORT_4 var_572_arg_0 = var_393; [L1660] SORT_4 var_572_arg_1 = var_198; [L1661] SORT_4 var_572 = var_572_arg_0 - var_572_arg_1; [L1662] SORT_4 var_573_arg_0 = var_572; [L1663] SORT_2 var_573 = var_573_arg_0 >> 0; [L1664] SORT_1 var_574_arg_0 = input_349; [L1665] SORT_2 var_574_arg_1 = var_573; [L1666] SORT_2 var_574_arg_2 = var_392; [L1667] EXPR var_574_arg_0 ? var_574_arg_1 : var_574_arg_2 [L1667] SORT_2 var_574 = var_574_arg_0 ? var_574_arg_1 : var_574_arg_2; [L1668] var_574 = var_574 & mask_SORT_2 [L1669] SORT_2 var_575_arg_0 = var_574; [L1670] SORT_2 var_575_arg_1 = state_14; [L1671] SORT_1 var_575 = var_575_arg_0 == var_575_arg_1; [L1672] SORT_1 var_576_arg_0 = var_571; [L1673] SORT_1 var_576_arg_1 = var_575; [L1674] SORT_1 var_576 = var_576_arg_0 & var_576_arg_1; [L1675] SORT_4 var_577_arg_0 = var_219; [L1676] SORT_4 var_577_arg_1 = var_198; [L1677] SORT_4 var_577 = var_577_arg_0 - var_577_arg_1; [L1678] SORT_4 var_578_arg_0 = var_577; [L1679] SORT_2 var_578 = var_578_arg_0 >> 0; [L1680] SORT_1 var_579_arg_0 = input_214; [L1681] SORT_2 var_579_arg_1 = var_578; [L1682] SORT_2 var_579_arg_2 = var_218; [L1683] EXPR var_579_arg_0 ? var_579_arg_1 : var_579_arg_2 [L1683] SORT_2 var_579 = var_579_arg_0 ? var_579_arg_1 : var_579_arg_2; [L1684] var_579 = var_579 & mask_SORT_2 [L1685] SORT_2 var_580_arg_0 = var_579; [L1686] SORT_2 var_580_arg_1 = state_16; [L1687] SORT_1 var_580 = var_580_arg_0 == var_580_arg_1; [L1688] SORT_1 var_581_arg_0 = var_576; [L1689] SORT_1 var_581_arg_1 = var_580; [L1690] SORT_1 var_581 = var_581_arg_0 & var_581_arg_1; [L1691] SORT_4 var_582_arg_0 = var_290; [L1692] SORT_4 var_582_arg_1 = var_198; [L1693] SORT_4 var_582 = var_582_arg_0 - var_582_arg_1; [L1694] SORT_4 var_583_arg_0 = var_582; [L1695] SORT_2 var_583 = var_583_arg_0 >> 0; [L1696] SORT_1 var_584_arg_0 = input_286; [L1697] SORT_2 var_584_arg_1 = var_583; [L1698] SORT_2 var_584_arg_2 = var_289; [L1699] EXPR var_584_arg_0 ? var_584_arg_1 : var_584_arg_2 [L1699] SORT_2 var_584 = var_584_arg_0 ? var_584_arg_1 : var_584_arg_2; [L1700] var_584 = var_584 & mask_SORT_2 [L1701] SORT_2 var_585_arg_0 = var_584; [L1702] SORT_2 var_585_arg_1 = state_18; [L1703] SORT_1 var_585 = var_585_arg_0 == var_585_arg_1; [L1704] SORT_1 var_586_arg_0 = var_581; [L1705] SORT_1 var_586_arg_1 = var_585; [L1706] SORT_1 var_586 = var_586_arg_0 & var_586_arg_1; [L1707] SORT_4 var_587_arg_0 = var_395; [L1708] SORT_4 var_587_arg_1 = var_198; [L1709] SORT_4 var_587 = var_587_arg_0 - var_587_arg_1; [L1710] SORT_4 var_588_arg_0 = var_587; [L1711] SORT_2 var_588 = var_588_arg_0 >> 0; [L1712] SORT_1 var_589_arg_0 = input_349; [L1713] SORT_2 var_589_arg_1 = var_588; [L1714] SORT_2 var_589_arg_2 = input_143; [L1715] EXPR var_589_arg_0 ? var_589_arg_1 : var_589_arg_2 [L1715] SORT_2 var_589 = var_589_arg_0 ? var_589_arg_1 : var_589_arg_2; [L1716] var_589 = var_589 & mask_SORT_2 [L1717] SORT_2 var_590_arg_0 = var_589; [L1718] SORT_2 var_590_arg_1 = state_20; [L1719] SORT_1 var_590 = var_590_arg_0 == var_590_arg_1; [L1720] SORT_1 var_591_arg_0 = var_586; [L1721] SORT_1 var_591_arg_1 = var_590; [L1722] SORT_1 var_591 = var_591_arg_0 & var_591_arg_1; [L1723] SORT_3 var_592_arg_0 = var_199; [L1724] SORT_2 var_592_arg_1 = input_145; [L1725] SORT_4 var_592 = ((SORT_4)var_592_arg_0 << 8) | var_592_arg_1; [L1726] SORT_4 var_593_arg_0 = var_198; [L1727] SORT_4 var_593_arg_1 = var_592; [L1728] SORT_4 var_593 = var_593_arg_0 + var_593_arg_1; [L1729] SORT_4 var_594_arg_0 = var_593; [L1730] SORT_2 var_594 = var_594_arg_0 >> 0; [L1731] SORT_1 var_595_arg_0 = input_214; [L1732] SORT_2 var_595_arg_1 = var_594; [L1733] SORT_2 var_595_arg_2 = input_145; [L1734] EXPR var_595_arg_0 ? var_595_arg_1 : var_595_arg_2 [L1734] SORT_2 var_595 = var_595_arg_0 ? var_595_arg_1 : var_595_arg_2; [L1735] var_595 = var_595 & mask_SORT_2 [L1736] SORT_3 var_596_arg_0 = var_199; [L1737] SORT_2 var_596_arg_1 = var_595; [L1738] SORT_4 var_596 = ((SORT_4)var_596_arg_0 << 8) | var_596_arg_1; [L1739] SORT_4 var_597_arg_0 = var_198; [L1740] SORT_4 var_597_arg_1 = var_596; [L1741] SORT_4 var_597 = var_597_arg_0 + var_597_arg_1; [L1742] SORT_4 var_598_arg_0 = var_597; [L1743] SORT_2 var_598 = var_598_arg_0 >> 0; [L1744] SORT_1 var_599_arg_0 = input_251; [L1745] SORT_2 var_599_arg_1 = var_598; [L1746] SORT_2 var_599_arg_2 = var_595; [L1747] EXPR var_599_arg_0 ? var_599_arg_1 : var_599_arg_2 [L1747] SORT_2 var_599 = var_599_arg_0 ? var_599_arg_1 : var_599_arg_2; [L1748] var_599 = var_599 & mask_SORT_2 [L1749] SORT_3 var_600_arg_0 = var_199; [L1750] SORT_2 var_600_arg_1 = var_599; [L1751] SORT_4 var_600 = ((SORT_4)var_600_arg_0 << 8) | var_600_arg_1; [L1752] SORT_4 var_601_arg_0 = var_198; [L1753] SORT_4 var_601_arg_1 = var_600; [L1754] SORT_4 var_601 = var_601_arg_0 + var_601_arg_1; [L1755] SORT_4 var_602_arg_0 = var_601; [L1756] SORT_2 var_602 = var_602_arg_0 >> 0; [L1757] SORT_1 var_603_arg_0 = input_261; [L1758] SORT_2 var_603_arg_1 = var_602; [L1759] SORT_2 var_603_arg_2 = var_599; [L1760] EXPR var_603_arg_0 ? var_603_arg_1 : var_603_arg_2 [L1760] SORT_2 var_603 = var_603_arg_0 ? var_603_arg_1 : var_603_arg_2; [L1761] var_603 = var_603 & mask_SORT_2 [L1762] SORT_3 var_604_arg_0 = var_199; [L1763] SORT_2 var_604_arg_1 = var_603; [L1764] SORT_4 var_604 = ((SORT_4)var_604_arg_0 << 8) | var_604_arg_1; [L1765] SORT_4 var_605_arg_0 = var_198; [L1766] SORT_4 var_605_arg_1 = var_604; [L1767] SORT_4 var_605 = var_605_arg_0 + var_605_arg_1; [L1768] SORT_4 var_606_arg_0 = var_605; [L1769] SORT_2 var_606 = var_606_arg_0 >> 0; [L1770] SORT_1 var_607_arg_0 = input_305; [L1771] SORT_2 var_607_arg_1 = var_606; [L1772] SORT_2 var_607_arg_2 = var_603; [L1773] EXPR var_607_arg_0 ? var_607_arg_1 : var_607_arg_2 [L1773] SORT_2 var_607 = var_607_arg_0 ? var_607_arg_1 : var_607_arg_2; [L1774] var_607 = var_607 & mask_SORT_2 [L1775] SORT_3 var_608_arg_0 = var_199; [L1776] SORT_2 var_608_arg_1 = var_607; [L1777] SORT_4 var_608 = ((SORT_4)var_608_arg_0 << 8) | var_608_arg_1; [L1778] SORT_4 var_609_arg_0 = var_198; [L1779] SORT_4 var_609_arg_1 = var_608; [L1780] SORT_4 var_609 = var_609_arg_0 + var_609_arg_1; [L1781] SORT_4 var_610_arg_0 = var_609; [L1782] SORT_2 var_610 = var_610_arg_0 >> 0; [L1783] SORT_1 var_611_arg_0 = input_315; [L1784] SORT_2 var_611_arg_1 = var_610; [L1785] SORT_2 var_611_arg_2 = var_607; [L1786] EXPR var_611_arg_0 ? var_611_arg_1 : var_611_arg_2 [L1786] SORT_2 var_611 = var_611_arg_0 ? var_611_arg_1 : var_611_arg_2; [L1787] var_611 = var_611 & mask_SORT_2 [L1788] SORT_2 var_612_arg_0 = var_611; [L1789] SORT_2 var_612_arg_1 = state_22; [L1790] SORT_1 var_612 = var_612_arg_0 == var_612_arg_1; [L1791] SORT_1 var_613_arg_0 = var_591; [L1792] SORT_1 var_613_arg_1 = var_612; [L1793] SORT_1 var_613 = var_613_arg_0 & var_613_arg_1; [L1794] SORT_4 var_614_arg_0 = var_410; [L1795] SORT_4 var_614_arg_1 = var_202; [L1796] SORT_4 var_614 = var_614_arg_0 - var_614_arg_1; [L1797] SORT_4 var_615_arg_0 = var_614; [L1798] SORT_2 var_615 = var_615_arg_0 >> 0; [L1799] SORT_1 var_616_arg_0 = input_349; [L1800] SORT_2 var_616_arg_1 = var_615; [L1801] SORT_2 var_616_arg_2 = var_409; [L1802] EXPR var_616_arg_0 ? var_616_arg_1 : var_616_arg_2 [L1802] SORT_2 var_616 = var_616_arg_0 ? var_616_arg_1 : var_616_arg_2; [L1803] var_616 = var_616 & mask_SORT_2 [L1804] SORT_2 var_617_arg_0 = var_616; [L1805] SORT_2 var_617_arg_1 = state_24; [L1806] SORT_1 var_617 = var_617_arg_0 == var_617_arg_1; [L1807] SORT_1 var_618_arg_0 = var_613; [L1808] SORT_1 var_618_arg_1 = var_617; [L1809] SORT_1 var_618 = var_618_arg_0 & var_618_arg_1; [L1810] SORT_4 var_619_arg_0 = var_330; [L1811] SORT_4 var_619_arg_1 = var_198; [L1812] SORT_4 var_619 = var_619_arg_0 - var_619_arg_1; [L1813] SORT_4 var_620_arg_0 = var_619; [L1814] SORT_2 var_620 = var_620_arg_0 >> 0; [L1815] SORT_1 var_621_arg_0 = input_325; [L1816] SORT_2 var_621_arg_1 = var_620; [L1817] SORT_2 var_621_arg_2 = var_329; [L1818] EXPR var_621_arg_0 ? var_621_arg_1 : var_621_arg_2 [L1818] SORT_2 var_621 = var_621_arg_0 ? var_621_arg_1 : var_621_arg_2; [L1819] var_621 = var_621 & mask_SORT_2 [L1820] SORT_3 var_622_arg_0 = var_199; [L1821] SORT_2 var_622_arg_1 = var_621; [L1822] SORT_4 var_622 = ((SORT_4)var_622_arg_0 << 8) | var_622_arg_1; [L1823] SORT_4 var_623_arg_0 = var_198; [L1824] SORT_4 var_623_arg_1 = var_622; [L1825] SORT_4 var_623 = var_623_arg_0 + var_623_arg_1; [L1826] SORT_4 var_624_arg_0 = var_623; [L1827] SORT_2 var_624 = var_624_arg_0 >> 0; [L1828] SORT_1 var_625_arg_0 = input_349; [L1829] SORT_2 var_625_arg_1 = var_624; [L1830] SORT_2 var_625_arg_2 = var_621; [L1831] EXPR var_625_arg_0 ? var_625_arg_1 : var_625_arg_2 [L1831] SORT_2 var_625 = var_625_arg_0 ? var_625_arg_1 : var_625_arg_2; [L1832] var_625 = var_625 & mask_SORT_2 [L1833] SORT_2 var_626_arg_0 = var_625; [L1834] SORT_2 var_626_arg_1 = state_26; [L1835] SORT_1 var_626 = var_626_arg_0 == var_626_arg_1; [L1836] SORT_1 var_627_arg_0 = var_618; [L1837] SORT_1 var_627_arg_1 = var_626; [L1838] SORT_1 var_627 = var_627_arg_0 & var_627_arg_1; [L1839] SORT_3 var_628_arg_0 = var_199; [L1840] SORT_2 var_628_arg_1 = input_151; [L1841] SORT_4 var_628 = ((SORT_4)var_628_arg_0 << 8) | var_628_arg_1; [L1842] var_628 = var_628 & mask_SORT_4 [L1843] SORT_4 var_629_arg_0 = var_198; [L1844] SORT_4 var_629_arg_1 = var_628; [L1845] SORT_4 var_629 = var_629_arg_0 + var_629_arg_1; [L1846] SORT_4 var_630_arg_0 = var_629; [L1847] SORT_2 var_630 = var_630_arg_0 >> 0; [L1848] SORT_1 var_631_arg_0 = input_340; [L1849] SORT_2 var_631_arg_1 = var_630; [L1850] SORT_2 var_631_arg_2 = input_151; [L1851] EXPR var_631_arg_0 ? var_631_arg_1 : var_631_arg_2 [L1851] SORT_2 var_631 = var_631_arg_0 ? var_631_arg_1 : var_631_arg_2; [L1852] var_631 = var_631 & mask_SORT_2 [L1853] SORT_2 var_632_arg_0 = var_631; [L1854] SORT_2 var_632_arg_1 = state_28; [L1855] SORT_1 var_632 = var_632_arg_0 == var_632_arg_1; [L1856] SORT_1 var_633_arg_0 = var_627; [L1857] SORT_1 var_633_arg_1 = var_632; [L1858] SORT_1 var_633 = var_633_arg_0 & var_633_arg_1; [L1859] SORT_1 var_634_arg_0 = input_153; [L1860] SORT_1 var_634_arg_1 = state_31; [L1861] SORT_1 var_634 = var_634_arg_0 == var_634_arg_1; [L1862] SORT_1 var_635_arg_0 = var_633; [L1863] SORT_1 var_635_arg_1 = var_634; [L1864] SORT_1 var_635 = var_635_arg_0 & var_635_arg_1; [L1865] SORT_1 var_636_arg_0 = input_155; [L1866] SORT_1 var_636_arg_1 = state_33; [L1867] SORT_1 var_636 = var_636_arg_0 == var_636_arg_1; [L1868] SORT_1 var_637_arg_0 = var_635; [L1869] SORT_1 var_637_arg_1 = var_636; [L1870] SORT_1 var_637 = var_637_arg_0 & var_637_arg_1; [L1871] SORT_1 var_638_arg_0 = var_487; [L1872] SORT_1 var_638_arg_1 = state_35; [L1873] SORT_1 var_638 = var_638_arg_0 == var_638_arg_1; [L1874] SORT_1 var_639_arg_0 = var_637; [L1875] SORT_1 var_639_arg_1 = var_638; [L1876] SORT_1 var_639 = var_639_arg_0 & var_639_arg_1; [L1877] SORT_1 var_640_arg_0 = var_485; [L1878] SORT_1 var_640_arg_1 = state_37; [L1879] SORT_1 var_640 = var_640_arg_0 == var_640_arg_1; [L1880] SORT_1 var_641_arg_0 = var_639; [L1881] SORT_1 var_641_arg_1 = var_640; [L1882] SORT_1 var_641 = var_641_arg_0 & var_641_arg_1; [L1883] SORT_1 var_642_arg_0 = var_489; [L1884] SORT_1 var_642_arg_1 = state_39; [L1885] SORT_1 var_642 = var_642_arg_0 == var_642_arg_1; [L1886] SORT_1 var_643_arg_0 = var_641; [L1887] SORT_1 var_643_arg_1 = var_642; [L1888] SORT_1 var_643 = var_643_arg_0 & var_643_arg_1; [L1889] SORT_1 var_644_arg_0 = var_493; [L1890] SORT_1 var_644_arg_1 = state_41; [L1891] SORT_1 var_644 = var_644_arg_0 == var_644_arg_1; [L1892] SORT_1 var_645_arg_0 = var_643; [L1893] SORT_1 var_645_arg_1 = var_644; [L1894] SORT_1 var_645 = var_645_arg_0 & var_645_arg_1; [L1895] SORT_1 var_646_arg_0 = input_165; [L1896] SORT_1 var_646_arg_1 = state_43; [L1897] SORT_1 var_646 = var_646_arg_0 == var_646_arg_1; [L1898] SORT_1 var_647_arg_0 = var_645; [L1899] SORT_1 var_647_arg_1 = var_646; [L1900] SORT_1 var_647 = var_647_arg_0 & var_647_arg_1; [L1901] SORT_1 var_648_arg_0 = input_167; [L1902] SORT_1 var_648_arg_1 = state_45; [L1903] SORT_1 var_648 = var_648_arg_0 == var_648_arg_1; [L1904] SORT_1 var_649_arg_0 = var_647; [L1905] SORT_1 var_649_arg_1 = var_648; [L1906] SORT_1 var_649 = var_649_arg_0 & var_649_arg_1; [L1907] SORT_1 var_650_arg_0 = var_503; [L1908] SORT_1 var_650_arg_1 = state_47; [L1909] SORT_1 var_650 = var_650_arg_0 == var_650_arg_1; [L1910] SORT_1 var_651_arg_0 = var_649; [L1911] SORT_1 var_651_arg_1 = var_650; [L1912] SORT_1 var_651 = var_651_arg_0 & var_651_arg_1; [L1913] SORT_1 var_652_arg_0 = var_507; [L1914] SORT_1 var_652_arg_1 = state_49; [L1915] SORT_1 var_652 = var_652_arg_0 == var_652_arg_1; [L1916] SORT_1 var_653_arg_0 = var_651; [L1917] SORT_1 var_653_arg_1 = var_652; [L1918] SORT_1 var_653 = var_653_arg_0 & var_653_arg_1; [L1919] SORT_1 var_654_arg_0 = var_516; [L1920] SORT_1 var_654_arg_1 = state_51; [L1921] SORT_1 var_654 = var_654_arg_0 == var_654_arg_1; [L1922] SORT_1 var_655_arg_0 = var_653; [L1923] SORT_1 var_655_arg_1 = var_654; [L1924] SORT_1 var_655 = var_655_arg_0 & var_655_arg_1; [L1925] SORT_1 var_656_arg_0 = var_514; [L1926] SORT_1 var_656_arg_1 = state_53; [L1927] SORT_1 var_656 = var_656_arg_0 == var_656_arg_1; [L1928] SORT_1 var_657_arg_0 = var_655; [L1929] SORT_1 var_657_arg_1 = var_656; [L1930] SORT_1 var_657 = var_657_arg_0 & var_657_arg_1; [L1931] SORT_1 var_658_arg_0 = var_518; [L1932] SORT_1 var_658_arg_1 = state_55; [L1933] SORT_1 var_658 = var_658_arg_0 == var_658_arg_1; [L1934] SORT_1 var_659_arg_0 = var_657; [L1935] SORT_1 var_659_arg_1 = var_658; [L1936] SORT_1 var_659 = var_659_arg_0 & var_659_arg_1; [L1937] SORT_1 var_660_arg_0 = var_522; [L1938] SORT_1 var_660_arg_1 = state_57; [L1939] SORT_1 var_660 = var_660_arg_0 == var_660_arg_1; [L1940] SORT_1 var_661_arg_0 = var_659; [L1941] SORT_1 var_661_arg_1 = var_660; [L1942] SORT_1 var_661 = var_661_arg_0 & var_661_arg_1; [L1943] SORT_1 var_662_arg_0 = input_181; [L1944] SORT_1 var_662_arg_1 = state_59; [L1945] SORT_1 var_662 = var_662_arg_0 == var_662_arg_1; [L1946] SORT_1 var_663_arg_0 = var_661; [L1947] SORT_1 var_663_arg_1 = var_662; [L1948] SORT_1 var_663 = var_663_arg_0 & var_663_arg_1; [L1949] SORT_1 var_664_arg_0 = input_183; [L1950] SORT_1 var_664_arg_1 = state_61; [L1951] SORT_1 var_664 = var_664_arg_0 == var_664_arg_1; [L1952] SORT_1 var_665_arg_0 = var_663; [L1953] SORT_1 var_665_arg_1 = var_664; [L1954] SORT_1 var_665 = var_665_arg_0 & var_665_arg_1; [L1955] SORT_1 var_666_arg_0 = var_532; [L1956] SORT_1 var_666_arg_1 = state_63; [L1957] SORT_1 var_666 = var_666_arg_0 == var_666_arg_1; [L1958] SORT_1 var_667_arg_0 = var_665; [L1959] SORT_1 var_667_arg_1 = var_666; [L1960] SORT_1 var_667 = var_667_arg_0 & var_667_arg_1; [L1961] SORT_1 var_668_arg_0 = var_536; [L1962] SORT_1 var_668_arg_1 = state_65; [L1963] SORT_1 var_668 = var_668_arg_0 == var_668_arg_1; [L1964] SORT_1 var_669_arg_0 = var_667; [L1965] SORT_1 var_669_arg_1 = var_668; [L1966] SORT_1 var_669 = var_669_arg_0 & var_669_arg_1; [L1967] SORT_1 var_670_arg_0 = input_189; [L1968] SORT_1 var_670_arg_1 = state_67; [L1969] SORT_1 var_670 = var_670_arg_0 == var_670_arg_1; [L1970] SORT_1 var_671_arg_0 = var_669; [L1971] SORT_1 var_671_arg_1 = var_670; [L1972] SORT_1 var_671 = var_671_arg_0 & var_671_arg_1; [L1973] SORT_1 var_672_arg_0 = input_191; [L1974] SORT_1 var_672_arg_1 = state_69; [L1975] SORT_1 var_672 = var_672_arg_0 == var_672_arg_1; [L1976] SORT_1 var_673_arg_0 = var_671; [L1977] SORT_1 var_673_arg_1 = var_672; [L1978] SORT_1 var_673 = var_673_arg_0 & var_673_arg_1; [L1979] SORT_1 var_674_arg_0 = input_193; [L1980] SORT_1 var_674_arg_1 = state_71; [L1981] SORT_1 var_674 = var_674_arg_0 == var_674_arg_1; [L1982] SORT_1 var_675_arg_0 = var_673; [L1983] SORT_1 var_675_arg_1 = var_674; [L1984] SORT_1 var_675 = var_675_arg_0 & var_675_arg_1; [L1985] SORT_1 var_676_arg_0 = var_675; [L1986] SORT_1 var_676_arg_1 = state_75; [L1987] SORT_1 var_676 = var_676_arg_0 & var_676_arg_1; [L1988] SORT_4 var_678_arg_0 = var_628; [L1989] SORT_4 var_678_arg_1 = var_677; [L1990] SORT_1 var_678 = var_678_arg_0 <= var_678_arg_1; [L1991] SORT_1 var_679_arg_0 = state_73; [L1992] SORT_1 var_679_arg_1 = var_676; [L1993] SORT_1 var_679_arg_2 = ~var_678; [L1994] var_679_arg_2 = var_679_arg_2 & mask_SORT_1 [L1995] EXPR var_679_arg_0 ? var_679_arg_1 : var_679_arg_2 [L1995] SORT_1 var_679 = var_679_arg_0 ? var_679_arg_1 : var_679_arg_2; [L1996] SORT_1 next_680_arg_1 = var_679; [L1998] state_6 = next_130_arg_1 [L1999] state_8 = next_132_arg_1 [L2000] state_10 = next_134_arg_1 [L2001] state_12 = next_136_arg_1 [L2002] state_14 = next_138_arg_1 [L2003] state_16 = next_140_arg_1 [L2004] state_18 = next_142_arg_1 [L2005] state_20 = next_144_arg_1 [L2006] state_22 = next_146_arg_1 [L2007] state_24 = next_148_arg_1 [L2008] state_26 = next_150_arg_1 [L2009] state_28 = next_152_arg_1 [L2010] state_31 = next_154_arg_1 [L2011] state_33 = next_156_arg_1 [L2012] state_35 = next_158_arg_1 [L2013] state_37 = next_160_arg_1 [L2014] state_39 = next_162_arg_1 [L2015] state_41 = next_164_arg_1 [L2016] state_43 = next_166_arg_1 [L2017] state_45 = next_168_arg_1 [L2018] state_47 = next_170_arg_1 [L2019] state_49 = next_172_arg_1 [L2020] state_51 = next_174_arg_1 [L2021] state_53 = next_176_arg_1 [L2022] state_55 = next_178_arg_1 [L2023] state_57 = next_180_arg_1 [L2024] state_59 = next_182_arg_1 [L2025] state_61 = next_184_arg_1 [L2026] state_63 = next_186_arg_1 [L2027] state_65 = next_188_arg_1 [L2028] state_67 = next_190_arg_1 [L2029] state_69 = next_192_arg_1 [L2030] state_71 = next_194_arg_1 [L2031] state_73 = next_196_arg_1 [L2032] state_75 = next_680_arg_1 VAL [bad_128_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_76_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_129=10, input_131=4, input_133=4, input_135=12, input_137=2, input_139=0, input_141=0, input_143=15, input_145=0, input_147=10, input_149=10, input_151=0, input_153=1, input_155=1, input_157=1, input_159=0, input_161=0, input_163=1, input_165=0, input_167=1, input_169=1, input_171=1, input_173=1, input_175=1, input_177=1, input_179=0, input_181=1, input_183=0, input_185=1, input_187=1, input_189=1, input_191=1, input_193=1, input_197=1, input_214=1, input_230=1, input_248=9, input_251=0, input_261=0, input_271=1, input_281=0, input_286=1, input_302=11, input_305=1, input_315=0, input_325=0, input_335=0, input_340=0, input_349=1, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, next_130_arg_1=10, next_132_arg_1=4, next_134_arg_1=4, next_136_arg_1=12, next_138_arg_1=2, next_140_arg_1=0, next_142_arg_1=0, next_144_arg_1=15, next_146_arg_1=0, next_148_arg_1=10, next_150_arg_1=10, next_152_arg_1=0, next_154_arg_1=1, next_156_arg_1=1, next_158_arg_1=1, next_160_arg_1=0, next_162_arg_1=0, next_164_arg_1=1, next_166_arg_1=0, next_168_arg_1=1, next_170_arg_1=1, next_172_arg_1=1, next_174_arg_1=1, next_176_arg_1=1, next_178_arg_1=1, next_180_arg_1=0, next_182_arg_1=1, next_184_arg_1=0, next_186_arg_1=1, next_188_arg_1=1, next_190_arg_1=1, next_192_arg_1=1, next_194_arg_1=1, next_196_arg_1=1, next_680_arg_1=1, state_10=4, state_12=12, state_14=2, state_16=0, state_18=0, state_20=15, state_22=0, state_24=10, state_26=10, state_28=0, state_31=1, state_33=1, state_35=1, state_37=0, state_39=0, state_41=1, state_43=0, state_45=1, state_47=1, state_49=1, state_51=1, state_53=1, state_55=1, state_57=0, state_59=1, state_6=10, state_61=0, state_63=1, state_65=1, state_67=1, state_69=1, state_71=1, state_73=1, state_75=1, state_8=4, var_100=4, var_101=0, var_101_arg_0=4, var_101_arg_1=0, var_102=0, var_102_arg_0=0, var_102_arg_1=0, var_103=0, var_103_arg_0=4, var_103_arg_1=0, var_104=0, var_104_arg_0=0, var_104_arg_1=0, var_105=12, var_106=0, var_106_arg_0=12, var_106_arg_1=0, var_107=0, var_107_arg_0=0, var_107_arg_1=0, var_108=2, var_109=0, var_109_arg_0=2, var_109_arg_1=0, var_110=0, var_110_arg_0=0, var_110_arg_1=0, var_111=0, var_112=1, var_112_arg_0=0, var_112_arg_1=0, var_113=0, var_113_arg_0=0, var_113_arg_1=1, var_114=1, var_114_arg_0=0, var_114_arg_1=0, var_115=0, var_115_arg_0=0, var_115_arg_1=1, var_116=15, var_117=0, var_117_arg_0=15, var_117_arg_1=0, var_118=0, var_118_arg_0=0, var_118_arg_1=0, var_119=1, var_119_arg_0=0, var_119_arg_1=0, var_120=0, var_120_arg_0=0, var_120_arg_1=1, var_121=0, var_121_arg_0=10, var_121_arg_1=0, var_122=0, var_122_arg_0=0, var_122_arg_1=0, var_123=0, var_123_arg_0=10, var_123_arg_1=0, var_124=0, var_124_arg_0=0, var_124_arg_1=0, var_125=1, var_125_arg_0=0, var_125_arg_1=0, var_126=0, var_126_arg_0=0, var_126_arg_1=1, var_127=0, var_127_arg_0=0, var_127_arg_1=0, var_195=1, var_198=1, var_199=0, var_200=4294966795, var_200_arg_0=0, var_200_arg_1=10, var_201=1, var_201_arg_0=1, var_201_arg_1=4294966795, var_202=2, var_203=1, var_203_arg_0=0, var_203_arg_1=4, var_204=0, var_204_arg_0=2, var_204_arg_1=1, var_205=0, var_205_arg_0=1, var_205_arg_1=0, var_206=0, var_206_arg_0=0, var_206_arg_1=4, var_207=0, var_207_arg_0=2, var_207_arg_1=0, var_208=0, var_208_arg_0=0, var_208_arg_1=0, var_209=14, var_209_arg_0=0, var_209_arg_1=12, var_210=1, var_210_arg_0=2, var_210_arg_1=14, var_211=0, var_211_arg_0=0, var_211_arg_1=1, var_212=0, var_212_arg_0=1, var_212_arg_1=0, var_213=1, var_213_arg_0=1, var_213_arg_1=0, var_215=0, var_215_arg_0=0, var_215_arg_1=0, var_216=2, var_216_arg_0=2, var_216_arg_1=0, var_217=2, var_217_arg_0=2, var_218=255, var_218_arg_0=1, var_218_arg_1=2, var_218_arg_2=0, var_219=0, var_219_arg_0=0, var_219_arg_1=255, var_220=0, var_220_arg_0=1, var_220_arg_1=0, var_221=12, var_221_arg_0=14, var_221_arg_1=2, var_222=12, var_222_arg_0=12, var_223=1, var_223_arg_0=1, var_223_arg_1=12, var_223_arg_2=12, var_224=244, var_224_arg_0=0, var_224_arg_1=1, var_225=1, var_225_arg_0=1, var_225_arg_1=244, var_226=0, var_226_arg_0=0, var_226_arg_1=1, var_227=0, var_227_arg_0=1, var_227_arg_1=0, var_228=0, var_228_arg_0=0, var_228_arg_1=0, var_229=0, var_229_arg_0=1, var_229_arg_1=0, var_231=0, var_231_arg_0=0, var_231_arg_1=0, var_232=1, var_232_arg_0=1, var_232_arg_1=0, var_233=1, var_233_arg_0=1, var_234=1, var_234_arg_0=1, var_234_arg_1=1, var_234_arg_2=0, var_235=4294966529, var_235_arg_0=0, var_235_arg_1=1, var_236=1, var_236_arg_0=1, var_236_arg_1=4294966529, var_237=264, var_237_arg_0=0, var_237_arg_1=10, var_238=266, var_238_arg_0=2, var_238_arg_1=264, var_239=10, var_239_arg_0=266, var_240=255, var_240_arg_0=1, var_240_arg_1=10, var_240_arg_2=10, var_241=0, var_241_arg_0=0, var_241_arg_1=255, var_242=0, var_242_arg_0=1, var_242_arg_1=0, var_243=0, var_243_arg_0=1, var_243_arg_1=0, var_244=0, var_244_arg_0=1, var_244_arg_1=0, var_245=1, var_245_arg_0=1, var_245_arg_1=0, var_246=0, var_246_arg_0=0, var_246_arg_1=1, var_247=1, var_247_arg_0=0, var_247_arg_1=1, var_249=1, var_249_arg_0=1, var_249_arg_1=0, var_250=0, var_250_arg_0=0, var_250_arg_1=1, var_252=83, var_252_arg_0=0, var_252_arg_1=9, var_253=243, var_253_arg_0=244, var_253_arg_1=1, var_254=243, var_254_arg_0=243, var_255=255, var_255_arg_0=1, var_255_arg_1=243, var_255_arg_2=1, var_256=512, var_256_arg_0=0, var_256_arg_1=255, var_257=1, var_257_arg_0=1, var_257_arg_1=512, var_258=1, var_258_arg_0=83, var_258_arg_1=1, var_259=1, var_259_arg_0=0, var_259_arg_1=1, var_260=0, var_260_arg_0=0, var_260_arg_1=1, var_262=1, var_262_arg_0=1, var_262_arg_1=0, var_263=511, var_263_arg_0=512, var_263_arg_1=1, var_264=255, var_264_arg_0=511, var_265=62, var_265_arg_0=0, var_265_arg_1=255, var_265_arg_2=255, var_266=4294967103, var_266_arg_0=0, var_266_arg_1=62, var_267=1, var_267_arg_0=1, var_267_arg_1=4294967103, var_268=1, var_268_arg_0=1, var_268_arg_1=1, var_269=1, var_269_arg_0=1, var_269_arg_1=1, var_270=0, var_270_arg_0=0, var_270_arg_1=1, var_272=1, var_272_arg_0=1, var_272_arg_1=0, var_273=4294967295, var_273_arg_0=0, var_273_arg_1=1, var_274=255, var_274_arg_0=4294967295, var_275=70, var_275_arg_0=1, var_275_arg_1=255, var_275_arg_2=255, var_276=327, var_276_arg_0=0, var_276_arg_1=70, var_277=1, var_277_arg_0=1, var_277_arg_1=327, var_278=1, var_278_arg_0=1, var_278_arg_1=1, var_279=1, var_279_arg_0=1, var_279_arg_1=1, var_280=0, var_280_arg_0=0, var_280_arg_1=1, var_282=1, var_282_arg_0=1, var_282_arg_1=1, var_283=1, var_283_arg_0=1, var_283_arg_1=1, var_284=1, var_284_arg_0=1, var_284_arg_1=1, var_285=0, var_285_arg_0=0, var_285_arg_1=1, var_287=4294966528, var_287_arg_0=4294966529, var_287_arg_1=1, var_288=0, var_288_arg_0=4294966528, var_289=0, var_289_arg_0=1, var_289_arg_1=0, var_289_arg_2=1, var_290=0, var_290_arg_0=0, var_290_arg_1=0, var_291=0, var_291_arg_0=1, var_291_arg_1=0, var_292=326, var_292_arg_0=327, var_292_arg_1=1, var_293=70, var_293_arg_0=326, var_294=246, var_294_arg_0=1, var_294_arg_1=70, var_294_arg_2=70, var_295=4294966775, var_295_arg_0=0, var_295_arg_1=246, var_296=1, var_296_arg_0=1, var_296_arg_1=4294966775, var_297=0, var_297_arg_0=0, var_297_arg_1=1, var_298=0, var_298_arg_0=1, var_298_arg_1=0, var_299=1, var_299_arg_0=1, var_299_arg_1=0, var_30=0, var_300=0, var_300_arg_0=0, var_300_arg_1=1, var_301=1, var_301_arg_0=1, var_301_arg_1=1, var_303=1, var_303_arg_0=1, var_303_arg_1=0, var_304=0, var_304_arg_0=0, var_304_arg_1=1, var_306=1, var_306_arg_0=1, var_306_arg_1=11, var_307=4294967102, var_307_arg_0=4294967103, var_307_arg_1=1, var_308=62, var_308_arg_0=4294967102, var_309=62, var_309_arg_0=0, var_309_arg_1=62, var_309_arg_2=62, var_310=63, var_310_arg_0=0, var_310_arg_1=62, var_311=1, var_311_arg_0=1, var_311_arg_1=63, var_312=1, var_312_arg_0=1, var_312_arg_1=1, var_313=1, var_313_arg_0=1, var_313_arg_1=1, var_314=0, var_314_arg_0=0, var_314_arg_1=1, var_316=1, var_316_arg_0=0, var_316_arg_1=1, var_317=62, var_317_arg_0=63, var_317_arg_1=1, var_318=62, var_318_arg_0=62, var_319=0, var_319_arg_0=1, var_319_arg_1=62, var_319_arg_2=62, var_320=0, var_320_arg_0=0, var_320_arg_1=0, var_321=0, var_321_arg_0=1, var_321_arg_1=0, var_322=0, var_322_arg_0=1, var_322_arg_1=0, var_323=1, var_323_arg_0=1, var_323_arg_1=0, var_324=0, var_324_arg_0=0, var_324_arg_1=1, var_326=1, var_326_arg_0=1, var_326_arg_1=0, var_327=4294966774, var_327_arg_0=4294966775, var_327_arg_1=1, var_328=246, var_328_arg_0=4294966774, var_329=57, var_329_arg_0=1, var_329_arg_1=246, var_329_arg_2=246, var_330=58, var_330_arg_0=0, var_330_arg_1=57, var_331=1, var_331_arg_0=1, var_331_arg_1=58, var_332=1, var_332_arg_0=1, var_332_arg_1=1, var_333=1, var_333_arg_0=1, var_333_arg_1=1, var_334=0, var_334_arg_0=0, var_334_arg_1=1, var_336=1, var_336_arg_0=1, var_336_arg_1=0, var_337=0, var_337_arg_0=0, var_337_arg_1=1, var_338=0, var_338_arg_0=0, var_338_arg_1=0, var_339=0, var_339_arg_0=0, var_339_arg_1=0, var_341=3, var_341_arg_0=2, var_341_arg_1=1, var_342=3, var_342_arg_0=3, var_343=255, var_343_arg_0=1, var_343_arg_1=3, var_343_arg_2=4, var_344=0, var_344_arg_0=0, var_344_arg_1=255, var_345=0, var_345_arg_0=1, var_345_arg_1=0, var_346=0, var_346_arg_0=1, var_346_arg_1=0, var_347=0, var_347_arg_0=0, var_347_arg_1=0, var_348=0, var_348_arg_0=0, var_348_arg_1=0, var_350=1, var_350_arg_0=1, var_350_arg_1=1, var_351=4294967294, var_351_arg_0=0, var_351_arg_1=2, var_352=254, var_352_arg_0=4294967294, var_353=37, var_353_arg_0=1, var_353_arg_1=254, var_353_arg_2=4, var_354=0, var_354_arg_0=0, var_354_arg_1=37, var_355=1, var_355_arg_0=1, var_355_arg_1=0, var_356=1, var_356_arg_0=1, var_357=1, var_357_arg_0=0, var_357_arg_1=1, var_357_arg_2=37, var_358=4294967041, var_358_arg_0=0, var_358_arg_1=1, var_359=1, var_359_arg_0=2, var_359_arg_1=4294967041, var_360=1, var_360_arg_0=1, var_360_arg_1=1, var_361=1280, var_361_arg_0=0, var_361_arg_1=2, var_362=1282, var_362_arg_0=2, var_362_arg_1=1280, var_363=2, var_363_arg_0=1282, var_364=252, var_364_arg_0=1, var_364_arg_1=2, var_364_arg_2=2, var_365=4294967291, var_365_arg_0=0, var_365_arg_1=252, var_366=4294967292, var_366_arg_0=1, var_366_arg_1=4294967291, var_367=252, var_367_arg_0=4294967292, var_368=60, var_368_arg_0=1, var_368_arg_1=252, var_368_arg_2=252, var_369=315, var_369_arg_0=0, var_369_arg_1=60, var_370=316, var_370_arg_0=1, var_370_arg_1=315, var_371=60, var_371_arg_0=316, var_372=255, var_372_arg_0=0, var_372_arg_1=60, var_372_arg_2=60, var_373=254, var_373_arg_0=0, var_373_arg_1=255, var_374=255, var_374_arg_0=1, var_374_arg_1=254, var_375=255, var_375_arg_0=255, var_376=2, var_376_arg_0=0, var_376_arg_1=255, var_376_arg_2=255, var_377=1, var_377_arg_0=0, var_377_arg_1=2, var_378=2, var_378_arg_0=1, var_378_arg_1=1, var_379=2, var_379_arg_0=2, var_380=5, var_380_arg_0=0, var_380_arg_1=2, var_380_arg_2=2, var_381=4294966020, var_381_arg_0=0, var_381_arg_1=5, var_382=4294966021, var_382_arg_0=1, var_382_arg_1=4294966020, var_383=5, var_383_arg_0=4294966021, var_384=255, var_384_arg_0=1, var_384_arg_1=5, var_384_arg_2=5, var_385=1278, var_385_arg_0=0, var_385_arg_1=255, var_386=1279, var_386_arg_0=1, var_386_arg_1=1278, var_387=255, var_387_arg_0=1279, var_388=255, var_388_arg_0=0, var_388_arg_1=255, var_388_arg_2=255, var_389=254, var_389_arg_0=0, var_389_arg_1=255, var_390=255, var_390_arg_0=1, var_390_arg_1=254, var_391=255, var_391_arg_0=255, var_392=250, var_392_arg_0=0, var_392_arg_1=255, var_392_arg_2=255, var_393=4294967041, var_393_arg_0=0, var_393_arg_1=250, var_394=1, var_394_arg_0=1, var_394_arg_1=4294967041, var_395=16, var_395_arg_0=0, var_395_arg_1=15, var_396=1, var_396_arg_0=1, var_396_arg_1=16, var_397=1, var_397_arg_0=1, var_397_arg_1=1, var_398=4294967048, var_398_arg_0=0, var_398_arg_1=10, var_399=4294967050, var_399_arg_0=2, var_399_arg_1=4294967048, var_400=10, var_400_arg_0=4294967050, var_401=0, var_401_arg_0=1, var_401_arg_1=10, var_401_arg_2=10, var_402=0, var_402_arg_0=0, var_402_arg_1=0, var_403=1, var_403_arg_0=1, var_403_arg_1=0, var_404=1, var_404_arg_0=1, var_405=0, var_405_arg_0=0, var_405_arg_1=1, var_405_arg_2=0, var_406=0, var_406_arg_0=0, var_406_arg_1=0, var_407=1, var_407_arg_0=1, var_407_arg_1=0, var_408=1, var_408_arg_0=1, var_409=1, var_409_arg_0=1, var_409_arg_1=1, var_409_arg_2=0, var_410=1, var_410_arg_0=0, var_410_arg_1=1, var_411=0, var_411_arg_0=2, var_411_arg_1=1, var_412=0, var_412_arg_0=1, var_412_arg_1=0, var_413=0, var_413_arg_0=1, var_413_arg_1=0, var_414=0, var_414_arg_0=0, var_414_arg_1=0, var_415=0, var_415_arg_0=0, var_415_arg_1=0, var_416=1, var_416_arg_0=1, var_416_arg_1=1, var_417=1, var_417_arg_0=1, var_417_arg_1=1, var_418=19, var_418_arg_0=9, var_418_arg_1=1, var_419=53, var_419_arg_0=0, var_419_arg_1=19, var_420=53, var_420_arg_0=0, var_420_arg_1=53, var_421=247, var_421_arg_0=1, var_421_arg_1=53, var_422=253, var_422_arg_0=0, var_422_arg_1=247, var_423=22, var_423_arg_0=1, var_423_arg_1=253, var_424=13, var_424_arg_0=11, var_424_arg_1=22, var_425=7, var_425_arg_0=1, var_425_arg_1=13, var_426=7, var_426_arg_0=0, var_426_arg_1=7, var_427=7, var_427_arg_0=0, var_427_arg_1=7, var_428=17, var_428_arg_0=0, var_428_arg_1=7, var_429=0, var_429_arg_0=0, var_429_arg_1=17, var_430=1, var_430_arg_0=1, var_430_arg_1=0, var_431=0, var_431_arg_0=0, var_431_arg_1=1, var_432=1, var_432_arg_0=1, var_432_arg_1=1, var_433=1, var_433_arg_0=1, var_433_arg_1=1, var_434=1, var_434_arg_0=1, var_434_arg_1=1, var_435=1, var_435_arg_0=1, var_435_arg_1=1, var_436=0, var_436_arg_0=1, var_436_arg_1=0, var_437=1, var_437_arg_0=1, var_437_arg_1=0, var_438=0, var_438_arg_0=0, var_438_arg_1=1, var_439=0, var_439_arg_0=0, var_439_arg_1=0, var_440=1, var_440_arg_0=0, var_440_arg_1=1, var_441=1, var_441_arg_0=1, var_441_arg_1=1, var_442=1, var_442_arg_0=0, var_442_arg_1=1, var_443=1, var_443_arg_0=1, var_443_arg_1=1, var_444=0, var_444_arg_0=0, var_444_arg_1=1, var_445=1, var_445_arg_0=1, var_445_arg_1=0, var_446=1, var_446_arg_0=0, var_446_arg_1=1, var_447=1, var_447_arg_0=1, var_447_arg_1=1, var_448=1, var_448_arg_0=1, var_448_arg_1=1, var_449=1, var_449_arg_0=1, var_449_arg_1=1, var_450=1, var_450_arg_0=1, var_450_arg_1=1, var_451=1, var_451_arg_0=1, var_451_arg_1=1, var_452=1, var_452_arg_0=1, var_452_arg_1=1, var_453=1, var_453_arg_0=1, var_453_arg_1=1, var_454=1, var_454_arg_0=1, var_454_arg_1=1, var_455=0, var_455_arg_0=1, var_455_arg_1=0, var_456=1, var_456_arg_0=1, var_456_arg_1=1, var_457=0, var_457_arg_0=0, var_457_arg_1=1, var_458=1, var_458_arg_0=1, var_458_arg_1=1, var_459=1, var_459_arg_0=1, var_459_arg_1=1, var_460=1, var_460_arg_0=1, var_460_arg_1=1, var_461=1, var_461_arg_0=1, var_461_arg_1=1, var_462=1, var_462_arg_0=1, var_462_arg_1=1, var_463=0, var_463_arg_0=0, var_463_arg_1=1, var_464=1, var_464_arg_0=1, var_464_arg_1=0, var_465=1, var_465_arg_0=0, var_465_arg_1=1, var_466=1, var_466_arg_0=1, var_466_arg_1=1, var_467=1, var_467_arg_0=1, var_467_arg_1=1, var_468=1, var_468_arg_0=1, var_468_arg_1=1, var_469=0, var_469_arg_0=0, var_469_arg_1=1, var_470=1, var_470_arg_0=1, var_470_arg_1=0, var_471=1, var_471_arg_0=0, var_471_arg_1=1, var_472=1, var_472_arg_0=1, var_472_arg_1=1, var_473=1, var_473_arg_0=1, var_473_arg_1=1, var_474=1, var_474_arg_0=1, var_474_arg_1=1, var_475=1, var_475_arg_0=1, var_475_arg_1=1, var_476=1, var_476_arg_0=1, var_476_arg_1=1, var_477=0, var_477_arg_0=0, var_477_arg_1=1, var_478=1, var_478_arg_0=1, var_478_arg_1=1, var_479=0, var_479_arg_0=0, var_479_arg_1=1, var_480=0, var_480_arg_0=0, var_480_arg_1=0, var_481=1, var_481_arg_0=1, var_481_arg_1=1, var_482=1, var_482_arg_0=1, var_482_arg_1=1, var_483=1, var_483_arg_0=1, var_483_arg_1=1, var_484=1, var_484_arg_0=1, var_484_arg_1=1, var_485=0, var_485_arg_0=1, var_485_arg_1=0, var_486=1, var_486_arg_0=1, var_486_arg_1=1, var_487=1, var_487_arg_0=1, var_487_arg_1=0, var_488=0, var_488_arg_0=0, var_488_arg_1=1, var_489=1, var_489_arg_0=83, var_489_arg_1=1, var_490=1, var_490_arg_0=0, var_490_arg_1=1, var_491=1, var_491_arg_0=1, var_491_arg_1=1, var_492=1, var_492_arg_0=0, var_492_arg_1=1, var_493=1, var_493_arg_0=1, var_493_arg_1=1, var_494=1, var_494_arg_0=1, var_494_arg_1=1, var_495=1, var_495_arg_0=1, var_495_arg_1=1, var_496=1, var_496_arg_0=1, var_496_arg_1=1, var_497=1, var_497_arg_0=1, var_497_arg_1=1, var_498=0, var_498_arg_0=0, var_498_arg_1=1, var_499=1, var_499_arg_0=1, var_499_arg_1=0, var_5=0, var_500=1, var_500_arg_0=0, var_500_arg_1=1, var_501=1, var_501_arg_0=1, var_501_arg_1=1, var_502=1, var_502_arg_0=1, var_502_arg_1=1, var_503=1, var_503_arg_0=1, var_503_arg_1=1, var_504=1, var_504_arg_0=1, var_504_arg_1=1, var_505=1, var_505_arg_0=1, var_505_arg_1=1, var_506=1, var_506_arg_0=1, var_506_arg_1=1, var_507=0, var_507_arg_0=1, var_507_arg_1=0, var_508=1, var_508_arg_0=1, var_508_arg_1=1, var_509=0, var_509_arg_0=0, var_509_arg_1=1, var_510=1, var_510_arg_0=1, var_510_arg_1=0, var_511=1, var_511_arg_0=1, var_511_arg_1=1, var_512=1, var_512_arg_0=0, var_512_arg_1=1, var_513=1, var_513_arg_0=1, var_513_arg_1=1, var_514=0, var_514_arg_0=1, var_514_arg_1=0, var_515=0, var_515_arg_0=1, var_515_arg_1=0, var_516=0, var_516_arg_0=0, var_516_arg_1=0, var_517=0, var_517_arg_0=0, var_517_arg_1=0, var_518=0, var_518_arg_0=1, var_518_arg_1=0, var_519=0, var_519_arg_0=0, var_519_arg_1=0, var_520=0, var_520_arg_0=0, var_520_arg_1=0, var_521=0, var_521_arg_0=0, var_521_arg_1=0, var_522=0, var_522_arg_0=1, var_522_arg_1=0, var_523=0, var_523_arg_0=0, var_523_arg_1=0, var_524=0, var_524_arg_0=0, var_524_arg_1=0, var_525=0, var_525_arg_0=0, var_525_arg_1=0, var_526=0, var_526_arg_0=0, var_526_arg_1=0, var_527=0, var_527_arg_0=1, var_527_arg_1=0, var_528=0, var_528_arg_0=0, var_528_arg_1=0, var_529=1, var_529_arg_0=1, var_529_arg_1=0, var_530=0, var_530_arg_0=0, var_530_arg_1=1, var_531=0, var_531_arg_0=0, var_531_arg_1=0, var_532=0, var_532_arg_0=1, var_532_arg_1=0, var_533=1, var_533_arg_0=0, var_533_arg_1=1, var_534=0, var_534_arg_0=0, var_534_arg_1=1, var_535=0, var_535_arg_0=0, var_535_arg_1=0, var_536=1, var_536_arg_0=1, var_536_arg_1=1, var_537=1, var_537_arg_0=0, var_537_arg_1=1, var_538=1, var_538_arg_0=1, var_538_arg_1=1, var_539=1, var_539_arg_0=0, var_539_arg_1=1, var_540=1, var_540_arg_0=1, var_540_arg_1=1, var_541=1, var_541_arg_0=1, var_541_arg_1=1, var_542=1, var_542_arg_0=1, var_542_arg_1=1, var_543=0, var_543_arg_0=0, var_543_arg_1=1, var_544=4294966794, var_544_arg_0=4294966795, var_544_arg_1=1, var_545=10, var_545_arg_0=4294966794, var_546=0, var_546_arg_0=1, var_546_arg_1=10, var_546_arg_2=10, var_547=1, var_547_arg_0=0, var_547_arg_1=0, var_548=0, var_548_arg_0=0, var_548_arg_1=1, var_549=4294967295, var_549_arg_0=0, var_549_arg_1=1, var_550=255, var_550_arg_0=4294967295, var_551=1, var_551_arg_0=0, var_551_arg_1=255, var_551_arg_2=255, var_552=1, var_552_arg_0=0, var_552_arg_1=1, var_553=3, var_553_arg_0=2, var_553_arg_1=1, var_554=3, var_554_arg_0=3, var_555=1, var_555_arg_0=1, var_555_arg_1=3, var_555_arg_2=1, var_556=0, var_556_arg_0=1, var_556_arg_1=0, var_557=0, var_557_arg_0=0, var_557_arg_1=0, var_558=4294967039, var_558_arg_0=4294967041, var_558_arg_1=2, var_559=255, var_559_arg_0=4294967039, var_560=255, var_560_arg_0=1, var_560_arg_1=255, var_560_arg_2=1, var_561=0, var_561_arg_0=255, var_561_arg_1=0, var_562=0, var_562_arg_0=0, var_562_arg_1=0, var_563=4294967295, var_563_arg_0=0, var_563_arg_1=1, var_564=255, var_564_arg_0=4294967295, var_565=0, var_565_arg_0=0, var_565_arg_1=255, var_565_arg_2=0, var_566=0, var_566_arg_0=0, var_566_arg_1=0, var_567=1, var_567_arg_0=1, var_567_arg_1=0, var_568=1, var_568_arg_0=1, var_569=1, var_569_arg_0=1, var_569_arg_1=1, var_569_arg_2=0, var_570=0, var_570_arg_0=1, var_570_arg_1=0, var_571=0, var_571_arg_0=0, var_571_arg_1=0, var_572=4294967040, var_572_arg_0=4294967041, var_572_arg_1=1, var_573=0, var_573_arg_0=4294967040, var_574=0, var_574_arg_0=1, var_574_arg_1=0, var_574_arg_2=250, var_575=1, var_575_arg_0=0, var_575_arg_1=0, var_576=0, var_576_arg_0=0, var_576_arg_1=1, var_577=4294967295, var_577_arg_0=0, var_577_arg_1=1, var_578=255, var_578_arg_0=4294967295, var_579=50, var_579_arg_0=1, var_579_arg_1=255, var_579_arg_2=255, var_580=0, var_580_arg_0=50, var_580_arg_1=0, var_581=0, var_581_arg_0=0, var_581_arg_1=0, var_582=4294967295, var_582_arg_0=0, var_582_arg_1=1, var_583=255, var_583_arg_0=4294967295, var_584=0, var_584_arg_0=1, var_584_arg_1=255, var_584_arg_2=0, var_585=1, var_585_arg_0=0, var_585_arg_1=0, var_586=0, var_586_arg_0=0, var_586_arg_1=1, var_587=15, var_587_arg_0=16, var_587_arg_1=1, var_588=15, var_588_arg_0=15, var_589=0, var_589_arg_0=1, var_589_arg_1=15, var_589_arg_2=15, var_590=1, var_590_arg_0=0, var_590_arg_1=0, var_591=0, var_591_arg_0=0, var_591_arg_1=1, var_592=0, var_592_arg_0=0, var_592_arg_1=0, var_593=1, var_593_arg_0=1, var_593_arg_1=0, var_594=1, var_594_arg_0=1, var_595=1, var_595_arg_0=1, var_595_arg_1=1, var_595_arg_2=0, var_596=1, var_596_arg_0=0, var_596_arg_1=1, var_597=2, var_597_arg_0=1, var_597_arg_1=1, var_598=2, var_598_arg_0=2, var_599=1, var_599_arg_0=0, var_599_arg_1=2, var_599_arg_2=1, var_600=1, var_600_arg_0=0, var_600_arg_1=1, var_601=2, var_601_arg_0=1, var_601_arg_1=1, var_602=2, var_602_arg_0=2, var_603=1, var_603_arg_0=0, var_603_arg_1=2, var_603_arg_2=1, var_604=1, var_604_arg_0=0, var_604_arg_1=1, var_605=2, var_605_arg_0=1, var_605_arg_1=1, var_606=2, var_606_arg_0=2, var_607=1, var_607_arg_0=1, var_607_arg_1=2, var_607_arg_2=1, var_608=1, var_608_arg_0=0, var_608_arg_1=1, var_609=2, var_609_arg_0=1, var_609_arg_1=1, var_610=2, var_610_arg_0=2, var_611=1, var_611_arg_0=0, var_611_arg_1=2, var_611_arg_2=1, var_612=0, var_612_arg_0=1, var_612_arg_1=0, var_613=0, var_613_arg_0=0, var_613_arg_1=0, var_614=4294967295, var_614_arg_0=1, var_614_arg_1=2, var_615=255, var_615_arg_0=4294967295, var_616=253, var_616_arg_0=1, var_616_arg_1=255, var_616_arg_2=1, var_617=0, var_617_arg_0=253, var_617_arg_1=0, var_618=0, var_618_arg_0=0, var_618_arg_1=0, var_619=57, var_619_arg_0=58, var_619_arg_1=1, var_620=57, var_620_arg_0=57, var_621=57, var_621_arg_0=0, var_621_arg_1=57, var_621_arg_2=57, var_622=57, var_622_arg_0=0, var_622_arg_1=57, var_623=58, var_623_arg_0=1, var_623_arg_1=57, var_624=58, var_624_arg_0=58, var_625=0, var_625_arg_0=1, var_625_arg_1=58, var_625_arg_2=57, var_626=1, var_626_arg_0=0, var_626_arg_1=0, var_627=0, var_627_arg_0=0, var_627_arg_1=1, var_628=0, var_628_arg_0=0, var_628_arg_1=0, var_629=1, var_629_arg_0=1, var_629_arg_1=0, var_630=1, var_630_arg_0=1, var_631=0, var_631_arg_0=0, var_631_arg_1=1, var_631_arg_2=0, var_632=1, var_632_arg_0=0, var_632_arg_1=0, var_633=0, var_633_arg_0=0, var_633_arg_1=1, var_634=0, var_634_arg_0=1, var_634_arg_1=0, var_635=0, var_635_arg_0=0, var_635_arg_1=0, var_636=0, var_636_arg_0=1, var_636_arg_1=0, var_637=0, var_637_arg_0=0, var_637_arg_1=0, var_638=0, var_638_arg_0=1, var_638_arg_1=0, var_639=0, var_639_arg_0=0, var_639_arg_1=0, var_640=1, var_640_arg_0=0, var_640_arg_1=0, var_641=0, var_641_arg_0=0, var_641_arg_1=1, var_642=0, var_642_arg_0=1, var_642_arg_1=0, var_643=0, var_643_arg_0=0, var_643_arg_1=0, var_644=0, var_644_arg_0=1, var_644_arg_1=0, var_645=0, var_645_arg_0=0, var_645_arg_1=0, var_646=1, var_646_arg_0=0, var_646_arg_1=0, var_647=0, var_647_arg_0=0, var_647_arg_1=1, var_648=0, var_648_arg_0=1, var_648_arg_1=0, var_649=0, var_649_arg_0=0, var_649_arg_1=0, var_650=0, var_650_arg_0=1, var_650_arg_1=0, var_651=0, var_651_arg_0=0, var_651_arg_1=0, var_652=1, var_652_arg_0=0, var_652_arg_1=0, var_653=0, var_653_arg_0=0, var_653_arg_1=1, var_654=1, var_654_arg_0=0, var_654_arg_1=0, var_655=0, var_655_arg_0=0, var_655_arg_1=1, var_656=1, var_656_arg_0=0, var_656_arg_1=0, var_657=0, var_657_arg_0=0, var_657_arg_1=1, var_658=1, var_658_arg_0=0, var_658_arg_1=0, var_659=0, var_659_arg_0=0, var_659_arg_1=1, var_660=1, var_660_arg_0=0, var_660_arg_1=0, var_661=0, var_661_arg_0=0, var_661_arg_1=1, var_662=0, var_662_arg_0=1, var_662_arg_1=0, var_663=0, var_663_arg_0=0, var_663_arg_1=0, var_664=1, var_664_arg_0=0, var_664_arg_1=0, var_665=0, var_665_arg_0=0, var_665_arg_1=1, var_666=1, var_666_arg_0=0, var_666_arg_1=0, var_667=0, var_667_arg_0=0, var_667_arg_1=1, var_668=0, var_668_arg_0=1, var_668_arg_1=0, var_669=0, var_669_arg_0=0, var_669_arg_1=0, var_670=0, var_670_arg_0=1, var_670_arg_1=0, var_671=0, var_671_arg_0=0, var_671_arg_1=0, var_672=0, var_672_arg_0=1, var_672_arg_1=0, var_673=0, var_673_arg_0=0, var_673_arg_1=0, var_674=0, var_674_arg_0=1, var_674_arg_1=0, var_675=0, var_675_arg_0=0, var_675_arg_1=0, var_676=0, var_676_arg_0=0, var_676_arg_1=0, var_677=50, var_678=1, var_678_arg_0=0, var_678_arg_1=50, var_679=1, var_679_arg_0=0, var_679_arg_1=0, var_679_arg_2=1, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_78=0, var_78_arg_0=0, var_78_arg_1=0, var_79=0, var_79_arg_0=0, var_79_arg_1=1, var_80=0, var_80_arg_0=0, var_80_arg_1=1, var_81=0, var_81_arg_0=0, var_81_arg_1=0, var_82=0, var_82_arg_0=0, var_82_arg_1=1, var_83=0, var_83_arg_0=0, var_83_arg_1=0, var_84=0, var_84_arg_0=0, var_84_arg_1=0, var_85=0, var_85_arg_0=0, var_85_arg_1=1, var_86=0, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_89=0, var_89_arg_0=0, var_89_arg_1=0, var_90=0, var_90_arg_0=0, var_90_arg_1=1, var_91=0, var_91_arg_0=0, var_91_arg_1=0, var_92=0, var_92_arg_0=0, var_92_arg_1=0, var_93=0, var_93_arg_0=0, var_93_arg_1=1, var_94=0, var_94_arg_0=0, var_94_arg_1=0, var_95=0, var_95_arg_0=0, var_95_arg_1=0, var_96=0, var_96_arg_0=0, var_96_arg_1=0, var_97=10, var_98=0, var_98_arg_0=10, var_98_arg_1=0, var_99=0, var_99_arg_0=0, var_99_arg_1=0] [L209] input_129 = __VERIFIER_nondet_uchar() [L210] input_129 = input_129 & mask_SORT_2 [L211] input_131 = __VERIFIER_nondet_uchar() [L212] input_131 = input_131 & mask_SORT_2 [L213] input_133 = __VERIFIER_nondet_uchar() [L214] input_133 = input_133 & mask_SORT_2 [L215] input_135 = __VERIFIER_nondet_uchar() [L216] input_135 = input_135 & mask_SORT_2 [L217] input_137 = __VERIFIER_nondet_uchar() [L218] input_137 = input_137 & mask_SORT_2 [L219] input_139 = __VERIFIER_nondet_uchar() [L220] input_139 = input_139 & mask_SORT_2 [L221] input_141 = __VERIFIER_nondet_uchar() [L222] input_141 = input_141 & mask_SORT_2 [L223] input_143 = __VERIFIER_nondet_uchar() [L224] input_143 = input_143 & mask_SORT_2 [L225] input_145 = __VERIFIER_nondet_uchar() [L226] input_145 = input_145 & mask_SORT_2 [L227] input_147 = __VERIFIER_nondet_uchar() [L228] input_147 = input_147 & mask_SORT_2 [L229] input_149 = __VERIFIER_nondet_uchar() [L230] input_149 = input_149 & mask_SORT_2 [L231] input_151 = __VERIFIER_nondet_uchar() [L232] input_151 = input_151 & mask_SORT_2 [L233] input_153 = __VERIFIER_nondet_uchar() [L234] input_153 = input_153 & mask_SORT_1 [L235] input_155 = __VERIFIER_nondet_uchar() [L236] input_155 = input_155 & mask_SORT_1 [L237] input_157 = __VERIFIER_nondet_uchar() [L238] input_157 = input_157 & mask_SORT_1 [L239] input_159 = __VERIFIER_nondet_uchar() [L240] input_159 = input_159 & mask_SORT_1 [L241] input_161 = __VERIFIER_nondet_uchar() [L242] input_161 = input_161 & mask_SORT_1 [L243] input_163 = __VERIFIER_nondet_uchar() [L244] input_163 = input_163 & mask_SORT_1 [L245] input_165 = __VERIFIER_nondet_uchar() [L246] input_165 = input_165 & mask_SORT_1 [L247] input_167 = __VERIFIER_nondet_uchar() [L248] input_167 = input_167 & mask_SORT_1 [L249] input_169 = __VERIFIER_nondet_uchar() [L250] input_169 = input_169 & mask_SORT_1 [L251] input_171 = __VERIFIER_nondet_uchar() [L252] input_171 = input_171 & mask_SORT_1 [L253] input_173 = __VERIFIER_nondet_uchar() [L254] input_173 = input_173 & mask_SORT_1 [L255] input_175 = __VERIFIER_nondet_uchar() [L256] input_175 = input_175 & mask_SORT_1 [L257] input_177 = __VERIFIER_nondet_uchar() [L258] input_177 = input_177 & mask_SORT_1 [L259] input_179 = __VERIFIER_nondet_uchar() [L260] input_179 = input_179 & mask_SORT_1 [L261] input_181 = __VERIFIER_nondet_uchar() [L262] input_181 = input_181 & mask_SORT_1 [L263] input_183 = __VERIFIER_nondet_uchar() [L264] input_183 = input_183 & mask_SORT_1 [L265] input_185 = __VERIFIER_nondet_uchar() [L266] input_185 = input_185 & mask_SORT_1 [L267] input_187 = __VERIFIER_nondet_uchar() [L268] input_187 = input_187 & mask_SORT_1 [L269] input_189 = __VERIFIER_nondet_uchar() [L270] input_189 = input_189 & mask_SORT_1 [L271] input_191 = __VERIFIER_nondet_uchar() [L272] input_191 = input_191 & mask_SORT_1 [L273] input_193 = __VERIFIER_nondet_uchar() [L274] input_193 = input_193 & mask_SORT_1 [L275] input_197 = __VERIFIER_nondet_uchar() [L276] input_197 = input_197 & mask_SORT_1 [L277] input_214 = __VERIFIER_nondet_uchar() [L278] input_214 = input_214 & mask_SORT_1 [L279] input_230 = __VERIFIER_nondet_uchar() [L280] input_230 = input_230 & mask_SORT_1 [L281] input_248 = __VERIFIER_nondet_uchar() [L282] input_251 = __VERIFIER_nondet_uchar() [L283] input_251 = input_251 & mask_SORT_1 [L284] input_261 = __VERIFIER_nondet_uchar() [L285] input_261 = input_261 & mask_SORT_1 [L286] input_271 = __VERIFIER_nondet_uchar() [L287] input_271 = input_271 & mask_SORT_1 [L288] input_281 = __VERIFIER_nondet_uchar() [L289] input_281 = input_281 & mask_SORT_1 [L290] input_286 = __VERIFIER_nondet_uchar() [L291] input_286 = input_286 & mask_SORT_1 [L292] input_302 = __VERIFIER_nondet_uchar() [L293] input_305 = __VERIFIER_nondet_uchar() [L294] input_305 = input_305 & mask_SORT_1 [L295] input_315 = __VERIFIER_nondet_uchar() [L296] input_315 = input_315 & mask_SORT_1 [L297] input_325 = __VERIFIER_nondet_uchar() [L298] input_325 = input_325 & mask_SORT_1 [L299] input_335 = __VERIFIER_nondet_uchar() [L300] input_335 = input_335 & mask_SORT_1 [L301] input_340 = __VERIFIER_nondet_uchar() [L302] input_340 = input_340 & mask_SORT_1 [L303] input_349 = __VERIFIER_nondet_uchar() [L304] input_349 = input_349 & mask_SORT_1 [L307] SORT_1 var_77_arg_0 = state_31; [L308] SORT_1 var_77_arg_1 = state_33; [L309] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L310] SORT_1 var_78_arg_0 = var_77; [L311] SORT_1 var_78_arg_1 = state_35; [L312] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L313] SORT_1 var_79_arg_0 = var_78; [L314] SORT_1 var_79_arg_1 = ~state_37; [L315] var_79_arg_1 = var_79_arg_1 & mask_SORT_1 [L316] SORT_1 var_79 = var_79_arg_0 & var_79_arg_1; [L317] SORT_1 var_80_arg_0 = var_79; [L318] SORT_1 var_80_arg_1 = ~state_39; [L319] var_80_arg_1 = var_80_arg_1 & mask_SORT_1 [L320] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L321] SORT_1 var_81_arg_0 = var_80; [L322] SORT_1 var_81_arg_1 = ~state_41; [L323] var_81_arg_1 = var_81_arg_1 & mask_SORT_1 [L324] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L325] SORT_1 var_82_arg_0 = var_81; [L326] SORT_1 var_82_arg_1 = ~state_43; [L327] var_82_arg_1 = var_82_arg_1 & mask_SORT_1 [L328] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L329] SORT_1 var_83_arg_0 = var_82; [L330] SORT_1 var_83_arg_1 = ~state_45; [L331] var_83_arg_1 = var_83_arg_1 & mask_SORT_1 [L332] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L333] SORT_1 var_84_arg_0 = var_83; [L334] SORT_1 var_84_arg_1 = ~state_47; [L335] var_84_arg_1 = var_84_arg_1 & mask_SORT_1 [L336] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L337] SORT_1 var_85_arg_0 = var_84; [L338] SORT_1 var_85_arg_1 = ~state_49; [L339] var_85_arg_1 = var_85_arg_1 & mask_SORT_1 [L340] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L341] SORT_1 var_86_arg_0 = var_85; [L342] SORT_1 var_86_arg_1 = state_51; [L343] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L344] SORT_1 var_87_arg_0 = var_86; [L345] SORT_1 var_87_arg_1 = ~state_53; [L346] var_87_arg_1 = var_87_arg_1 & mask_SORT_1 [L347] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L348] SORT_1 var_88_arg_0 = var_87; [L349] SORT_1 var_88_arg_1 = ~state_55; [L350] var_88_arg_1 = var_88_arg_1 & mask_SORT_1 [L351] SORT_1 var_88 = var_88_arg_0 & var_88_arg_1; [L352] SORT_1 var_89_arg_0 = var_88; [L353] SORT_1 var_89_arg_1 = ~state_57; [L354] var_89_arg_1 = var_89_arg_1 & mask_SORT_1 [L355] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L356] SORT_1 var_90_arg_0 = var_89; [L357] SORT_1 var_90_arg_1 = ~state_59; [L358] var_90_arg_1 = var_90_arg_1 & mask_SORT_1 [L359] SORT_1 var_90 = var_90_arg_0 & var_90_arg_1; [L360] SORT_1 var_91_arg_0 = var_90; [L361] SORT_1 var_91_arg_1 = ~state_61; [L362] var_91_arg_1 = var_91_arg_1 & mask_SORT_1 [L363] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L364] SORT_1 var_92_arg_0 = var_91; [L365] SORT_1 var_92_arg_1 = ~state_63; [L366] var_92_arg_1 = var_92_arg_1 & mask_SORT_1 [L367] SORT_1 var_92 = var_92_arg_0 & var_92_arg_1; [L368] SORT_1 var_93_arg_0 = var_92; [L369] SORT_1 var_93_arg_1 = ~state_65; [L370] var_93_arg_1 = var_93_arg_1 & mask_SORT_1 [L371] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L372] SORT_1 var_94_arg_0 = var_93; [L373] SORT_1 var_94_arg_1 = state_67; [L374] SORT_1 var_94 = var_94_arg_0 & var_94_arg_1; [L375] SORT_1 var_95_arg_0 = var_94; [L376] SORT_1 var_95_arg_1 = state_69; [L377] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L378] SORT_1 var_96_arg_0 = var_95; [L379] SORT_1 var_96_arg_1 = state_71; [L380] SORT_1 var_96 = var_96_arg_0 & var_96_arg_1; [L381] SORT_2 var_98_arg_0 = var_97; [L382] SORT_2 var_98_arg_1 = state_6; [L383] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L384] SORT_1 var_99_arg_0 = var_96; [L385] SORT_1 var_99_arg_1 = var_98; [L386] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L387] SORT_2 var_101_arg_0 = var_100; [L388] SORT_2 var_101_arg_1 = state_8; [L389] SORT_1 var_101 = var_101_arg_0 == var_101_arg_1; [L390] SORT_1 var_102_arg_0 = var_99; [L391] SORT_1 var_102_arg_1 = var_101; [L392] SORT_1 var_102 = var_102_arg_0 & var_102_arg_1; [L393] SORT_2 var_103_arg_0 = var_100; [L394] SORT_2 var_103_arg_1 = state_10; [L395] SORT_1 var_103 = var_103_arg_0 == var_103_arg_1; [L396] SORT_1 var_104_arg_0 = var_102; [L397] SORT_1 var_104_arg_1 = var_103; [L398] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L399] SORT_2 var_106_arg_0 = var_105; [L400] SORT_2 var_106_arg_1 = state_12; [L401] SORT_1 var_106 = var_106_arg_0 == var_106_arg_1; [L402] SORT_1 var_107_arg_0 = var_104; [L403] SORT_1 var_107_arg_1 = var_106; [L404] SORT_1 var_107 = var_107_arg_0 & var_107_arg_1; [L405] SORT_2 var_109_arg_0 = var_108; [L406] SORT_2 var_109_arg_1 = state_14; [L407] SORT_1 var_109 = var_109_arg_0 == var_109_arg_1; [L408] SORT_1 var_110_arg_0 = var_107; [L409] SORT_1 var_110_arg_1 = var_109; [L410] SORT_1 var_110 = var_110_arg_0 & var_110_arg_1; [L411] SORT_2 var_112_arg_0 = var_111; [L412] SORT_2 var_112_arg_1 = state_16; [L413] SORT_1 var_112 = var_112_arg_0 == var_112_arg_1; [L414] SORT_1 var_113_arg_0 = var_110; [L415] SORT_1 var_113_arg_1 = var_112; [L416] SORT_1 var_113 = var_113_arg_0 & var_113_arg_1; [L417] SORT_2 var_114_arg_0 = var_111; [L418] SORT_2 var_114_arg_1 = state_18; [L419] SORT_1 var_114 = var_114_arg_0 == var_114_arg_1; [L420] SORT_1 var_115_arg_0 = var_113; [L421] SORT_1 var_115_arg_1 = var_114; [L422] SORT_1 var_115 = var_115_arg_0 & var_115_arg_1; [L423] SORT_2 var_117_arg_0 = var_116; [L424] SORT_2 var_117_arg_1 = state_20; [L425] SORT_1 var_117 = var_117_arg_0 == var_117_arg_1; [L426] SORT_1 var_118_arg_0 = var_115; [L427] SORT_1 var_118_arg_1 = var_117; [L428] SORT_1 var_118 = var_118_arg_0 & var_118_arg_1; [L429] SORT_2 var_119_arg_0 = var_111; [L430] SORT_2 var_119_arg_1 = state_22; [L431] SORT_1 var_119 = var_119_arg_0 == var_119_arg_1; [L432] SORT_1 var_120_arg_0 = var_118; [L433] SORT_1 var_120_arg_1 = var_119; [L434] SORT_1 var_120 = var_120_arg_0 & var_120_arg_1; [L435] SORT_2 var_121_arg_0 = var_97; [L436] SORT_2 var_121_arg_1 = state_24; [L437] SORT_1 var_121 = var_121_arg_0 == var_121_arg_1; [L438] SORT_1 var_122_arg_0 = var_120; [L439] SORT_1 var_122_arg_1 = var_121; [L440] SORT_1 var_122 = var_122_arg_0 & var_122_arg_1; [L441] SORT_2 var_123_arg_0 = var_97; [L442] SORT_2 var_123_arg_1 = state_26; [L443] SORT_1 var_123 = var_123_arg_0 == var_123_arg_1; [L444] SORT_1 var_124_arg_0 = var_122; [L445] SORT_1 var_124_arg_1 = var_123; [L446] SORT_1 var_124 = var_124_arg_0 & var_124_arg_1; [L447] SORT_2 var_125_arg_0 = var_111; [L448] SORT_2 var_125_arg_1 = state_28; [L449] SORT_1 var_125 = var_125_arg_0 == var_125_arg_1; [L450] SORT_1 var_126_arg_0 = var_124; [L451] SORT_1 var_126_arg_1 = var_125; [L452] SORT_1 var_126 = var_126_arg_0 & var_126_arg_1; [L453] SORT_1 var_127_arg_0 = state_75; [L454] SORT_1 var_127_arg_1 = var_126; [L455] SORT_1 var_127 = var_127_arg_0 & var_127_arg_1; [L456] var_127 = var_127 & mask_SORT_1 [L457] SORT_1 bad_128_arg_0 = var_127; [L458] CALL __VERIFIER_assert(!(bad_128_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 749.4s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 7.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 2 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 7.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 7.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 6 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 6 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.2s SsaConstructionTime, 414.3s SatisfiabilityAnalysisTime, 9.2s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 8 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 04:14:18,105 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash b6819c080be0252472ffbb9d2e5ec70fe87807fca1a5e6b3460972b7b91a9ca6 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 04:14:20,590 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 04:14:20,592 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 04:14:20,630 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 04:14:20,630 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 04:14:20,631 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 04:14:20,633 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 04:14:20,635 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 04:14:20,636 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 04:14:20,637 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 04:14:20,638 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 04:14:20,640 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 04:14:20,640 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 04:14:20,641 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 04:14:20,642 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 04:14:20,643 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 04:14:20,644 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 04:14:20,645 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 04:14:20,647 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 04:14:20,649 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 04:14:20,650 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 04:14:20,652 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 04:14:20,653 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 04:14:20,654 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 04:14:20,657 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 04:14:20,658 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 04:14:20,658 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 04:14:20,659 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 04:14:20,660 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 04:14:20,661 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 04:14:20,661 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 04:14:20,662 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 04:14:20,663 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 04:14:20,664 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 04:14:20,665 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 04:14:20,665 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 04:14:20,666 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 04:14:20,666 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 04:14:20,667 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 04:14:20,668 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 04:14:20,668 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 04:14:20,669 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 04:14:20,693 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 04:14:20,693 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 04:14:20,694 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 04:14:20,694 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 04:14:20,695 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 04:14:20,695 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 04:14:20,696 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 04:14:20,696 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 04:14:20,696 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 04:14:20,697 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 04:14:20,697 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 04:14:20,697 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 04:14:20,698 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 04:14:20,698 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 04:14:20,698 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 04:14:20,699 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 04:14:20,699 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 04:14:20,699 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 04:14:20,699 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 04:14:20,700 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 04:14:20,700 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 04:14:20,700 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 04:14:20,700 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 04:14:20,701 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 04:14:20,701 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 04:14:20,701 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 04:14:20,701 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 04:14:20,702 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 04:14:20,702 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 04:14:20,702 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 04:14:20,702 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 04:14:20,703 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 04:14:20,703 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 04:14:20,703 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 04:14:20,703 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 04:14:20,704 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b6819c080be0252472ffbb9d2e5ec70fe87807fca1a5e6b3460972b7b91a9ca6 [2022-11-03 04:14:21,083 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 04:14:21,114 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 04:14:21,117 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 04:14:21,118 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 04:14:21,119 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 04:14:21,121 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:14:21,205 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/a9312acca/53f27df09d8741f39cd0f9f0b93dd24f/FLAGa23985f79 [2022-11-03 04:14:21,978 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 04:14:21,978 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:14:21,993 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/a9312acca/53f27df09d8741f39cd0f9f0b93dd24f/FLAGa23985f79 [2022-11-03 04:14:22,157 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/data/a9312acca/53f27df09d8741f39cd0f9f0b93dd24f [2022-11-03 04:14:22,159 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 04:14:22,160 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 04:14:22,162 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 04:14:22,162 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 04:14:22,170 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 04:14:22,171 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 04:14:22" (1/1) ... [2022-11-03 04:14:22,172 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c3e9730 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:22, skipping insertion in model container [2022-11-03 04:14:22,173 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 04:14:22" (1/1) ... [2022-11-03 04:14:22,180 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 04:14:22,275 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 04:14:22,426 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c[1014,1027] [2022-11-03 04:14:22,882 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 04:14:22,892 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 04:14:22,904 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.krebs.3.prop1-back-serstep.c[1014,1027] [2022-11-03 04:14:23,071 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 04:14:23,083 INFO L208 MainTranslator]: Completed translation [2022-11-03 04:14:23,083 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23 WrapperNode [2022-11-03 04:14:23,083 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 04:14:23,084 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 04:14:23,084 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 04:14:23,085 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 04:14:23,092 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,147 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,265 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2276 [2022-11-03 04:14:23,265 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 04:14:23,266 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 04:14:23,266 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 04:14:23,266 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 04:14:23,280 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,281 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,298 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,304 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,354 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,363 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,371 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,379 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,396 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 04:14:23,396 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 04:14:23,397 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 04:14:23,397 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 04:14:23,398 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (1/1) ... [2022-11-03 04:14:23,404 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 04:14:23,431 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 04:14:23,445 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 04:14:23,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 04:14:23,501 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 04:14:23,501 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 04:14:24,025 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 04:14:24,027 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 04:14:25,769 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 04:14:25,781 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 04:14:25,781 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 04:14:25,784 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 04:14:25 BoogieIcfgContainer [2022-11-03 04:14:25,784 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 04:14:25,789 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 04:14:25,789 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 04:14:25,793 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 04:14:25,793 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 04:14:22" (1/3) ... [2022-11-03 04:14:25,794 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@dcee6cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 04:14:25, skipping insertion in model container [2022-11-03 04:14:25,794 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 04:14:23" (2/3) ... [2022-11-03 04:14:25,794 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@dcee6cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 04:14:25, skipping insertion in model container [2022-11-03 04:14:25,794 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 04:14:25" (3/3) ... [2022-11-03 04:14:25,796 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.krebs.3.prop1-back-serstep.c [2022-11-03 04:14:25,816 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 04:14:25,817 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 04:14:25,898 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 04:14:25,905 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@54339d08, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 04:14:25,906 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 04:14:25,911 INFO L276 IsEmpty]: Start isEmpty. Operand has 103 states, 101 states have (on average 1.495049504950495) internal successors, (151), 102 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:25,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 04:14:25,917 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:25,918 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 04:14:25,919 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:25,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:25,924 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 04:14:25,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:25,939 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1744834825] [2022-11-03 04:14:25,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:25,940 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:25,940 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:25,944 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:25,951 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 04:14:26,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:26,546 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 04:14:26,558 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:26,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:26,659 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:26,660 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:26,660 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1744834825] [2022-11-03 04:14:26,661 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1744834825] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:26,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:26,661 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 04:14:26,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449350148] [2022-11-03 04:14:26,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:26,670 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 04:14:26,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:26,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 04:14:26,707 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 04:14:26,710 INFO L87 Difference]: Start difference. First operand has 103 states, 101 states have (on average 1.495049504950495) internal successors, (151), 102 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:27,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:27,164 INFO L93 Difference]: Finished difference Result 296 states and 444 transitions. [2022-11-03 04:14:27,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 04:14:27,168 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 04:14:27,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:27,177 INFO L225 Difference]: With dead ends: 296 [2022-11-03 04:14:27,178 INFO L226 Difference]: Without dead ends: 195 [2022-11-03 04:14:27,181 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 04:14:27,184 INFO L413 NwaCegarLoop]: 131 mSDtfsCounter, 280 mSDsluCounter, 271 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 280 SdHoareTripleChecker+Valid, 402 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:27,185 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [280 Valid, 402 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 04:14:27,203 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2022-11-03 04:14:27,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 101. [2022-11-03 04:14:27,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 100 states have (on average 1.47) internal successors, (147), 100 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:27,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 147 transitions. [2022-11-03 04:14:27,226 INFO L78 Accepts]: Start accepts. Automaton has 101 states and 147 transitions. Word has length 5 [2022-11-03 04:14:27,226 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:27,226 INFO L495 AbstractCegarLoop]: Abstraction has 101 states and 147 transitions. [2022-11-03 04:14:27,227 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:27,227 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 147 transitions. [2022-11-03 04:14:27,229 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:27,229 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:27,230 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:27,255 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:27,452 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:27,452 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:27,453 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:27,453 INFO L85 PathProgramCache]: Analyzing trace with hash -2093197609, now seen corresponding path program 1 times [2022-11-03 04:14:27,456 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:27,456 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [372894626] [2022-11-03 04:14:27,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:27,457 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:27,457 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:27,458 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:27,497 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 04:14:28,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:28,656 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:28,678 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:28,856 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:28,857 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:28,857 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:28,857 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [372894626] [2022-11-03 04:14:28,857 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [372894626] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:28,858 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:28,858 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 04:14:28,858 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766848641] [2022-11-03 04:14:28,858 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:28,859 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 04:14:28,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:28,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 04:14:28,860 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 04:14:28,861 INFO L87 Difference]: Start difference. First operand 101 states and 147 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:29,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:29,078 INFO L93 Difference]: Finished difference Result 202 states and 296 transitions. [2022-11-03 04:14:29,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:14:29,081 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:29,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:29,082 INFO L225 Difference]: With dead ends: 202 [2022-11-03 04:14:29,082 INFO L226 Difference]: Without dead ends: 105 [2022-11-03 04:14:29,083 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 04:14:29,084 INFO L413 NwaCegarLoop]: 139 mSDtfsCounter, 2 mSDsluCounter, 529 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 18 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:29,085 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 668 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 18 Unchecked, 0.2s Time] [2022-11-03 04:14:29,086 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2022-11-03 04:14:29,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2022-11-03 04:14:29,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 104 states have (on average 1.4615384615384615) internal successors, (152), 104 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:29,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 152 transitions. [2022-11-03 04:14:29,101 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 152 transitions. Word has length 100 [2022-11-03 04:14:29,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:29,102 INFO L495 AbstractCegarLoop]: Abstraction has 105 states and 152 transitions. [2022-11-03 04:14:29,102 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:29,106 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 152 transitions. [2022-11-03 04:14:29,107 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:29,108 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:29,108 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:29,142 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:29,308 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:29,309 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:29,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:29,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1209688619, now seen corresponding path program 1 times [2022-11-03 04:14:29,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:29,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1110587890] [2022-11-03 04:14:29,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:29,312 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:29,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:29,320 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:29,365 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 04:14:30,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:30,505 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:30,518 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:30,791 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:30,791 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:30,792 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:30,792 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1110587890] [2022-11-03 04:14:30,792 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1110587890] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:30,792 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:30,792 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 04:14:30,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518825412] [2022-11-03 04:14:30,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:30,793 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 04:14:30,793 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:30,794 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 04:14:30,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 04:14:30,794 INFO L87 Difference]: Start difference. First operand 105 states and 152 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:30,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:30,928 INFO L93 Difference]: Finished difference Result 236 states and 346 transitions. [2022-11-03 04:14:30,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 04:14:30,931 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:30,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:30,932 INFO L225 Difference]: With dead ends: 236 [2022-11-03 04:14:30,932 INFO L226 Difference]: Without dead ends: 139 [2022-11-03 04:14:30,933 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 04:14:30,934 INFO L413 NwaCegarLoop]: 138 mSDtfsCounter, 40 mSDsluCounter, 664 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 802 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 28 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:30,935 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 802 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 4 Invalid, 0 Unknown, 28 Unchecked, 0.1s Time] [2022-11-03 04:14:30,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-11-03 04:14:30,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2022-11-03 04:14:30,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 139 states, 138 states have (on average 1.463768115942029) internal successors, (202), 138 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:30,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 202 transitions. [2022-11-03 04:14:30,949 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 202 transitions. Word has length 100 [2022-11-03 04:14:30,949 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:30,949 INFO L495 AbstractCegarLoop]: Abstraction has 139 states and 202 transitions. [2022-11-03 04:14:30,949 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:30,950 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 202 transitions. [2022-11-03 04:14:30,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:30,952 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:30,952 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:30,984 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:31,166 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:31,167 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:31,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:31,167 INFO L85 PathProgramCache]: Analyzing trace with hash 1123704019, now seen corresponding path program 1 times [2022-11-03 04:14:31,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:31,169 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1676138875] [2022-11-03 04:14:31,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:31,169 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:31,169 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:31,170 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:31,173 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 04:14:32,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:32,247 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:32,260 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:32,594 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:32,594 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:32,594 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:32,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1676138875] [2022-11-03 04:14:32,594 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1676138875] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:32,595 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:32,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 04:14:32,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112863764] [2022-11-03 04:14:32,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:32,596 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 04:14:32,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:32,596 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 04:14:32,596 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 04:14:32,597 INFO L87 Difference]: Start difference. First operand 139 states and 202 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:32,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:32,741 INFO L93 Difference]: Finished difference Result 250 states and 366 transitions. [2022-11-03 04:14:32,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 04:14:32,742 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:32,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:32,744 INFO L225 Difference]: With dead ends: 250 [2022-11-03 04:14:32,744 INFO L226 Difference]: Without dead ends: 153 [2022-11-03 04:14:32,745 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 04:14:32,746 INFO L413 NwaCegarLoop]: 137 mSDtfsCounter, 76 mSDsluCounter, 476 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 76 SdHoareTripleChecker+Valid, 613 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 25 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:32,746 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [76 Valid, 613 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 25 Unchecked, 0.1s Time] [2022-11-03 04:14:32,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2022-11-03 04:14:32,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 153. [2022-11-03 04:14:32,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 153 states, 152 states have (on average 1.4605263157894737) internal successors, (222), 152 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:32,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 222 transitions. [2022-11-03 04:14:32,764 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 222 transitions. Word has length 100 [2022-11-03 04:14:32,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:32,765 INFO L495 AbstractCegarLoop]: Abstraction has 153 states and 222 transitions. [2022-11-03 04:14:32,765 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:32,765 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 222 transitions. [2022-11-03 04:14:32,767 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:32,767 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:32,767 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:32,802 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:32,968 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:32,969 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:32,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:32,969 INFO L85 PathProgramCache]: Analyzing trace with hash 1476792401, now seen corresponding path program 1 times [2022-11-03 04:14:32,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:32,971 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [640239142] [2022-11-03 04:14:32,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:32,971 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:32,972 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:32,973 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:32,978 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 04:14:34,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:34,095 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:34,106 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:34,529 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:34,529 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:34,530 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:34,530 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [640239142] [2022-11-03 04:14:34,530 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [640239142] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:34,530 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:34,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 04:14:34,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596295975] [2022-11-03 04:14:34,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:34,532 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 04:14:34,532 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:34,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 04:14:34,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 04:14:34,533 INFO L87 Difference]: Start difference. First operand 153 states and 222 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:34,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:34,662 INFO L93 Difference]: Finished difference Result 350 states and 513 transitions. [2022-11-03 04:14:34,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 04:14:34,665 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:34,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:34,667 INFO L225 Difference]: With dead ends: 350 [2022-11-03 04:14:34,667 INFO L226 Difference]: Without dead ends: 253 [2022-11-03 04:14:34,668 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 04:14:34,669 INFO L413 NwaCegarLoop]: 135 mSDtfsCounter, 121 mSDsluCounter, 491 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 121 SdHoareTripleChecker+Valid, 626 SdHoareTripleChecker+Invalid, 36 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 25 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:34,669 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [121 Valid, 626 Invalid, 36 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 25 Unchecked, 0.1s Time] [2022-11-03 04:14:34,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 253 states. [2022-11-03 04:14:34,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 253 to 253. [2022-11-03 04:14:34,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253 states, 252 states have (on average 1.4642857142857142) internal successors, (369), 252 states have internal predecessors, (369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:34,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253 states to 253 states and 369 transitions. [2022-11-03 04:14:34,681 INFO L78 Accepts]: Start accepts. Automaton has 253 states and 369 transitions. Word has length 100 [2022-11-03 04:14:34,681 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:34,681 INFO L495 AbstractCegarLoop]: Abstraction has 253 states and 369 transitions. [2022-11-03 04:14:34,682 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:34,682 INFO L276 IsEmpty]: Start isEmpty. Operand 253 states and 369 transitions. [2022-11-03 04:14:34,684 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:34,684 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:34,684 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:34,714 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:34,906 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:34,906 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:34,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:34,907 INFO L85 PathProgramCache]: Analyzing trace with hash 90589007, now seen corresponding path program 1 times [2022-11-03 04:14:34,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:34,908 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1359025068] [2022-11-03 04:14:34,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:34,908 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:34,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:34,909 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:34,911 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 04:14:35,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:35,982 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:35,993 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:36,371 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:36,372 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:36,372 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:36,372 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1359025068] [2022-11-03 04:14:36,372 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1359025068] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:36,373 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:36,373 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 04:14:36,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180669356] [2022-11-03 04:14:36,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:36,374 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 04:14:36,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:36,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 04:14:36,375 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 04:14:36,375 INFO L87 Difference]: Start difference. First operand 253 states and 369 transitions. Second operand has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:36,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:36,515 INFO L93 Difference]: Finished difference Result 456 states and 668 transitions. [2022-11-03 04:14:36,516 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 04:14:36,516 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:36,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:36,518 INFO L225 Difference]: With dead ends: 456 [2022-11-03 04:14:36,518 INFO L226 Difference]: Without dead ends: 359 [2022-11-03 04:14:36,518 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 04:14:36,519 INFO L413 NwaCegarLoop]: 136 mSDtfsCounter, 94 mSDsluCounter, 572 mSDsCounter, 0 mSdLazyCounter, 12 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 94 SdHoareTripleChecker+Valid, 708 SdHoareTripleChecker+Invalid, 36 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 12 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:36,520 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [94 Valid, 708 Invalid, 36 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 12 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-11-03 04:14:36,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states. [2022-11-03 04:14:36,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 359. [2022-11-03 04:14:36,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 359 states, 358 states have (on average 1.4636871508379887) internal successors, (524), 358 states have internal predecessors, (524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:36,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 524 transitions. [2022-11-03 04:14:36,547 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 524 transitions. Word has length 100 [2022-11-03 04:14:36,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:36,547 INFO L495 AbstractCegarLoop]: Abstraction has 359 states and 524 transitions. [2022-11-03 04:14:36,547 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 14.285714285714286) internal successors, (100), 7 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:36,548 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 524 transitions. [2022-11-03 04:14:36,549 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:36,549 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:36,549 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:36,588 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:36,770 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:36,771 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:36,771 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:36,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1370452685, now seen corresponding path program 1 times [2022-11-03 04:14:36,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:36,773 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1365264809] [2022-11-03 04:14:36,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:36,773 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:36,774 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:36,775 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:36,779 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 04:14:37,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:37,783 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 04:14:37,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:37,974 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:37,974 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 04:14:37,974 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:37,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1365264809] [2022-11-03 04:14:37,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1365264809] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 04:14:37,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 04:14:37,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 04:14:37,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1476853464] [2022-11-03 04:14:37,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:37,976 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 04:14:37,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:37,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 04:14:37,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 04:14:37,977 INFO L87 Difference]: Start difference. First operand 359 states and 524 transitions. Second operand has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:38,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:38,041 INFO L93 Difference]: Finished difference Result 601 states and 881 transitions. [2022-11-03 04:14:38,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 04:14:38,042 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:38,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:38,044 INFO L225 Difference]: With dead ends: 601 [2022-11-03 04:14:38,044 INFO L226 Difference]: Without dead ends: 504 [2022-11-03 04:14:38,044 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 97 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 04:14:38,045 INFO L413 NwaCegarLoop]: 281 mSDtfsCounter, 189 mSDsluCounter, 283 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 189 SdHoareTripleChecker+Valid, 564 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:38,045 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [189 Valid, 564 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 04:14:38,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states. [2022-11-03 04:14:38,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 407. [2022-11-03 04:14:38,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407 states, 406 states have (on average 1.4655172413793103) internal successors, (595), 406 states have internal predecessors, (595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:38,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407 states to 407 states and 595 transitions. [2022-11-03 04:14:38,055 INFO L78 Accepts]: Start accepts. Automaton has 407 states and 595 transitions. Word has length 100 [2022-11-03 04:14:38,055 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:38,056 INFO L495 AbstractCegarLoop]: Abstraction has 407 states and 595 transitions. [2022-11-03 04:14:38,056 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 25.0) internal successors, (100), 4 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:38,056 INFO L276 IsEmpty]: Start isEmpty. Operand 407 states and 595 transitions. [2022-11-03 04:14:38,057 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2022-11-03 04:14:38,057 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:38,057 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:38,091 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:38,274 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:38,275 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:38,275 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:38,275 INFO L85 PathProgramCache]: Analyzing trace with hash 1372299727, now seen corresponding path program 1 times [2022-11-03 04:14:38,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:38,277 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1234739885] [2022-11-03 04:14:38,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:38,277 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:38,277 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:38,279 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:38,283 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 04:14:39,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:39,337 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-03 04:14:39,347 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:40,986 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:40,986 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:42,551 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:42,551 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:42,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1234739885] [2022-11-03 04:14:42,551 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1234739885] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 04:14:42,551 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1123384314] [2022-11-03 04:14:42,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:42,552 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 04:14:42,552 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 04:14:42,555 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 04:14:42,578 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2022-11-03 04:14:44,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:44,371 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 29 conjunts are in the unsatisfiable core [2022-11-03 04:14:44,384 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:45,980 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:45,980 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:47,131 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:47,132 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1123384314] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 04:14:47,132 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [838741505] [2022-11-03 04:14:47,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:47,133 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 04:14:47,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 04:14:47,135 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 04:14:47,149 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-03 04:14:48,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:48,031 INFO L263 TraceCheckSpWp]: Trace formula consists of 2023 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 04:14:48,039 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:49,561 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:49,561 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:50,780 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 04:14:50,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [838741505] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 04:14:50,781 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 04:14:50,781 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 10, 10] total 18 [2022-11-03 04:14:50,781 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1696816611] [2022-11-03 04:14:50,782 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 04:14:50,782 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-03 04:14:50,783 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:50,783 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-03 04:14:50,783 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2022-11-03 04:14:50,784 INFO L87 Difference]: Start difference. First operand 407 states and 595 transitions. Second operand has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:51,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:51,485 INFO L93 Difference]: Finished difference Result 503 states and 736 transitions. [2022-11-03 04:14:51,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-03 04:14:51,490 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 100 [2022-11-03 04:14:51,490 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:51,492 INFO L225 Difference]: With dead ends: 503 [2022-11-03 04:14:51,492 INFO L226 Difference]: Without dead ends: 501 [2022-11-03 04:14:51,493 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 597 GetRequests, 576 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=81, Invalid=339, Unknown=0, NotChecked=0, Total=420 [2022-11-03 04:14:51,494 INFO L413 NwaCegarLoop]: 104 mSDtfsCounter, 996 mSDsluCounter, 1168 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 996 SdHoareTripleChecker+Valid, 1272 SdHoareTripleChecker+Invalid, 494 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 407 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:51,494 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [996 Valid, 1272 Invalid, 494 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 84 Invalid, 0 Unknown, 407 Unchecked, 0.5s Time] [2022-11-03 04:14:51,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501 states. [2022-11-03 04:14:51,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501 to 410. [2022-11-03 04:14:51,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 410 states, 409 states have (on average 1.4621026894865525) internal successors, (598), 409 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:51,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 410 states to 410 states and 598 transitions. [2022-11-03 04:14:51,506 INFO L78 Accepts]: Start accepts. Automaton has 410 states and 598 transitions. Word has length 100 [2022-11-03 04:14:51,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:51,507 INFO L495 AbstractCegarLoop]: Abstraction has 410 states and 598 transitions. [2022-11-03 04:14:51,508 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 11.222222222222221) internal successors, (202), 18 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:51,508 INFO L276 IsEmpty]: Start isEmpty. Operand 410 states and 598 transitions. [2022-11-03 04:14:51,511 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:14:51,511 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:51,511 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:51,550 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:51,755 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Ended with exit code 0 [2022-11-03 04:14:51,946 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:52,134 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 04:14:52,134 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:52,135 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:52,135 INFO L85 PathProgramCache]: Analyzing trace with hash -982244143, now seen corresponding path program 1 times [2022-11-03 04:14:52,137 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:52,137 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1283861098] [2022-11-03 04:14:52,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:52,137 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:52,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:52,138 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:52,139 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 04:14:53,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:53,634 INFO L263 TraceCheckSpWp]: Trace formula consists of 3763 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:53,645 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:53,875 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 93 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 04:14:53,875 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:53,921 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 96 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-03 04:14:53,922 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:53,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1283861098] [2022-11-03 04:14:53,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1283861098] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 04:14:53,922 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 04:14:53,923 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 04:14:53,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [868974454] [2022-11-03 04:14:53,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:53,923 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 04:14:53,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:53,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 04:14:53,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 04:14:53,924 INFO L87 Difference]: Start difference. First operand 410 states and 598 transitions. Second operand has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:54,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:54,220 INFO L93 Difference]: Finished difference Result 1301 states and 1905 transitions. [2022-11-03 04:14:54,225 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:14:54,225 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 04:14:54,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:54,230 INFO L225 Difference]: With dead ends: 1301 [2022-11-03 04:14:54,230 INFO L226 Difference]: Without dead ends: 1204 [2022-11-03 04:14:54,231 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 04:14:54,231 INFO L413 NwaCegarLoop]: 138 mSDtfsCounter, 683 mSDsluCounter, 395 mSDsCounter, 0 mSdLazyCounter, 46 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 683 SdHoareTripleChecker+Valid, 533 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 46 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:54,232 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [683 Valid, 533 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 46 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 04:14:54,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1204 states. [2022-11-03 04:14:54,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1204 to 412. [2022-11-03 04:14:54,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 412 states, 411 states have (on average 1.4598540145985401) internal successors, (600), 411 states have internal predecessors, (600), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:54,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 412 states to 412 states and 600 transitions. [2022-11-03 04:14:54,246 INFO L78 Accepts]: Start accepts. Automaton has 412 states and 600 transitions. Word has length 195 [2022-11-03 04:14:54,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:54,246 INFO L495 AbstractCegarLoop]: Abstraction has 412 states and 600 transitions. [2022-11-03 04:14:54,247 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 38.6) internal successors, (193), 5 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:54,247 INFO L276 IsEmpty]: Start isEmpty. Operand 412 states and 600 transitions. [2022-11-03 04:14:54,249 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:14:54,249 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:54,250 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:54,291 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:54,470 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:54,470 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:54,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:54,471 INFO L85 PathProgramCache]: Analyzing trace with hash -98735153, now seen corresponding path program 1 times [2022-11-03 04:14:54,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:54,474 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [811506854] [2022-11-03 04:14:54,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:54,474 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:54,474 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:54,475 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:54,486 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 04:14:55,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:55,955 INFO L263 TraceCheckSpWp]: Trace formula consists of 3763 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:55,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:56,353 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 61 proven. 37 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 04:14:56,354 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:56,443 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 04:14:56,444 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:56,444 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [811506854] [2022-11-03 04:14:56,444 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [811506854] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 04:14:56,444 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 04:14:56,444 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 04:14:56,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76311006] [2022-11-03 04:14:56,444 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:56,445 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 04:14:56,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:56,445 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 04:14:56,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 04:14:56,446 INFO L87 Difference]: Start difference. First operand 412 states and 600 transitions. Second operand has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:56,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:56,660 INFO L93 Difference]: Finished difference Result 979 states and 1431 transitions. [2022-11-03 04:14:56,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:14:56,661 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 04:14:56,661 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:56,664 INFO L225 Difference]: With dead ends: 979 [2022-11-03 04:14:56,664 INFO L226 Difference]: Without dead ends: 880 [2022-11-03 04:14:56,665 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 04:14:56,665 INFO L413 NwaCegarLoop]: 191 mSDtfsCounter, 599 mSDsluCounter, 404 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 599 SdHoareTripleChecker+Valid, 595 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:56,666 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [599 Valid, 595 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 04:14:56,667 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 880 states. [2022-11-03 04:14:56,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 880 to 436. [2022-11-03 04:14:56,677 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 436 states, 435 states have (on average 1.4597701149425288) internal successors, (635), 435 states have internal predecessors, (635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:56,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 635 transitions. [2022-11-03 04:14:56,679 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 635 transitions. Word has length 195 [2022-11-03 04:14:56,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:56,679 INFO L495 AbstractCegarLoop]: Abstraction has 436 states and 635 transitions. [2022-11-03 04:14:56,680 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:56,680 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 635 transitions. [2022-11-03 04:14:56,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:14:56,682 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:56,682 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:56,722 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:56,898 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:56,898 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:56,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:56,899 INFO L85 PathProgramCache]: Analyzing trace with hash -2060309811, now seen corresponding path program 1 times [2022-11-03 04:14:56,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:56,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [674379053] [2022-11-03 04:14:56,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:56,901 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:56,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:56,902 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:56,903 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 04:14:58,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:14:58,370 INFO L263 TraceCheckSpWp]: Trace formula consists of 3763 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:14:58,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:14:58,856 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 47 proven. 51 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 04:14:58,857 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:14:58,974 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 86 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 04:14:58,975 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:14:58,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [674379053] [2022-11-03 04:14:58,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [674379053] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 04:14:58,975 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 04:14:58,975 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 04:14:58,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1643397939] [2022-11-03 04:14:58,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:14:58,976 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 04:14:58,977 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:14:58,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 04:14:58,978 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 04:14:58,978 INFO L87 Difference]: Start difference. First operand 436 states and 635 transitions. Second operand has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:59,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:14:59,215 INFO L93 Difference]: Finished difference Result 977 states and 1425 transitions. [2022-11-03 04:14:59,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:14:59,219 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 04:14:59,219 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:14:59,222 INFO L225 Difference]: With dead ends: 977 [2022-11-03 04:14:59,222 INFO L226 Difference]: Without dead ends: 854 [2022-11-03 04:14:59,223 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 04:14:59,223 INFO L413 NwaCegarLoop]: 209 mSDtfsCounter, 501 mSDsluCounter, 439 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 501 SdHoareTripleChecker+Valid, 648 SdHoareTripleChecker+Invalid, 39 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:14:59,224 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [501 Valid, 648 Invalid, 39 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 38 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 04:14:59,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 854 states. [2022-11-03 04:14:59,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 854 to 450. [2022-11-03 04:14:59,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 450 states, 449 states have (on average 1.4587973273942094) internal successors, (655), 449 states have internal predecessors, (655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:59,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 655 transitions. [2022-11-03 04:14:59,236 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 655 transitions. Word has length 195 [2022-11-03 04:14:59,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:14:59,236 INFO L495 AbstractCegarLoop]: Abstraction has 450 states and 655 transitions. [2022-11-03 04:14:59,237 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 36.6) internal successors, (183), 5 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:14:59,237 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 655 transitions. [2022-11-03 04:14:59,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:14:59,239 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:14:59,240 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:14:59,291 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 04:14:59,459 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:14:59,459 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:14:59,459 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:14:59,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1707221429, now seen corresponding path program 1 times [2022-11-03 04:14:59,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:14:59,462 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [747268559] [2022-11-03 04:14:59,462 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:14:59,463 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:14:59,463 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:14:59,464 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:14:59,476 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 04:15:00,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:15:00,940 INFO L263 TraceCheckSpWp]: Trace formula consists of 3763 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:15:00,946 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:15:01,404 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 29 proven. 69 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 04:15:01,405 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:15:01,535 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 92 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2022-11-03 04:15:01,535 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:15:01,535 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [747268559] [2022-11-03 04:15:01,535 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [747268559] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 04:15:01,535 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 04:15:01,536 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 04:15:01,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139384525] [2022-11-03 04:15:01,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:15:01,536 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 04:15:01,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:15:01,537 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 04:15:01,537 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 04:15:01,538 INFO L87 Difference]: Start difference. First operand 450 states and 655 transitions. Second operand has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:01,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:15:01,860 INFO L93 Difference]: Finished difference Result 1029 states and 1500 transitions. [2022-11-03 04:15:01,861 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:15:01,861 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 04:15:01,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:15:01,864 INFO L225 Difference]: With dead ends: 1029 [2022-11-03 04:15:01,864 INFO L226 Difference]: Without dead ends: 892 [2022-11-03 04:15:01,865 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 04:15:01,865 INFO L413 NwaCegarLoop]: 233 mSDtfsCounter, 530 mSDsluCounter, 418 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 530 SdHoareTripleChecker+Valid, 651 SdHoareTripleChecker+Invalid, 45 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 04:15:01,866 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [530 Valid, 651 Invalid, 45 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 44 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 04:15:01,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 892 states. [2022-11-03 04:15:01,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 892 to 550. [2022-11-03 04:15:01,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 550 states, 549 states have (on average 1.4608378870673953) internal successors, (802), 549 states have internal predecessors, (802), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:01,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 550 states to 550 states and 802 transitions. [2022-11-03 04:15:01,882 INFO L78 Accepts]: Start accepts. Automaton has 550 states and 802 transitions. Word has length 195 [2022-11-03 04:15:01,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:15:01,883 INFO L495 AbstractCegarLoop]: Abstraction has 550 states and 802 transitions. [2022-11-03 04:15:01,883 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 37.8) internal successors, (189), 5 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:01,883 INFO L276 IsEmpty]: Start isEmpty. Operand 550 states and 802 transitions. [2022-11-03 04:15:01,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:15:01,886 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:15:01,886 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 04:15:01,943 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 04:15:02,110 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:15:02,110 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:15:02,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:15:02,111 INFO L85 PathProgramCache]: Analyzing trace with hash 1201542473, now seen corresponding path program 1 times [2022-11-03 04:15:02,113 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:15:02,113 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [545717932] [2022-11-03 04:15:02,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:15:02,113 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:15:02,113 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:15:02,114 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:15:02,117 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 04:15:03,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 04:15:03,590 INFO L263 TraceCheckSpWp]: Trace formula consists of 3763 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 04:15:03,597 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 04:15:04,110 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 15 proven. 83 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 04:15:04,111 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 04:15:04,214 INFO L134 CoverageAnalysis]: Checked inductivity of 99 backedges. 54 proven. 0 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2022-11-03 04:15:04,214 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 04:15:04,215 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [545717932] [2022-11-03 04:15:04,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [545717932] provided 1 perfect and 1 imperfect interpolant sequences [2022-11-03 04:15:04,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-11-03 04:15:04,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 10 [2022-11-03 04:15:04,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282224968] [2022-11-03 04:15:04,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 04:15:04,216 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 04:15:04,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 04:15:04,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 04:15:04,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-11-03 04:15:04,217 INFO L87 Difference]: Start difference. First operand 550 states and 802 transitions. Second operand has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:04,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 04:15:04,502 INFO L93 Difference]: Finished difference Result 1207 states and 1758 transitions. [2022-11-03 04:15:04,503 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 04:15:04,503 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 195 [2022-11-03 04:15:04,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 04:15:04,506 INFO L225 Difference]: With dead ends: 1207 [2022-11-03 04:15:04,506 INFO L226 Difference]: Without dead ends: 970 [2022-11-03 04:15:04,507 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 392 GetRequests, 382 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2022-11-03 04:15:04,507 INFO L413 NwaCegarLoop]: 259 mSDtfsCounter, 359 mSDsluCounter, 537 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 359 SdHoareTripleChecker+Valid, 796 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 04:15:04,508 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [359 Valid, 796 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 34 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 04:15:04,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 970 states. [2022-11-03 04:15:04,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 970 to 624. [2022-11-03 04:15:04,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 624 states, 623 states have (on average 1.4590690208667736) internal successors, (909), 623 states have internal predecessors, (909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:04,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 624 states to 624 states and 909 transitions. [2022-11-03 04:15:04,529 INFO L78 Accepts]: Start accepts. Automaton has 624 states and 909 transitions. Word has length 195 [2022-11-03 04:15:04,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 04:15:04,530 INFO L495 AbstractCegarLoop]: Abstraction has 624 states and 909 transitions. [2022-11-03 04:15:04,530 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 30.2) internal successors, (151), 5 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 04:15:04,530 INFO L276 IsEmpty]: Start isEmpty. Operand 624 states and 909 transitions. [2022-11-03 04:15:04,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 196 [2022-11-03 04:15:04,533 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 04:15:04,533 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1] [2022-11-03 04:15:04,583 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Forceful destruction successful, exit code 0 [2022-11-03 04:15:04,746 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 04:15:04,746 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 04:15:04,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 04:15:04,747 INFO L85 PathProgramCache]: Analyzing trace with hash -1813561145, now seen corresponding path program 1 times [2022-11-03 04:15:04,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 04:15:04,750 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1195789471] [2022-11-03 04:15:04,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 04:15:04,750 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 04:15:04,750 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 04:15:04,751 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 04:15:04,759 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0d62f084-7fe8-4694-9b1e-23c03aeeb3b0/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Waiting until timeout for monitored process