./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cb318f5c0d13f1d3f3b84629d932eb14f1eec68c2a2b1e175e5d7ad18b1b70bf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:49:36,948 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:49:36,951 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:49:36,986 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:49:36,987 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:49:36,988 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:49:36,990 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:49:36,992 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:49:36,994 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:49:36,995 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:49:36,996 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:49:36,997 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:49:36,998 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:49:36,999 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:49:37,001 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:49:37,002 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:49:37,003 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:49:37,004 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:49:37,007 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:49:37,009 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:49:37,011 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:49:37,013 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:49:37,015 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:49:37,016 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:49:37,020 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:49:37,021 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:49:37,021 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:49:37,022 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:49:37,023 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:49:37,024 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:49:37,025 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:49:37,026 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:49:37,030 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:49:37,032 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:49:37,034 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:49:37,035 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:49:37,037 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:49:37,038 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:49:37,039 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:49:37,040 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:49:37,041 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:49:37,042 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:49:37,091 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:49:37,097 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:49:37,098 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:49:37,098 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:49:37,099 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:49:37,099 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:49:37,100 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:49:37,100 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:49:37,100 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:49:37,101 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:49:37,102 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:49:37,102 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:49:37,102 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:49:37,103 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:49:37,103 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:49:37,103 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:49:37,104 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:49:37,104 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:49:37,105 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:49:37,105 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:49:37,105 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:49:37,106 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:49:37,106 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:49:37,106 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:49:37,106 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:49:37,107 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:49:37,107 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:49:37,107 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:49:37,107 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:49:37,108 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:49:37,108 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:49:37,109 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:49:37,109 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:49:37,109 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:49:37,109 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:49:37,110 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:49:37,110 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:49:37,110 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:49:37,112 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cb318f5c0d13f1d3f3b84629d932eb14f1eec68c2a2b1e175e5d7ad18b1b70bf [2022-11-03 02:49:37,435 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:49:37,469 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:49:37,473 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:49:37,475 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:49:37,476 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:49:37,493 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:49:37,599 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/43a22a52e/eba092342dc14280b7aacee375f8d992/FLAG7de9612c9 [2022-11-03 02:49:38,457 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:49:38,458 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:49:38,478 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/43a22a52e/eba092342dc14280b7aacee375f8d992/FLAG7de9612c9 [2022-11-03 02:49:38,598 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/43a22a52e/eba092342dc14280b7aacee375f8d992 [2022-11-03 02:49:38,603 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:49:38,605 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:49:38,613 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:49:38,613 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:49:38,617 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:49:38,619 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:49:38" (1/1) ... [2022-11-03 02:49:38,622 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3c1b5089 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:38, skipping insertion in model container [2022-11-03 02:49:38,622 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:49:38" (1/1) ... [2022-11-03 02:49:38,632 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:49:38,737 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:49:39,057 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c[1014,1027] [2022-11-03 02:49:39,521 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:49:39,525 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:49:39,544 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c[1014,1027] [2022-11-03 02:49:39,792 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:49:39,808 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:49:39,808 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39 WrapperNode [2022-11-03 02:49:39,809 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:49:39,811 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:49:39,811 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:49:39,811 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:49:39,821 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:39,876 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,172 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1951 [2022-11-03 02:49:40,172 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:49:40,174 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:49:40,174 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:49:40,175 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:49:40,187 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,187 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,218 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,219 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,389 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,405 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,444 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,469 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,551 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:49:40,554 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:49:40,554 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:49:40,554 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:49:40,556 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (1/1) ... [2022-11-03 02:49:40,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:49:40,578 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:49:40,600 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:49:40,620 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:49:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:49:40,651 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:49:41,268 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:49:41,271 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:50:07,061 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:50:16,649 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:50:16,650 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:50:16,652 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:50:16 BoogieIcfgContainer [2022-11-03 02:50:16,653 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:50:16,655 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:50:16,656 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:50:16,659 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:50:16,660 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:49:38" (1/3) ... [2022-11-03 02:50:16,660 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@75046ee9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:50:16, skipping insertion in model container [2022-11-03 02:50:16,660 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:39" (2/3) ... [2022-11-03 02:50:16,661 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@75046ee9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:50:16, skipping insertion in model container [2022-11-03 02:50:16,661 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:50:16" (3/3) ... [2022-11-03 02:50:16,663 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:50:16,681 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:50:16,681 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:50:16,743 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:50:16,751 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@4e8d2c68, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:50:16,751 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:50:16,757 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:16,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:50:16,765 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:16,766 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:50:16,767 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:16,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:16,774 INFO L85 PathProgramCache]: Analyzing trace with hash 10764579, now seen corresponding path program 1 times [2022-11-03 02:50:16,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:50:16,783 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455188784] [2022-11-03 02:50:16,784 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:16,784 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:50:17,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:22,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:22,338 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 02:50:22,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455188784] [2022-11-03 02:50:22,340 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455188784] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:50:22,341 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:50:22,341 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 02:50:22,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [442747973] [2022-11-03 02:50:22,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:50:22,355 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:50:22,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 02:50:22,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:50:22,397 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:50:22,400 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:23,515 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.08s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:50:25,801 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.24s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:50:27,891 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.09s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:50:29,937 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.05s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:50:29,988 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:50:29,989 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 02:50:29,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:50:29,996 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 02:50:29,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:50:30,004 INFO L225 Difference]: With dead ends: 15 [2022-11-03 02:50:30,006 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 02:50:30,008 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:50:30,016 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 5 mSolverCounterSat, 1 mSolverCounterUnsat, 3 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 7.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 5 IncrementalHoareTripleChecker+Invalid, 3 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 7.5s IncrementalHoareTripleChecker+Time [2022-11-03 02:50:30,020 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 5 Invalid, 3 Unknown, 0 Unchecked, 7.5s Time] [2022-11-03 02:50:30,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 02:50:30,080 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 02:50:30,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:30,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 02:50:30,084 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 02:50:30,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:50:30,085 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 02:50:30,085 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:30,085 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 02:50:30,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 02:50:30,086 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:30,086 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 02:50:30,087 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:50:30,087 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:30,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:30,102 INFO L85 PathProgramCache]: Analyzing trace with hash -1417000210, now seen corresponding path program 1 times [2022-11-03 02:50:30,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:50:30,103 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [969978800] [2022-11-03 02:50:30,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:30,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:55:52,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:55:52,029 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:59:42,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:59:42,931 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:59:42,932 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:59:42,933 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:59:42,935 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 02:59:42,938 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 02:59:42,942 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:59:43,068 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:59:43,068 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:59:43,145 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:59:43 BoogieIcfgContainer [2022-11-03 02:59:43,145 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:59:43,147 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:59:43,148 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:59:43,148 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:59:43,149 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:50:16" (3/4) ... [2022-11-03 02:59:43,152 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:59:43,152 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:59:43,153 INFO L158 Benchmark]: Toolchain (without parser) took 604547.58ms. Allocated memory was 123.7MB in the beginning and 3.7GB in the end (delta: 3.6GB). Free memory was 88.2MB in the beginning and 3.2GB in the end (delta: -3.2GB). Peak memory consumption was 401.7MB. Max. memory is 16.1GB. [2022-11-03 02:59:43,158 INFO L158 Benchmark]: CDTParser took 0.41ms. Allocated memory is still 86.0MB. Free memory was 57.6MB in the beginning and 57.6MB in the end (delta: 29.0kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:59:43,159 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1196.60ms. Allocated memory is still 123.7MB. Free memory was 88.2MB in the beginning and 54.0MB in the end (delta: 34.2MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2022-11-03 02:59:43,160 INFO L158 Benchmark]: Boogie Procedure Inliner took 362.02ms. Allocated memory is still 123.7MB. Free memory was 54.0MB in the beginning and 61.6MB in the end (delta: -7.7MB). Peak memory consumption was 26.8MB. Max. memory is 16.1GB. [2022-11-03 02:59:43,160 INFO L158 Benchmark]: Boogie Preprocessor took 379.19ms. Allocated memory was 123.7MB in the beginning and 209.7MB in the end (delta: 86.0MB). Free memory was 61.6MB in the beginning and 148.0MB in the end (delta: -86.4MB). Peak memory consumption was 48.0MB. Max. memory is 16.1GB. [2022-11-03 02:59:43,161 INFO L158 Benchmark]: RCFGBuilder took 36098.81ms. Allocated memory was 209.7MB in the beginning and 1.8GB in the end (delta: 1.6GB). Free memory was 148.0MB in the beginning and 1.1GB in the end (delta: -978.9MB). Peak memory consumption was 652.3MB. Max. memory is 16.1GB. [2022-11-03 02:59:43,164 INFO L158 Benchmark]: TraceAbstraction took 566489.53ms. Allocated memory was 1.8GB in the beginning and 3.7GB in the end (delta: 1.8GB). Free memory was 1.1GB in the beginning and 3.2GB in the end (delta: -2.1GB). Peak memory consumption was 1.8GB. Max. memory is 16.1GB. [2022-11-03 02:59:43,164 INFO L158 Benchmark]: Witness Printer took 4.53ms. Allocated memory is still 3.7GB. Free memory was 3.2GB in the beginning and 3.2GB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:59:43,167 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.41ms. Allocated memory is still 86.0MB. Free memory was 57.6MB in the beginning and 57.6MB in the end (delta: 29.0kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1196.60ms. Allocated memory is still 123.7MB. Free memory was 88.2MB in the beginning and 54.0MB in the end (delta: 34.2MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 362.02ms. Allocated memory is still 123.7MB. Free memory was 54.0MB in the beginning and 61.6MB in the end (delta: -7.7MB). Peak memory consumption was 26.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 379.19ms. Allocated memory was 123.7MB in the beginning and 209.7MB in the end (delta: 86.0MB). Free memory was 61.6MB in the beginning and 148.0MB in the end (delta: -86.4MB). Peak memory consumption was 48.0MB. Max. memory is 16.1GB. * RCFGBuilder took 36098.81ms. Allocated memory was 209.7MB in the beginning and 1.8GB in the end (delta: 1.6GB). Free memory was 148.0MB in the beginning and 1.1GB in the end (delta: -978.9MB). Peak memory consumption was 652.3MB. Max. memory is 16.1GB. * TraceAbstraction took 566489.53ms. Allocated memory was 1.8GB in the beginning and 3.7GB in the end (delta: 1.8GB). Free memory was 1.1GB in the beginning and 3.2GB in the end (delta: -2.1GB). Peak memory consumption was 1.8GB. Max. memory is 16.1GB. * Witness Printer took 4.53ms. Allocated memory is still 3.7GB. Free memory was 3.2GB in the beginning and 3.2GB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 285, overapproximation of bitwiseOr at line 448, overapproximation of bitwiseAnd at line 190. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 8); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (8 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 24); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (24 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_2 var_5 = 0; [L38] const SORT_1 var_30 = 0; [L39] const SORT_2 var_79 = 0; [L40] const SORT_1 var_160 = 1; [L41] const SORT_4 var_166 = 3; [L42] const SORT_3 var_167 = 0; [L43] const SORT_2 var_168 = 1; [L44] const SORT_4 var_197 = 0; [L45] const SORT_4 var_198 = 1; [L46] const SORT_4 var_206 = 2; [L47] const SORT_2 var_213 = 3; [L48] const SORT_2 var_325 = 2; [L50] SORT_2 input_106; [L51] SORT_2 input_108; [L52] SORT_2 input_110; [L53] SORT_2 input_112; [L54] SORT_2 input_114; [L55] SORT_2 input_116; [L56] SORT_2 input_118; [L57] SORT_2 input_120; [L58] SORT_2 input_122; [L59] SORT_2 input_124; [L60] SORT_2 input_126; [L61] SORT_2 input_128; [L62] SORT_1 input_130; [L63] SORT_1 input_132; [L64] SORT_1 input_134; [L65] SORT_1 input_136; [L66] SORT_1 input_138; [L67] SORT_1 input_140; [L68] SORT_1 input_142; [L69] SORT_1 input_144; [L70] SORT_1 input_146; [L71] SORT_1 input_148; [L72] SORT_1 input_150; [L73] SORT_1 input_152; [L74] SORT_1 input_154; [L75] SORT_1 input_156; [L76] SORT_1 input_158; [L77] SORT_1 input_162; [L78] SORT_1 input_164; [L79] SORT_1 input_176; [L80] SORT_1 input_179; [L81] SORT_1 input_196; [L82] SORT_1 input_222; [L83] SORT_1 input_233; [L84] SORT_1 input_236; [L85] SORT_1 input_239; [L86] SORT_1 input_248; [L87] SORT_1 input_251; [L88] SORT_1 input_269; [L89] SORT_1 input_291; [L90] SORT_1 input_302; [L91] SORT_1 input_305; [L92] SORT_1 input_308; [L93] SORT_1 input_317; [L94] SORT_1 input_320; [L95] SORT_1 input_340; [L96] SORT_1 input_362; [L97] SORT_1 input_373; [L99] SORT_2 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L100] SORT_2 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L101] SORT_2 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L102] SORT_2 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L103] SORT_2 state_14 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L104] SORT_2 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L105] SORT_2 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L106] SORT_2 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L107] SORT_2 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L108] SORT_2 state_24 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L109] SORT_2 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L110] SORT_2 state_28 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L111] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L112] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L113] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L114] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L115] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L116] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L117] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L118] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L119] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L120] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L121] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L122] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L123] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L124] SORT_1 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L125] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L126] SORT_1 state_61 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L127] SORT_1 state_63 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L129] SORT_2 init_7_arg_1 = var_5; [L130] state_6 = init_7_arg_1 [L131] SORT_2 init_9_arg_1 = var_5; [L132] state_8 = init_9_arg_1 [L133] SORT_2 init_11_arg_1 = var_5; [L134] state_10 = init_11_arg_1 [L135] SORT_2 init_13_arg_1 = var_5; [L136] state_12 = init_13_arg_1 [L137] SORT_2 init_15_arg_1 = var_5; [L138] state_14 = init_15_arg_1 [L139] SORT_2 init_17_arg_1 = var_5; [L140] state_16 = init_17_arg_1 [L141] SORT_2 init_19_arg_1 = var_5; [L142] state_18 = init_19_arg_1 [L143] SORT_2 init_21_arg_1 = var_5; [L144] state_20 = init_21_arg_1 [L145] SORT_2 init_23_arg_1 = var_5; [L146] state_22 = init_23_arg_1 [L147] SORT_2 init_25_arg_1 = var_5; [L148] state_24 = init_25_arg_1 [L149] SORT_2 init_27_arg_1 = var_5; [L150] state_26 = init_27_arg_1 [L151] SORT_2 init_29_arg_1 = var_5; [L152] state_28 = init_29_arg_1 [L153] SORT_1 init_32_arg_1 = var_30; [L154] state_31 = init_32_arg_1 [L155] SORT_1 init_34_arg_1 = var_30; [L156] state_33 = init_34_arg_1 [L157] SORT_1 init_36_arg_1 = var_30; [L158] state_35 = init_36_arg_1 [L159] SORT_1 init_38_arg_1 = var_30; [L160] state_37 = init_38_arg_1 [L161] SORT_1 init_40_arg_1 = var_30; [L162] state_39 = init_40_arg_1 [L163] SORT_1 init_42_arg_1 = var_30; [L164] state_41 = init_42_arg_1 [L165] SORT_1 init_44_arg_1 = var_30; [L166] state_43 = init_44_arg_1 [L167] SORT_1 init_46_arg_1 = var_30; [L168] state_45 = init_46_arg_1 [L169] SORT_1 init_48_arg_1 = var_30; [L170] state_47 = init_48_arg_1 [L171] SORT_1 init_50_arg_1 = var_30; [L172] state_49 = init_50_arg_1 [L173] SORT_1 init_52_arg_1 = var_30; [L174] state_51 = init_52_arg_1 [L175] SORT_1 init_54_arg_1 = var_30; [L176] state_53 = init_54_arg_1 [L177] SORT_1 init_56_arg_1 = var_30; [L178] state_55 = init_56_arg_1 [L179] SORT_1 init_58_arg_1 = var_30; [L180] state_57 = init_58_arg_1 [L181] SORT_1 init_60_arg_1 = var_30; [L182] state_59 = init_60_arg_1 [L183] SORT_1 init_62_arg_1 = var_30; [L184] state_61 = init_62_arg_1 [L185] SORT_1 init_64_arg_1 = var_30; [L186] state_63 = init_64_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_57=0, state_59=0, state_6=0, state_61=0, state_63=0, state_8=0, var_160=1, var_166=3, var_167=0, var_168=1, var_197=0, var_198=1, var_206=2, var_213=3, var_30=0, var_325=2, var_5=0, var_79=0] [L189] input_106 = __VERIFIER_nondet_uchar() [L190] input_106 = input_106 & mask_SORT_2 [L191] input_108 = __VERIFIER_nondet_uchar() [L192] input_108 = input_108 & mask_SORT_2 [L193] input_110 = __VERIFIER_nondet_uchar() [L194] input_110 = input_110 & mask_SORT_2 [L195] input_112 = __VERIFIER_nondet_uchar() [L196] input_112 = input_112 & mask_SORT_2 [L197] input_114 = __VERIFIER_nondet_uchar() [L198] input_114 = input_114 & mask_SORT_2 [L199] input_116 = __VERIFIER_nondet_uchar() [L200] input_116 = input_116 & mask_SORT_2 [L201] input_118 = __VERIFIER_nondet_uchar() [L202] input_118 = input_118 & mask_SORT_2 [L203] input_120 = __VERIFIER_nondet_uchar() [L204] input_120 = input_120 & mask_SORT_2 [L205] input_122 = __VERIFIER_nondet_uchar() [L206] input_122 = input_122 & mask_SORT_2 [L207] input_124 = __VERIFIER_nondet_uchar() [L208] input_124 = input_124 & mask_SORT_2 [L209] input_126 = __VERIFIER_nondet_uchar() [L210] input_126 = input_126 & mask_SORT_2 [L211] input_128 = __VERIFIER_nondet_uchar() [L212] input_128 = input_128 & mask_SORT_2 [L213] input_130 = __VERIFIER_nondet_uchar() [L214] input_130 = input_130 & mask_SORT_1 [L215] input_132 = __VERIFIER_nondet_uchar() [L216] input_132 = input_132 & mask_SORT_1 [L217] input_134 = __VERIFIER_nondet_uchar() [L218] input_134 = input_134 & mask_SORT_1 [L219] input_136 = __VERIFIER_nondet_uchar() [L220] input_136 = input_136 & mask_SORT_1 [L221] input_138 = __VERIFIER_nondet_uchar() [L222] input_138 = input_138 & mask_SORT_1 [L223] input_140 = __VERIFIER_nondet_uchar() [L224] input_140 = input_140 & mask_SORT_1 [L225] input_142 = __VERIFIER_nondet_uchar() [L226] input_142 = input_142 & mask_SORT_1 [L227] input_144 = __VERIFIER_nondet_uchar() [L228] input_144 = input_144 & mask_SORT_1 [L229] input_146 = __VERIFIER_nondet_uchar() [L230] input_146 = input_146 & mask_SORT_1 [L231] input_148 = __VERIFIER_nondet_uchar() [L232] input_148 = input_148 & mask_SORT_1 [L233] input_150 = __VERIFIER_nondet_uchar() [L234] input_150 = input_150 & mask_SORT_1 [L235] input_152 = __VERIFIER_nondet_uchar() [L236] input_152 = input_152 & mask_SORT_1 [L237] input_154 = __VERIFIER_nondet_uchar() [L238] input_154 = input_154 & mask_SORT_1 [L239] input_156 = __VERIFIER_nondet_uchar() [L240] input_156 = input_156 & mask_SORT_1 [L241] input_158 = __VERIFIER_nondet_uchar() [L242] input_158 = input_158 & mask_SORT_1 [L243] input_162 = __VERIFIER_nondet_uchar() [L244] input_162 = input_162 & mask_SORT_1 [L245] input_164 = __VERIFIER_nondet_uchar() [L246] input_164 = input_164 & mask_SORT_1 [L247] input_176 = __VERIFIER_nondet_uchar() [L248] input_176 = input_176 & mask_SORT_1 [L249] input_179 = __VERIFIER_nondet_uchar() [L250] input_179 = input_179 & mask_SORT_1 [L251] input_196 = __VERIFIER_nondet_uchar() [L252] input_196 = input_196 & mask_SORT_1 [L253] input_222 = __VERIFIER_nondet_uchar() [L254] input_233 = __VERIFIER_nondet_uchar() [L255] input_233 = input_233 & mask_SORT_1 [L256] input_236 = __VERIFIER_nondet_uchar() [L257] input_236 = input_236 & mask_SORT_1 [L258] input_239 = __VERIFIER_nondet_uchar() [L259] input_239 = input_239 & mask_SORT_1 [L260] input_248 = __VERIFIER_nondet_uchar() [L261] input_248 = input_248 & mask_SORT_1 [L262] input_251 = __VERIFIER_nondet_uchar() [L263] input_251 = input_251 & mask_SORT_1 [L264] input_269 = __VERIFIER_nondet_uchar() [L265] input_269 = input_269 & mask_SORT_1 [L266] input_291 = __VERIFIER_nondet_uchar() [L267] input_302 = __VERIFIER_nondet_uchar() [L268] input_302 = input_302 & mask_SORT_1 [L269] input_305 = __VERIFIER_nondet_uchar() [L270] input_305 = input_305 & mask_SORT_1 [L271] input_308 = __VERIFIER_nondet_uchar() [L272] input_308 = input_308 & mask_SORT_1 [L273] input_317 = __VERIFIER_nondet_uchar() [L274] input_317 = input_317 & mask_SORT_1 [L275] input_320 = __VERIFIER_nondet_uchar() [L276] input_320 = input_320 & mask_SORT_1 [L277] input_340 = __VERIFIER_nondet_uchar() [L278] input_340 = input_340 & mask_SORT_1 [L279] input_362 = __VERIFIER_nondet_uchar() [L280] input_373 = __VERIFIER_nondet_uchar() [L281] input_373 = input_373 & mask_SORT_1 [L284] SORT_1 var_65_arg_0 = state_31; [L285] SORT_1 var_65_arg_1 = ~state_33; [L286] var_65_arg_1 = var_65_arg_1 & mask_SORT_1 [L287] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L288] SORT_1 var_66_arg_0 = var_65; [L289] SORT_1 var_66_arg_1 = ~state_35; [L290] var_66_arg_1 = var_66_arg_1 & mask_SORT_1 [L291] SORT_1 var_66 = var_66_arg_0 & var_66_arg_1; [L292] SORT_1 var_67_arg_0 = var_66; [L293] SORT_1 var_67_arg_1 = ~state_37; [L294] var_67_arg_1 = var_67_arg_1 & mask_SORT_1 [L295] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L296] SORT_1 var_68_arg_0 = var_67; [L297] SORT_1 var_68_arg_1 = ~state_39; [L298] var_68_arg_1 = var_68_arg_1 & mask_SORT_1 [L299] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L300] SORT_1 var_69_arg_0 = var_68; [L301] SORT_1 var_69_arg_1 = state_41; [L302] SORT_1 var_69 = var_69_arg_0 & var_69_arg_1; [L303] SORT_1 var_70_arg_0 = var_69; [L304] SORT_1 var_70_arg_1 = ~state_43; [L305] var_70_arg_1 = var_70_arg_1 & mask_SORT_1 [L306] SORT_1 var_70 = var_70_arg_0 & var_70_arg_1; [L307] SORT_1 var_71_arg_0 = var_70; [L308] SORT_1 var_71_arg_1 = ~state_45; [L309] var_71_arg_1 = var_71_arg_1 & mask_SORT_1 [L310] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L311] SORT_1 var_72_arg_0 = var_71; [L312] SORT_1 var_72_arg_1 = ~state_47; [L313] var_72_arg_1 = var_72_arg_1 & mask_SORT_1 [L314] SORT_1 var_72 = var_72_arg_0 & var_72_arg_1; [L315] SORT_1 var_73_arg_0 = var_72; [L316] SORT_1 var_73_arg_1 = ~state_49; [L317] var_73_arg_1 = var_73_arg_1 & mask_SORT_1 [L318] SORT_1 var_73 = var_73_arg_0 & var_73_arg_1; [L319] SORT_1 var_74_arg_0 = var_73; [L320] SORT_1 var_74_arg_1 = state_51; [L321] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L322] SORT_1 var_75_arg_0 = var_74; [L323] SORT_1 var_75_arg_1 = ~state_53; [L324] var_75_arg_1 = var_75_arg_1 & mask_SORT_1 [L325] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L326] SORT_1 var_76_arg_0 = var_75; [L327] SORT_1 var_76_arg_1 = ~state_55; [L328] var_76_arg_1 = var_76_arg_1 & mask_SORT_1 [L329] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L330] SORT_1 var_77_arg_0 = var_76; [L331] SORT_1 var_77_arg_1 = ~state_57; [L332] var_77_arg_1 = var_77_arg_1 & mask_SORT_1 [L333] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L334] SORT_1 var_78_arg_0 = var_77; [L335] SORT_1 var_78_arg_1 = ~state_59; [L336] var_78_arg_1 = var_78_arg_1 & mask_SORT_1 [L337] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L338] SORT_2 var_80_arg_0 = var_79; [L339] SORT_2 var_80_arg_1 = state_6; [L340] SORT_1 var_80 = var_80_arg_0 == var_80_arg_1; [L341] SORT_1 var_81_arg_0 = var_78; [L342] SORT_1 var_81_arg_1 = var_80; [L343] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L344] SORT_2 var_82_arg_0 = var_79; [L345] SORT_2 var_82_arg_1 = state_8; [L346] SORT_1 var_82 = var_82_arg_0 == var_82_arg_1; [L347] SORT_1 var_83_arg_0 = var_81; [L348] SORT_1 var_83_arg_1 = var_82; [L349] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L350] SORT_2 var_84_arg_0 = var_79; [L351] SORT_2 var_84_arg_1 = state_10; [L352] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L353] SORT_1 var_85_arg_0 = var_83; [L354] SORT_1 var_85_arg_1 = var_84; [L355] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L356] SORT_2 var_86_arg_0 = var_79; [L357] SORT_2 var_86_arg_1 = state_12; [L358] SORT_1 var_86 = var_86_arg_0 == var_86_arg_1; [L359] SORT_1 var_87_arg_0 = var_85; [L360] SORT_1 var_87_arg_1 = var_86; [L361] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L362] SORT_2 var_88_arg_0 = var_79; [L363] SORT_2 var_88_arg_1 = state_14; [L364] SORT_1 var_88 = var_88_arg_0 == var_88_arg_1; [L365] SORT_1 var_89_arg_0 = var_87; [L366] SORT_1 var_89_arg_1 = var_88; [L367] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L368] SORT_2 var_90_arg_0 = var_79; [L369] SORT_2 var_90_arg_1 = state_16; [L370] SORT_1 var_90 = var_90_arg_0 == var_90_arg_1; [L371] SORT_1 var_91_arg_0 = var_89; [L372] SORT_1 var_91_arg_1 = var_90; [L373] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L374] SORT_2 var_92_arg_0 = var_79; [L375] SORT_2 var_92_arg_1 = state_18; [L376] SORT_1 var_92 = var_92_arg_0 == var_92_arg_1; [L377] SORT_1 var_93_arg_0 = var_91; [L378] SORT_1 var_93_arg_1 = var_92; [L379] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L380] SORT_2 var_94_arg_0 = var_79; [L381] SORT_2 var_94_arg_1 = state_20; [L382] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L383] SORT_1 var_95_arg_0 = var_93; [L384] SORT_1 var_95_arg_1 = var_94; [L385] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L386] SORT_2 var_96_arg_0 = var_79; [L387] SORT_2 var_96_arg_1 = state_22; [L388] SORT_1 var_96 = var_96_arg_0 == var_96_arg_1; [L389] SORT_1 var_97_arg_0 = var_95; [L390] SORT_1 var_97_arg_1 = var_96; [L391] SORT_1 var_97 = var_97_arg_0 & var_97_arg_1; [L392] SORT_2 var_98_arg_0 = var_79; [L393] SORT_2 var_98_arg_1 = state_24; [L394] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L395] SORT_1 var_99_arg_0 = var_97; [L396] SORT_1 var_99_arg_1 = var_98; [L397] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L398] SORT_2 var_100_arg_0 = var_79; [L399] SORT_2 var_100_arg_1 = state_26; [L400] SORT_1 var_100 = var_100_arg_0 == var_100_arg_1; [L401] SORT_1 var_101_arg_0 = var_99; [L402] SORT_1 var_101_arg_1 = var_100; [L403] SORT_1 var_101 = var_101_arg_0 & var_101_arg_1; [L404] SORT_2 var_102_arg_0 = var_79; [L405] SORT_2 var_102_arg_1 = state_28; [L406] SORT_1 var_102 = var_102_arg_0 == var_102_arg_1; [L407] SORT_1 var_103_arg_0 = var_101; [L408] SORT_1 var_103_arg_1 = var_102; [L409] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L410] SORT_1 var_104_arg_0 = state_63; [L411] SORT_1 var_104_arg_1 = var_103; [L412] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L413] var_104 = var_104 & mask_SORT_1 [L414] SORT_1 bad_105_arg_0 = var_104; [L415] CALL __VERIFIER_assert(!(bad_105_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L415] RET __VERIFIER_assert(!(bad_105_arg_0)) [L417] SORT_2 next_107_arg_1 = input_106; [L418] SORT_2 next_109_arg_1 = input_108; [L419] SORT_2 next_111_arg_1 = input_110; [L420] SORT_2 next_113_arg_1 = input_112; [L421] SORT_2 next_115_arg_1 = input_114; [L422] SORT_2 next_117_arg_1 = input_116; [L423] SORT_2 next_119_arg_1 = input_118; [L424] SORT_2 next_121_arg_1 = input_120; [L425] SORT_2 next_123_arg_1 = input_122; [L426] SORT_2 next_125_arg_1 = input_124; [L427] SORT_2 next_127_arg_1 = input_126; [L428] SORT_2 next_129_arg_1 = input_128; [L429] SORT_1 next_131_arg_1 = input_130; [L430] SORT_1 next_133_arg_1 = input_132; [L431] SORT_1 next_135_arg_1 = input_134; [L432] SORT_1 next_137_arg_1 = input_136; [L433] SORT_1 next_139_arg_1 = input_138; [L434] SORT_1 next_141_arg_1 = input_140; [L435] SORT_1 next_143_arg_1 = input_142; [L436] SORT_1 next_145_arg_1 = input_144; [L437] SORT_1 next_147_arg_1 = input_146; [L438] SORT_1 next_149_arg_1 = input_148; [L439] SORT_1 next_151_arg_1 = input_150; [L440] SORT_1 next_153_arg_1 = input_152; [L441] SORT_1 next_155_arg_1 = input_154; [L442] SORT_1 next_157_arg_1 = input_156; [L443] SORT_1 next_159_arg_1 = input_158; [L444] SORT_1 next_161_arg_1 = var_160; [L445] SORT_1 var_163_arg_0 = input_130; [L446] SORT_1 var_163_arg_1 = ~input_162; [L447] var_163_arg_1 = var_163_arg_1 & mask_SORT_1 [L448] SORT_1 var_163 = var_163_arg_0 | var_163_arg_1; [L449] SORT_1 var_165_arg_0 = input_134; [L450] SORT_1 var_165_arg_1 = input_162; [L451] SORT_1 var_165 = var_165_arg_0 | var_165_arg_1; [L452] SORT_1 var_169_arg_0 = input_162; [L453] SORT_2 var_169_arg_1 = var_168; [L454] SORT_2 var_169_arg_2 = input_118; [L455] EXPR var_169_arg_0 ? var_169_arg_1 : var_169_arg_2 [L455] SORT_2 var_169 = var_169_arg_0 ? var_169_arg_1 : var_169_arg_2; [L456] var_169 = var_169 & mask_SORT_2 [L457] SORT_3 var_170_arg_0 = var_167; [L458] SORT_2 var_170_arg_1 = var_169; [L459] SORT_4 var_170 = ((SORT_4)var_170_arg_0 << 8) | var_170_arg_1; [L460] var_170 = var_170 & mask_SORT_4 [L461] SORT_4 var_171_arg_0 = var_166; [L462] SORT_4 var_171_arg_1 = var_170; [L463] SORT_1 var_171 = var_171_arg_0 <= var_171_arg_1; [L464] SORT_1 var_172_arg_0 = var_165; [L465] SORT_1 var_172_arg_1 = ~var_171; [L466] var_172_arg_1 = var_172_arg_1 & mask_SORT_1 [L467] SORT_1 var_172 = var_172_arg_0 & var_172_arg_1; [L468] SORT_1 var_173_arg_0 = ~input_164; [L469] var_173_arg_0 = var_173_arg_0 & mask_SORT_1 [L470] SORT_1 var_173_arg_1 = var_172; [L471] SORT_1 var_173 = var_173_arg_0 | var_173_arg_1; [L472] SORT_1 var_174_arg_0 = var_163; [L473] SORT_1 var_174_arg_1 = var_173; [L474] SORT_1 var_174 = var_174_arg_0 & var_174_arg_1; [L475] SORT_1 var_175_arg_0 = input_136; [L476] SORT_1 var_175_arg_1 = input_164; [L477] SORT_1 var_175 = var_175_arg_0 | var_175_arg_1; [L478] SORT_1 var_177_arg_0 = var_175; [L479] SORT_1 var_177_arg_1 = ~input_176; [L480] var_177_arg_1 = var_177_arg_1 & mask_SORT_1 [L481] SORT_1 var_177 = var_177_arg_0 | var_177_arg_1; [L482] SORT_1 var_178_arg_0 = var_174; [L483] SORT_1 var_178_arg_1 = var_177; [L484] SORT_1 var_178 = var_178_arg_0 & var_178_arg_1; [L485] SORT_1 var_180_arg_0 = input_138; [L486] SORT_1 var_180_arg_1 = input_176; [L487] SORT_1 var_180 = var_180_arg_0 | var_180_arg_1; [L488] SORT_1 var_181_arg_0 = input_176; [L489] SORT_2 var_181_arg_1 = var_79; [L490] SORT_2 var_181_arg_2 = input_120; [L491] EXPR var_181_arg_0 ? var_181_arg_1 : var_181_arg_2 [L491] SORT_2 var_181 = var_181_arg_0 ? var_181_arg_1 : var_181_arg_2; [L492] var_181 = var_181 & mask_SORT_2 [L493] SORT_3 var_182_arg_0 = var_167; [L494] SORT_2 var_182_arg_1 = var_181; [L495] SORT_4 var_182 = ((SORT_4)var_182_arg_0 << 8) | var_182_arg_1; [L496] var_182 = var_182 & mask_SORT_4 [L497] SORT_4 var_183_arg_0 = var_166; [L498] SORT_4 var_183_arg_1 = var_182; [L499] SORT_1 var_183 = var_183_arg_0 <= var_183_arg_1; [L500] SORT_2 var_184_arg_0 = var_79; [L501] SORT_2 var_184_arg_1 = var_181; [L502] SORT_1 var_184 = var_184_arg_0 == var_184_arg_1; [L503] SORT_1 var_185_arg_0 = input_164; [L504] SORT_2 var_185_arg_1 = var_169; [L505] SORT_2 var_185_arg_2 = input_106; [L506] EXPR var_185_arg_0 ? var_185_arg_1 : var_185_arg_2 [L506] SORT_2 var_185 = var_185_arg_0 ? var_185_arg_1 : var_185_arg_2; [L507] SORT_2 var_186_arg_0 = var_168; [L508] SORT_2 var_186_arg_1 = var_181; [L509] SORT_1 var_186 = var_186_arg_0 == var_186_arg_1; [L510] SORT_1 var_187_arg_0 = var_186; [L511] SORT_2 var_187_arg_1 = input_108; [L512] SORT_2 var_187_arg_2 = input_110; [L513] EXPR var_187_arg_0 ? var_187_arg_1 : var_187_arg_2 [L513] SORT_2 var_187 = var_187_arg_0 ? var_187_arg_1 : var_187_arg_2; [L514] SORT_1 var_188_arg_0 = var_184; [L515] SORT_2 var_188_arg_1 = var_185; [L516] SORT_2 var_188_arg_2 = var_187; [L517] EXPR var_188_arg_0 ? var_188_arg_1 : var_188_arg_2 [L517] SORT_2 var_188 = var_188_arg_0 ? var_188_arg_1 : var_188_arg_2; [L518] var_188 = var_188 & mask_SORT_2 [L519] SORT_3 var_189_arg_0 = var_167; [L520] SORT_2 var_189_arg_1 = var_188; [L521] SORT_4 var_189 = ((SORT_4)var_189_arg_0 << 8) | var_189_arg_1; [L522] var_189 = var_189 & mask_SORT_4 [L523] SORT_4 var_190_arg_0 = var_170; [L524] SORT_4 var_190_arg_1 = var_189; [L525] SORT_1 var_190 = var_190_arg_0 <= var_190_arg_1; [L526] SORT_1 var_191_arg_0 = var_184; [L527] SORT_1 var_191_arg_1 = ~var_190; [L528] var_191_arg_1 = var_191_arg_1 & mask_SORT_1 [L529] SORT_1 var_191 = var_191_arg_0 | var_191_arg_1; [L530] SORT_1 var_192_arg_0 = ~var_183; [L531] var_192_arg_0 = var_192_arg_0 & mask_SORT_1 [L532] SORT_1 var_192_arg_1 = var_191; [L533] SORT_1 var_192 = var_192_arg_0 & var_192_arg_1; [L534] SORT_1 var_193_arg_0 = var_180; [L535] SORT_1 var_193_arg_1 = var_192; [L536] SORT_1 var_193 = var_193_arg_0 & var_193_arg_1; [L537] SORT_1 var_194_arg_0 = ~input_179; [L538] var_194_arg_0 = var_194_arg_0 & mask_SORT_1 [L539] SORT_1 var_194_arg_1 = var_193; [L540] SORT_1 var_194 = var_194_arg_0 | var_194_arg_1; [L541] SORT_1 var_195_arg_0 = var_178; [L542] SORT_1 var_195_arg_1 = var_194; [L543] SORT_1 var_195 = var_195_arg_0 & var_195_arg_1; [L544] SORT_4 var_199_arg_0 = var_170; [L545] SORT_4 var_199_arg_1 = var_198; [L546] SORT_4 var_199 = var_199_arg_0 - var_199_arg_1; [L547] var_199 = var_199 & mask_SORT_4 [L548] SORT_4 var_200_arg_0 = var_197; [L549] SORT_4 var_200_arg_1 = var_199; [L550] SORT_1 var_200 = var_200_arg_0 == var_200_arg_1; [L551] SORT_1 var_201_arg_0 = input_176; [L552] SORT_1 var_201_arg_1 = var_200; [L553] SORT_1 var_201 = var_201_arg_0 & var_201_arg_1; [L554] var_201 = var_201 & mask_SORT_1 [L555] SORT_1 var_202_arg_0 = var_201; [L556] SORT_2 var_202_arg_1 = var_79; [L557] SORT_2 var_202_arg_2 = input_112; [L558] EXPR var_202_arg_0 ? var_202_arg_1 : var_202_arg_2 [L558] SORT_2 var_202 = var_202_arg_0 ? var_202_arg_1 : var_202_arg_2; [L559] SORT_4 var_203_arg_0 = var_198; [L560] SORT_4 var_203_arg_1 = var_199; [L561] SORT_1 var_203 = var_203_arg_0 == var_203_arg_1; [L562] SORT_1 var_204_arg_0 = input_176; [L563] SORT_1 var_204_arg_1 = var_203; [L564] SORT_1 var_204 = var_204_arg_0 & var_204_arg_1; [L565] var_204 = var_204 & mask_SORT_1 [L566] SORT_1 var_205_arg_0 = var_204; [L567] SORT_2 var_205_arg_1 = var_79; [L568] SORT_2 var_205_arg_2 = input_114; [L569] EXPR var_205_arg_0 ? var_205_arg_1 : var_205_arg_2 [L569] SORT_2 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L570] SORT_4 var_207_arg_0 = var_206; [L571] SORT_4 var_207_arg_1 = var_199; [L572] SORT_1 var_207 = var_207_arg_0 == var_207_arg_1; [L573] SORT_1 var_208_arg_0 = input_176; [L574] SORT_1 var_208_arg_1 = var_207; [L575] SORT_1 var_208 = var_208_arg_0 & var_208_arg_1; [L576] var_208 = var_208 & mask_SORT_1 [L577] SORT_1 var_209_arg_0 = var_208; [L578] SORT_2 var_209_arg_1 = var_79; [L579] SORT_2 var_209_arg_2 = input_116; [L580] EXPR var_209_arg_0 ? var_209_arg_1 : var_209_arg_2 [L580] SORT_2 var_209 = var_209_arg_0 ? var_209_arg_1 : var_209_arg_2; [L581] SORT_1 var_210_arg_0 = var_203; [L582] SORT_2 var_210_arg_1 = var_205; [L583] SORT_2 var_210_arg_2 = var_209; [L584] EXPR var_210_arg_0 ? var_210_arg_1 : var_210_arg_2 [L584] SORT_2 var_210 = var_210_arg_0 ? var_210_arg_1 : var_210_arg_2; [L585] SORT_1 var_211_arg_0 = var_200; [L586] SORT_2 var_211_arg_1 = var_202; [L587] SORT_2 var_211_arg_2 = var_210; [L588] EXPR var_211_arg_0 ? var_211_arg_1 : var_211_arg_2 [L588] SORT_2 var_211 = var_211_arg_0 ? var_211_arg_1 : var_211_arg_2; [L589] var_211 = var_211 & mask_SORT_2 [L590] SORT_2 var_212_arg_0 = var_79; [L591] SORT_2 var_212_arg_1 = var_211; [L592] SORT_1 var_212 = var_212_arg_0 == var_212_arg_1; [L593] SORT_4 var_214_arg_0 = var_198; [L594] SORT_4 var_214_arg_1 = var_182; [L595] SORT_4 var_214 = var_214_arg_0 + var_214_arg_1; [L596] SORT_4 var_215_arg_0 = var_214; [L597] SORT_2 var_215 = var_215_arg_0 >> 0; [L598] SORT_1 var_216_arg_0 = input_179; [L599] SORT_2 var_216_arg_1 = var_215; [L600] SORT_2 var_216_arg_2 = var_181; [L601] EXPR var_216_arg_0 ? var_216_arg_1 : var_216_arg_2 [L601] SORT_2 var_216 = var_216_arg_0 ? var_216_arg_1 : var_216_arg_2; [L602] var_216 = var_216 & mask_SORT_2 [L603] SORT_2 var_217_arg_0 = var_213; [L604] SORT_2 var_217_arg_1 = var_216; [L605] SORT_1 var_217 = var_217_arg_0 == var_217_arg_1; [L606] SORT_1 var_218_arg_0 = ~var_212; [L607] var_218_arg_0 = var_218_arg_0 & mask_SORT_1 [L608] SORT_1 var_218_arg_1 = var_217; [L609] SORT_1 var_218 = var_218_arg_0 | var_218_arg_1; [L610] SORT_1 var_219_arg_0 = var_180; [L611] SORT_1 var_219_arg_1 = var_218; [L612] SORT_1 var_219 = var_219_arg_0 & var_219_arg_1; [L613] SORT_1 var_220_arg_0 = ~input_196; [L614] var_220_arg_0 = var_220_arg_0 & mask_SORT_1 [L615] SORT_1 var_220_arg_1 = var_219; [L616] SORT_1 var_220 = var_220_arg_0 | var_220_arg_1; [L617] SORT_1 var_221_arg_0 = var_195; [L618] SORT_1 var_221_arg_1 = var_220; [L619] SORT_1 var_221 = var_221_arg_0 & var_221_arg_1; [L620] SORT_1 var_223_arg_0 = var_165; [L621] SORT_1 var_223_arg_1 = ~input_164; [L622] var_223_arg_1 = var_223_arg_1 & mask_SORT_1 [L623] SORT_1 var_223 = var_223_arg_0 & var_223_arg_1; [L624] SORT_1 var_224_arg_0 = var_223; [L625] SORT_1 var_224_arg_1 = input_196; [L626] SORT_1 var_224 = var_224_arg_0 | var_224_arg_1; [L627] SORT_4 var_225_arg_0 = var_198; [L628] SORT_4 var_225_arg_1 = var_170; [L629] SORT_4 var_225 = var_225_arg_0 + var_225_arg_1; [L630] SORT_4 var_226_arg_0 = var_225; [L631] SORT_2 var_226 = var_226_arg_0 >> 0; [L632] SORT_1 var_227_arg_0 = input_196; [L633] SORT_2 var_227_arg_1 = var_226; [L634] SORT_2 var_227_arg_2 = var_169; [L635] EXPR var_227_arg_0 ? var_227_arg_1 : var_227_arg_2 [L635] SORT_2 var_227 = var_227_arg_0 ? var_227_arg_1 : var_227_arg_2; [L636] var_227 = var_227 & mask_SORT_2 [L637] SORT_2 var_228_arg_0 = var_213; [L638] SORT_2 var_228_arg_1 = var_227; [L639] SORT_1 var_228 = var_228_arg_0 == var_228_arg_1; [L640] SORT_1 var_229_arg_0 = var_224; [L641] SORT_1 var_229_arg_1 = var_228; [L642] SORT_1 var_229 = var_229_arg_0 & var_229_arg_1; [L643] SORT_1 var_230_arg_0 = ~input_222; [L644] var_230_arg_0 = var_230_arg_0 & mask_SORT_1 [L645] SORT_1 var_230_arg_1 = var_229; [L646] SORT_1 var_230 = var_230_arg_0 | var_230_arg_1; [L647] SORT_1 var_231_arg_0 = var_221; [L648] SORT_1 var_231_arg_1 = var_230; [L649] SORT_1 var_231 = var_231_arg_0 & var_231_arg_1; [L650] SORT_1 var_232_arg_0 = input_132; [L651] SORT_1 var_232_arg_1 = input_222; [L652] SORT_1 var_232 = var_232_arg_0 | var_232_arg_1; [L653] SORT_1 var_234_arg_0 = var_232; [L654] SORT_1 var_234_arg_1 = ~input_233; [L655] var_234_arg_1 = var_234_arg_1 & mask_SORT_1 [L656] SORT_1 var_234 = var_234_arg_0 | var_234_arg_1; [L657] SORT_1 var_235_arg_0 = var_231; [L658] SORT_1 var_235_arg_1 = var_234; [L659] SORT_1 var_235 = var_235_arg_0 & var_235_arg_1; [L660] SORT_1 var_237_arg_0 = input_140; [L661] SORT_1 var_237_arg_1 = ~input_236; [L662] var_237_arg_1 = var_237_arg_1 & mask_SORT_1 [L663] SORT_1 var_237 = var_237_arg_0 | var_237_arg_1; [L664] SORT_1 var_238_arg_0 = var_235; [L665] SORT_1 var_238_arg_1 = var_237; [L666] SORT_1 var_238 = var_238_arg_0 & var_238_arg_1; [L667] SORT_1 var_240_arg_0 = input_144; [L668] SORT_1 var_240_arg_1 = input_236; [L669] SORT_1 var_240 = var_240_arg_0 | var_240_arg_1; [L670] SORT_1 var_241_arg_0 = input_236; [L671] SORT_2 var_241_arg_1 = var_168; [L672] SORT_2 var_241_arg_2 = input_122; [L673] EXPR var_241_arg_0 ? var_241_arg_1 : var_241_arg_2 [L673] SORT_2 var_241 = var_241_arg_0 ? var_241_arg_1 : var_241_arg_2; [L674] var_241 = var_241 & mask_SORT_2 [L675] SORT_3 var_242_arg_0 = var_167; [L676] SORT_2 var_242_arg_1 = var_241; [L677] SORT_4 var_242 = ((SORT_4)var_242_arg_0 << 8) | var_242_arg_1; [L678] var_242 = var_242 & mask_SORT_4 [L679] SORT_4 var_243_arg_0 = var_166; [L680] SORT_4 var_243_arg_1 = var_242; [L681] SORT_1 var_243 = var_243_arg_0 <= var_243_arg_1; [L682] SORT_1 var_244_arg_0 = var_240; [L683] SORT_1 var_244_arg_1 = ~var_243; [L684] var_244_arg_1 = var_244_arg_1 & mask_SORT_1 [L685] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L686] SORT_1 var_245_arg_0 = ~input_239; [L687] var_245_arg_0 = var_245_arg_0 & mask_SORT_1 [L688] SORT_1 var_245_arg_1 = var_244; [L689] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L690] SORT_1 var_246_arg_0 = var_238; [L691] SORT_1 var_246_arg_1 = var_245; [L692] SORT_1 var_246 = var_246_arg_0 & var_246_arg_1; [L693] SORT_1 var_247_arg_0 = input_146; [L694] SORT_1 var_247_arg_1 = input_239; [L695] SORT_1 var_247 = var_247_arg_0 | var_247_arg_1; [L696] SORT_1 var_249_arg_0 = var_247; [L697] SORT_1 var_249_arg_1 = ~input_248; [L698] var_249_arg_1 = var_249_arg_1 & mask_SORT_1 [L699] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L700] SORT_1 var_250_arg_0 = var_246; [L701] SORT_1 var_250_arg_1 = var_249; [L702] SORT_1 var_250 = var_250_arg_0 & var_250_arg_1; [L703] SORT_1 var_252_arg_0 = input_148; [L704] SORT_1 var_252_arg_1 = input_248; [L705] SORT_1 var_252 = var_252_arg_0 | var_252_arg_1; [L706] SORT_1 var_253_arg_0 = input_248; [L707] SORT_2 var_253_arg_1 = var_79; [L708] SORT_2 var_253_arg_2 = input_124; [L709] EXPR var_253_arg_0 ? var_253_arg_1 : var_253_arg_2 [L709] SORT_2 var_253 = var_253_arg_0 ? var_253_arg_1 : var_253_arg_2; [L710] var_253 = var_253 & mask_SORT_2 [L711] SORT_3 var_254_arg_0 = var_167; [L712] SORT_2 var_254_arg_1 = var_253; [L713] SORT_4 var_254 = ((SORT_4)var_254_arg_0 << 8) | var_254_arg_1; [L714] var_254 = var_254 & mask_SORT_4 [L715] SORT_4 var_255_arg_0 = var_166; [L716] SORT_4 var_255_arg_1 = var_254; [L717] SORT_1 var_255 = var_255_arg_0 <= var_255_arg_1; [L718] SORT_2 var_256_arg_0 = var_168; [L719] SORT_2 var_256_arg_1 = var_253; [L720] SORT_1 var_256 = var_256_arg_0 == var_256_arg_1; [L721] SORT_2 var_257_arg_0 = var_79; [L722] SORT_2 var_257_arg_1 = var_253; [L723] SORT_1 var_257 = var_257_arg_0 == var_257_arg_1; [L724] SORT_1 var_258_arg_0 = input_233; [L725] SORT_2 var_258_arg_1 = var_79; [L726] SORT_2 var_258_arg_2 = var_185; [L727] EXPR var_258_arg_0 ? var_258_arg_1 : var_258_arg_2 [L727] SORT_2 var_258 = var_258_arg_0 ? var_258_arg_1 : var_258_arg_2; [L728] var_258 = var_258 & mask_SORT_2 [L729] SORT_1 var_259_arg_0 = input_239; [L730] SORT_2 var_259_arg_1 = var_241; [L731] SORT_2 var_259_arg_2 = input_108; [L732] EXPR var_259_arg_0 ? var_259_arg_1 : var_259_arg_2 [L732] SORT_2 var_259 = var_259_arg_0 ? var_259_arg_1 : var_259_arg_2; [L733] SORT_1 var_260_arg_0 = var_256; [L734] SORT_2 var_260_arg_1 = var_259; [L735] SORT_2 var_260_arg_2 = input_110; [L736] EXPR var_260_arg_0 ? var_260_arg_1 : var_260_arg_2 [L736] SORT_2 var_260 = var_260_arg_0 ? var_260_arg_1 : var_260_arg_2; [L737] SORT_1 var_261_arg_0 = var_257; [L738] SORT_2 var_261_arg_1 = var_258; [L739] SORT_2 var_261_arg_2 = var_260; [L740] EXPR var_261_arg_0 ? var_261_arg_1 : var_261_arg_2 [L740] SORT_2 var_261 = var_261_arg_0 ? var_261_arg_1 : var_261_arg_2; [L741] var_261 = var_261 & mask_SORT_2 [L742] SORT_3 var_262_arg_0 = var_167; [L743] SORT_2 var_262_arg_1 = var_261; [L744] SORT_4 var_262 = ((SORT_4)var_262_arg_0 << 8) | var_262_arg_1; [L745] var_262 = var_262 & mask_SORT_4 [L746] SORT_4 var_263_arg_0 = var_242; [L747] SORT_4 var_263_arg_1 = var_262; [L748] SORT_1 var_263 = var_263_arg_0 <= var_263_arg_1; [L749] SORT_1 var_264_arg_0 = var_256; [L750] SORT_1 var_264_arg_1 = ~var_263; [L751] var_264_arg_1 = var_264_arg_1 & mask_SORT_1 [L752] SORT_1 var_264 = var_264_arg_0 | var_264_arg_1; [L753] SORT_1 var_265_arg_0 = ~var_255; [L754] var_265_arg_0 = var_265_arg_0 & mask_SORT_1 [L755] SORT_1 var_265_arg_1 = var_264; [L756] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L757] SORT_1 var_266_arg_0 = var_252; [L758] SORT_1 var_266_arg_1 = var_265; [L759] SORT_1 var_266 = var_266_arg_0 & var_266_arg_1; [L760] SORT_1 var_267_arg_0 = ~input_251; [L761] var_267_arg_0 = var_267_arg_0 & mask_SORT_1 [L762] SORT_1 var_267_arg_1 = var_266; [L763] SORT_1 var_267 = var_267_arg_0 | var_267_arg_1; [L764] SORT_1 var_268_arg_0 = var_250; [L765] SORT_1 var_268_arg_1 = var_267; [L766] SORT_1 var_268 = var_268_arg_0 & var_268_arg_1; [L767] SORT_4 var_270_arg_0 = var_242; [L768] SORT_4 var_270_arg_1 = var_198; [L769] SORT_4 var_270 = var_270_arg_0 - var_270_arg_1; [L770] var_270 = var_270 & mask_SORT_4 [L771] SORT_4 var_271_arg_0 = var_197; [L772] SORT_4 var_271_arg_1 = var_270; [L773] SORT_1 var_271 = var_271_arg_0 == var_271_arg_1; [L774] SORT_1 var_272_arg_0 = input_248; [L775] SORT_1 var_272_arg_1 = var_271; [L776] SORT_1 var_272 = var_272_arg_0 & var_272_arg_1; [L777] var_272 = var_272 & mask_SORT_1 [L778] SORT_1 var_273_arg_0 = var_272; [L779] SORT_2 var_273_arg_1 = var_168; [L780] SORT_2 var_273_arg_2 = var_202; [L781] EXPR var_273_arg_0 ? var_273_arg_1 : var_273_arg_2 [L781] SORT_2 var_273 = var_273_arg_0 ? var_273_arg_1 : var_273_arg_2; [L782] SORT_4 var_274_arg_0 = var_198; [L783] SORT_4 var_274_arg_1 = var_270; [L784] SORT_1 var_274 = var_274_arg_0 == var_274_arg_1; [L785] SORT_1 var_275_arg_0 = input_248; [L786] SORT_1 var_275_arg_1 = var_274; [L787] SORT_1 var_275 = var_275_arg_0 & var_275_arg_1; [L788] var_275 = var_275 & mask_SORT_1 [L789] SORT_1 var_276_arg_0 = var_275; [L790] SORT_2 var_276_arg_1 = var_168; [L791] SORT_2 var_276_arg_2 = var_205; [L792] EXPR var_276_arg_0 ? var_276_arg_1 : var_276_arg_2 [L792] SORT_2 var_276 = var_276_arg_0 ? var_276_arg_1 : var_276_arg_2; [L793] SORT_4 var_277_arg_0 = var_206; [L794] SORT_4 var_277_arg_1 = var_270; [L795] SORT_1 var_277 = var_277_arg_0 == var_277_arg_1; [L796] SORT_1 var_278_arg_0 = input_248; [L797] SORT_1 var_278_arg_1 = var_277; [L798] SORT_1 var_278 = var_278_arg_0 & var_278_arg_1; [L799] var_278 = var_278 & mask_SORT_1 [L800] SORT_1 var_279_arg_0 = var_278; [L801] SORT_2 var_279_arg_1 = var_168; [L802] SORT_2 var_279_arg_2 = var_209; [L803] EXPR var_279_arg_0 ? var_279_arg_1 : var_279_arg_2 [L803] SORT_2 var_279 = var_279_arg_0 ? var_279_arg_1 : var_279_arg_2; [L804] SORT_1 var_280_arg_0 = var_274; [L805] SORT_2 var_280_arg_1 = var_276; [L806] SORT_2 var_280_arg_2 = var_279; [L807] EXPR var_280_arg_0 ? var_280_arg_1 : var_280_arg_2 [L807] SORT_2 var_280 = var_280_arg_0 ? var_280_arg_1 : var_280_arg_2; [L808] SORT_1 var_281_arg_0 = var_271; [L809] SORT_2 var_281_arg_1 = var_273; [L810] SORT_2 var_281_arg_2 = var_280; [L811] EXPR var_281_arg_0 ? var_281_arg_1 : var_281_arg_2 [L811] SORT_2 var_281 = var_281_arg_0 ? var_281_arg_1 : var_281_arg_2; [L812] var_281 = var_281 & mask_SORT_2 [L813] SORT_2 var_282_arg_0 = var_168; [L814] SORT_2 var_282_arg_1 = var_281; [L815] SORT_1 var_282 = var_282_arg_0 == var_282_arg_1; [L816] SORT_4 var_283_arg_0 = var_198; [L817] SORT_4 var_283_arg_1 = var_254; [L818] SORT_4 var_283 = var_283_arg_0 + var_283_arg_1; [L819] SORT_4 var_284_arg_0 = var_283; [L820] SORT_2 var_284 = var_284_arg_0 >> 0; [L821] SORT_1 var_285_arg_0 = input_251; [L822] SORT_2 var_285_arg_1 = var_284; [L823] SORT_2 var_285_arg_2 = var_253; [L824] EXPR var_285_arg_0 ? var_285_arg_1 : var_285_arg_2 [L824] SORT_2 var_285 = var_285_arg_0 ? var_285_arg_1 : var_285_arg_2; [L825] var_285 = var_285 & mask_SORT_2 [L826] SORT_2 var_286_arg_0 = var_213; [L827] SORT_2 var_286_arg_1 = var_285; [L828] SORT_1 var_286 = var_286_arg_0 == var_286_arg_1; [L829] SORT_1 var_287_arg_0 = ~var_282; [L830] var_287_arg_0 = var_287_arg_0 & mask_SORT_1 [L831] SORT_1 var_287_arg_1 = var_286; [L832] SORT_1 var_287 = var_287_arg_0 | var_287_arg_1; [L833] SORT_1 var_288_arg_0 = var_252; [L834] SORT_1 var_288_arg_1 = var_287; [L835] SORT_1 var_288 = var_288_arg_0 & var_288_arg_1; [L836] SORT_1 var_289_arg_0 = ~input_269; [L837] var_289_arg_0 = var_289_arg_0 & mask_SORT_1 [L838] SORT_1 var_289_arg_1 = var_288; [L839] SORT_1 var_289 = var_289_arg_0 | var_289_arg_1; [L840] SORT_1 var_290_arg_0 = var_268; [L841] SORT_1 var_290_arg_1 = var_289; [L842] SORT_1 var_290 = var_290_arg_0 & var_290_arg_1; [L843] SORT_1 var_292_arg_0 = var_240; [L844] SORT_1 var_292_arg_1 = ~input_239; [L845] var_292_arg_1 = var_292_arg_1 & mask_SORT_1 [L846] SORT_1 var_292 = var_292_arg_0 & var_292_arg_1; [L847] SORT_1 var_293_arg_0 = var_292; [L848] SORT_1 var_293_arg_1 = input_269; [L849] SORT_1 var_293 = var_293_arg_0 | var_293_arg_1; [L850] SORT_4 var_294_arg_0 = var_198; [L851] SORT_4 var_294_arg_1 = var_242; [L852] SORT_4 var_294 = var_294_arg_0 + var_294_arg_1; [L853] SORT_4 var_295_arg_0 = var_294; [L854] SORT_2 var_295 = var_295_arg_0 >> 0; [L855] SORT_1 var_296_arg_0 = input_269; [L856] SORT_2 var_296_arg_1 = var_295; [L857] SORT_2 var_296_arg_2 = var_241; [L858] EXPR var_296_arg_0 ? var_296_arg_1 : var_296_arg_2 [L858] SORT_2 var_296 = var_296_arg_0 ? var_296_arg_1 : var_296_arg_2; [L859] var_296 = var_296 & mask_SORT_2 [L860] SORT_2 var_297_arg_0 = var_213; [L861] SORT_2 var_297_arg_1 = var_296; [L862] SORT_1 var_297 = var_297_arg_0 == var_297_arg_1; [L863] SORT_1 var_298_arg_0 = var_293; [L864] SORT_1 var_298_arg_1 = var_297; [L865] SORT_1 var_298 = var_298_arg_0 & var_298_arg_1; [L866] SORT_1 var_299_arg_0 = ~input_291; [L867] var_299_arg_0 = var_299_arg_0 & mask_SORT_1 [L868] SORT_1 var_299_arg_1 = var_298; [L869] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L870] SORT_1 var_300_arg_0 = var_290; [L871] SORT_1 var_300_arg_1 = var_299; [L872] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L873] SORT_1 var_301_arg_0 = input_142; [L874] SORT_1 var_301_arg_1 = input_291; [L875] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L876] SORT_1 var_303_arg_0 = var_301; [L877] SORT_1 var_303_arg_1 = ~input_302; [L878] var_303_arg_1 = var_303_arg_1 & mask_SORT_1 [L879] SORT_1 var_303 = var_303_arg_0 | var_303_arg_1; [L880] SORT_1 var_304_arg_0 = var_300; [L881] SORT_1 var_304_arg_1 = var_303; [L882] SORT_1 var_304 = var_304_arg_0 & var_304_arg_1; [L883] SORT_1 var_306_arg_0 = input_150; [L884] SORT_1 var_306_arg_1 = ~input_305; [L885] var_306_arg_1 = var_306_arg_1 & mask_SORT_1 [L886] SORT_1 var_306 = var_306_arg_0 | var_306_arg_1; [L887] SORT_1 var_307_arg_0 = var_304; [L888] SORT_1 var_307_arg_1 = var_306; [L889] SORT_1 var_307 = var_307_arg_0 & var_307_arg_1; [L890] SORT_1 var_309_arg_0 = input_154; [L891] SORT_1 var_309_arg_1 = input_305; [L892] SORT_1 var_309 = var_309_arg_0 | var_309_arg_1; [L893] SORT_1 var_310_arg_0 = input_305; [L894] SORT_2 var_310_arg_1 = var_168; [L895] SORT_2 var_310_arg_2 = input_126; [L896] EXPR var_310_arg_0 ? var_310_arg_1 : var_310_arg_2 [L896] SORT_2 var_310 = var_310_arg_0 ? var_310_arg_1 : var_310_arg_2; [L897] var_310 = var_310 & mask_SORT_2 [L898] SORT_3 var_311_arg_0 = var_167; [L899] SORT_2 var_311_arg_1 = var_310; [L900] SORT_4 var_311 = ((SORT_4)var_311_arg_0 << 8) | var_311_arg_1; [L901] var_311 = var_311 & mask_SORT_4 [L902] SORT_4 var_312_arg_0 = var_166; [L903] SORT_4 var_312_arg_1 = var_311; [L904] SORT_1 var_312 = var_312_arg_0 <= var_312_arg_1; [L905] SORT_1 var_313_arg_0 = var_309; [L906] SORT_1 var_313_arg_1 = ~var_312; [L907] var_313_arg_1 = var_313_arg_1 & mask_SORT_1 [L908] SORT_1 var_313 = var_313_arg_0 & var_313_arg_1; [L909] SORT_1 var_314_arg_0 = ~input_308; [L910] var_314_arg_0 = var_314_arg_0 & mask_SORT_1 [L911] SORT_1 var_314_arg_1 = var_313; [L912] SORT_1 var_314 = var_314_arg_0 | var_314_arg_1; [L913] SORT_1 var_315_arg_0 = var_307; [L914] SORT_1 var_315_arg_1 = var_314; [L915] SORT_1 var_315 = var_315_arg_0 & var_315_arg_1; [L916] SORT_1 var_316_arg_0 = input_156; [L917] SORT_1 var_316_arg_1 = input_308; [L918] SORT_1 var_316 = var_316_arg_0 | var_316_arg_1; [L919] SORT_1 var_318_arg_0 = var_316; [L920] SORT_1 var_318_arg_1 = ~input_317; [L921] var_318_arg_1 = var_318_arg_1 & mask_SORT_1 [L922] SORT_1 var_318 = var_318_arg_0 | var_318_arg_1; [L923] SORT_1 var_319_arg_0 = var_315; [L924] SORT_1 var_319_arg_1 = var_318; [L925] SORT_1 var_319 = var_319_arg_0 & var_319_arg_1; [L926] SORT_1 var_321_arg_0 = input_158; [L927] SORT_1 var_321_arg_1 = input_317; [L928] SORT_1 var_321 = var_321_arg_0 | var_321_arg_1; [L929] SORT_1 var_322_arg_0 = input_317; [L930] SORT_2 var_322_arg_1 = var_79; [L931] SORT_2 var_322_arg_2 = input_128; [L932] EXPR var_322_arg_0 ? var_322_arg_1 : var_322_arg_2 [L932] SORT_2 var_322 = var_322_arg_0 ? var_322_arg_1 : var_322_arg_2; [L933] var_322 = var_322 & mask_SORT_2 [L934] SORT_3 var_323_arg_0 = var_167; [L935] SORT_2 var_323_arg_1 = var_322; [L936] SORT_4 var_323 = ((SORT_4)var_323_arg_0 << 8) | var_323_arg_1; [L937] var_323 = var_323 & mask_SORT_4 [L938] SORT_4 var_324_arg_0 = var_166; [L939] SORT_4 var_324_arg_1 = var_323; [L940] SORT_1 var_324 = var_324_arg_0 <= var_324_arg_1; [L941] SORT_2 var_326_arg_0 = var_325; [L942] SORT_2 var_326_arg_1 = var_322; [L943] SORT_1 var_326 = var_326_arg_0 == var_326_arg_1; [L944] SORT_2 var_327_arg_0 = var_79; [L945] SORT_2 var_327_arg_1 = var_322; [L946] SORT_1 var_327 = var_327_arg_0 == var_327_arg_1; [L947] SORT_2 var_328_arg_0 = var_168; [L948] SORT_2 var_328_arg_1 = var_322; [L949] SORT_1 var_328 = var_328_arg_0 == var_328_arg_1; [L950] SORT_1 var_329_arg_0 = input_302; [L951] SORT_2 var_329_arg_1 = var_79; [L952] SORT_2 var_329_arg_2 = var_259; [L953] EXPR var_329_arg_0 ? var_329_arg_1 : var_329_arg_2 [L953] SORT_2 var_329 = var_329_arg_0 ? var_329_arg_1 : var_329_arg_2; [L954] var_329 = var_329 & mask_SORT_2 [L955] SORT_1 var_330_arg_0 = input_308; [L956] SORT_2 var_330_arg_1 = var_310; [L957] SORT_2 var_330_arg_2 = input_110; [L958] EXPR var_330_arg_0 ? var_330_arg_1 : var_330_arg_2 [L958] SORT_2 var_330 = var_330_arg_0 ? var_330_arg_1 : var_330_arg_2; [L959] SORT_1 var_331_arg_0 = var_328; [L960] SORT_2 var_331_arg_1 = var_329; [L961] SORT_2 var_331_arg_2 = var_330; [L962] EXPR var_331_arg_0 ? var_331_arg_1 : var_331_arg_2 [L962] SORT_2 var_331 = var_331_arg_0 ? var_331_arg_1 : var_331_arg_2; [L963] SORT_1 var_332_arg_0 = var_327; [L964] SORT_2 var_332_arg_1 = var_258; [L965] SORT_2 var_332_arg_2 = var_331; [L966] EXPR var_332_arg_0 ? var_332_arg_1 : var_332_arg_2 [L966] SORT_2 var_332 = var_332_arg_0 ? var_332_arg_1 : var_332_arg_2; [L967] var_332 = var_332 & mask_SORT_2 [L968] SORT_3 var_333_arg_0 = var_167; [L969] SORT_2 var_333_arg_1 = var_332; [L970] SORT_4 var_333 = ((SORT_4)var_333_arg_0 << 8) | var_333_arg_1; [L971] var_333 = var_333 & mask_SORT_4 [L972] SORT_4 var_334_arg_0 = var_311; [L973] SORT_4 var_334_arg_1 = var_333; [L974] SORT_1 var_334 = var_334_arg_0 <= var_334_arg_1; [L975] SORT_1 var_335_arg_0 = var_326; [L976] SORT_1 var_335_arg_1 = ~var_334; [L977] var_335_arg_1 = var_335_arg_1 & mask_SORT_1 [L978] SORT_1 var_335 = var_335_arg_0 | var_335_arg_1; [L979] SORT_1 var_336_arg_0 = ~var_324; [L980] var_336_arg_0 = var_336_arg_0 & mask_SORT_1 [L981] SORT_1 var_336_arg_1 = var_335; [L982] SORT_1 var_336 = var_336_arg_0 & var_336_arg_1; [L983] SORT_1 var_337_arg_0 = var_321; [L984] SORT_1 var_337_arg_1 = var_336; [L985] SORT_1 var_337 = var_337_arg_0 & var_337_arg_1; [L986] SORT_1 var_338_arg_0 = ~input_320; [L987] var_338_arg_0 = var_338_arg_0 & mask_SORT_1 [L988] SORT_1 var_338_arg_1 = var_337; [L989] SORT_1 var_338 = var_338_arg_0 | var_338_arg_1; [L990] SORT_1 var_339_arg_0 = var_319; [L991] SORT_1 var_339_arg_1 = var_338; [L992] SORT_1 var_339 = var_339_arg_0 & var_339_arg_1; [L993] SORT_4 var_341_arg_0 = var_311; [L994] SORT_4 var_341_arg_1 = var_198; [L995] SORT_4 var_341 = var_341_arg_0 - var_341_arg_1; [L996] var_341 = var_341 & mask_SORT_4 [L997] SORT_4 var_342_arg_0 = var_197; [L998] SORT_4 var_342_arg_1 = var_341; [L999] SORT_1 var_342 = var_342_arg_0 == var_342_arg_1; [L1000] SORT_1 var_343_arg_0 = input_317; [L1001] SORT_1 var_343_arg_1 = var_342; [L1002] SORT_1 var_343 = var_343_arg_0 & var_343_arg_1; [L1003] var_343 = var_343 & mask_SORT_1 [L1004] SORT_1 var_344_arg_0 = var_343; [L1005] SORT_2 var_344_arg_1 = var_325; [L1006] SORT_2 var_344_arg_2 = var_273; [L1007] EXPR var_344_arg_0 ? var_344_arg_1 : var_344_arg_2 [L1007] SORT_2 var_344 = var_344_arg_0 ? var_344_arg_1 : var_344_arg_2; [L1008] var_344 = var_344 & mask_SORT_2 [L1009] SORT_4 var_345_arg_0 = var_198; [L1010] SORT_4 var_345_arg_1 = var_341; [L1011] SORT_1 var_345 = var_345_arg_0 == var_345_arg_1; [L1012] SORT_1 var_346_arg_0 = input_317; [L1013] SORT_1 var_346_arg_1 = var_345; [L1014] SORT_1 var_346 = var_346_arg_0 & var_346_arg_1; [L1015] var_346 = var_346 & mask_SORT_1 [L1016] SORT_1 var_347_arg_0 = var_346; [L1017] SORT_2 var_347_arg_1 = var_325; [L1018] SORT_2 var_347_arg_2 = var_276; [L1019] EXPR var_347_arg_0 ? var_347_arg_1 : var_347_arg_2 [L1019] SORT_2 var_347 = var_347_arg_0 ? var_347_arg_1 : var_347_arg_2; [L1020] var_347 = var_347 & mask_SORT_2 [L1021] SORT_4 var_348_arg_0 = var_206; [L1022] SORT_4 var_348_arg_1 = var_341; [L1023] SORT_1 var_348 = var_348_arg_0 == var_348_arg_1; [L1024] SORT_1 var_349_arg_0 = input_317; [L1025] SORT_1 var_349_arg_1 = var_348; [L1026] SORT_1 var_349 = var_349_arg_0 & var_349_arg_1; [L1027] var_349 = var_349 & mask_SORT_1 [L1028] SORT_1 var_350_arg_0 = var_349; [L1029] SORT_2 var_350_arg_1 = var_325; [L1030] SORT_2 var_350_arg_2 = var_279; [L1031] EXPR var_350_arg_0 ? var_350_arg_1 : var_350_arg_2 [L1031] SORT_2 var_350 = var_350_arg_0 ? var_350_arg_1 : var_350_arg_2; [L1032] var_350 = var_350 & mask_SORT_2 [L1033] SORT_1 var_351_arg_0 = var_345; [L1034] SORT_2 var_351_arg_1 = var_347; [L1035] SORT_2 var_351_arg_2 = var_350; [L1036] EXPR var_351_arg_0 ? var_351_arg_1 : var_351_arg_2 [L1036] SORT_2 var_351 = var_351_arg_0 ? var_351_arg_1 : var_351_arg_2; [L1037] SORT_1 var_352_arg_0 = var_342; [L1038] SORT_2 var_352_arg_1 = var_344; [L1039] SORT_2 var_352_arg_2 = var_351; [L1040] EXPR var_352_arg_0 ? var_352_arg_1 : var_352_arg_2 [L1040] SORT_2 var_352 = var_352_arg_0 ? var_352_arg_1 : var_352_arg_2; [L1041] var_352 = var_352 & mask_SORT_2 [L1042] SORT_2 var_353_arg_0 = var_325; [L1043] SORT_2 var_353_arg_1 = var_352; [L1044] SORT_1 var_353 = var_353_arg_0 == var_353_arg_1; [L1045] SORT_4 var_354_arg_0 = var_198; [L1046] SORT_4 var_354_arg_1 = var_323; [L1047] SORT_4 var_354 = var_354_arg_0 + var_354_arg_1; [L1048] SORT_4 var_355_arg_0 = var_354; [L1049] SORT_2 var_355 = var_355_arg_0 >> 0; [L1050] SORT_1 var_356_arg_0 = input_320; [L1051] SORT_2 var_356_arg_1 = var_355; [L1052] SORT_2 var_356_arg_2 = var_322; [L1053] EXPR var_356_arg_0 ? var_356_arg_1 : var_356_arg_2 [L1053] SORT_2 var_356 = var_356_arg_0 ? var_356_arg_1 : var_356_arg_2; [L1054] var_356 = var_356 & mask_SORT_2 [L1055] SORT_2 var_357_arg_0 = var_213; [L1056] SORT_2 var_357_arg_1 = var_356; [L1057] SORT_1 var_357 = var_357_arg_0 == var_357_arg_1; [L1058] SORT_1 var_358_arg_0 = ~var_353; [L1059] var_358_arg_0 = var_358_arg_0 & mask_SORT_1 [L1060] SORT_1 var_358_arg_1 = var_357; [L1061] SORT_1 var_358 = var_358_arg_0 | var_358_arg_1; [L1062] SORT_1 var_359_arg_0 = var_321; [L1063] SORT_1 var_359_arg_1 = var_358; [L1064] SORT_1 var_359 = var_359_arg_0 & var_359_arg_1; [L1065] SORT_1 var_360_arg_0 = ~input_340; [L1066] var_360_arg_0 = var_360_arg_0 & mask_SORT_1 [L1067] SORT_1 var_360_arg_1 = var_359; [L1068] SORT_1 var_360 = var_360_arg_0 | var_360_arg_1; [L1069] SORT_1 var_361_arg_0 = var_339; [L1070] SORT_1 var_361_arg_1 = var_360; [L1071] SORT_1 var_361 = var_361_arg_0 & var_361_arg_1; [L1072] SORT_1 var_363_arg_0 = var_309; [L1073] SORT_1 var_363_arg_1 = ~input_308; [L1074] var_363_arg_1 = var_363_arg_1 & mask_SORT_1 [L1075] SORT_1 var_363 = var_363_arg_0 & var_363_arg_1; [L1076] SORT_1 var_364_arg_0 = var_363; [L1077] SORT_1 var_364_arg_1 = input_340; [L1078] SORT_1 var_364 = var_364_arg_0 | var_364_arg_1; [L1079] SORT_4 var_365_arg_0 = var_198; [L1080] SORT_4 var_365_arg_1 = var_311; [L1081] SORT_4 var_365 = var_365_arg_0 + var_365_arg_1; [L1082] SORT_4 var_366_arg_0 = var_365; [L1083] SORT_2 var_366 = var_366_arg_0 >> 0; [L1084] SORT_1 var_367_arg_0 = input_340; [L1085] SORT_2 var_367_arg_1 = var_366; [L1086] SORT_2 var_367_arg_2 = var_310; [L1087] EXPR var_367_arg_0 ? var_367_arg_1 : var_367_arg_2 [L1087] SORT_2 var_367 = var_367_arg_0 ? var_367_arg_1 : var_367_arg_2; [L1088] var_367 = var_367 & mask_SORT_2 [L1089] SORT_2 var_368_arg_0 = var_213; [L1090] SORT_2 var_368_arg_1 = var_367; [L1091] SORT_1 var_368 = var_368_arg_0 == var_368_arg_1; [L1092] SORT_1 var_369_arg_0 = var_364; [L1093] SORT_1 var_369_arg_1 = var_368; [L1094] SORT_1 var_369 = var_369_arg_0 & var_369_arg_1; [L1095] SORT_1 var_370_arg_0 = ~input_362; [L1096] var_370_arg_0 = var_370_arg_0 & mask_SORT_1 [L1097] SORT_1 var_370_arg_1 = var_369; [L1098] SORT_1 var_370 = var_370_arg_0 | var_370_arg_1; [L1099] SORT_1 var_371_arg_0 = var_361; [L1100] SORT_1 var_371_arg_1 = var_370; [L1101] SORT_1 var_371 = var_371_arg_0 & var_371_arg_1; [L1102] SORT_1 var_372_arg_0 = input_152; [L1103] SORT_1 var_372_arg_1 = input_362; [L1104] SORT_1 var_372 = var_372_arg_0 | var_372_arg_1; [L1105] SORT_1 var_374_arg_0 = var_372; [L1106] SORT_1 var_374_arg_1 = ~input_373; [L1107] var_374_arg_1 = var_374_arg_1 & mask_SORT_1 [L1108] SORT_1 var_374 = var_374_arg_0 | var_374_arg_1; [L1109] SORT_1 var_375_arg_0 = var_371; [L1110] SORT_1 var_375_arg_1 = var_374; [L1111] SORT_1 var_375 = var_375_arg_0 & var_375_arg_1; [L1112] SORT_1 var_376_arg_0 = input_162; [L1113] SORT_1 var_376_arg_1 = input_164; [L1114] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L1115] SORT_1 var_377_arg_0 = input_176; [L1116] SORT_1 var_377_arg_1 = var_376; [L1117] SORT_1 var_377 = var_377_arg_0 | var_377_arg_1; [L1118] SORT_1 var_378_arg_0 = input_179; [L1119] SORT_1 var_378_arg_1 = var_377; [L1120] SORT_1 var_378 = var_378_arg_0 | var_378_arg_1; [L1121] SORT_1 var_379_arg_0 = input_196; [L1122] SORT_1 var_379_arg_1 = var_378; [L1123] SORT_1 var_379 = var_379_arg_0 | var_379_arg_1; [L1124] SORT_1 var_380_arg_0 = input_222; [L1125] SORT_1 var_380_arg_1 = var_379; [L1126] SORT_1 var_380 = var_380_arg_0 | var_380_arg_1; [L1127] SORT_1 var_381_arg_0 = input_233; [L1128] SORT_1 var_381_arg_1 = var_380; [L1129] SORT_1 var_381 = var_381_arg_0 | var_381_arg_1; [L1130] SORT_1 var_382_arg_0 = input_236; [L1131] SORT_1 var_382_arg_1 = var_381; [L1132] SORT_1 var_382 = var_382_arg_0 | var_382_arg_1; [L1133] SORT_1 var_383_arg_0 = input_239; [L1134] SORT_1 var_383_arg_1 = var_382; [L1135] SORT_1 var_383 = var_383_arg_0 | var_383_arg_1; [L1136] SORT_1 var_384_arg_0 = input_248; [L1137] SORT_1 var_384_arg_1 = var_383; [L1138] SORT_1 var_384 = var_384_arg_0 | var_384_arg_1; [L1139] SORT_1 var_385_arg_0 = input_251; [L1140] SORT_1 var_385_arg_1 = var_384; [L1141] SORT_1 var_385 = var_385_arg_0 | var_385_arg_1; [L1142] SORT_1 var_386_arg_0 = input_269; [L1143] SORT_1 var_386_arg_1 = var_385; [L1144] SORT_1 var_386 = var_386_arg_0 | var_386_arg_1; [L1145] SORT_1 var_387_arg_0 = input_291; [L1146] SORT_1 var_387_arg_1 = var_386; [L1147] SORT_1 var_387 = var_387_arg_0 | var_387_arg_1; [L1148] SORT_1 var_388_arg_0 = input_302; [L1149] SORT_1 var_388_arg_1 = var_387; [L1150] SORT_1 var_388 = var_388_arg_0 | var_388_arg_1; [L1151] SORT_1 var_389_arg_0 = input_305; [L1152] SORT_1 var_389_arg_1 = var_388; [L1153] SORT_1 var_389 = var_389_arg_0 | var_389_arg_1; [L1154] SORT_1 var_390_arg_0 = input_308; [L1155] SORT_1 var_390_arg_1 = var_389; [L1156] SORT_1 var_390 = var_390_arg_0 | var_390_arg_1; [L1157] SORT_1 var_391_arg_0 = input_317; [L1158] SORT_1 var_391_arg_1 = var_390; [L1159] SORT_1 var_391 = var_391_arg_0 | var_391_arg_1; [L1160] SORT_1 var_392_arg_0 = input_320; [L1161] SORT_1 var_392_arg_1 = var_391; [L1162] SORT_1 var_392 = var_392_arg_0 | var_392_arg_1; [L1163] SORT_1 var_393_arg_0 = input_340; [L1164] SORT_1 var_393_arg_1 = var_392; [L1165] SORT_1 var_393 = var_393_arg_0 | var_393_arg_1; [L1166] SORT_1 var_394_arg_0 = input_362; [L1167] SORT_1 var_394_arg_1 = var_393; [L1168] SORT_1 var_394 = var_394_arg_0 | var_394_arg_1; [L1169] SORT_1 var_395_arg_0 = input_373; [L1170] SORT_1 var_395_arg_1 = var_394; [L1171] SORT_1 var_395 = var_395_arg_0 | var_395_arg_1; [L1172] SORT_1 var_396_arg_0 = var_375; [L1173] SORT_1 var_396_arg_1 = var_395; [L1174] SORT_1 var_396 = var_396_arg_0 & var_396_arg_1; [L1175] SORT_1 var_397_arg_0 = input_130; [L1176] SORT_1 var_397_arg_1 = input_132; [L1177] SORT_1 var_397 = var_397_arg_0 & var_397_arg_1; [L1178] SORT_1 var_398_arg_0 = input_130; [L1179] SORT_1 var_398_arg_1 = input_132; [L1180] SORT_1 var_398 = var_398_arg_0 | var_398_arg_1; [L1181] SORT_1 var_399_arg_0 = input_134; [L1182] SORT_1 var_399_arg_1 = var_398; [L1183] SORT_1 var_399 = var_399_arg_0 & var_399_arg_1; [L1184] SORT_1 var_400_arg_0 = var_397; [L1185] SORT_1 var_400_arg_1 = var_399; [L1186] SORT_1 var_400 = var_400_arg_0 | var_400_arg_1; [L1187] SORT_1 var_401_arg_0 = input_134; [L1188] SORT_1 var_401_arg_1 = var_398; [L1189] SORT_1 var_401 = var_401_arg_0 | var_401_arg_1; [L1190] SORT_1 var_402_arg_0 = input_136; [L1191] SORT_1 var_402_arg_1 = var_401; [L1192] SORT_1 var_402 = var_402_arg_0 & var_402_arg_1; [L1193] SORT_1 var_403_arg_0 = var_400; [L1194] SORT_1 var_403_arg_1 = var_402; [L1195] SORT_1 var_403 = var_403_arg_0 | var_403_arg_1; [L1196] SORT_1 var_404_arg_0 = input_136; [L1197] SORT_1 var_404_arg_1 = var_401; [L1198] SORT_1 var_404 = var_404_arg_0 | var_404_arg_1; [L1199] SORT_1 var_405_arg_0 = input_138; [L1200] SORT_1 var_405_arg_1 = var_404; [L1201] SORT_1 var_405 = var_405_arg_0 & var_405_arg_1; [L1202] SORT_1 var_406_arg_0 = var_403; [L1203] SORT_1 var_406_arg_1 = var_405; [L1204] SORT_1 var_406 = var_406_arg_0 | var_406_arg_1; [L1205] SORT_1 var_407_arg_0 = input_138; [L1206] SORT_1 var_407_arg_1 = var_404; [L1207] SORT_1 var_407 = var_407_arg_0 | var_407_arg_1; [L1208] SORT_1 var_408_arg_0 = ~var_406; [L1209] var_408_arg_0 = var_408_arg_0 & mask_SORT_1 [L1210] SORT_1 var_408_arg_1 = var_407; [L1211] SORT_1 var_408 = var_408_arg_0 & var_408_arg_1; [L1212] SORT_1 var_409_arg_0 = input_140; [L1213] SORT_1 var_409_arg_1 = input_142; [L1214] SORT_1 var_409 = var_409_arg_0 & var_409_arg_1; [L1215] SORT_1 var_410_arg_0 = input_140; [L1216] SORT_1 var_410_arg_1 = input_142; [L1217] SORT_1 var_410 = var_410_arg_0 | var_410_arg_1; [L1218] SORT_1 var_411_arg_0 = input_144; [L1219] SORT_1 var_411_arg_1 = var_410; [L1220] SORT_1 var_411 = var_411_arg_0 & var_411_arg_1; [L1221] SORT_1 var_412_arg_0 = var_409; [L1222] SORT_1 var_412_arg_1 = var_411; [L1223] SORT_1 var_412 = var_412_arg_0 | var_412_arg_1; [L1224] SORT_1 var_413_arg_0 = input_144; [L1225] SORT_1 var_413_arg_1 = var_410; [L1226] SORT_1 var_413 = var_413_arg_0 | var_413_arg_1; [L1227] SORT_1 var_414_arg_0 = input_146; [L1228] SORT_1 var_414_arg_1 = var_413; [L1229] SORT_1 var_414 = var_414_arg_0 & var_414_arg_1; [L1230] SORT_1 var_415_arg_0 = var_412; [L1231] SORT_1 var_415_arg_1 = var_414; [L1232] SORT_1 var_415 = var_415_arg_0 | var_415_arg_1; [L1233] SORT_1 var_416_arg_0 = input_146; [L1234] SORT_1 var_416_arg_1 = var_413; [L1235] SORT_1 var_416 = var_416_arg_0 | var_416_arg_1; [L1236] SORT_1 var_417_arg_0 = input_148; [L1237] SORT_1 var_417_arg_1 = var_416; [L1238] SORT_1 var_417 = var_417_arg_0 & var_417_arg_1; [L1239] SORT_1 var_418_arg_0 = var_415; [L1240] SORT_1 var_418_arg_1 = var_417; [L1241] SORT_1 var_418 = var_418_arg_0 | var_418_arg_1; [L1242] SORT_1 var_419_arg_0 = var_408; [L1243] SORT_1 var_419_arg_1 = ~var_418; [L1244] var_419_arg_1 = var_419_arg_1 & mask_SORT_1 [L1245] SORT_1 var_419 = var_419_arg_0 & var_419_arg_1; [L1246] SORT_1 var_420_arg_0 = input_148; [L1247] SORT_1 var_420_arg_1 = var_416; [L1248] SORT_1 var_420 = var_420_arg_0 | var_420_arg_1; [L1249] SORT_1 var_421_arg_0 = var_419; [L1250] SORT_1 var_421_arg_1 = var_420; [L1251] SORT_1 var_421 = var_421_arg_0 & var_421_arg_1; [L1252] SORT_1 var_422_arg_0 = input_150; [L1253] SORT_1 var_422_arg_1 = input_152; [L1254] SORT_1 var_422 = var_422_arg_0 & var_422_arg_1; [L1255] SORT_1 var_423_arg_0 = input_150; [L1256] SORT_1 var_423_arg_1 = input_152; [L1257] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1258] SORT_1 var_424_arg_0 = input_154; [L1259] SORT_1 var_424_arg_1 = var_423; [L1260] SORT_1 var_424 = var_424_arg_0 & var_424_arg_1; [L1261] SORT_1 var_425_arg_0 = var_422; [L1262] SORT_1 var_425_arg_1 = var_424; [L1263] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1264] SORT_1 var_426_arg_0 = input_154; [L1265] SORT_1 var_426_arg_1 = var_423; [L1266] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1267] SORT_1 var_427_arg_0 = input_156; [L1268] SORT_1 var_427_arg_1 = var_426; [L1269] SORT_1 var_427 = var_427_arg_0 & var_427_arg_1; [L1270] SORT_1 var_428_arg_0 = var_425; [L1271] SORT_1 var_428_arg_1 = var_427; [L1272] SORT_1 var_428 = var_428_arg_0 | var_428_arg_1; [L1273] SORT_1 var_429_arg_0 = input_156; [L1274] SORT_1 var_429_arg_1 = var_426; [L1275] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1276] SORT_1 var_430_arg_0 = input_158; [L1277] SORT_1 var_430_arg_1 = var_429; [L1278] SORT_1 var_430 = var_430_arg_0 & var_430_arg_1; [L1279] SORT_1 var_431_arg_0 = var_428; [L1280] SORT_1 var_431_arg_1 = var_430; [L1281] SORT_1 var_431 = var_431_arg_0 | var_431_arg_1; [L1282] SORT_1 var_432_arg_0 = var_421; [L1283] SORT_1 var_432_arg_1 = ~var_431; [L1284] var_432_arg_1 = var_432_arg_1 & mask_SORT_1 [L1285] SORT_1 var_432 = var_432_arg_0 & var_432_arg_1; [L1286] SORT_1 var_433_arg_0 = input_158; [L1287] SORT_1 var_433_arg_1 = var_429; [L1288] SORT_1 var_433 = var_433_arg_0 | var_433_arg_1; [L1289] SORT_1 var_434_arg_0 = var_432; [L1290] SORT_1 var_434_arg_1 = var_433; [L1291] SORT_1 var_434 = var_434_arg_0 & var_434_arg_1; [L1292] SORT_1 var_435_arg_0 = var_396; [L1293] SORT_1 var_435_arg_1 = var_434; [L1294] SORT_1 var_435 = var_435_arg_0 & var_435_arg_1; [L1295] SORT_1 var_436_arg_0 = input_130; [L1296] SORT_1 var_436_arg_1 = ~input_162; [L1297] var_436_arg_1 = var_436_arg_1 & mask_SORT_1 [L1298] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1299] SORT_1 var_437_arg_0 = var_436; [L1300] SORT_1 var_437_arg_1 = input_233; [L1301] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1302] var_437 = var_437 & mask_SORT_1 [L1303] SORT_1 var_438_arg_0 = var_232; [L1304] SORT_1 var_438_arg_1 = ~input_233; [L1305] var_438_arg_1 = var_438_arg_1 & mask_SORT_1 [L1306] SORT_1 var_438 = var_438_arg_0 & var_438_arg_1; [L1307] var_438 = var_438 & mask_SORT_1 [L1308] SORT_1 var_439_arg_0 = var_437; [L1309] SORT_1 var_439_arg_1 = var_438; [L1310] SORT_1 var_439 = var_439_arg_0 & var_439_arg_1; [L1311] SORT_1 var_440_arg_0 = var_224; [L1312] SORT_1 var_440_arg_1 = ~input_222; [L1313] var_440_arg_1 = var_440_arg_1 & mask_SORT_1 [L1314] SORT_1 var_440 = var_440_arg_0 & var_440_arg_1; [L1315] var_440 = var_440 & mask_SORT_1 [L1316] SORT_1 var_441_arg_0 = var_437; [L1317] SORT_1 var_441_arg_1 = var_438; [L1318] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1319] SORT_1 var_442_arg_0 = var_440; [L1320] SORT_1 var_442_arg_1 = var_441; [L1321] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1322] SORT_1 var_443_arg_0 = var_439; [L1323] SORT_1 var_443_arg_1 = var_442; [L1324] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1325] SORT_1 var_444_arg_0 = var_175; [L1326] SORT_1 var_444_arg_1 = ~input_176; [L1327] var_444_arg_1 = var_444_arg_1 & mask_SORT_1 [L1328] SORT_1 var_444 = var_444_arg_0 & var_444_arg_1; [L1329] var_444 = var_444 & mask_SORT_1 [L1330] SORT_1 var_445_arg_0 = var_440; [L1331] SORT_1 var_445_arg_1 = var_441; [L1332] SORT_1 var_445 = var_445_arg_0 | var_445_arg_1; [L1333] SORT_1 var_446_arg_0 = var_444; [L1334] SORT_1 var_446_arg_1 = var_445; [L1335] SORT_1 var_446 = var_446_arg_0 & var_446_arg_1; [L1336] SORT_1 var_447_arg_0 = var_443; [L1337] SORT_1 var_447_arg_1 = var_446; [L1338] SORT_1 var_447 = var_447_arg_0 | var_447_arg_1; [L1339] SORT_1 var_448_arg_0 = var_180; [L1340] SORT_1 var_448_arg_1 = ~input_196; [L1341] var_448_arg_1 = var_448_arg_1 & mask_SORT_1 [L1342] SORT_1 var_448 = var_448_arg_0 & var_448_arg_1; [L1343] var_448 = var_448 & mask_SORT_1 [L1344] SORT_1 var_449_arg_0 = var_444; [L1345] SORT_1 var_449_arg_1 = var_445; [L1346] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1347] SORT_1 var_450_arg_0 = var_448; [L1348] SORT_1 var_450_arg_1 = var_449; [L1349] SORT_1 var_450 = var_450_arg_0 & var_450_arg_1; [L1350] SORT_1 var_451_arg_0 = var_447; [L1351] SORT_1 var_451_arg_1 = var_450; [L1352] SORT_1 var_451 = var_451_arg_0 | var_451_arg_1; [L1353] SORT_1 var_452_arg_0 = var_448; [L1354] SORT_1 var_452_arg_1 = var_449; [L1355] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1356] SORT_1 var_453_arg_0 = ~var_451; [L1357] var_453_arg_0 = var_453_arg_0 & mask_SORT_1 [L1358] SORT_1 var_453_arg_1 = var_452; [L1359] SORT_1 var_453 = var_453_arg_0 & var_453_arg_1; [L1360] SORT_1 var_454_arg_0 = input_140; [L1361] SORT_1 var_454_arg_1 = ~input_236; [L1362] var_454_arg_1 = var_454_arg_1 & mask_SORT_1 [L1363] SORT_1 var_454 = var_454_arg_0 & var_454_arg_1; [L1364] SORT_1 var_455_arg_0 = var_454; [L1365] SORT_1 var_455_arg_1 = input_302; [L1366] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1367] var_455 = var_455 & mask_SORT_1 [L1368] SORT_1 var_456_arg_0 = var_301; [L1369] SORT_1 var_456_arg_1 = ~input_302; [L1370] var_456_arg_1 = var_456_arg_1 & mask_SORT_1 [L1371] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1372] var_456 = var_456 & mask_SORT_1 [L1373] SORT_1 var_457_arg_0 = var_455; [L1374] SORT_1 var_457_arg_1 = var_456; [L1375] SORT_1 var_457 = var_457_arg_0 & var_457_arg_1; [L1376] SORT_1 var_458_arg_0 = var_293; [L1377] SORT_1 var_458_arg_1 = ~input_291; [L1378] var_458_arg_1 = var_458_arg_1 & mask_SORT_1 [L1379] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1380] var_458 = var_458 & mask_SORT_1 [L1381] SORT_1 var_459_arg_0 = var_455; [L1382] SORT_1 var_459_arg_1 = var_456; [L1383] SORT_1 var_459 = var_459_arg_0 | var_459_arg_1; [L1384] SORT_1 var_460_arg_0 = var_458; [L1385] SORT_1 var_460_arg_1 = var_459; [L1386] SORT_1 var_460 = var_460_arg_0 & var_460_arg_1; [L1387] SORT_1 var_461_arg_0 = var_457; [L1388] SORT_1 var_461_arg_1 = var_460; [L1389] SORT_1 var_461 = var_461_arg_0 | var_461_arg_1; [L1390] SORT_1 var_462_arg_0 = var_247; [L1391] SORT_1 var_462_arg_1 = ~input_248; [L1392] var_462_arg_1 = var_462_arg_1 & mask_SORT_1 [L1393] SORT_1 var_462 = var_462_arg_0 & var_462_arg_1; [L1394] var_462 = var_462 & mask_SORT_1 [L1395] SORT_1 var_463_arg_0 = var_458; [L1396] SORT_1 var_463_arg_1 = var_459; [L1397] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1398] SORT_1 var_464_arg_0 = var_462; [L1399] SORT_1 var_464_arg_1 = var_463; [L1400] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1401] SORT_1 var_465_arg_0 = var_461; [L1402] SORT_1 var_465_arg_1 = var_464; [L1403] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1404] SORT_1 var_466_arg_0 = var_252; [L1405] SORT_1 var_466_arg_1 = ~input_269; [L1406] var_466_arg_1 = var_466_arg_1 & mask_SORT_1 [L1407] SORT_1 var_466 = var_466_arg_0 & var_466_arg_1; [L1408] var_466 = var_466 & mask_SORT_1 [L1409] SORT_1 var_467_arg_0 = var_462; [L1410] SORT_1 var_467_arg_1 = var_463; [L1411] SORT_1 var_467 = var_467_arg_0 | var_467_arg_1; [L1412] SORT_1 var_468_arg_0 = var_466; [L1413] SORT_1 var_468_arg_1 = var_467; [L1414] SORT_1 var_468 = var_468_arg_0 & var_468_arg_1; [L1415] SORT_1 var_469_arg_0 = var_465; [L1416] SORT_1 var_469_arg_1 = var_468; [L1417] SORT_1 var_469 = var_469_arg_0 | var_469_arg_1; [L1418] SORT_1 var_470_arg_0 = var_453; [L1419] SORT_1 var_470_arg_1 = ~var_469; [L1420] var_470_arg_1 = var_470_arg_1 & mask_SORT_1 [L1421] SORT_1 var_470 = var_470_arg_0 & var_470_arg_1; [L1422] SORT_1 var_471_arg_0 = var_466; [L1423] SORT_1 var_471_arg_1 = var_467; [L1424] SORT_1 var_471 = var_471_arg_0 | var_471_arg_1; [L1425] SORT_1 var_472_arg_0 = var_470; [L1426] SORT_1 var_472_arg_1 = var_471; [L1427] SORT_1 var_472 = var_472_arg_0 & var_472_arg_1; [L1428] SORT_1 var_473_arg_0 = input_150; [L1429] SORT_1 var_473_arg_1 = ~input_305; [L1430] var_473_arg_1 = var_473_arg_1 & mask_SORT_1 [L1431] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1432] SORT_1 var_474_arg_0 = var_473; [L1433] SORT_1 var_474_arg_1 = input_373; [L1434] SORT_1 var_474 = var_474_arg_0 | var_474_arg_1; [L1435] var_474 = var_474 & mask_SORT_1 [L1436] SORT_1 var_475_arg_0 = var_372; [L1437] SORT_1 var_475_arg_1 = ~input_373; [L1438] var_475_arg_1 = var_475_arg_1 & mask_SORT_1 [L1439] SORT_1 var_475 = var_475_arg_0 & var_475_arg_1; [L1440] var_475 = var_475 & mask_SORT_1 [L1441] SORT_1 var_476_arg_0 = var_474; [L1442] SORT_1 var_476_arg_1 = var_475; [L1443] SORT_1 var_476 = var_476_arg_0 & var_476_arg_1; [L1444] SORT_1 var_477_arg_0 = var_364; [L1445] SORT_1 var_477_arg_1 = ~input_362; [L1446] var_477_arg_1 = var_477_arg_1 & mask_SORT_1 [L1447] SORT_1 var_477 = var_477_arg_0 & var_477_arg_1; [L1448] var_477 = var_477 & mask_SORT_1 [L1449] SORT_1 var_478_arg_0 = var_474; [L1450] SORT_1 var_478_arg_1 = var_475; [L1451] SORT_1 var_478 = var_478_arg_0 | var_478_arg_1; [L1452] SORT_1 var_479_arg_0 = var_477; [L1453] SORT_1 var_479_arg_1 = var_478; [L1454] SORT_1 var_479 = var_479_arg_0 & var_479_arg_1; [L1455] SORT_1 var_480_arg_0 = var_476; [L1456] SORT_1 var_480_arg_1 = var_479; [L1457] SORT_1 var_480 = var_480_arg_0 | var_480_arg_1; [L1458] SORT_1 var_481_arg_0 = var_316; [L1459] SORT_1 var_481_arg_1 = ~input_317; [L1460] var_481_arg_1 = var_481_arg_1 & mask_SORT_1 [L1461] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1462] var_481 = var_481 & mask_SORT_1 [L1463] SORT_1 var_482_arg_0 = var_477; [L1464] SORT_1 var_482_arg_1 = var_478; [L1465] SORT_1 var_482 = var_482_arg_0 | var_482_arg_1; [L1466] SORT_1 var_483_arg_0 = var_481; [L1467] SORT_1 var_483_arg_1 = var_482; [L1468] SORT_1 var_483 = var_483_arg_0 & var_483_arg_1; [L1469] SORT_1 var_484_arg_0 = var_480; [L1470] SORT_1 var_484_arg_1 = var_483; [L1471] SORT_1 var_484 = var_484_arg_0 | var_484_arg_1; [L1472] SORT_1 var_485_arg_0 = var_321; [L1473] SORT_1 var_485_arg_1 = ~input_340; [L1474] var_485_arg_1 = var_485_arg_1 & mask_SORT_1 [L1475] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1476] var_485 = var_485 & mask_SORT_1 [L1477] SORT_1 var_486_arg_0 = var_481; [L1478] SORT_1 var_486_arg_1 = var_482; [L1479] SORT_1 var_486 = var_486_arg_0 | var_486_arg_1; [L1480] SORT_1 var_487_arg_0 = var_485; [L1481] SORT_1 var_487_arg_1 = var_486; [L1482] SORT_1 var_487 = var_487_arg_0 & var_487_arg_1; [L1483] SORT_1 var_488_arg_0 = var_484; [L1484] SORT_1 var_488_arg_1 = var_487; [L1485] SORT_1 var_488 = var_488_arg_0 | var_488_arg_1; [L1486] SORT_1 var_489_arg_0 = var_472; [L1487] SORT_1 var_489_arg_1 = ~var_488; [L1488] var_489_arg_1 = var_489_arg_1 & mask_SORT_1 [L1489] SORT_1 var_489 = var_489_arg_0 & var_489_arg_1; [L1490] SORT_1 var_490_arg_0 = var_485; [L1491] SORT_1 var_490_arg_1 = var_486; [L1492] SORT_1 var_490 = var_490_arg_0 | var_490_arg_1; [L1493] SORT_1 var_491_arg_0 = var_489; [L1494] SORT_1 var_491_arg_1 = var_490; [L1495] SORT_1 var_491 = var_491_arg_0 & var_491_arg_1; [L1496] SORT_1 var_492_arg_0 = var_435; [L1497] SORT_1 var_492_arg_1 = var_491; [L1498] SORT_1 var_492 = var_492_arg_0 & var_492_arg_1; [L1499] SORT_2 var_493_arg_0 = var_258; [L1500] SORT_2 var_493_arg_1 = state_6; [L1501] SORT_1 var_493 = var_493_arg_0 == var_493_arg_1; [L1502] SORT_1 var_494_arg_0 = var_492; [L1503] SORT_1 var_494_arg_1 = var_493; [L1504] SORT_1 var_494 = var_494_arg_0 & var_494_arg_1; [L1505] SORT_2 var_495_arg_0 = var_329; [L1506] SORT_2 var_495_arg_1 = state_8; [L1507] SORT_1 var_495 = var_495_arg_0 == var_495_arg_1; [L1508] SORT_1 var_496_arg_0 = var_494; [L1509] SORT_1 var_496_arg_1 = var_495; [L1510] SORT_1 var_496 = var_496_arg_0 & var_496_arg_1; [L1511] SORT_1 var_497_arg_0 = input_373; [L1512] SORT_2 var_497_arg_1 = var_79; [L1513] SORT_2 var_497_arg_2 = var_330; [L1514] EXPR var_497_arg_0 ? var_497_arg_1 : var_497_arg_2 [L1514] SORT_2 var_497 = var_497_arg_0 ? var_497_arg_1 : var_497_arg_2; [L1515] var_497 = var_497 & mask_SORT_2 [L1516] SORT_2 var_498_arg_0 = var_497; [L1517] SORT_2 var_498_arg_1 = state_10; [L1518] SORT_1 var_498 = var_498_arg_0 == var_498_arg_1; [L1519] SORT_1 var_499_arg_0 = var_496; [L1520] SORT_1 var_499_arg_1 = var_498; [L1521] SORT_1 var_499 = var_499_arg_0 & var_499_arg_1; [L1522] SORT_2 var_500_arg_0 = var_344; [L1523] SORT_2 var_500_arg_1 = state_12; [L1524] SORT_1 var_500 = var_500_arg_0 == var_500_arg_1; [L1525] SORT_1 var_501_arg_0 = var_499; [L1526] SORT_1 var_501_arg_1 = var_500; [L1527] SORT_1 var_501 = var_501_arg_0 & var_501_arg_1; [L1528] SORT_2 var_502_arg_0 = var_347; [L1529] SORT_2 var_502_arg_1 = state_14; [L1530] SORT_1 var_502 = var_502_arg_0 == var_502_arg_1; [L1531] SORT_1 var_503_arg_0 = var_501; [L1532] SORT_1 var_503_arg_1 = var_502; [L1533] SORT_1 var_503 = var_503_arg_0 & var_503_arg_1; [L1534] SORT_2 var_504_arg_0 = var_350; [L1535] SORT_2 var_504_arg_1 = state_16; [L1536] SORT_1 var_504 = var_504_arg_0 == var_504_arg_1; [L1537] SORT_1 var_505_arg_0 = var_503; [L1538] SORT_1 var_505_arg_1 = var_504; [L1539] SORT_1 var_505 = var_505_arg_0 & var_505_arg_1; [L1540] SORT_2 var_506_arg_0 = var_227; [L1541] SORT_2 var_506_arg_1 = state_18; [L1542] SORT_1 var_506 = var_506_arg_0 == var_506_arg_1; [L1543] SORT_1 var_507_arg_0 = var_505; [L1544] SORT_1 var_507_arg_1 = var_506; [L1545] SORT_1 var_507 = var_507_arg_0 & var_507_arg_1; [L1546] SORT_2 var_508_arg_0 = var_216; [L1547] SORT_2 var_508_arg_1 = state_20; [L1548] SORT_1 var_508 = var_508_arg_0 == var_508_arg_1; [L1549] SORT_1 var_509_arg_0 = var_507; [L1550] SORT_1 var_509_arg_1 = var_508; [L1551] SORT_1 var_509 = var_509_arg_0 & var_509_arg_1; [L1552] SORT_2 var_510_arg_0 = var_296; [L1553] SORT_2 var_510_arg_1 = state_22; [L1554] SORT_1 var_510 = var_510_arg_0 == var_510_arg_1; [L1555] SORT_1 var_511_arg_0 = var_509; [L1556] SORT_1 var_511_arg_1 = var_510; [L1557] SORT_1 var_511 = var_511_arg_0 & var_511_arg_1; [L1558] SORT_2 var_512_arg_0 = var_285; [L1559] SORT_2 var_512_arg_1 = state_24; [L1560] SORT_1 var_512 = var_512_arg_0 == var_512_arg_1; [L1561] SORT_1 var_513_arg_0 = var_511; [L1562] SORT_1 var_513_arg_1 = var_512; [L1563] SORT_1 var_513 = var_513_arg_0 & var_513_arg_1; [L1564] SORT_2 var_514_arg_0 = var_367; [L1565] SORT_2 var_514_arg_1 = state_26; [L1566] SORT_1 var_514 = var_514_arg_0 == var_514_arg_1; [L1567] SORT_1 var_515_arg_0 = var_513; [L1568] SORT_1 var_515_arg_1 = var_514; [L1569] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1570] SORT_2 var_516_arg_0 = var_356; [L1571] SORT_2 var_516_arg_1 = state_28; [L1572] SORT_1 var_516 = var_516_arg_0 == var_516_arg_1; [L1573] SORT_1 var_517_arg_0 = var_515; [L1574] SORT_1 var_517_arg_1 = var_516; [L1575] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L1576] SORT_1 var_518_arg_0 = var_437; [L1577] SORT_1 var_518_arg_1 = state_31; [L1578] SORT_1 var_518 = var_518_arg_0 == var_518_arg_1; [L1579] SORT_1 var_519_arg_0 = var_517; [L1580] SORT_1 var_519_arg_1 = var_518; [L1581] SORT_1 var_519 = var_519_arg_0 & var_519_arg_1; [L1582] SORT_1 var_520_arg_0 = var_438; [L1583] SORT_1 var_520_arg_1 = state_33; [L1584] SORT_1 var_520 = var_520_arg_0 == var_520_arg_1; [L1585] SORT_1 var_521_arg_0 = var_519; [L1586] SORT_1 var_521_arg_1 = var_520; [L1587] SORT_1 var_521 = var_521_arg_0 & var_521_arg_1; [L1588] SORT_1 var_522_arg_0 = var_440; [L1589] SORT_1 var_522_arg_1 = state_35; [L1590] SORT_1 var_522 = var_522_arg_0 == var_522_arg_1; [L1591] SORT_1 var_523_arg_0 = var_521; [L1592] SORT_1 var_523_arg_1 = var_522; [L1593] SORT_1 var_523 = var_523_arg_0 & var_523_arg_1; [L1594] SORT_1 var_524_arg_0 = var_444; [L1595] SORT_1 var_524_arg_1 = state_37; [L1596] SORT_1 var_524 = var_524_arg_0 == var_524_arg_1; [L1597] SORT_1 var_525_arg_0 = var_523; [L1598] SORT_1 var_525_arg_1 = var_524; [L1599] SORT_1 var_525 = var_525_arg_0 & var_525_arg_1; [L1600] SORT_1 var_526_arg_0 = var_448; [L1601] SORT_1 var_526_arg_1 = state_39; [L1602] SORT_1 var_526 = var_526_arg_0 == var_526_arg_1; [L1603] SORT_1 var_527_arg_0 = var_525; [L1604] SORT_1 var_527_arg_1 = var_526; [L1605] SORT_1 var_527 = var_527_arg_0 & var_527_arg_1; [L1606] SORT_1 var_528_arg_0 = var_455; [L1607] SORT_1 var_528_arg_1 = state_41; [L1608] SORT_1 var_528 = var_528_arg_0 == var_528_arg_1; [L1609] SORT_1 var_529_arg_0 = var_527; [L1610] SORT_1 var_529_arg_1 = var_528; [L1611] SORT_1 var_529 = var_529_arg_0 & var_529_arg_1; [L1612] SORT_1 var_530_arg_0 = var_456; [L1613] SORT_1 var_530_arg_1 = state_43; [L1614] SORT_1 var_530 = var_530_arg_0 == var_530_arg_1; [L1615] SORT_1 var_531_arg_0 = var_529; [L1616] SORT_1 var_531_arg_1 = var_530; [L1617] SORT_1 var_531 = var_531_arg_0 & var_531_arg_1; [L1618] SORT_1 var_532_arg_0 = var_458; [L1619] SORT_1 var_532_arg_1 = state_45; [L1620] SORT_1 var_532 = var_532_arg_0 == var_532_arg_1; [L1621] SORT_1 var_533_arg_0 = var_531; [L1622] SORT_1 var_533_arg_1 = var_532; [L1623] SORT_1 var_533 = var_533_arg_0 & var_533_arg_1; [L1624] SORT_1 var_534_arg_0 = var_462; [L1625] SORT_1 var_534_arg_1 = state_47; [L1626] SORT_1 var_534 = var_534_arg_0 == var_534_arg_1; [L1627] SORT_1 var_535_arg_0 = var_533; [L1628] SORT_1 var_535_arg_1 = var_534; [L1629] SORT_1 var_535 = var_535_arg_0 & var_535_arg_1; [L1630] SORT_1 var_536_arg_0 = var_466; [L1631] SORT_1 var_536_arg_1 = state_49; [L1632] SORT_1 var_536 = var_536_arg_0 == var_536_arg_1; [L1633] SORT_1 var_537_arg_0 = var_535; [L1634] SORT_1 var_537_arg_1 = var_536; [L1635] SORT_1 var_537 = var_537_arg_0 & var_537_arg_1; [L1636] SORT_1 var_538_arg_0 = var_474; [L1637] SORT_1 var_538_arg_1 = state_51; [L1638] SORT_1 var_538 = var_538_arg_0 == var_538_arg_1; [L1639] SORT_1 var_539_arg_0 = var_537; [L1640] SORT_1 var_539_arg_1 = var_538; [L1641] SORT_1 var_539 = var_539_arg_0 & var_539_arg_1; [L1642] SORT_1 var_540_arg_0 = var_475; [L1643] SORT_1 var_540_arg_1 = state_53; [L1644] SORT_1 var_540 = var_540_arg_0 == var_540_arg_1; [L1645] SORT_1 var_541_arg_0 = var_539; [L1646] SORT_1 var_541_arg_1 = var_540; [L1647] SORT_1 var_541 = var_541_arg_0 & var_541_arg_1; [L1648] SORT_1 var_542_arg_0 = var_477; [L1649] SORT_1 var_542_arg_1 = state_55; [L1650] SORT_1 var_542 = var_542_arg_0 == var_542_arg_1; [L1651] SORT_1 var_543_arg_0 = var_541; [L1652] SORT_1 var_543_arg_1 = var_542; [L1653] SORT_1 var_543 = var_543_arg_0 & var_543_arg_1; [L1654] SORT_1 var_544_arg_0 = var_481; [L1655] SORT_1 var_544_arg_1 = state_57; [L1656] SORT_1 var_544 = var_544_arg_0 == var_544_arg_1; [L1657] SORT_1 var_545_arg_0 = var_543; [L1658] SORT_1 var_545_arg_1 = var_544; [L1659] SORT_1 var_545 = var_545_arg_0 & var_545_arg_1; [L1660] SORT_1 var_546_arg_0 = var_485; [L1661] SORT_1 var_546_arg_1 = state_59; [L1662] SORT_1 var_546 = var_546_arg_0 == var_546_arg_1; [L1663] SORT_1 var_547_arg_0 = var_545; [L1664] SORT_1 var_547_arg_1 = var_546; [L1665] SORT_1 var_547 = var_547_arg_0 & var_547_arg_1; [L1666] SORT_1 var_548_arg_0 = var_547; [L1667] SORT_1 var_548_arg_1 = state_63; [L1668] SORT_1 var_548 = var_548_arg_0 & var_548_arg_1; [L1669] SORT_1 var_549_arg_0 = input_132; [L1670] SORT_4 var_549_arg_1 = var_198; [L1671] SORT_4 var_549_arg_2 = var_197; [L1672] EXPR var_549_arg_0 ? var_549_arg_1 : var_549_arg_2 [L1672] SORT_4 var_549 = var_549_arg_0 ? var_549_arg_1 : var_549_arg_2; [L1673] SORT_1 var_550_arg_0 = input_142; [L1674] SORT_4 var_550_arg_1 = var_198; [L1675] SORT_4 var_550_arg_2 = var_197; [L1676] EXPR var_550_arg_0 ? var_550_arg_1 : var_550_arg_2 [L1676] SORT_4 var_550 = var_550_arg_0 ? var_550_arg_1 : var_550_arg_2; [L1677] SORT_4 var_551_arg_0 = var_549; [L1678] SORT_4 var_551_arg_1 = var_550; [L1679] SORT_4 var_551 = var_551_arg_0 + var_551_arg_1; [L1680] SORT_1 var_552_arg_0 = input_152; [L1681] SORT_4 var_552_arg_1 = var_198; [L1682] SORT_4 var_552_arg_2 = var_197; [L1683] EXPR var_552_arg_0 ? var_552_arg_1 : var_552_arg_2 [L1683] SORT_4 var_552 = var_552_arg_0 ? var_552_arg_1 : var_552_arg_2; [L1684] SORT_4 var_553_arg_0 = var_551; [L1685] SORT_4 var_553_arg_1 = var_552; [L1686] SORT_4 var_553 = var_553_arg_0 + var_553_arg_1; [L1687] var_553 = var_553 & mask_SORT_4 [L1688] SORT_4 var_554_arg_0 = var_553; [L1689] SORT_4 var_554_arg_1 = var_198; [L1690] SORT_1 var_554 = var_554_arg_0 <= var_554_arg_1; [L1691] SORT_1 var_555_arg_0 = state_61; [L1692] SORT_1 var_555_arg_1 = var_548; [L1693] SORT_1 var_555_arg_2 = ~var_554; [L1694] var_555_arg_2 = var_555_arg_2 & mask_SORT_1 [L1695] EXPR var_555_arg_0 ? var_555_arg_1 : var_555_arg_2 [L1695] SORT_1 var_555 = var_555_arg_0 ? var_555_arg_1 : var_555_arg_2; [L1696] SORT_1 next_556_arg_1 = var_555; [L1698] state_6 = next_107_arg_1 [L1699] state_8 = next_109_arg_1 [L1700] state_10 = next_111_arg_1 [L1701] state_12 = next_113_arg_1 [L1702] state_14 = next_115_arg_1 [L1703] state_16 = next_117_arg_1 [L1704] state_18 = next_119_arg_1 [L1705] state_20 = next_121_arg_1 [L1706] state_22 = next_123_arg_1 [L1707] state_24 = next_125_arg_1 [L1708] state_26 = next_127_arg_1 [L1709] state_28 = next_129_arg_1 [L1710] state_31 = next_131_arg_1 [L1711] state_33 = next_133_arg_1 [L1712] state_35 = next_135_arg_1 [L1713] state_37 = next_137_arg_1 [L1714] state_39 = next_139_arg_1 [L1715] state_41 = next_141_arg_1 [L1716] state_43 = next_143_arg_1 [L1717] state_45 = next_145_arg_1 [L1718] state_47 = next_147_arg_1 [L1719] state_49 = next_149_arg_1 [L1720] state_51 = next_151_arg_1 [L1721] state_53 = next_153_arg_1 [L1722] state_55 = next_155_arg_1 [L1723] state_57 = next_157_arg_1 [L1724] state_59 = next_159_arg_1 [L1725] state_61 = next_161_arg_1 [L1726] state_63 = next_556_arg_1 VAL [bad_105_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_29_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_106=0, input_108=0, input_110=0, input_112=0, input_114=0, input_116=0, input_118=0, input_120=0, input_122=0, input_124=0, input_126=0, input_128=0, input_130=1, input_132=0, input_134=1, input_136=1, input_138=1, input_140=1, input_142=0, input_144=1, input_146=0, input_148=1, input_150=1, input_152=0, input_154=0, input_156=1, input_158=0, input_162=0, input_164=1, input_176=0, input_179=1, input_196=1, input_222=254, input_233=1, input_236=0, input_239=0, input_248=0, input_251=0, input_269=0, input_291=19, input_302=0, input_305=1, input_308=0, input_317=1, input_320=0, input_340=1, input_362=3, input_373=1, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, next_107_arg_1=0, next_109_arg_1=0, next_111_arg_1=0, next_113_arg_1=0, next_115_arg_1=0, next_117_arg_1=0, next_119_arg_1=0, next_121_arg_1=0, next_123_arg_1=0, next_125_arg_1=0, next_127_arg_1=0, next_129_arg_1=0, next_131_arg_1=1, next_133_arg_1=0, next_135_arg_1=1, next_137_arg_1=1, next_139_arg_1=1, next_141_arg_1=1, next_143_arg_1=0, next_145_arg_1=1, next_147_arg_1=0, next_149_arg_1=1, next_151_arg_1=1, next_153_arg_1=0, next_155_arg_1=0, next_157_arg_1=1, next_159_arg_1=0, next_161_arg_1=1, next_556_arg_1=1, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_28=0, state_31=1, state_33=0, state_35=1, state_37=1, state_39=1, state_41=1, state_43=0, state_45=1, state_47=0, state_49=1, state_51=1, state_53=0, state_55=0, state_57=1, state_59=0, state_6=0, state_61=1, state_63=1, state_8=0, var_100=1, var_100_arg_0=0, var_100_arg_1=0, var_101=0, var_101_arg_0=0, var_101_arg_1=1, var_102=1, var_102_arg_0=0, var_102_arg_1=0, var_103=0, var_103_arg_0=0, var_103_arg_1=1, var_104=0, var_104_arg_0=0, var_104_arg_1=0, var_160=1, var_163=1, var_163_arg_0=1, var_163_arg_1=1, var_165=1, var_165_arg_0=1, var_165_arg_1=0, var_166=3, var_167=0, var_168=1, var_169=0, var_169_arg_0=0, var_169_arg_1=1, var_169_arg_2=0, var_170=0, var_170_arg_0=0, var_170_arg_1=0, var_171=0, var_171_arg_0=3, var_171_arg_1=0, var_172=0, var_172_arg_0=1, var_172_arg_1=0, var_173=1, var_173_arg_0=1, var_173_arg_1=0, var_174=1, var_174_arg_0=1, var_174_arg_1=1, var_175=1, var_175_arg_0=1, var_175_arg_1=1, var_177=1, var_177_arg_0=1, var_177_arg_1=1, var_178=1, var_178_arg_0=1, var_178_arg_1=1, var_180=1, var_180_arg_0=1, var_180_arg_1=0, var_181=0, var_181_arg_0=0, var_181_arg_1=0, var_181_arg_2=0, var_182=0, var_182_arg_0=0, var_182_arg_1=0, var_183=0, var_183_arg_0=3, var_183_arg_1=0, var_184=1, var_184_arg_0=0, var_184_arg_1=0, var_185=0, var_185_arg_0=1, var_185_arg_1=0, var_185_arg_2=0, var_186=0, var_186_arg_0=1, var_186_arg_1=0, var_187=0, var_187_arg_0=0, var_187_arg_1=0, var_187_arg_2=0, var_188=0, var_188_arg_0=1, var_188_arg_1=0, var_188_arg_2=0, var_189=0, var_189_arg_0=0, var_189_arg_1=0, var_190=1, var_190_arg_0=0, var_190_arg_1=0, var_191=1, var_191_arg_0=1, var_191_arg_1=0, var_192=1, var_192_arg_0=1, var_192_arg_1=1, var_193=1, var_193_arg_0=1, var_193_arg_1=1, var_194=1, var_194_arg_0=1, var_194_arg_1=1, var_195=1, var_195_arg_0=1, var_195_arg_1=1, var_197=0, var_198=1, var_199=3, var_199_arg_0=0, var_199_arg_1=1, var_200=0, var_200_arg_0=0, var_200_arg_1=3, var_201=0, var_201_arg_0=0, var_201_arg_1=0, var_202=0, var_202_arg_0=0, var_202_arg_1=0, var_202_arg_2=0, var_203=0, var_203_arg_0=1, var_203_arg_1=3, var_204=0, var_204_arg_0=0, var_204_arg_1=0, var_205=0, var_205_arg_0=0, var_205_arg_1=0, var_205_arg_2=0, var_206=2, var_207=0, var_207_arg_0=2, var_207_arg_1=3, var_208=0, var_208_arg_0=0, var_208_arg_1=0, var_209=0, var_209_arg_0=0, var_209_arg_1=0, var_209_arg_2=0, var_210=0, var_210_arg_0=0, var_210_arg_1=0, var_210_arg_2=0, var_211=0, var_211_arg_0=0, var_211_arg_1=0, var_211_arg_2=0, var_212=1, var_212_arg_0=0, var_212_arg_1=0, var_213=3, var_214=1, var_214_arg_0=1, var_214_arg_1=0, var_215=1, var_215_arg_0=1, var_216=1, var_216_arg_0=1, var_216_arg_1=1, var_216_arg_2=0, var_217=0, var_217_arg_0=3, var_217_arg_1=1, var_218=0, var_218_arg_0=0, var_218_arg_1=0, var_219=0, var_219_arg_0=1, var_219_arg_1=0, var_220=1, var_220_arg_0=1, var_220_arg_1=0, var_221=1, var_221_arg_0=1, var_221_arg_1=1, var_223=1, var_223_arg_0=1, var_223_arg_1=1, var_224=1, var_224_arg_0=1, var_224_arg_1=1, var_225=1, var_225_arg_0=1, var_225_arg_1=0, var_226=1, var_226_arg_0=1, var_227=1, var_227_arg_0=1, var_227_arg_1=1, var_227_arg_2=0, var_228=0, var_228_arg_0=3, var_228_arg_1=1, var_229=0, var_229_arg_0=1, var_229_arg_1=0, var_230=1, var_230_arg_0=1, var_230_arg_1=0, var_231=1, var_231_arg_0=1, var_231_arg_1=1, var_232=1, var_232_arg_0=0, var_232_arg_1=254, var_234=1, var_234_arg_0=1, var_234_arg_1=1, var_235=1, var_235_arg_0=1, var_235_arg_1=1, var_237=1, var_237_arg_0=1, var_237_arg_1=1, var_238=1, var_238_arg_0=1, var_238_arg_1=1, var_240=1, var_240_arg_0=1, var_240_arg_1=0, var_241=0, var_241_arg_0=0, var_241_arg_1=1, var_241_arg_2=0, var_242=0, var_242_arg_0=0, var_242_arg_1=0, var_243=0, var_243_arg_0=3, var_243_arg_1=0, var_244=1, var_244_arg_0=1, var_244_arg_1=1, var_245=1, var_245_arg_0=1, var_245_arg_1=1, var_246=1, var_246_arg_0=1, var_246_arg_1=1, var_247=0, var_247_arg_0=0, var_247_arg_1=0, var_249=0, var_249_arg_0=0, var_249_arg_1=0, var_250=0, var_250_arg_0=1, var_250_arg_1=0, var_252=1, var_252_arg_0=1, var_252_arg_1=0, var_253=0, var_253_arg_0=0, var_253_arg_1=0, var_253_arg_2=0, var_254=0, var_254_arg_0=0, var_254_arg_1=0, var_255=0, var_255_arg_0=3, var_255_arg_1=0, var_256=0, var_256_arg_0=1, var_256_arg_1=0, var_257=1, var_257_arg_0=0, var_257_arg_1=0, var_258=0, var_258_arg_0=1, var_258_arg_1=0, var_258_arg_2=0, var_259=0, var_259_arg_0=0, var_259_arg_1=0, var_259_arg_2=0, var_260=0, var_260_arg_0=0, var_260_arg_1=0, var_260_arg_2=0, var_261=0, var_261_arg_0=1, var_261_arg_1=0, var_261_arg_2=0, var_262=0, var_262_arg_0=0, var_262_arg_1=0, var_263=1, var_263_arg_0=0, var_263_arg_1=0, var_264=0, var_264_arg_0=0, var_264_arg_1=0, var_265=0, var_265_arg_0=0, var_265_arg_1=0, var_266=0, var_266_arg_0=1, var_266_arg_1=0, var_267=0, var_267_arg_0=0, var_267_arg_1=0, var_268=0, var_268_arg_0=0, var_268_arg_1=0, var_270=0, var_270_arg_0=0, var_270_arg_1=1, var_271=1, var_271_arg_0=0, var_271_arg_1=0, var_272=0, var_272_arg_0=0, var_272_arg_1=1, var_273=0, var_273_arg_0=0, var_273_arg_1=1, var_273_arg_2=0, var_274=0, var_274_arg_0=1, var_274_arg_1=0, var_275=0, var_275_arg_0=0, var_275_arg_1=0, var_276=0, var_276_arg_0=0, var_276_arg_1=1, var_276_arg_2=0, var_277=0, var_277_arg_0=2, var_277_arg_1=0, var_278=0, var_278_arg_0=0, var_278_arg_1=0, var_279=0, var_279_arg_0=0, var_279_arg_1=1, var_279_arg_2=0, var_280=0, var_280_arg_0=0, var_280_arg_1=0, var_280_arg_2=0, var_281=0, var_281_arg_0=1, var_281_arg_1=0, var_281_arg_2=0, var_282=0, var_282_arg_0=1, var_282_arg_1=0, var_283=1, var_283_arg_0=1, var_283_arg_1=0, var_284=1, var_284_arg_0=1, var_285=0, var_285_arg_0=0, var_285_arg_1=1, var_285_arg_2=0, var_286=0, var_286_arg_0=3, var_286_arg_1=0, var_287=0, var_287_arg_0=0, var_287_arg_1=0, var_288=0, var_288_arg_0=1, var_288_arg_1=0, var_289=1, var_289_arg_0=1, var_289_arg_1=0, var_290=0, var_290_arg_0=0, var_290_arg_1=1, var_292=1, var_292_arg_0=1, var_292_arg_1=1, var_293=1, var_293_arg_0=1, var_293_arg_1=0, var_294=1, var_294_arg_0=1, var_294_arg_1=0, var_295=1, var_295_arg_0=1, var_296=0, var_296_arg_0=0, var_296_arg_1=1, var_296_arg_2=0, var_297=0, var_297_arg_0=3, var_297_arg_1=0, var_298=0, var_298_arg_0=1, var_298_arg_1=0, var_299=1, var_299_arg_0=1, var_299_arg_1=0, var_30=0, var_300=0, var_300_arg_0=0, var_300_arg_1=1, var_301=2, var_301_arg_0=0, var_301_arg_1=19, var_303=2, var_303_arg_0=2, var_303_arg_1=0, var_304=0, var_304_arg_0=0, var_304_arg_1=2, var_306=1, var_306_arg_0=1, var_306_arg_1=1, var_307=0, var_307_arg_0=0, var_307_arg_1=1, var_309=1, var_309_arg_0=0, var_309_arg_1=1, var_310=1, var_310_arg_0=1, var_310_arg_1=1, var_310_arg_2=0, var_311=2, var_311_arg_0=0, var_311_arg_1=1, var_312=0, var_312_arg_0=3, var_312_arg_1=2, var_313=0, var_313_arg_0=1, var_313_arg_1=0, var_314=1, var_314_arg_0=1, var_314_arg_1=0, var_315=0, var_315_arg_0=0, var_315_arg_1=1, var_316=1, var_316_arg_0=1, var_316_arg_1=0, var_318=1, var_318_arg_0=1, var_318_arg_1=1, var_319=0, var_319_arg_0=0, var_319_arg_1=1, var_321=1, var_321_arg_0=0, var_321_arg_1=1, var_322=0, var_322_arg_0=1, var_322_arg_1=0, var_322_arg_2=0, var_323=0, var_323_arg_0=0, var_323_arg_1=0, var_324=0, var_324_arg_0=3, var_324_arg_1=0, var_325=2, var_326=0, var_326_arg_0=2, var_326_arg_1=0, var_327=1, var_327_arg_0=0, var_327_arg_1=0, var_328=0, var_328_arg_0=1, var_328_arg_1=0, var_329=0, var_329_arg_0=0, var_329_arg_1=0, var_329_arg_2=0, var_330=0, var_330_arg_0=0, var_330_arg_1=1, var_330_arg_2=0, var_331=0, var_331_arg_0=0, var_331_arg_1=0, var_331_arg_2=0, var_332=0, var_332_arg_0=1, var_332_arg_1=0, var_332_arg_2=0, var_333=0, var_333_arg_0=0, var_333_arg_1=0, var_334=0, var_334_arg_0=2, var_334_arg_1=0, var_335=1, var_335_arg_0=0, var_335_arg_1=1, var_336=1, var_336_arg_0=1, var_336_arg_1=1, var_337=1, var_337_arg_0=1, var_337_arg_1=1, var_338=1, var_338_arg_0=1, var_338_arg_1=1, var_339=0, var_339_arg_0=0, var_339_arg_1=1, var_341=3, var_341_arg_0=2, var_341_arg_1=1, var_342=0, var_342_arg_0=0, var_342_arg_1=3, var_343=0, var_343_arg_0=1, var_343_arg_1=0, var_344=0, var_344_arg_0=0, var_344_arg_1=2, var_344_arg_2=0, var_345=0, var_345_arg_0=1, var_345_arg_1=3, var_346=0, var_346_arg_0=1, var_346_arg_1=0, var_347=0, var_347_arg_0=0, var_347_arg_1=2, var_347_arg_2=0, var_348=0, var_348_arg_0=2, var_348_arg_1=3, var_349=0, var_349_arg_0=1, var_349_arg_1=0, var_350=0, var_350_arg_0=0, var_350_arg_1=2, var_350_arg_2=0, var_351=0, var_351_arg_0=0, var_351_arg_1=0, var_351_arg_2=0, var_352=0, var_352_arg_0=0, var_352_arg_1=0, var_352_arg_2=0, var_353=0, var_353_arg_0=2, var_353_arg_1=0, var_354=1, var_354_arg_0=1, var_354_arg_1=0, var_355=1, var_355_arg_0=1, var_356=0, var_356_arg_0=0, var_356_arg_1=1, var_356_arg_2=0, var_357=0, var_357_arg_0=3, var_357_arg_1=0, var_358=0, var_358_arg_0=0, var_358_arg_1=0, var_359=0, var_359_arg_0=1, var_359_arg_1=0, var_360=0, var_360_arg_0=0, var_360_arg_1=0, var_361=0, var_361_arg_0=0, var_361_arg_1=0, var_363=1, var_363_arg_0=1, var_363_arg_1=1, var_364=1, var_364_arg_0=1, var_364_arg_1=1, var_365=3, var_365_arg_0=1, var_365_arg_1=2, var_366=3, var_366_arg_0=3, var_367=0, var_367_arg_0=1, var_367_arg_1=3, var_367_arg_2=1, var_368=0, var_368_arg_0=3, var_368_arg_1=0, var_369=0, var_369_arg_0=1, var_369_arg_1=0, var_370=1, var_370_arg_0=1, var_370_arg_1=0, var_371=0, var_371_arg_0=0, var_371_arg_1=1, var_372=3, var_372_arg_0=0, var_372_arg_1=3, var_374=1, var_374_arg_0=3, var_374_arg_1=0, var_375=0, var_375_arg_0=0, var_375_arg_1=1, var_376=1, var_376_arg_0=0, var_376_arg_1=1, var_377=1, var_377_arg_0=0, var_377_arg_1=1, var_378=1, var_378_arg_0=1, var_378_arg_1=1, var_379=1, var_379_arg_0=1, var_379_arg_1=1, var_380=7, var_380_arg_0=254, var_380_arg_1=1, var_381=7, var_381_arg_0=1, var_381_arg_1=7, var_382=2, var_382_arg_0=0, var_382_arg_1=7, var_383=2, var_383_arg_0=0, var_383_arg_1=2, var_384=2, var_384_arg_0=0, var_384_arg_1=2, var_385=1, var_385_arg_0=0, var_385_arg_1=2, var_386=1, var_386_arg_0=0, var_386_arg_1=1, var_387=5, var_387_arg_0=19, var_387_arg_1=1, var_388=2, var_388_arg_0=0, var_388_arg_1=5, var_389=2, var_389_arg_0=1, var_389_arg_1=2, var_390=13, var_390_arg_0=0, var_390_arg_1=2, var_391=253, var_391_arg_0=1, var_391_arg_1=13, var_392=11, var_392_arg_0=0, var_392_arg_1=253, var_393=1, var_393_arg_0=1, var_393_arg_1=11, var_394=15, var_394_arg_0=3, var_394_arg_1=1, var_395=1, var_395_arg_0=1, var_395_arg_1=15, var_396=0, var_396_arg_0=0, var_396_arg_1=1, var_397=0, var_397_arg_0=1, var_397_arg_1=0, var_398=1, var_398_arg_0=1, var_398_arg_1=0, var_399=1, var_399_arg_0=1, var_399_arg_1=1, var_400=1, var_400_arg_0=0, var_400_arg_1=1, var_401=1, var_401_arg_0=1, var_401_arg_1=1, var_402=1, var_402_arg_0=1, var_402_arg_1=1, var_403=1, var_403_arg_0=1, var_403_arg_1=1, var_404=1, var_404_arg_0=1, var_404_arg_1=1, var_405=1, var_405_arg_0=1, var_405_arg_1=1, var_406=1, var_406_arg_0=1, var_406_arg_1=1, var_407=1, var_407_arg_0=1, var_407_arg_1=1, var_408=0, var_408_arg_0=0, var_408_arg_1=1, var_409=0, var_409_arg_0=1, var_409_arg_1=0, var_410=1, var_410_arg_0=1, var_410_arg_1=0, var_411=1, var_411_arg_0=1, var_411_arg_1=1, var_412=1, var_412_arg_0=0, var_412_arg_1=1, var_413=1, var_413_arg_0=1, var_413_arg_1=1, var_414=0, var_414_arg_0=0, var_414_arg_1=1, var_415=1, var_415_arg_0=1, var_415_arg_1=0, var_416=1, var_416_arg_0=0, var_416_arg_1=1, var_417=1, var_417_arg_0=1, var_417_arg_1=1, var_418=1, var_418_arg_0=1, var_418_arg_1=1, var_419=0, var_419_arg_0=0, var_419_arg_1=0, var_420=1, var_420_arg_0=1, var_420_arg_1=1, var_421=0, var_421_arg_0=0, var_421_arg_1=1, var_422=0, var_422_arg_0=1, var_422_arg_1=0, var_423=1, var_423_arg_0=1, var_423_arg_1=0, var_424=0, var_424_arg_0=0, var_424_arg_1=1, var_425=0, var_425_arg_0=0, var_425_arg_1=0, var_426=1, var_426_arg_0=0, var_426_arg_1=1, var_427=1, var_427_arg_0=1, var_427_arg_1=1, var_428=1, var_428_arg_0=0, var_428_arg_1=1, var_429=1, var_429_arg_0=1, var_429_arg_1=1, var_430=0, var_430_arg_0=0, var_430_arg_1=1, var_431=1, var_431_arg_0=1, var_431_arg_1=0, var_432=0, var_432_arg_0=0, var_432_arg_1=0, var_433=1, var_433_arg_0=0, var_433_arg_1=1, var_434=0, var_434_arg_0=0, var_434_arg_1=1, var_435=0, var_435_arg_0=0, var_435_arg_1=0, var_436=1, var_436_arg_0=1, var_436_arg_1=1, var_437=1, var_437_arg_0=1, var_437_arg_1=1, var_438=1, var_438_arg_0=1, var_438_arg_1=1, var_439=1, var_439_arg_0=1, var_439_arg_1=1, var_440=1, var_440_arg_0=1, var_440_arg_1=1, var_441=1, var_441_arg_0=1, var_441_arg_1=1, var_442=1, var_442_arg_0=1, var_442_arg_1=1, var_443=1, var_443_arg_0=1, var_443_arg_1=1, var_444=0, var_444_arg_0=1, var_444_arg_1=0, var_445=1, var_445_arg_0=1, var_445_arg_1=1, var_446=0, var_446_arg_0=0, var_446_arg_1=1, var_447=1, var_447_arg_0=1, var_447_arg_1=0, var_448=0, var_448_arg_0=1, var_448_arg_1=0, var_449=1, var_449_arg_0=0, var_449_arg_1=1, var_450=0, var_450_arg_0=0, var_450_arg_1=1, var_451=1, var_451_arg_0=1, var_451_arg_1=0, var_452=1, var_452_arg_0=0, var_452_arg_1=1, var_453=0, var_453_arg_0=0, var_453_arg_1=1, var_454=0, var_454_arg_0=1, var_454_arg_1=0, var_455=0, var_455_arg_0=0, var_455_arg_1=0, var_456=0, var_456_arg_0=2, var_456_arg_1=1, var_457=0, var_457_arg_0=0, var_457_arg_1=0, var_458=1, var_458_arg_0=1, var_458_arg_1=1, var_459=0, var_459_arg_0=0, var_459_arg_1=0, var_460=0, var_460_arg_0=1, var_460_arg_1=0, var_461=0, var_461_arg_0=0, var_461_arg_1=0, var_462=0, var_462_arg_0=0, var_462_arg_1=0, var_463=1, var_463_arg_0=1, var_463_arg_1=0, var_464=0, var_464_arg_0=0, var_464_arg_1=1, var_465=0, var_465_arg_0=0, var_465_arg_1=0, var_466=0, var_466_arg_0=1, var_466_arg_1=0, var_467=1, var_467_arg_0=0, var_467_arg_1=1, var_468=0, var_468_arg_0=0, var_468_arg_1=1, var_469=0, var_469_arg_0=0, var_469_arg_1=0, var_470=0, var_470_arg_0=0, var_470_arg_1=0, var_471=1, var_471_arg_0=0, var_471_arg_1=1, var_472=0, var_472_arg_0=0, var_472_arg_1=1, var_473=1, var_473_arg_0=1, var_473_arg_1=1, var_474=1, var_474_arg_0=1, var_474_arg_1=1, var_475=0, var_475_arg_0=3, var_475_arg_1=0, var_476=0, var_476_arg_0=1, var_476_arg_1=0, var_477=1, var_477_arg_0=1, var_477_arg_1=1, var_478=1, var_478_arg_0=1, var_478_arg_1=0, var_479=1, var_479_arg_0=1, var_479_arg_1=1, var_480=1, var_480_arg_0=0, var_480_arg_1=1, var_481=1, var_481_arg_0=1, var_481_arg_1=1, var_482=1, var_482_arg_0=1, var_482_arg_1=1, var_483=1, var_483_arg_0=1, var_483_arg_1=1, var_484=1, var_484_arg_0=1, var_484_arg_1=1, var_485=1, var_485_arg_0=1, var_485_arg_1=1, var_486=1, var_486_arg_0=1, var_486_arg_1=1, var_487=1, var_487_arg_0=1, var_487_arg_1=1, var_488=1, var_488_arg_0=1, var_488_arg_1=1, var_489=0, var_489_arg_0=0, var_489_arg_1=1, var_490=1, var_490_arg_0=1, var_490_arg_1=1, var_491=0, var_491_arg_0=0, var_491_arg_1=1, var_492=0, var_492_arg_0=0, var_492_arg_1=0, var_493=1, var_493_arg_0=0, var_493_arg_1=0, var_494=0, var_494_arg_0=0, var_494_arg_1=1, var_495=1, var_495_arg_0=0, var_495_arg_1=0, var_496=0, var_496_arg_0=0, var_496_arg_1=1, var_497=0, var_497_arg_0=1, var_497_arg_1=0, var_497_arg_2=0, var_498=1, var_498_arg_0=0, var_498_arg_1=0, var_499=0, var_499_arg_0=0, var_499_arg_1=1, var_5=0, var_500=1, var_500_arg_0=0, var_500_arg_1=0, var_501=0, var_501_arg_0=0, var_501_arg_1=1, var_502=1, var_502_arg_0=0, var_502_arg_1=0, var_503=0, var_503_arg_0=0, var_503_arg_1=1, var_504=1, var_504_arg_0=0, var_504_arg_1=0, var_505=0, var_505_arg_0=0, var_505_arg_1=1, var_506=0, var_506_arg_0=1, var_506_arg_1=0, var_507=0, var_507_arg_0=0, var_507_arg_1=0, var_508=0, var_508_arg_0=1, var_508_arg_1=0, var_509=0, var_509_arg_0=0, var_509_arg_1=0, var_510=1, var_510_arg_0=0, var_510_arg_1=0, var_511=0, var_511_arg_0=0, var_511_arg_1=1, var_512=1, var_512_arg_0=0, var_512_arg_1=0, var_513=0, var_513_arg_0=0, var_513_arg_1=1, var_514=1, var_514_arg_0=0, var_514_arg_1=0, var_515=0, var_515_arg_0=0, var_515_arg_1=1, var_516=1, var_516_arg_0=0, var_516_arg_1=0, var_517=0, var_517_arg_0=0, var_517_arg_1=1, var_518=0, var_518_arg_0=1, var_518_arg_1=0, var_519=0, var_519_arg_0=0, var_519_arg_1=0, var_520=0, var_520_arg_0=1, var_520_arg_1=0, var_521=0, var_521_arg_0=0, var_521_arg_1=0, var_522=0, var_522_arg_0=1, var_522_arg_1=0, var_523=0, var_523_arg_0=0, var_523_arg_1=0, var_524=1, var_524_arg_0=0, var_524_arg_1=0, var_525=0, var_525_arg_0=0, var_525_arg_1=1, var_526=1, var_526_arg_0=0, var_526_arg_1=0, var_527=0, var_527_arg_0=0, var_527_arg_1=1, var_528=1, var_528_arg_0=0, var_528_arg_1=0, var_529=0, var_529_arg_0=0, var_529_arg_1=1, var_530=1, var_530_arg_0=0, var_530_arg_1=0, var_531=0, var_531_arg_0=0, var_531_arg_1=1, var_532=0, var_532_arg_0=1, var_532_arg_1=0, var_533=0, var_533_arg_0=0, var_533_arg_1=0, var_534=1, var_534_arg_0=0, var_534_arg_1=0, var_535=0, var_535_arg_0=0, var_535_arg_1=1, var_536=1, var_536_arg_0=0, var_536_arg_1=0, var_537=0, var_537_arg_0=0, var_537_arg_1=1, var_538=0, var_538_arg_0=1, var_538_arg_1=0, var_539=0, var_539_arg_0=0, var_539_arg_1=0, var_540=1, var_540_arg_0=0, var_540_arg_1=0, var_541=0, var_541_arg_0=0, var_541_arg_1=1, var_542=0, var_542_arg_0=1, var_542_arg_1=0, var_543=0, var_543_arg_0=0, var_543_arg_1=0, var_544=0, var_544_arg_0=1, var_544_arg_1=0, var_545=0, var_545_arg_0=0, var_545_arg_1=0, var_546=0, var_546_arg_0=1, var_546_arg_1=0, var_547=0, var_547_arg_0=0, var_547_arg_1=0, var_548=0, var_548_arg_0=0, var_548_arg_1=0, var_549=0, var_549_arg_0=0, var_549_arg_1=1, var_549_arg_2=0, var_550=0, var_550_arg_0=0, var_550_arg_1=1, var_550_arg_2=0, var_551=0, var_551_arg_0=0, var_551_arg_1=0, var_552=0, var_552_arg_0=0, var_552_arg_1=1, var_552_arg_2=0, var_553=0, var_553_arg_0=0, var_553_arg_1=0, var_554=1, var_554_arg_0=0, var_554_arg_1=1, var_555=1, var_555_arg_0=0, var_555_arg_1=0, var_555_arg_2=1, var_65=0, var_65_arg_0=0, var_65_arg_1=0, var_66=0, var_66_arg_0=0, var_66_arg_1=0, var_67=0, var_67_arg_0=0, var_67_arg_1=1, var_68=0, var_68_arg_0=0, var_68_arg_1=1, var_69=0, var_69_arg_0=0, var_69_arg_1=0, var_70=0, var_70_arg_0=0, var_70_arg_1=1, var_71=0, var_71_arg_0=0, var_71_arg_1=0, var_72=0, var_72_arg_0=0, var_72_arg_1=1, var_73=0, var_73_arg_0=0, var_73_arg_1=1, var_74=0, var_74_arg_0=0, var_74_arg_1=0, var_75=0, var_75_arg_0=0, var_75_arg_1=0, var_76=0, var_76_arg_0=0, var_76_arg_1=1, var_77=0, var_77_arg_0=0, var_77_arg_1=1, var_78=0, var_78_arg_0=0, var_78_arg_1=1, var_79=0, var_80=1, var_80_arg_0=0, var_80_arg_1=0, var_81=0, var_81_arg_0=0, var_81_arg_1=1, var_82=1, var_82_arg_0=0, var_82_arg_1=0, var_83=0, var_83_arg_0=0, var_83_arg_1=1, var_84=1, var_84_arg_0=0, var_84_arg_1=0, var_85=0, var_85_arg_0=0, var_85_arg_1=1, var_86=1, var_86_arg_0=0, var_86_arg_1=0, var_87=0, var_87_arg_0=0, var_87_arg_1=1, var_88=1, var_88_arg_0=0, var_88_arg_1=0, var_89=0, var_89_arg_0=0, var_89_arg_1=1, var_90=1, var_90_arg_0=0, var_90_arg_1=0, var_91=0, var_91_arg_0=0, var_91_arg_1=1, var_92=1, var_92_arg_0=0, var_92_arg_1=0, var_93=0, var_93_arg_0=0, var_93_arg_1=1, var_94=1, var_94_arg_0=0, var_94_arg_1=0, var_95=0, var_95_arg_0=0, var_95_arg_1=1, var_96=1, var_96_arg_0=0, var_96_arg_1=0, var_97=0, var_97_arg_0=0, var_97_arg_1=1, var_98=1, var_98_arg_0=0, var_98_arg_1=0, var_99=0, var_99_arg_0=0, var_99_arg_1=1] [L189] input_106 = __VERIFIER_nondet_uchar() [L190] input_106 = input_106 & mask_SORT_2 [L191] input_108 = __VERIFIER_nondet_uchar() [L192] input_108 = input_108 & mask_SORT_2 [L193] input_110 = __VERIFIER_nondet_uchar() [L194] input_110 = input_110 & mask_SORT_2 [L195] input_112 = __VERIFIER_nondet_uchar() [L196] input_112 = input_112 & mask_SORT_2 [L197] input_114 = __VERIFIER_nondet_uchar() [L198] input_114 = input_114 & mask_SORT_2 [L199] input_116 = __VERIFIER_nondet_uchar() [L200] input_116 = input_116 & mask_SORT_2 [L201] input_118 = __VERIFIER_nondet_uchar() [L202] input_118 = input_118 & mask_SORT_2 [L203] input_120 = __VERIFIER_nondet_uchar() [L204] input_120 = input_120 & mask_SORT_2 [L205] input_122 = __VERIFIER_nondet_uchar() [L206] input_122 = input_122 & mask_SORT_2 [L207] input_124 = __VERIFIER_nondet_uchar() [L208] input_124 = input_124 & mask_SORT_2 [L209] input_126 = __VERIFIER_nondet_uchar() [L210] input_126 = input_126 & mask_SORT_2 [L211] input_128 = __VERIFIER_nondet_uchar() [L212] input_128 = input_128 & mask_SORT_2 [L213] input_130 = __VERIFIER_nondet_uchar() [L214] input_130 = input_130 & mask_SORT_1 [L215] input_132 = __VERIFIER_nondet_uchar() [L216] input_132 = input_132 & mask_SORT_1 [L217] input_134 = __VERIFIER_nondet_uchar() [L218] input_134 = input_134 & mask_SORT_1 [L219] input_136 = __VERIFIER_nondet_uchar() [L220] input_136 = input_136 & mask_SORT_1 [L221] input_138 = __VERIFIER_nondet_uchar() [L222] input_138 = input_138 & mask_SORT_1 [L223] input_140 = __VERIFIER_nondet_uchar() [L224] input_140 = input_140 & mask_SORT_1 [L225] input_142 = __VERIFIER_nondet_uchar() [L226] input_142 = input_142 & mask_SORT_1 [L227] input_144 = __VERIFIER_nondet_uchar() [L228] input_144 = input_144 & mask_SORT_1 [L229] input_146 = __VERIFIER_nondet_uchar() [L230] input_146 = input_146 & mask_SORT_1 [L231] input_148 = __VERIFIER_nondet_uchar() [L232] input_148 = input_148 & mask_SORT_1 [L233] input_150 = __VERIFIER_nondet_uchar() [L234] input_150 = input_150 & mask_SORT_1 [L235] input_152 = __VERIFIER_nondet_uchar() [L236] input_152 = input_152 & mask_SORT_1 [L237] input_154 = __VERIFIER_nondet_uchar() [L238] input_154 = input_154 & mask_SORT_1 [L239] input_156 = __VERIFIER_nondet_uchar() [L240] input_156 = input_156 & mask_SORT_1 [L241] input_158 = __VERIFIER_nondet_uchar() [L242] input_158 = input_158 & mask_SORT_1 [L243] input_162 = __VERIFIER_nondet_uchar() [L244] input_162 = input_162 & mask_SORT_1 [L245] input_164 = __VERIFIER_nondet_uchar() [L246] input_164 = input_164 & mask_SORT_1 [L247] input_176 = __VERIFIER_nondet_uchar() [L248] input_176 = input_176 & mask_SORT_1 [L249] input_179 = __VERIFIER_nondet_uchar() [L250] input_179 = input_179 & mask_SORT_1 [L251] input_196 = __VERIFIER_nondet_uchar() [L252] input_196 = input_196 & mask_SORT_1 [L253] input_222 = __VERIFIER_nondet_uchar() [L254] input_233 = __VERIFIER_nondet_uchar() [L255] input_233 = input_233 & mask_SORT_1 [L256] input_236 = __VERIFIER_nondet_uchar() [L257] input_236 = input_236 & mask_SORT_1 [L258] input_239 = __VERIFIER_nondet_uchar() [L259] input_239 = input_239 & mask_SORT_1 [L260] input_248 = __VERIFIER_nondet_uchar() [L261] input_248 = input_248 & mask_SORT_1 [L262] input_251 = __VERIFIER_nondet_uchar() [L263] input_251 = input_251 & mask_SORT_1 [L264] input_269 = __VERIFIER_nondet_uchar() [L265] input_269 = input_269 & mask_SORT_1 [L266] input_291 = __VERIFIER_nondet_uchar() [L267] input_302 = __VERIFIER_nondet_uchar() [L268] input_302 = input_302 & mask_SORT_1 [L269] input_305 = __VERIFIER_nondet_uchar() [L270] input_305 = input_305 & mask_SORT_1 [L271] input_308 = __VERIFIER_nondet_uchar() [L272] input_308 = input_308 & mask_SORT_1 [L273] input_317 = __VERIFIER_nondet_uchar() [L274] input_317 = input_317 & mask_SORT_1 [L275] input_320 = __VERIFIER_nondet_uchar() [L276] input_320 = input_320 & mask_SORT_1 [L277] input_340 = __VERIFIER_nondet_uchar() [L278] input_340 = input_340 & mask_SORT_1 [L279] input_362 = __VERIFIER_nondet_uchar() [L280] input_373 = __VERIFIER_nondet_uchar() [L281] input_373 = input_373 & mask_SORT_1 [L284] SORT_1 var_65_arg_0 = state_31; [L285] SORT_1 var_65_arg_1 = ~state_33; [L286] var_65_arg_1 = var_65_arg_1 & mask_SORT_1 [L287] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L288] SORT_1 var_66_arg_0 = var_65; [L289] SORT_1 var_66_arg_1 = ~state_35; [L290] var_66_arg_1 = var_66_arg_1 & mask_SORT_1 [L291] SORT_1 var_66 = var_66_arg_0 & var_66_arg_1; [L292] SORT_1 var_67_arg_0 = var_66; [L293] SORT_1 var_67_arg_1 = ~state_37; [L294] var_67_arg_1 = var_67_arg_1 & mask_SORT_1 [L295] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L296] SORT_1 var_68_arg_0 = var_67; [L297] SORT_1 var_68_arg_1 = ~state_39; [L298] var_68_arg_1 = var_68_arg_1 & mask_SORT_1 [L299] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L300] SORT_1 var_69_arg_0 = var_68; [L301] SORT_1 var_69_arg_1 = state_41; [L302] SORT_1 var_69 = var_69_arg_0 & var_69_arg_1; [L303] SORT_1 var_70_arg_0 = var_69; [L304] SORT_1 var_70_arg_1 = ~state_43; [L305] var_70_arg_1 = var_70_arg_1 & mask_SORT_1 [L306] SORT_1 var_70 = var_70_arg_0 & var_70_arg_1; [L307] SORT_1 var_71_arg_0 = var_70; [L308] SORT_1 var_71_arg_1 = ~state_45; [L309] var_71_arg_1 = var_71_arg_1 & mask_SORT_1 [L310] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L311] SORT_1 var_72_arg_0 = var_71; [L312] SORT_1 var_72_arg_1 = ~state_47; [L313] var_72_arg_1 = var_72_arg_1 & mask_SORT_1 [L314] SORT_1 var_72 = var_72_arg_0 & var_72_arg_1; [L315] SORT_1 var_73_arg_0 = var_72; [L316] SORT_1 var_73_arg_1 = ~state_49; [L317] var_73_arg_1 = var_73_arg_1 & mask_SORT_1 [L318] SORT_1 var_73 = var_73_arg_0 & var_73_arg_1; [L319] SORT_1 var_74_arg_0 = var_73; [L320] SORT_1 var_74_arg_1 = state_51; [L321] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L322] SORT_1 var_75_arg_0 = var_74; [L323] SORT_1 var_75_arg_1 = ~state_53; [L324] var_75_arg_1 = var_75_arg_1 & mask_SORT_1 [L325] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L326] SORT_1 var_76_arg_0 = var_75; [L327] SORT_1 var_76_arg_1 = ~state_55; [L328] var_76_arg_1 = var_76_arg_1 & mask_SORT_1 [L329] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L330] SORT_1 var_77_arg_0 = var_76; [L331] SORT_1 var_77_arg_1 = ~state_57; [L332] var_77_arg_1 = var_77_arg_1 & mask_SORT_1 [L333] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L334] SORT_1 var_78_arg_0 = var_77; [L335] SORT_1 var_78_arg_1 = ~state_59; [L336] var_78_arg_1 = var_78_arg_1 & mask_SORT_1 [L337] SORT_1 var_78 = var_78_arg_0 & var_78_arg_1; [L338] SORT_2 var_80_arg_0 = var_79; [L339] SORT_2 var_80_arg_1 = state_6; [L340] SORT_1 var_80 = var_80_arg_0 == var_80_arg_1; [L341] SORT_1 var_81_arg_0 = var_78; [L342] SORT_1 var_81_arg_1 = var_80; [L343] SORT_1 var_81 = var_81_arg_0 & var_81_arg_1; [L344] SORT_2 var_82_arg_0 = var_79; [L345] SORT_2 var_82_arg_1 = state_8; [L346] SORT_1 var_82 = var_82_arg_0 == var_82_arg_1; [L347] SORT_1 var_83_arg_0 = var_81; [L348] SORT_1 var_83_arg_1 = var_82; [L349] SORT_1 var_83 = var_83_arg_0 & var_83_arg_1; [L350] SORT_2 var_84_arg_0 = var_79; [L351] SORT_2 var_84_arg_1 = state_10; [L352] SORT_1 var_84 = var_84_arg_0 == var_84_arg_1; [L353] SORT_1 var_85_arg_0 = var_83; [L354] SORT_1 var_85_arg_1 = var_84; [L355] SORT_1 var_85 = var_85_arg_0 & var_85_arg_1; [L356] SORT_2 var_86_arg_0 = var_79; [L357] SORT_2 var_86_arg_1 = state_12; [L358] SORT_1 var_86 = var_86_arg_0 == var_86_arg_1; [L359] SORT_1 var_87_arg_0 = var_85; [L360] SORT_1 var_87_arg_1 = var_86; [L361] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L362] SORT_2 var_88_arg_0 = var_79; [L363] SORT_2 var_88_arg_1 = state_14; [L364] SORT_1 var_88 = var_88_arg_0 == var_88_arg_1; [L365] SORT_1 var_89_arg_0 = var_87; [L366] SORT_1 var_89_arg_1 = var_88; [L367] SORT_1 var_89 = var_89_arg_0 & var_89_arg_1; [L368] SORT_2 var_90_arg_0 = var_79; [L369] SORT_2 var_90_arg_1 = state_16; [L370] SORT_1 var_90 = var_90_arg_0 == var_90_arg_1; [L371] SORT_1 var_91_arg_0 = var_89; [L372] SORT_1 var_91_arg_1 = var_90; [L373] SORT_1 var_91 = var_91_arg_0 & var_91_arg_1; [L374] SORT_2 var_92_arg_0 = var_79; [L375] SORT_2 var_92_arg_1 = state_18; [L376] SORT_1 var_92 = var_92_arg_0 == var_92_arg_1; [L377] SORT_1 var_93_arg_0 = var_91; [L378] SORT_1 var_93_arg_1 = var_92; [L379] SORT_1 var_93 = var_93_arg_0 & var_93_arg_1; [L380] SORT_2 var_94_arg_0 = var_79; [L381] SORT_2 var_94_arg_1 = state_20; [L382] SORT_1 var_94 = var_94_arg_0 == var_94_arg_1; [L383] SORT_1 var_95_arg_0 = var_93; [L384] SORT_1 var_95_arg_1 = var_94; [L385] SORT_1 var_95 = var_95_arg_0 & var_95_arg_1; [L386] SORT_2 var_96_arg_0 = var_79; [L387] SORT_2 var_96_arg_1 = state_22; [L388] SORT_1 var_96 = var_96_arg_0 == var_96_arg_1; [L389] SORT_1 var_97_arg_0 = var_95; [L390] SORT_1 var_97_arg_1 = var_96; [L391] SORT_1 var_97 = var_97_arg_0 & var_97_arg_1; [L392] SORT_2 var_98_arg_0 = var_79; [L393] SORT_2 var_98_arg_1 = state_24; [L394] SORT_1 var_98 = var_98_arg_0 == var_98_arg_1; [L395] SORT_1 var_99_arg_0 = var_97; [L396] SORT_1 var_99_arg_1 = var_98; [L397] SORT_1 var_99 = var_99_arg_0 & var_99_arg_1; [L398] SORT_2 var_100_arg_0 = var_79; [L399] SORT_2 var_100_arg_1 = state_26; [L400] SORT_1 var_100 = var_100_arg_0 == var_100_arg_1; [L401] SORT_1 var_101_arg_0 = var_99; [L402] SORT_1 var_101_arg_1 = var_100; [L403] SORT_1 var_101 = var_101_arg_0 & var_101_arg_1; [L404] SORT_2 var_102_arg_0 = var_79; [L405] SORT_2 var_102_arg_1 = state_28; [L406] SORT_1 var_102 = var_102_arg_0 == var_102_arg_1; [L407] SORT_1 var_103_arg_0 = var_101; [L408] SORT_1 var_103_arg_1 = var_102; [L409] SORT_1 var_103 = var_103_arg_0 & var_103_arg_1; [L410] SORT_1 var_104_arg_0 = state_63; [L411] SORT_1 var_104_arg_1 = var_103; [L412] SORT_1 var_104 = var_104_arg_0 & var_104_arg_1; [L413] var_104 = var_104 & mask_SORT_1 [L414] SORT_1 bad_105_arg_0 = var_104; [L415] CALL __VERIFIER_assert(!(bad_105_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 566.2s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 7.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 3 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 7.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 7.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 5 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 5 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 322.4s SatisfiabilityAnalysisTime, 4.5s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 8 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:59:43,226 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cb318f5c0d13f1d3f3b84629d932eb14f1eec68c2a2b1e175e5d7ad18b1b70bf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:59:45,771 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:59:45,773 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:59:45,812 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:59:45,813 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:59:45,817 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:59:45,819 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:59:45,823 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:59:45,828 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:59:45,838 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:59:45,839 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:59:45,841 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:59:45,842 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:59:45,845 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:59:45,847 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:59:45,849 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:59:45,850 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:59:45,851 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:59:45,852 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:59:45,854 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:59:45,855 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:59:45,860 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:59:45,861 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:59:45,862 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:59:45,866 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:59:45,869 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:59:45,869 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:59:45,870 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:59:45,870 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:59:45,871 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:59:45,872 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:59:45,872 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:59:45,873 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:59:45,874 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:59:45,875 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:59:45,875 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:59:45,884 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:59:45,885 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:59:45,885 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:59:45,886 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:59:45,886 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:59:45,888 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:59:45,930 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:59:45,931 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:59:45,931 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:59:45,931 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:59:45,932 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:59:45,932 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:59:45,932 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:59:45,932 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:59:45,933 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:59:45,933 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:59:45,933 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:59:45,933 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:59:45,934 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:59:45,934 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:59:45,934 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:59:45,934 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:59:45,935 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:59:45,936 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:59:45,936 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:59:45,936 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:59:45,936 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:59:45,936 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:59:45,937 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:59:45,937 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:59:45,937 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:59:45,937 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:59:45,937 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:59:45,937 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:59:45,938 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:59:45,938 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:59:45,938 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cb318f5c0d13f1d3f3b84629d932eb14f1eec68c2a2b1e175e5d7ad18b1b70bf [2022-11-03 02:59:46,324 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:59:46,361 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:59:46,364 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:59:46,365 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:59:46,366 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:59:46,368 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:59:46,436 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/9c1332599/fb2b17e79db84441bc279120cc13270f/FLAG9671f9e8c [2022-11-03 02:59:47,082 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:59:47,082 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:59:47,102 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/9c1332599/fb2b17e79db84441bc279120cc13270f/FLAG9671f9e8c [2022-11-03 02:59:47,283 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/data/9c1332599/fb2b17e79db84441bc279120cc13270f [2022-11-03 02:59:47,287 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:59:47,289 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:59:47,293 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:59:47,293 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:59:47,297 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:59:47,298 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:59:47" (1/1) ... [2022-11-03 02:59:47,300 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@12e378 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:47, skipping insertion in model container [2022-11-03 02:59:47,300 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:59:47" (1/1) ... [2022-11-03 02:59:47,309 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:59:47,397 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:59:47,643 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c[1014,1027] [2022-11-03 02:59:48,102 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:59:48,106 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:59:48,119 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.peterson.1.prop1-back-serstep.c[1014,1027] [2022-11-03 02:59:48,252 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:59:48,264 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:59:48,265 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48 WrapperNode [2022-11-03 02:59:48,266 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:59:48,268 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:59:48,268 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:59:48,268 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:59:48,275 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,347 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,430 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1951 [2022-11-03 02:59:48,431 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:59:48,432 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:59:48,432 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:59:48,432 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:59:48,442 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,442 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,453 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,454 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,493 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,502 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,509 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,517 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,532 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:59:48,533 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:59:48,533 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:59:48,533 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:59:48,534 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (1/1) ... [2022-11-03 02:59:48,541 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:59:48,554 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:59:48,585 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:59:48,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:59:48,672 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:59:48,672 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:59:49,143 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:59:49,145 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:59:50,708 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:59:50,719 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:59:50,719 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:59:50,722 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:59:50 BoogieIcfgContainer [2022-11-03 02:59:50,722 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:59:50,726 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:59:50,726 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:59:50,730 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:59:50,731 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:59:47" (1/3) ... [2022-11-03 02:59:50,732 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cec2c53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:59:50, skipping insertion in model container [2022-11-03 02:59:50,732 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:59:48" (2/3) ... [2022-11-03 02:59:50,733 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4cec2c53 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:59:50, skipping insertion in model container [2022-11-03 02:59:50,733 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:59:50" (3/3) ... [2022-11-03 02:59:50,735 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.peterson.1.prop1-back-serstep.c [2022-11-03 02:59:50,758 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:59:50,759 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:59:50,841 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:59:50,849 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@4b4f3a2e, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:59:50,849 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:59:50,854 INFO L276 IsEmpty]: Start isEmpty. Operand has 97 states, 95 states have (on average 1.4947368421052631) internal successors, (142), 96 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:50,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 02:59:50,861 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:50,861 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 02:59:50,862 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:59:50,867 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:59:50,868 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 02:59:50,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:59:50,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [559970677] [2022-11-03 02:59:50,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:59:50,884 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:59:50,884 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:59:50,888 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:59:50,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:59:51,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:59:51,467 INFO L263 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 02:59:51,479 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:59:51,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:59:51,592 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:59:51,592 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:59:51,593 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [559970677] [2022-11-03 02:59:51,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [559970677] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:59:51,593 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:59:51,594 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:59:51,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2067492420] [2022-11-03 02:59:51,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:59:51,600 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:59:51,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:59:51,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:59:51,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:59:51,633 INFO L87 Difference]: Start difference. First operand has 97 states, 95 states have (on average 1.4947368421052631) internal successors, (142), 96 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:52,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:59:52,128 INFO L93 Difference]: Finished difference Result 278 states and 417 transitions. [2022-11-03 02:59:52,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:59:52,132 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 02:59:52,132 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:59:52,142 INFO L225 Difference]: With dead ends: 278 [2022-11-03 02:59:52,143 INFO L226 Difference]: Without dead ends: 183 [2022-11-03 02:59:52,146 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:59:52,150 INFO L413 NwaCegarLoop]: 114 mSDtfsCounter, 262 mSDsluCounter, 245 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 262 SdHoareTripleChecker+Valid, 359 SdHoareTripleChecker+Invalid, 49 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:59:52,151 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [262 Valid, 359 Invalid, 49 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 02:59:52,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2022-11-03 02:59:52,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 95. [2022-11-03 02:59:52,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 94 states have (on average 1.4680851063829787) internal successors, (138), 94 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:52,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 138 transitions. [2022-11-03 02:59:52,193 INFO L78 Accepts]: Start accepts. Automaton has 95 states and 138 transitions. Word has length 5 [2022-11-03 02:59:52,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:59:52,194 INFO L495 AbstractCegarLoop]: Abstraction has 95 states and 138 transitions. [2022-11-03 02:59:52,194 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:52,194 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 138 transitions. [2022-11-03 02:59:52,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 02:59:52,197 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:52,197 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:59:52,214 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 02:59:52,410 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:59:52,411 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:59:52,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:59:52,412 INFO L85 PathProgramCache]: Analyzing trace with hash -2079681341, now seen corresponding path program 1 times [2022-11-03 02:59:52,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:59:52,416 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [878773300] [2022-11-03 02:59:52,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:59:52,416 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:59:52,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:59:52,418 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:59:52,430 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:59:53,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:59:53,434 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:59:53,449 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:59:53,758 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:59:53,759 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:59:53,759 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:59:53,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [878773300] [2022-11-03 02:59:53,760 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [878773300] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:59:53,761 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:59:53,761 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:59:53,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [635586692] [2022-11-03 02:59:53,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:59:53,767 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:59:53,769 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:59:53,770 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:59:53,770 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:59:53,770 INFO L87 Difference]: Start difference. First operand 95 states and 138 transitions. Second operand has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:54,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:59:54,643 INFO L93 Difference]: Finished difference Result 370 states and 541 transitions. [2022-11-03 02:59:54,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:59:54,644 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 02:59:54,644 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:59:54,646 INFO L225 Difference]: With dead ends: 370 [2022-11-03 02:59:54,646 INFO L226 Difference]: Without dead ends: 279 [2022-11-03 02:59:54,647 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=56, Invalid=100, Unknown=0, NotChecked=0, Total=156 [2022-11-03 02:59:54,648 INFO L413 NwaCegarLoop]: 119 mSDtfsCounter, 1146 mSDsluCounter, 358 mSDsCounter, 0 mSdLazyCounter, 120 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1146 SdHoareTripleChecker+Valid, 477 SdHoareTripleChecker+Invalid, 123 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 120 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 02:59:54,649 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1146 Valid, 477 Invalid, 123 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 120 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-03 02:59:54,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2022-11-03 02:59:54,663 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 97. [2022-11-03 02:59:54,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 96 states have (on average 1.4583333333333333) internal successors, (140), 96 states have internal predecessors, (140), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:54,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 140 transitions. [2022-11-03 02:59:54,669 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 140 transitions. Word has length 94 [2022-11-03 02:59:54,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:59:54,670 INFO L495 AbstractCegarLoop]: Abstraction has 97 states and 140 transitions. [2022-11-03 02:59:54,673 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:54,674 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 140 transitions. [2022-11-03 02:59:54,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 02:59:54,676 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:54,676 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:59:54,707 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 02:59:54,877 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:59:54,877 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:59:54,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:59:54,878 INFO L85 PathProgramCache]: Analyzing trace with hash 1157447877, now seen corresponding path program 1 times [2022-11-03 02:59:54,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:59:54,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [538988391] [2022-11-03 02:59:54,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:59:54,880 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:59:54,881 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:59:54,881 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:59:54,883 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:59:55,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:59:55,838 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-03 02:59:55,850 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:59:55,921 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:59:55,921 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:59:55,922 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:59:55,922 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [538988391] [2022-11-03 02:59:55,922 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [538988391] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:59:55,922 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:59:55,922 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 02:59:55,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1888771028] [2022-11-03 02:59:55,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:59:55,923 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:59:55,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:59:55,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:59:55,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-03 02:59:55,924 INFO L87 Difference]: Start difference. First operand 97 states and 140 transitions. Second operand has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:56,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:59:56,368 INFO L93 Difference]: Finished difference Result 377 states and 549 transitions. [2022-11-03 02:59:56,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:59:56,369 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 02:59:56,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:59:56,371 INFO L225 Difference]: With dead ends: 377 [2022-11-03 02:59:56,371 INFO L226 Difference]: Without dead ends: 284 [2022-11-03 02:59:56,371 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:59:56,372 INFO L413 NwaCegarLoop]: 124 mSDtfsCounter, 624 mSDsluCounter, 339 mSDsCounter, 0 mSdLazyCounter, 107 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 624 SdHoareTripleChecker+Valid, 463 SdHoareTripleChecker+Invalid, 110 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 107 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:59:56,373 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [624 Valid, 463 Invalid, 110 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 107 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 02:59:56,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2022-11-03 02:59:56,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 107. [2022-11-03 02:59:56,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107 states, 106 states have (on average 1.4433962264150944) internal successors, (153), 106 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:56,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 153 transitions. [2022-11-03 02:59:56,382 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 153 transitions. Word has length 94 [2022-11-03 02:59:56,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:59:56,382 INFO L495 AbstractCegarLoop]: Abstraction has 107 states and 153 transitions. [2022-11-03 02:59:56,383 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:56,383 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 153 transitions. [2022-11-03 02:59:56,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 02:59:56,385 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:56,385 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:59:56,414 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:59:56,607 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:59:56,607 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:59:56,608 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:59:56,608 INFO L85 PathProgramCache]: Analyzing trace with hash 1397687623, now seen corresponding path program 1 times [2022-11-03 02:59:56,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:59:56,609 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [752920966] [2022-11-03 02:59:56,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:59:56,610 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:59:56,610 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:59:56,611 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:59:56,614 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 02:59:57,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:59:57,509 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-03 02:59:57,535 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:59:57,623 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:59:57,623 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:59:57,623 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:59:57,624 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [752920966] [2022-11-03 02:59:57,624 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [752920966] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:59:57,624 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:59:57,624 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 02:59:57,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200231600] [2022-11-03 02:59:57,625 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:59:57,625 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:59:57,625 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:59:57,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:59:57,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-03 02:59:57,626 INFO L87 Difference]: Start difference. First operand 107 states and 153 transitions. Second operand has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:58,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:59:58,107 INFO L93 Difference]: Finished difference Result 389 states and 563 transitions. [2022-11-03 02:59:58,108 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:59:58,108 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 02:59:58,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:59:58,110 INFO L225 Difference]: With dead ends: 389 [2022-11-03 02:59:58,110 INFO L226 Difference]: Without dead ends: 286 [2022-11-03 02:59:58,111 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:59:58,112 INFO L413 NwaCegarLoop]: 126 mSDtfsCounter, 867 mSDsluCounter, 337 mSDsCounter, 0 mSdLazyCounter, 108 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 867 SdHoareTripleChecker+Valid, 463 SdHoareTripleChecker+Invalid, 111 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 108 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:59:58,113 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [867 Valid, 463 Invalid, 111 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 108 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 02:59:58,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2022-11-03 02:59:58,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 109. [2022-11-03 02:59:58,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109 states, 108 states have (on average 1.4351851851851851) internal successors, (155), 108 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:58,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 155 transitions. [2022-11-03 02:59:58,123 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 155 transitions. Word has length 94 [2022-11-03 02:59:58,123 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:59:58,123 INFO L495 AbstractCegarLoop]: Abstraction has 109 states and 155 transitions. [2022-11-03 02:59:58,123 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:58,124 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 155 transitions. [2022-11-03 02:59:58,126 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 02:59:58,126 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:58,127 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:59:58,153 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:59:58,350 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:59:58,351 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:59:58,351 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:59:58,351 INFO L85 PathProgramCache]: Analyzing trace with hash 1424753225, now seen corresponding path program 1 times [2022-11-03 02:59:58,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:59:58,353 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [428826489] [2022-11-03 02:59:58,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:59:58,353 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:59:58,353 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:59:58,354 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:59:58,356 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 02:59:59,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:59:59,217 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 7 conjunts are in the unsatisfiable core [2022-11-03 02:59:59,226 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:59:59,316 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:59:59,316 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:59:59,316 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:59:59,317 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [428826489] [2022-11-03 02:59:59,317 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [428826489] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:59:59,317 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:59:59,317 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 02:59:59,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237445148] [2022-11-03 02:59:59,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:59:59,323 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 02:59:59,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:59:59,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 02:59:59,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-03 02:59:59,324 INFO L87 Difference]: Start difference. First operand 109 states and 155 transitions. Second operand has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:59,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:59:59,739 INFO L93 Difference]: Finished difference Result 393 states and 566 transitions. [2022-11-03 02:59:59,740 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:59:59,740 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 02:59:59,740 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:59:59,741 INFO L225 Difference]: With dead ends: 393 [2022-11-03 02:59:59,742 INFO L226 Difference]: Without dead ends: 288 [2022-11-03 02:59:59,742 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=55, Unknown=0, NotChecked=0, Total=90 [2022-11-03 02:59:59,743 INFO L413 NwaCegarLoop]: 128 mSDtfsCounter, 614 mSDsluCounter, 339 mSDsCounter, 0 mSdLazyCounter, 109 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 614 SdHoareTripleChecker+Valid, 467 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 109 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:59:59,743 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [614 Valid, 467 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 109 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 02:59:59,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states. [2022-11-03 02:59:59,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 111. [2022-11-03 02:59:59,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 110 states have (on average 1.4272727272727272) internal successors, (157), 110 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:59,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 157 transitions. [2022-11-03 02:59:59,757 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 157 transitions. Word has length 94 [2022-11-03 02:59:59,759 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:59:59,759 INFO L495 AbstractCegarLoop]: Abstraction has 111 states and 157 transitions. [2022-11-03 02:59:59,759 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 15.666666666666666) internal successors, (94), 6 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:59:59,759 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 157 transitions. [2022-11-03 02:59:59,761 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 02:59:59,761 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:59:59,761 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:59:59,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:00,000 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:00,000 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:00,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:00,000 INFO L85 PathProgramCache]: Analyzing trace with hash -1136109621, now seen corresponding path program 1 times [2022-11-03 03:00:00,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:00,001 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2113167356] [2022-11-03 03:00:00,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:00,002 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:00,002 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:00,003 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:00,004 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 03:00:00,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:00,855 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 03:00:00,864 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:01,033 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:01,033 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:01,034 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:01,034 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2113167356] [2022-11-03 03:00:01,034 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2113167356] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:01,034 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:01,034 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:01,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761638780] [2022-11-03 03:00:01,035 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:01,036 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:01,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:01,037 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:01,037 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:01,037 INFO L87 Difference]: Start difference. First operand 111 states and 157 transitions. Second operand has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:01,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:01,596 INFO L93 Difference]: Finished difference Result 481 states and 682 transitions. [2022-11-03 03:00:01,596 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 03:00:01,596 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:01,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:01,598 INFO L225 Difference]: With dead ends: 481 [2022-11-03 03:00:01,598 INFO L226 Difference]: Without dead ends: 374 [2022-11-03 03:00:01,599 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2022-11-03 03:00:01,599 INFO L413 NwaCegarLoop]: 150 mSDtfsCounter, 844 mSDsluCounter, 576 mSDsCounter, 0 mSdLazyCounter, 178 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 844 SdHoareTripleChecker+Valid, 726 SdHoareTripleChecker+Invalid, 187 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 178 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:01,600 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [844 Valid, 726 Invalid, 187 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 178 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 03:00:01,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374 states. [2022-11-03 03:00:01,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374 to 117. [2022-11-03 03:00:01,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 116 states have (on average 1.4224137931034482) internal successors, (165), 116 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:01,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 165 transitions. [2022-11-03 03:00:01,608 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 165 transitions. Word has length 94 [2022-11-03 03:00:01,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:01,608 INFO L495 AbstractCegarLoop]: Abstraction has 117 states and 165 transitions. [2022-11-03 03:00:01,608 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:01,609 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 165 transitions. [2022-11-03 03:00:01,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:01,610 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:01,610 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:01,639 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:01,834 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:01,835 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:01,835 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:01,835 INFO L85 PathProgramCache]: Analyzing trace with hash 124807629, now seen corresponding path program 1 times [2022-11-03 03:00:01,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:01,837 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [67243343] [2022-11-03 03:00:01,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:01,837 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:01,837 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:01,838 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:01,839 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 03:00:02,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:02,559 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 03:00:02,567 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:02,681 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:02,682 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:02,682 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:02,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [67243343] [2022-11-03 03:00:02,682 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [67243343] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:02,682 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:02,682 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:02,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404454061] [2022-11-03 03:00:02,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:02,684 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:02,684 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:02,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:02,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:02,685 INFO L87 Difference]: Start difference. First operand 117 states and 165 transitions. Second operand has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:03,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:03,063 INFO L93 Difference]: Finished difference Result 388 states and 548 transitions. [2022-11-03 03:00:03,063 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 03:00:03,063 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:03,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:03,065 INFO L225 Difference]: With dead ends: 388 [2022-11-03 03:00:03,065 INFO L226 Difference]: Without dead ends: 275 [2022-11-03 03:00:03,065 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=47, Invalid=85, Unknown=0, NotChecked=0, Total=132 [2022-11-03 03:00:03,066 INFO L413 NwaCegarLoop]: 164 mSDtfsCounter, 716 mSDsluCounter, 511 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 716 SdHoareTripleChecker+Valid, 675 SdHoareTripleChecker+Invalid, 118 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:03,066 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [716 Valid, 675 Invalid, 118 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 112 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 03:00:03,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states. [2022-11-03 03:00:03,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 119. [2022-11-03 03:00:03,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 119 states, 118 states have (on average 1.4152542372881356) internal successors, (167), 118 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:03,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 167 transitions. [2022-11-03 03:00:03,073 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 167 transitions. Word has length 94 [2022-11-03 03:00:03,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:03,073 INFO L495 AbstractCegarLoop]: Abstraction has 119 states and 167 transitions. [2022-11-03 03:00:03,073 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:03,073 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 167 transitions. [2022-11-03 03:00:03,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:03,081 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:03,082 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:03,111 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Ended with exit code 0 [2022-11-03 03:00:03,306 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:03,307 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:03,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:03,307 INFO L85 PathProgramCache]: Analyzing trace with hash -1261977781, now seen corresponding path program 1 times [2022-11-03 03:00:03,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:03,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [208053964] [2022-11-03 03:00:03,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:03,309 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:03,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:03,310 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:03,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 03:00:04,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:04,115 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-03 03:00:04,121 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:04,832 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:04,832 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:04,833 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:04,833 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [208053964] [2022-11-03 03:00:04,833 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [208053964] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:04,833 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:04,833 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 03:00:04,833 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402240895] [2022-11-03 03:00:04,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:04,834 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 03:00:04,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:04,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 03:00:04,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:04,835 INFO L87 Difference]: Start difference. First operand 119 states and 167 transitions. Second operand has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:05,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:05,404 INFO L93 Difference]: Finished difference Result 414 states and 582 transitions. [2022-11-03 03:00:05,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 03:00:05,407 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:05,407 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:05,409 INFO L225 Difference]: With dead ends: 414 [2022-11-03 03:00:05,409 INFO L226 Difference]: Without dead ends: 299 [2022-11-03 03:00:05,409 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2022-11-03 03:00:05,410 INFO L413 NwaCegarLoop]: 175 mSDtfsCounter, 162 mSDsluCounter, 801 mSDsCounter, 0 mSdLazyCounter, 157 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 162 SdHoareTripleChecker+Valid, 976 SdHoareTripleChecker+Invalid, 300 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 157 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 140 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:05,410 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [162 Valid, 976 Invalid, 300 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 157 Invalid, 0 Unknown, 140 Unchecked, 0.5s Time] [2022-11-03 03:00:05,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2022-11-03 03:00:05,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 183. [2022-11-03 03:00:05,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 183 states, 182 states have (on average 1.401098901098901) internal successors, (255), 182 states have internal predecessors, (255), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:05,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 255 transitions. [2022-11-03 03:00:05,419 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 255 transitions. Word has length 94 [2022-11-03 03:00:05,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:05,419 INFO L495 AbstractCegarLoop]: Abstraction has 183 states and 255 transitions. [2022-11-03 03:00:05,419 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:05,419 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 255 transitions. [2022-11-03 03:00:05,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:05,420 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:05,420 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:05,442 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:05,639 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:05,639 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:05,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:05,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1004403405, now seen corresponding path program 1 times [2022-11-03 03:00:05,641 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:05,641 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1040649553] [2022-11-03 03:00:05,641 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:05,642 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:05,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:05,643 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:05,653 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Waiting until timeout for monitored process [2022-11-03 03:00:06,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:06,408 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 21 conjunts are in the unsatisfiable core [2022-11-03 03:00:06,417 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:07,276 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:07,277 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:07,277 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:07,277 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1040649553] [2022-11-03 03:00:07,277 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1040649553] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:07,277 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:07,277 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 03:00:07,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917646178] [2022-11-03 03:00:07,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:07,278 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 03:00:07,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:07,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 03:00:07,279 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:07,279 INFO L87 Difference]: Start difference. First operand 183 states and 255 transitions. Second operand has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:07,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:07,829 INFO L93 Difference]: Finished difference Result 414 states and 581 transitions. [2022-11-03 03:00:07,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 03:00:07,830 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:07,830 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:07,831 INFO L225 Difference]: With dead ends: 414 [2022-11-03 03:00:07,831 INFO L226 Difference]: Without dead ends: 299 [2022-11-03 03:00:07,832 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2022-11-03 03:00:07,833 INFO L413 NwaCegarLoop]: 174 mSDtfsCounter, 159 mSDsluCounter, 807 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 159 SdHoareTripleChecker+Valid, 981 SdHoareTripleChecker+Invalid, 285 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 128 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:07,833 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [159 Valid, 981 Invalid, 285 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 154 Invalid, 0 Unknown, 128 Unchecked, 0.5s Time] [2022-11-03 03:00:07,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2022-11-03 03:00:07,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 185. [2022-11-03 03:00:07,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 184 states have (on average 1.3967391304347827) internal successors, (257), 184 states have internal predecessors, (257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:07,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 257 transitions. [2022-11-03 03:00:07,841 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 257 transitions. Word has length 94 [2022-11-03 03:00:07,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:07,841 INFO L495 AbstractCegarLoop]: Abstraction has 185 states and 257 transitions. [2022-11-03 03:00:07,842 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:07,842 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 257 transitions. [2022-11-03 03:00:07,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:07,843 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:07,843 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:07,870 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:08,061 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:08,061 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:08,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:08,061 INFO L85 PathProgramCache]: Analyzing trace with hash 988884687, now seen corresponding path program 1 times [2022-11-03 03:00:08,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:08,063 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1254733842] [2022-11-03 03:00:08,063 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:08,063 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:08,063 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:08,064 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:08,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-03 03:00:08,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:08,832 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 03:00:08,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:09,399 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:09,400 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:09,400 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:09,400 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1254733842] [2022-11-03 03:00:09,400 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1254733842] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:09,400 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:09,400 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2022-11-03 03:00:09,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078945107] [2022-11-03 03:00:09,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:09,401 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-03 03:00:09,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:09,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-03 03:00:09,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2022-11-03 03:00:09,402 INFO L87 Difference]: Start difference. First operand 185 states and 257 transitions. Second operand has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:10,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:10,060 INFO L93 Difference]: Finished difference Result 522 states and 732 transitions. [2022-11-03 03:00:10,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 03:00:10,061 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:10,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:10,063 INFO L225 Difference]: With dead ends: 522 [2022-11-03 03:00:10,063 INFO L226 Difference]: Without dead ends: 407 [2022-11-03 03:00:10,064 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=35, Invalid=121, Unknown=0, NotChecked=0, Total=156 [2022-11-03 03:00:10,065 INFO L413 NwaCegarLoop]: 175 mSDtfsCounter, 402 mSDsluCounter, 1068 mSDsCounter, 0 mSdLazyCounter, 165 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 402 SdHoareTripleChecker+Valid, 1243 SdHoareTripleChecker+Invalid, 241 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 165 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 73 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:10,065 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [402 Valid, 1243 Invalid, 241 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 165 Invalid, 0 Unknown, 73 Unchecked, 0.5s Time] [2022-11-03 03:00:10,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 407 states. [2022-11-03 03:00:10,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 407 to 187. [2022-11-03 03:00:10,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 187 states, 186 states have (on average 1.39247311827957) internal successors, (259), 186 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:10,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 259 transitions. [2022-11-03 03:00:10,074 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 259 transitions. Word has length 94 [2022-11-03 03:00:10,075 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:10,075 INFO L495 AbstractCegarLoop]: Abstraction has 187 states and 259 transitions. [2022-11-03 03:00:10,075 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:10,075 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 259 transitions. [2022-11-03 03:00:10,076 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:10,076 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:10,076 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:10,102 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:10,298 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:10,299 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:10,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:10,299 INFO L85 PathProgramCache]: Analyzing trace with hash 635796305, now seen corresponding path program 1 times [2022-11-03 03:00:10,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:10,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2126052630] [2022-11-03 03:00:10,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:10,301 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:10,301 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:10,302 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:10,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 03:00:10,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:11,022 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 03:00:11,029 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:11,323 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:11,323 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:11,323 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:11,323 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2126052630] [2022-11-03 03:00:11,323 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2126052630] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:11,324 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:11,324 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 03:00:11,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921507731] [2022-11-03 03:00:11,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:11,324 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 03:00:11,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:11,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 03:00:11,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-03 03:00:11,326 INFO L87 Difference]: Start difference. First operand 187 states and 259 transitions. Second operand has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:12,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:12,040 INFO L93 Difference]: Finished difference Result 573 states and 805 transitions. [2022-11-03 03:00:12,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 03:00:12,040 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:12,041 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:12,043 INFO L225 Difference]: With dead ends: 573 [2022-11-03 03:00:12,043 INFO L226 Difference]: Without dead ends: 458 [2022-11-03 03:00:12,043 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2022-11-03 03:00:12,044 INFO L413 NwaCegarLoop]: 182 mSDtfsCounter, 779 mSDsluCounter, 704 mSDsCounter, 0 mSdLazyCounter, 213 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 779 SdHoareTripleChecker+Valid, 886 SdHoareTripleChecker+Invalid, 222 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 213 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:12,044 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [779 Valid, 886 Invalid, 222 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 213 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-11-03 03:00:12,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states. [2022-11-03 03:00:12,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 193. [2022-11-03 03:00:12,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 192 states have (on average 1.390625) internal successors, (267), 192 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:12,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 267 transitions. [2022-11-03 03:00:12,053 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 267 transitions. Word has length 94 [2022-11-03 03:00:12,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:12,053 INFO L495 AbstractCegarLoop]: Abstraction has 193 states and 267 transitions. [2022-11-03 03:00:12,053 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 13.428571428571429) internal successors, (94), 7 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:12,053 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 267 transitions. [2022-11-03 03:00:12,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:12,055 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:12,055 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:12,088 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:12,270 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:12,271 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:12,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:12,271 INFO L85 PathProgramCache]: Analyzing trace with hash 1337396179, now seen corresponding path program 1 times [2022-11-03 03:00:12,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:12,273 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1846744087] [2022-11-03 03:00:12,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:12,273 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:12,273 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:12,274 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:12,275 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 03:00:13,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:13,036 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-03 03:00:13,045 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:14,030 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:14,031 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:14,031 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:14,031 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1846744087] [2022-11-03 03:00:14,031 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1846744087] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:14,031 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:14,031 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 03:00:14,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537248066] [2022-11-03 03:00:14,032 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:14,032 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 03:00:14,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:14,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 03:00:14,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 03:00:14,033 INFO L87 Difference]: Start difference. First operand 193 states and 267 transitions. Second operand has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:14,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:14,618 INFO L93 Difference]: Finished difference Result 490 states and 687 transitions. [2022-11-03 03:00:14,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 03:00:14,619 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:14,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:14,620 INFO L225 Difference]: With dead ends: 490 [2022-11-03 03:00:14,620 INFO L226 Difference]: Without dead ends: 369 [2022-11-03 03:00:14,621 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2022-11-03 03:00:14,621 INFO L413 NwaCegarLoop]: 205 mSDtfsCounter, 175 mSDsluCounter, 913 mSDsCounter, 0 mSdLazyCounter, 193 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 175 SdHoareTripleChecker+Valid, 1118 SdHoareTripleChecker+Invalid, 356 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 193 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 160 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:14,622 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [175 Valid, 1118 Invalid, 356 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 193 Invalid, 0 Unknown, 160 Unchecked, 0.5s Time] [2022-11-03 03:00:14,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2022-11-03 03:00:14,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 247. [2022-11-03 03:00:14,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 247 states, 246 states have (on average 1.3983739837398375) internal successors, (344), 246 states have internal predecessors, (344), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:14,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 344 transitions. [2022-11-03 03:00:14,633 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 344 transitions. Word has length 94 [2022-11-03 03:00:14,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:14,633 INFO L495 AbstractCegarLoop]: Abstraction has 247 states and 344 transitions. [2022-11-03 03:00:14,634 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 11.75) internal successors, (94), 8 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:14,634 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 344 transitions. [2022-11-03 03:00:14,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:14,635 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:14,635 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:14,658 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:14,858 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:14,858 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:14,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:14,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1477944789, now seen corresponding path program 1 times [2022-11-03 03:00:14,860 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:14,860 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [421015757] [2022-11-03 03:00:14,860 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:14,861 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:14,861 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:14,861 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:14,863 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 03:00:15,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:15,566 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 03:00:15,571 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:16,305 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:16,305 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:16,305 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:16,306 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [421015757] [2022-11-03 03:00:16,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [421015757] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:16,306 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:16,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2022-11-03 03:00:16,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088449467] [2022-11-03 03:00:16,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:16,306 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-11-03 03:00:16,306 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:16,307 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-11-03 03:00:16,307 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2022-11-03 03:00:16,307 INFO L87 Difference]: Start difference. First operand 247 states and 344 transitions. Second operand has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:16,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:16,929 INFO L93 Difference]: Finished difference Result 604 states and 846 transitions. [2022-11-03 03:00:16,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 03:00:16,930 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:16,930 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:16,931 INFO L225 Difference]: With dead ends: 604 [2022-11-03 03:00:16,931 INFO L226 Difference]: Without dead ends: 483 [2022-11-03 03:00:16,932 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=35, Invalid=121, Unknown=0, NotChecked=0, Total=156 [2022-11-03 03:00:16,932 INFO L413 NwaCegarLoop]: 205 mSDtfsCounter, 416 mSDsluCounter, 1169 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 416 SdHoareTripleChecker+Valid, 1374 SdHoareTripleChecker+Invalid, 297 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 90 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:16,933 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [416 Valid, 1374 Invalid, 297 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 204 Invalid, 0 Unknown, 90 Unchecked, 0.5s Time] [2022-11-03 03:00:16,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 483 states. [2022-11-03 03:00:16,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 483 to 251. [2022-11-03 03:00:16,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 251 states, 250 states have (on average 1.396) internal successors, (349), 250 states have internal predecessors, (349), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:16,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 251 states to 251 states and 349 transitions. [2022-11-03 03:00:16,942 INFO L78 Accepts]: Start accepts. Automaton has 251 states and 349 transitions. Word has length 94 [2022-11-03 03:00:16,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:16,944 INFO L495 AbstractCegarLoop]: Abstraction has 251 states and 349 transitions. [2022-11-03 03:00:16,944 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:16,944 INFO L276 IsEmpty]: Start isEmpty. Operand 251 states and 349 transitions. [2022-11-03 03:00:16,945 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:16,945 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:16,945 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:16,974 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:17,165 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:17,166 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:17,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:17,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1900646615, now seen corresponding path program 1 times [2022-11-03 03:00:17,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:17,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [976826974] [2022-11-03 03:00:17,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:17,168 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:17,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:17,169 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:17,170 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 03:00:17,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:17,902 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 03:00:17,906 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:18,053 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:18,053 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:00:18,053 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:18,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [976826974] [2022-11-03 03:00:18,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [976826974] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:00:18,053 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:00:18,054 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:00:18,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1053862023] [2022-11-03 03:00:18,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:00:18,054 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:00:18,054 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:18,055 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:00:18,055 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:00:18,055 INFO L87 Difference]: Start difference. First operand 251 states and 349 transitions. Second operand has 4 states, 4 states have (on average 23.5) internal successors, (94), 4 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:18,094 INFO L93 Difference]: Finished difference Result 533 states and 749 transitions. [2022-11-03 03:00:18,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:00:18,096 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 23.5) internal successors, (94), 4 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:18,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:18,097 INFO L225 Difference]: With dead ends: 533 [2022-11-03 03:00:18,097 INFO L226 Difference]: Without dead ends: 412 [2022-11-03 03:00:18,098 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:00:18,099 INFO L413 NwaCegarLoop]: 263 mSDtfsCounter, 177 mSDsluCounter, 265 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 177 SdHoareTripleChecker+Valid, 528 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:18,099 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [177 Valid, 528 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 03:00:18,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states. [2022-11-03 03:00:18,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 291. [2022-11-03 03:00:18,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 290 states have (on average 1.403448275862069) internal successors, (407), 290 states have internal predecessors, (407), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 407 transitions. [2022-11-03 03:00:18,109 INFO L78 Accepts]: Start accepts. Automaton has 291 states and 407 transitions. Word has length 94 [2022-11-03 03:00:18,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:18,110 INFO L495 AbstractCegarLoop]: Abstraction has 291 states and 407 transitions. [2022-11-03 03:00:18,110 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 23.5) internal successors, (94), 4 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:18,110 INFO L276 IsEmpty]: Start isEmpty. Operand 291 states and 407 transitions. [2022-11-03 03:00:18,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:18,111 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:18,111 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:18,140 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:18,326 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:18,326 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:18,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:18,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1902493657, now seen corresponding path program 1 times [2022-11-03 03:00:18,328 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:18,328 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1364798575] [2022-11-03 03:00:18,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:18,329 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:18,329 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:18,329 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:18,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 03:00:19,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:19,054 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-03 03:00:19,058 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:19,866 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:19,866 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:22,505 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:22,505 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:22,505 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1364798575] [2022-11-03 03:00:22,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1364798575] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:22,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1011177368] [2022-11-03 03:00:22,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:22,506 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:00:22,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:00:22,509 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:00:22,537 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2022-11-03 03:00:23,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:23,929 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-03 03:00:23,934 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:24,637 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:24,637 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:26,657 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:26,657 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1011177368] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:26,657 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1717815976] [2022-11-03 03:00:26,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:26,658 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:00:26,658 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:00:26,666 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:00:26,668 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-03 03:00:27,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:27,378 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-03 03:00:27,386 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:29,125 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:29,125 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:31,306 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:31,306 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1717815976] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:31,306 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:00:31,306 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 14, 14] total 38 [2022-11-03 03:00:31,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [148431940] [2022-11-03 03:00:31,307 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:00:31,308 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 38 states [2022-11-03 03:00:31,308 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:31,308 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2022-11-03 03:00:31,309 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=176, Invalid=1230, Unknown=0, NotChecked=0, Total=1406 [2022-11-03 03:00:31,309 INFO L87 Difference]: Start difference. First operand 291 states and 407 transitions. Second operand has 38 states, 38 states have (on average 9.68421052631579) internal successors, (368), 38 states have internal predecessors, (368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:32,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:32,472 INFO L93 Difference]: Finished difference Result 690 states and 967 transitions. [2022-11-03 03:00:32,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-03 03:00:32,475 INFO L78 Accepts]: Start accepts. Automaton has has 38 states, 38 states have (on average 9.68421052631579) internal successors, (368), 38 states have internal predecessors, (368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:32,475 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:32,478 INFO L225 Difference]: With dead ends: 690 [2022-11-03 03:00:32,478 INFO L226 Difference]: Without dead ends: 688 [2022-11-03 03:00:32,480 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 577 GetRequests, 525 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 631 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=363, Invalid=2289, Unknown=0, NotChecked=0, Total=2652 [2022-11-03 03:00:32,486 INFO L413 NwaCegarLoop]: 100 mSDtfsCounter, 1075 mSDsluCounter, 2597 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1075 SdHoareTripleChecker+Valid, 2697 SdHoareTripleChecker+Invalid, 179 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 173 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:32,487 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1075 Valid, 2697 Invalid, 179 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 173 Unchecked, 0.1s Time] [2022-11-03 03:00:32,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states. [2022-11-03 03:00:32,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 552. [2022-11-03 03:00:32,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 551 states have (on average 1.4047186932849365) internal successors, (774), 551 states have internal predecessors, (774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:32,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 774 transitions. [2022-11-03 03:00:32,509 INFO L78 Accepts]: Start accepts. Automaton has 552 states and 774 transitions. Word has length 94 [2022-11-03 03:00:32,510 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:32,510 INFO L495 AbstractCegarLoop]: Abstraction has 552 states and 774 transitions. [2022-11-03 03:00:32,510 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 38 states, 38 states have (on average 9.68421052631579) internal successors, (368), 38 states have internal predecessors, (368), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:32,510 INFO L276 IsEmpty]: Start isEmpty. Operand 552 states and 774 transitions. [2022-11-03 03:00:32,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:32,512 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:32,512 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:32,527 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:32,737 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Ended with exit code 0 [2022-11-03 03:00:32,948 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:33,122 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:00:33,122 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:33,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:33,123 INFO L85 PathProgramCache]: Analyzing trace with hash -617466277, now seen corresponding path program 1 times [2022-11-03 03:00:33,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:33,125 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1039322424] [2022-11-03 03:00:33,125 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:33,125 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:33,125 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:33,126 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:33,144 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-03 03:00:33,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:33,839 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 03:00:33,843 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:34,975 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:38,292 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:38,293 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:00:38,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1039322424] [2022-11-03 03:00:38,293 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1039322424] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:38,293 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1895499912] [2022-11-03 03:00:38,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:38,294 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:00:38,294 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:00:38,299 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:00:38,303 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Waiting until timeout for monitored process [2022-11-03 03:00:39,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:39,847 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 64 conjunts are in the unsatisfiable core [2022-11-03 03:00:39,854 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:40,997 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:40,997 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:48,480 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:48,480 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1895499912] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:48,481 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670246963] [2022-11-03 03:00:48,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:48,481 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:00:48,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:00:48,482 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:00:48,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2022-11-03 03:00:49,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:49,231 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 03:00:49,236 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:51,021 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:51,022 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:00:54,816 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:54,816 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [670246963] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:00:54,816 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:00:54,816 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 9, 9, 14, 14] total 52 [2022-11-03 03:00:54,817 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770043680] [2022-11-03 03:00:54,817 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:00:54,818 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 52 states [2022-11-03 03:00:54,818 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:00:54,818 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2022-11-03 03:00:54,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=2390, Unknown=0, NotChecked=0, Total=2652 [2022-11-03 03:00:54,820 INFO L87 Difference]: Start difference. First operand 552 states and 774 transitions. Second operand has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:56,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:00:56,324 INFO L93 Difference]: Finished difference Result 810 states and 1136 transitions. [2022-11-03 03:00:56,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-03 03:00:56,325 INFO L78 Accepts]: Start accepts. Automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:00:56,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:00:56,327 INFO L225 Difference]: With dead ends: 810 [2022-11-03 03:00:56,327 INFO L226 Difference]: Without dead ends: 808 [2022-11-03 03:00:56,329 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 510 SyntacticMatches, 1 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1272 ImplicationChecksByTransitivity, 12.1s TimeCoverageRelationStatistics Valid=443, Invalid=3847, Unknown=0, NotChecked=0, Total=4290 [2022-11-03 03:00:56,330 INFO L413 NwaCegarLoop]: 100 mSDtfsCounter, 420 mSDsluCounter, 2932 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 420 SdHoareTripleChecker+Valid, 3032 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 102 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:00:56,330 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [420 Valid, 3032 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 18 Invalid, 0 Unknown, 102 Unchecked, 0.1s Time] [2022-11-03 03:00:56,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 808 states. [2022-11-03 03:00:56,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 808 to 798. [2022-11-03 03:00:56,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 798 states, 797 states have (on average 1.4077791718946047) internal successors, (1122), 797 states have internal predecessors, (1122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:56,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 798 states to 798 states and 1122 transitions. [2022-11-03 03:00:56,366 INFO L78 Accepts]: Start accepts. Automaton has 798 states and 1122 transitions. Word has length 94 [2022-11-03 03:00:56,366 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:00:56,366 INFO L495 AbstractCegarLoop]: Abstraction has 798 states and 1122 transitions. [2022-11-03 03:00:56,366 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:00:56,367 INFO L276 IsEmpty]: Start isEmpty. Operand 798 states and 1122 transitions. [2022-11-03 03:00:56,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:00:56,368 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:00:56,368 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:00:56,389 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (20)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:56,612 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:56,804 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-03 03:00:56,988 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:00:56,988 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:00:56,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:00:56,989 INFO L85 PathProgramCache]: Analyzing trace with hash 83598301, now seen corresponding path program 1 times [2022-11-03 03:00:56,990 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:00:56,990 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1055894186] [2022-11-03 03:00:56,990 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:00:56,990 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:00:56,990 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:00:56,991 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:00:56,994 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Waiting until timeout for monitored process [2022-11-03 03:00:57,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:00:57,683 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 30 conjunts are in the unsatisfiable core [2022-11-03 03:00:57,687 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:00:58,132 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:00:58,132 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:00,571 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:00,571 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:01:00,571 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1055894186] [2022-11-03 03:01:00,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1055894186] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:00,574 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [294694158] [2022-11-03 03:01:00,574 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:00,574 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:01:00,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:01:00,575 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:01:00,598 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (23)] Waiting until timeout for monitored process [2022-11-03 03:01:02,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:02,199 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 03:01:02,203 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:03,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:03,203 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:06,268 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:06,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [294694158] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:06,269 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1504808802] [2022-11-03 03:01:06,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:06,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:01:06,269 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:01:06,270 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:01:06,272 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2022-11-03 03:01:06,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:06,938 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 03:01:06,943 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:07,655 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:07,656 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:09,163 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:09,164 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1504808802] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:09,164 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:01:09,164 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 14, 14] total 40 [2022-11-03 03:01:09,164 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1767827823] [2022-11-03 03:01:09,164 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:01:09,165 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 40 states [2022-11-03 03:01:09,165 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:01:09,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-03 03:01:09,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=1392, Unknown=0, NotChecked=0, Total=1560 [2022-11-03 03:01:09,167 INFO L87 Difference]: Start difference. First operand 798 states and 1122 transitions. Second operand has 40 states, 40 states have (on average 9.15) internal successors, (366), 40 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:12,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:01:12,491 INFO L93 Difference]: Finished difference Result 1194 states and 1674 transitions. [2022-11-03 03:01:12,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-03 03:01:12,492 INFO L78 Accepts]: Start accepts. Automaton has has 40 states, 40 states have (on average 9.15) internal successors, (366), 40 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:01:12,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:01:12,496 INFO L225 Difference]: With dead ends: 1194 [2022-11-03 03:01:12,496 INFO L226 Difference]: Without dead ends: 1192 [2022-11-03 03:01:12,498 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 582 GetRequests, 520 SyntacticMatches, 3 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 782 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=680, Invalid=2980, Unknown=0, NotChecked=0, Total=3660 [2022-11-03 03:01:12,498 INFO L413 NwaCegarLoop]: 410 mSDtfsCounter, 698 mSDsluCounter, 6148 mSDsCounter, 0 mSdLazyCounter, 681 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 698 SdHoareTripleChecker+Valid, 6558 SdHoareTripleChecker+Invalid, 1563 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 681 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 873 IncrementalHoareTripleChecker+Unchecked, 1.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:01:12,499 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [698 Valid, 6558 Invalid, 1563 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 681 Invalid, 0 Unknown, 873 Unchecked, 1.5s Time] [2022-11-03 03:01:12,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1192 states. [2022-11-03 03:01:12,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1192 to 817. [2022-11-03 03:01:12,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 817 states, 816 states have (on average 1.4068627450980393) internal successors, (1148), 816 states have internal predecessors, (1148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:12,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 817 states to 817 states and 1148 transitions. [2022-11-03 03:01:12,527 INFO L78 Accepts]: Start accepts. Automaton has 817 states and 1148 transitions. Word has length 94 [2022-11-03 03:01:12,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:01:12,528 INFO L495 AbstractCegarLoop]: Abstraction has 817 states and 1148 transitions. [2022-11-03 03:01:12,528 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 40 states, 40 states have (on average 9.15) internal successors, (366), 40 states have internal predecessors, (366), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:12,528 INFO L276 IsEmpty]: Start isEmpty. Operand 817 states and 1148 transitions. [2022-11-03 03:01:12,529 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:01:12,529 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:01:12,530 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:01:12,567 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (22)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:12,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:12,961 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (23)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:13,150 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 03:01:13,150 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:01:13,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:01:13,151 INFO L85 PathProgramCache]: Analyzing trace with hash -596460069, now seen corresponding path program 1 times [2022-11-03 03:01:13,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:01:13,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1279890432] [2022-11-03 03:01:13,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:13,152 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:01:13,152 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:01:13,153 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:01:13,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Waiting until timeout for monitored process [2022-11-03 03:01:13,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:13,949 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 03:01:13,955 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:15,191 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:15,191 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:18,569 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:18,569 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:01:18,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1279890432] [2022-11-03 03:01:18,570 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1279890432] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:18,570 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [166564211] [2022-11-03 03:01:18,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:18,570 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:01:18,570 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:01:18,572 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:01:18,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (26)] Waiting until timeout for monitored process [2022-11-03 03:01:20,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:20,150 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 54 conjunts are in the unsatisfiable core [2022-11-03 03:01:20,155 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:21,222 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:21,223 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:26,833 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:26,834 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [166564211] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:26,834 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1864816523] [2022-11-03 03:01:26,834 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:26,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:01:26,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:01:26,835 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:01:26,837 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2022-11-03 03:01:27,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:27,493 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 03:01:27,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:29,171 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:29,171 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:33,574 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:33,574 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1864816523] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:33,575 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:01:33,575 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 9, 9, 14, 14] total 52 [2022-11-03 03:01:33,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844282283] [2022-11-03 03:01:33,575 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:01:33,576 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 52 states [2022-11-03 03:01:33,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:01:33,577 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2022-11-03 03:01:33,578 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=2390, Unknown=0, NotChecked=0, Total=2652 [2022-11-03 03:01:33,578 INFO L87 Difference]: Start difference. First operand 817 states and 1148 transitions. Second operand has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:35,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:01:35,031 INFO L93 Difference]: Finished difference Result 1307 states and 1838 transitions. [2022-11-03 03:01:35,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2022-11-03 03:01:35,037 INFO L78 Accepts]: Start accepts. Automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:01:35,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:01:35,041 INFO L225 Difference]: With dead ends: 1307 [2022-11-03 03:01:35,041 INFO L226 Difference]: Without dead ends: 1305 [2022-11-03 03:01:35,042 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 510 SyntacticMatches, 1 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1266 ImplicationChecksByTransitivity, 11.3s TimeCoverageRelationStatistics Valid=447, Invalid=3843, Unknown=0, NotChecked=0, Total=4290 [2022-11-03 03:01:35,043 INFO L413 NwaCegarLoop]: 110 mSDtfsCounter, 934 mSDsluCounter, 3342 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 934 SdHoareTripleChecker+Valid, 3452 SdHoareTripleChecker+Invalid, 190 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 159 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:01:35,043 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [934 Valid, 3452 Invalid, 190 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 30 Invalid, 0 Unknown, 159 Unchecked, 0.1s Time] [2022-11-03 03:01:35,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1305 states. [2022-11-03 03:01:35,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1305 to 1301. [2022-11-03 03:01:35,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1301 states, 1300 states have (on average 1.4092307692307693) internal successors, (1832), 1300 states have internal predecessors, (1832), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:35,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1832 transitions. [2022-11-03 03:01:35,083 INFO L78 Accepts]: Start accepts. Automaton has 1301 states and 1832 transitions. Word has length 94 [2022-11-03 03:01:35,083 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:01:35,083 INFO L495 AbstractCegarLoop]: Abstraction has 1301 states and 1832 transitions. [2022-11-03 03:01:35,084 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:35,084 INFO L276 IsEmpty]: Start isEmpty. Operand 1301 states and 1832 transitions. [2022-11-03 03:01:35,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-03 03:01:35,085 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:01:35,086 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:01:35,098 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (26)] Ended with exit code 0 [2022-11-03 03:01:35,324 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:35,515 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (25)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:35,698 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:01:35,698 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:01:35,699 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:01:35,699 INFO L85 PathProgramCache]: Analyzing trace with hash 691285211, now seen corresponding path program 1 times [2022-11-03 03:01:35,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:01:35,700 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [371244759] [2022-11-03 03:01:35,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:35,700 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:01:35,700 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:01:35,701 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:01:35,702 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (28)] Waiting until timeout for monitored process [2022-11-03 03:01:36,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:36,435 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 03:01:36,439 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:37,609 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:37,609 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:40,960 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:40,961 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:01:40,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [371244759] [2022-11-03 03:01:40,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [371244759] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:40,961 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1729811263] [2022-11-03 03:01:40,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:40,961 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:01:40,961 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:01:40,962 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:01:40,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (29)] Waiting until timeout for monitored process [2022-11-03 03:01:42,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:42,540 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 44 conjunts are in the unsatisfiable core [2022-11-03 03:01:42,545 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:43,681 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:43,681 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:48,053 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:48,053 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1729811263] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:48,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1153479368] [2022-11-03 03:01:48,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:48,053 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:01:48,054 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:01:48,055 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:01:48,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2022-11-03 03:01:48,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:48,714 INFO L263 TraceCheckSpWp]: Trace formula consists of 1696 conjuncts, 35 conjunts are in the unsatisfiable core [2022-11-03 03:01:48,719 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:50,254 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:50,255 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:01:54,555 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:01:54,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1153479368] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:01:54,556 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:01:54,556 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 9, 9, 14, 14] total 52 [2022-11-03 03:01:54,556 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748224465] [2022-11-03 03:01:54,556 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:01:54,557 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 52 states [2022-11-03 03:01:54,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:01:54,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2022-11-03 03:01:54,559 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=244, Invalid=2408, Unknown=0, NotChecked=0, Total=2652 [2022-11-03 03:01:54,559 INFO L87 Difference]: Start difference. First operand 1301 states and 1832 transitions. Second operand has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:55,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:01:55,916 INFO L93 Difference]: Finished difference Result 1797 states and 2532 transitions. [2022-11-03 03:01:55,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-03 03:01:55,917 INFO L78 Accepts]: Start accepts. Automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 94 [2022-11-03 03:01:55,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:01:55,921 INFO L225 Difference]: With dead ends: 1797 [2022-11-03 03:01:55,921 INFO L226 Difference]: Without dead ends: 1795 [2022-11-03 03:01:55,923 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 575 GetRequests, 510 SyntacticMatches, 1 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1181 ImplicationChecksByTransitivity, 10.1s TimeCoverageRelationStatistics Valid=416, Invalid=3874, Unknown=0, NotChecked=0, Total=4290 [2022-11-03 03:01:55,923 INFO L413 NwaCegarLoop]: 102 mSDtfsCounter, 683 mSDsluCounter, 2483 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 683 SdHoareTripleChecker+Valid, 2585 SdHoareTripleChecker+Invalid, 181 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 167 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:01:55,924 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [683 Valid, 2585 Invalid, 181 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 167 Unchecked, 0.1s Time] [2022-11-03 03:01:55,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1795 states. [2022-11-03 03:01:55,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1795 to 1163. [2022-11-03 03:01:55,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1163 states, 1162 states have (on average 1.4113597246127367) internal successors, (1640), 1162 states have internal predecessors, (1640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:55,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1163 states to 1163 states and 1640 transitions. [2022-11-03 03:01:55,970 INFO L78 Accepts]: Start accepts. Automaton has 1163 states and 1640 transitions. Word has length 94 [2022-11-03 03:01:55,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:01:55,970 INFO L495 AbstractCegarLoop]: Abstraction has 1163 states and 1640 transitions. [2022-11-03 03:01:55,971 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 52 states, 52 states have (on average 10.461538461538462) internal successors, (544), 52 states have internal predecessors, (544), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:01:55,971 INFO L276 IsEmpty]: Start isEmpty. Operand 1163 states and 1640 transitions. [2022-11-03 03:01:55,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 184 [2022-11-03 03:01:55,975 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:01:55,976 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:01:56,002 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (28)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:56,198 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (29)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:56,421 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Forceful destruction successful, exit code 0 [2022-11-03 03:01:56,591 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:01:56,591 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:01:56,591 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:01:56,591 INFO L85 PathProgramCache]: Analyzing trace with hash 1890299521, now seen corresponding path program 1 times [2022-11-03 03:01:56,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:01:56,594 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [786587443] [2022-11-03 03:01:56,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:01:56,594 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:01:56,594 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:01:56,595 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:01:56,596 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (31)] Waiting until timeout for monitored process [2022-11-03 03:01:57,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:01:57,904 INFO L263 TraceCheckSpWp]: Trace formula consists of 3141 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-03 03:01:57,911 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:01:59,851 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 51 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2022-11-03 03:01:59,851 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:02:01,824 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 51 proven. 15 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2022-11-03 03:02:01,824 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:02:01,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [786587443] [2022-11-03 03:02:01,825 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [786587443] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:02:01,825 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1152721815] [2022-11-03 03:02:01,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:02:01,825 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:02:01,826 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:02:01,827 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:02:01,837 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (32)] Waiting until timeout for monitored process [2022-11-03 03:02:04,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:02:04,379 INFO L263 TraceCheckSpWp]: Trace formula consists of 3141 conjuncts, 104 conjunts are in the unsatisfiable core [2022-11-03 03:02:04,393 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:02:13,672 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 90 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:02:13,673 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:02:43,759 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-03 03:02:43,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1152721815] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:02:43,760 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1253775178] [2022-11-03 03:02:43,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:02:43,760 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:02:43,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:02:43,761 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:02:43,785 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3b2319aa-246c-4e95-a744-325bcf725ef2/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2022-11-03 03:02:44,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:02:44,860 INFO L263 TraceCheckSpWp]: Trace formula consists of 3141 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 03:02:44,866 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:02:48,538 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 45 proven. 9 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2022-11-03 03:02:48,538 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:02:50,990 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 45 proven. 9 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2022-11-03 03:02:50,990 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1253775178] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:02:50,990 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:02:50,990 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 16, 16, 8, 8] total 51 [2022-11-03 03:02:50,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1747178413] [2022-11-03 03:02:50,991 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:02:50,991 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 51 states [2022-11-03 03:02:50,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:02:50,992 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2022-11-03 03:02:50,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=2360, Unknown=0, NotChecked=0, Total=2550 [2022-11-03 03:02:50,993 INFO L87 Difference]: Start difference. First operand 1163 states and 1640 transitions. Second operand has 51 states, 51 states have (on average 16.11764705882353) internal successors, (822), 51 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)