./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash e0b3b6b781ffc688dafba255fdda5ddb1bc0b2a1529746a3260ac898e37a723c --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 01:45:22,733 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 01:45:22,735 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 01:45:22,786 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 01:45:22,787 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 01:45:22,791 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 01:45:22,793 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 01:45:22,796 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 01:45:22,798 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 01:45:22,803 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 01:45:22,804 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 01:45:22,806 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 01:45:22,807 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 01:45:22,809 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 01:45:22,811 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 01:45:22,816 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 01:45:22,817 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 01:45:22,818 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 01:45:22,819 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 01:45:22,827 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 01:45:22,829 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 01:45:22,830 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 01:45:22,833 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 01:45:22,834 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 01:45:22,843 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 01:45:22,843 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 01:45:22,844 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 01:45:22,846 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 01:45:22,846 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 01:45:22,847 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 01:45:22,847 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 01:45:22,849 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 01:45:22,850 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 01:45:22,852 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 01:45:22,853 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 01:45:22,854 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 01:45:22,854 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 01:45:22,854 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 01:45:22,855 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 01:45:22,856 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 01:45:22,856 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 01:45:22,857 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 01:45:22,887 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 01:45:22,888 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 01:45:22,888 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 01:45:22,888 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 01:45:22,889 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 01:45:22,889 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 01:45:22,889 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 01:45:22,890 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 01:45:22,890 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 01:45:22,892 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 01:45:22,893 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 01:45:22,893 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 01:45:22,894 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 01:45:22,894 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 01:45:22,894 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 01:45:22,894 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 01:45:22,894 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 01:45:22,895 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 01:45:22,895 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 01:45:22,895 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 01:45:22,896 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 01:45:22,896 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 01:45:22,896 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 01:45:22,897 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 01:45:22,897 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 01:45:22,897 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 01:45:22,897 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 01:45:22,897 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 01:45:22,898 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 01:45:22,898 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 01:45:22,898 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 01:45:22,899 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 01:45:22,900 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 01:45:22,900 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0b3b6b781ffc688dafba255fdda5ddb1bc0b2a1529746a3260ac898e37a723c [2022-11-03 01:45:23,269 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 01:45:23,295 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 01:45:23,297 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 01:45:23,299 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 01:45:23,300 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 01:45:23,301 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:45:23,379 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/9d9c9927e/41625f9d54254514b17c2901e2882d9d/FLAG03ce7a7cb [2022-11-03 01:45:24,108 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 01:45:24,109 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:45:24,130 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/9d9c9927e/41625f9d54254514b17c2901e2882d9d/FLAG03ce7a7cb [2022-11-03 01:45:24,281 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/9d9c9927e/41625f9d54254514b17c2901e2882d9d [2022-11-03 01:45:24,283 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 01:45:24,285 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 01:45:24,287 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 01:45:24,287 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 01:45:24,291 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 01:45:24,292 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 01:45:24" (1/1) ... [2022-11-03 01:45:24,293 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@45e9d259 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:24, skipping insertion in model container [2022-11-03 01:45:24,294 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 01:45:24" (1/1) ... [2022-11-03 01:45:24,307 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 01:45:24,387 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 01:45:24,601 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c[1014,1027] [2022-11-03 01:45:25,056 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 01:45:25,072 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 01:45:25,085 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c[1014,1027] [2022-11-03 01:45:25,262 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 01:45:25,274 INFO L208 MainTranslator]: Completed translation [2022-11-03 01:45:25,275 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25 WrapperNode [2022-11-03 01:45:25,275 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 01:45:25,277 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 01:45:25,277 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 01:45:25,277 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 01:45:25,285 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,362 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,596 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1894 [2022-11-03 01:45:25,597 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 01:45:25,597 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 01:45:25,598 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 01:45:25,599 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 01:45:25,609 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,609 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,648 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,648 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,859 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,880 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,906 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,925 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,962 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 01:45:25,965 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 01:45:25,965 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 01:45:25,965 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 01:45:25,966 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (1/1) ... [2022-11-03 01:45:25,973 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 01:45:25,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:45:26,004 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 01:45:26,030 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 01:45:26,052 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 01:45:26,052 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 01:45:26,595 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 01:45:26,598 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 01:46:09,922 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 01:46:45,535 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 01:46:45,535 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 01:46:45,538 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 01:46:45 BoogieIcfgContainer [2022-11-03 01:46:45,538 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 01:46:45,541 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 01:46:45,541 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 01:46:45,545 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 01:46:45,546 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 01:45:24" (1/3) ... [2022-11-03 01:46:45,546 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@481f450f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 01:46:45, skipping insertion in model container [2022-11-03 01:46:45,547 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:45:25" (2/3) ... [2022-11-03 01:46:45,547 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@481f450f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 01:46:45, skipping insertion in model container [2022-11-03 01:46:45,547 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 01:46:45" (3/3) ... [2022-11-03 01:46:45,549 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:46:45,568 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 01:46:45,569 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 01:46:45,636 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 01:46:45,652 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@624a9e2e, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 01:46:45,660 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 01:46:45,665 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:46:45,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 01:46:45,674 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:46:45,675 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 01:46:45,676 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:46:45,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:46:45,684 INFO L85 PathProgramCache]: Analyzing trace with hash 9960222, now seen corresponding path program 1 times [2022-11-03 01:46:45,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 01:46:45,699 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954825545] [2022-11-03 01:46:45,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:46:45,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 01:46:46,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:46:52,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:46:52,886 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 01:46:52,887 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1954825545] [2022-11-03 01:46:52,888 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1954825545] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:46:52,888 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:46:52,889 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 01:46:52,891 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440055434] [2022-11-03 01:46:52,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:46:52,903 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 01:46:52,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 01:46:52,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 01:46:52,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 01:46:52,952 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:46:55,921 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.25s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 01:46:57,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:46:57,014 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 01:46:57,015 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:46:57,016 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 01:46:57,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:46:57,024 INFO L225 Difference]: With dead ends: 15 [2022-11-03 01:46:57,024 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 01:46:57,027 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:46:57,031 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 3.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 4.0s IncrementalHoareTripleChecker+Time [2022-11-03 01:46:57,032 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 1 Unknown, 0 Unchecked, 4.0s Time] [2022-11-03 01:46:57,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 01:46:57,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 01:46:57,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:46:57,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 01:46:57,076 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 01:46:57,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:46:57,076 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 01:46:57,077 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:46:57,077 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 01:46:57,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 01:46:57,078 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:46:57,078 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 01:46:57,078 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 01:46:57,088 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:46:57,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:46:57,089 INFO L85 PathProgramCache]: Analyzing trace with hash 389012539, now seen corresponding path program 1 times [2022-11-03 01:46:57,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 01:46:57,089 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615305355] [2022-11-03 01:46:57,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:46:57,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 01:51:17,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 01:51:17,270 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 01:56:01,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 01:56:01,346 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 01:56:01,346 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 01:56:01,349 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 01:56:01,351 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 01:56:01,356 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 01:56:01,360 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 01:56:01,499 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 01:56:01,500 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 01:56:01,642 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 01:56:01 BoogieIcfgContainer [2022-11-03 01:56:01,643 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 01:56:01,645 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 01:56:01,645 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 01:56:01,645 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 01:56:01,646 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 01:46:45" (3/4) ... [2022-11-03 01:56:01,650 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 01:56:01,650 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 01:56:01,653 INFO L158 Benchmark]: Toolchain (without parser) took 637366.25ms. Allocated memory was 123.7MB in the beginning and 4.9GB in the end (delta: 4.7GB). Free memory was 83.3MB in the beginning and 3.3GB in the end (delta: -3.3GB). Peak memory consumption was 1.5GB. Max. memory is 16.1GB. [2022-11-03 01:56:01,654 INFO L158 Benchmark]: CDTParser took 0.27ms. Allocated memory is still 123.7MB. Free memory is still 102.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 01:56:01,658 INFO L158 Benchmark]: CACSL2BoogieTranslator took 988.85ms. Allocated memory is still 123.7MB. Free memory was 83.1MB in the beginning and 52.5MB in the end (delta: 30.6MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2022-11-03 01:56:01,659 INFO L158 Benchmark]: Boogie Procedure Inliner took 320.10ms. Allocated memory is still 123.7MB. Free memory was 52.5MB in the beginning and 52.1MB in the end (delta: 366.6kB). Peak memory consumption was 17.7MB. Max. memory is 16.1GB. [2022-11-03 01:56:01,664 INFO L158 Benchmark]: Boogie Preprocessor took 366.03ms. Allocated memory is still 123.7MB. Free memory was 52.1MB in the beginning and 54.5MB in the end (delta: -2.4MB). Peak memory consumption was 39.1MB. Max. memory is 16.1GB. [2022-11-03 01:56:01,665 INFO L158 Benchmark]: RCFGBuilder took 79574.05ms. Allocated memory was 123.7MB in the beginning and 4.9GB in the end (delta: 4.7GB). Free memory was 54.5MB in the beginning and 2.9GB in the end (delta: -2.9GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2022-11-03 01:56:01,665 INFO L158 Benchmark]: TraceAbstraction took 556102.73ms. Allocated memory is still 4.9GB. Free memory was 2.9GB in the beginning and 3.3GB in the end (delta: -387.1MB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2022-11-03 01:56:01,665 INFO L158 Benchmark]: Witness Printer took 5.90ms. Allocated memory is still 4.9GB. Free memory is still 3.3GB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 01:56:01,674 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27ms. Allocated memory is still 123.7MB. Free memory is still 102.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 988.85ms. Allocated memory is still 123.7MB. Free memory was 83.1MB in the beginning and 52.5MB in the end (delta: 30.6MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 320.10ms. Allocated memory is still 123.7MB. Free memory was 52.5MB in the beginning and 52.1MB in the end (delta: 366.6kB). Peak memory consumption was 17.7MB. Max. memory is 16.1GB. * Boogie Preprocessor took 366.03ms. Allocated memory is still 123.7MB. Free memory was 52.1MB in the beginning and 54.5MB in the end (delta: -2.4MB). Peak memory consumption was 39.1MB. Max. memory is 16.1GB. * RCFGBuilder took 79574.05ms. Allocated memory was 123.7MB in the beginning and 4.9GB in the end (delta: 4.7GB). Free memory was 54.5MB in the beginning and 2.9GB in the end (delta: -2.9GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. * TraceAbstraction took 556102.73ms. Allocated memory is still 4.9GB. Free memory was 2.9GB in the beginning and 3.3GB in the end (delta: -387.1MB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. * Witness Printer took 5.90ms. Allocated memory is still 4.9GB. Free memory is still 3.3GB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 405, overapproximation of shiftRight at line 409, overapproximation of bitwiseAnd at line 187, overapproximation of bitwiseComplement at line 273. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 5); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (5 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_3 var_5 = 0; [L38] const SORT_1 var_14 = 0; [L39] const SORT_3 var_78 = 0; [L40] const SORT_1 var_137 = 1; [L41] const SORT_4 var_140 = 1; [L42] const SORT_3 var_141 = 0; [L43] const SORT_4 var_143 = 16; [L44] const SORT_4 var_150 = 6200; [L45] const SORT_4 var_167 = 0; [L46] const SORT_3 var_168 = 1; [L47] const SORT_4 var_196 = 999; [L48] const SORT_4 var_198 = 5999; [L49] const SORT_4 var_206 = 1000; [L50] const SORT_4 var_219 = 5800; [L51] const SORT_4 var_234 = 5; [L52] const SORT_3 var_249 = 3; [L54] SORT_3 input_89; [L55] SORT_3 input_91; [L56] SORT_3 input_93; [L57] SORT_3 input_95; [L58] SORT_1 input_97; [L59] SORT_1 input_99; [L60] SORT_1 input_101; [L61] SORT_1 input_103; [L62] SORT_1 input_105; [L63] SORT_1 input_107; [L64] SORT_1 input_109; [L65] SORT_1 input_111; [L66] SORT_1 input_113; [L67] SORT_1 input_115; [L68] SORT_1 input_117; [L69] SORT_1 input_119; [L70] SORT_1 input_121; [L71] SORT_1 input_123; [L72] SORT_1 input_125; [L73] SORT_1 input_127; [L74] SORT_1 input_129; [L75] SORT_1 input_131; [L76] SORT_1 input_133; [L77] SORT_1 input_135; [L78] SORT_1 input_139; [L79] SORT_1 input_148; [L80] SORT_1 input_158; [L81] SORT_1 input_162; [L82] SORT_1 input_165; [L83] SORT_1 input_177; [L84] SORT_1 input_180; [L85] SORT_1 input_204; [L86] SORT_1 input_214; [L87] SORT_1 input_224; [L88] SORT_1 input_232; [L89] SORT_1 input_244; [L90] SORT_1 input_247; [L91] SORT_1 input_260; [L92] SORT_1 input_267; [L93] SORT_1 input_271; [L94] SORT_1 input_275; [L95] SORT_1 input_281; [L96] SORT_1 input_284; [L97] SORT_1 input_288; [L98] SORT_1 input_292; [L99] SORT_1 input_296; [L100] SORT_1 input_299; [L101] SORT_1 input_314; [L102] SORT_1 input_319; [L103] SORT_1 input_325; [L105] SORT_3 state_6 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L106] SORT_3 state_8 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L107] SORT_3 state_10 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L108] SORT_3 state_12 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L109] SORT_1 state_15 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L110] SORT_1 state_17 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L111] SORT_1 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L112] SORT_1 state_21 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L113] SORT_1 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L114] SORT_1 state_25 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L115] SORT_1 state_27 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L116] SORT_1 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L117] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L118] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L119] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L120] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L121] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L122] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L123] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L124] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L125] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L126] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L127] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L128] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L129] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L130] SORT_1 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L132] SORT_3 init_7_arg_1 = var_5; [L133] state_6 = init_7_arg_1 [L134] SORT_3 init_9_arg_1 = var_5; [L135] state_8 = init_9_arg_1 [L136] SORT_3 init_11_arg_1 = var_5; [L137] state_10 = init_11_arg_1 [L138] SORT_3 init_13_arg_1 = var_5; [L139] state_12 = init_13_arg_1 [L140] SORT_1 init_16_arg_1 = var_14; [L141] state_15 = init_16_arg_1 [L142] SORT_1 init_18_arg_1 = var_14; [L143] state_17 = init_18_arg_1 [L144] SORT_1 init_20_arg_1 = var_14; [L145] state_19 = init_20_arg_1 [L146] SORT_1 init_22_arg_1 = var_14; [L147] state_21 = init_22_arg_1 [L148] SORT_1 init_24_arg_1 = var_14; [L149] state_23 = init_24_arg_1 [L150] SORT_1 init_26_arg_1 = var_14; [L151] state_25 = init_26_arg_1 [L152] SORT_1 init_28_arg_1 = var_14; [L153] state_27 = init_28_arg_1 [L154] SORT_1 init_30_arg_1 = var_14; [L155] state_29 = init_30_arg_1 [L156] SORT_1 init_32_arg_1 = var_14; [L157] state_31 = init_32_arg_1 [L158] SORT_1 init_34_arg_1 = var_14; [L159] state_33 = init_34_arg_1 [L160] SORT_1 init_36_arg_1 = var_14; [L161] state_35 = init_36_arg_1 [L162] SORT_1 init_38_arg_1 = var_14; [L163] state_37 = init_38_arg_1 [L164] SORT_1 init_40_arg_1 = var_14; [L165] state_39 = init_40_arg_1 [L166] SORT_1 init_42_arg_1 = var_14; [L167] state_41 = init_42_arg_1 [L168] SORT_1 init_44_arg_1 = var_14; [L169] state_43 = init_44_arg_1 [L170] SORT_1 init_46_arg_1 = var_14; [L171] state_45 = init_46_arg_1 [L172] SORT_1 init_48_arg_1 = var_14; [L173] state_47 = init_48_arg_1 [L174] SORT_1 init_50_arg_1 = var_14; [L175] state_49 = init_50_arg_1 [L176] SORT_1 init_52_arg_1 = var_14; [L177] state_51 = init_52_arg_1 [L178] SORT_1 init_54_arg_1 = var_14; [L179] state_53 = init_54_arg_1 [L180] SORT_1 init_56_arg_1 = var_14; [L181] state_55 = init_56_arg_1 [L182] SORT_1 init_58_arg_1 = var_14; [L183] state_57 = init_58_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_16_arg_1=0, init_18_arg_1=0, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=31, mask_SORT_3=65535, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=16, msb_SORT_3=32768, msb_SORT_4=2147483648, state_10=0, state_12=0, state_15=0, state_17=0, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_57=0, state_6=0, state_8=0, var_137=1, var_14=0, var_140=1, var_141=0, var_143=16, var_150=6200, var_167=0, var_168=1, var_196=999, var_198=5999, var_206=1000, var_219=5800, var_234=5, var_249=3, var_5=0, var_78=0] [L186] input_89 = __VERIFIER_nondet_ushort() [L187] input_89 = input_89 & mask_SORT_3 [L188] input_91 = __VERIFIER_nondet_ushort() [L189] input_91 = input_91 & mask_SORT_3 [L190] input_93 = __VERIFIER_nondet_ushort() [L191] input_93 = input_93 & mask_SORT_3 [L192] input_95 = __VERIFIER_nondet_ushort() [L193] input_95 = input_95 & mask_SORT_3 [L194] input_97 = __VERIFIER_nondet_uchar() [L195] input_97 = input_97 & mask_SORT_1 [L196] input_99 = __VERIFIER_nondet_uchar() [L197] input_99 = input_99 & mask_SORT_1 [L198] input_101 = __VERIFIER_nondet_uchar() [L199] input_101 = input_101 & mask_SORT_1 [L200] input_103 = __VERIFIER_nondet_uchar() [L201] input_103 = input_103 & mask_SORT_1 [L202] input_105 = __VERIFIER_nondet_uchar() [L203] input_105 = input_105 & mask_SORT_1 [L204] input_107 = __VERIFIER_nondet_uchar() [L205] input_107 = input_107 & mask_SORT_1 [L206] input_109 = __VERIFIER_nondet_uchar() [L207] input_109 = input_109 & mask_SORT_1 [L208] input_111 = __VERIFIER_nondet_uchar() [L209] input_111 = input_111 & mask_SORT_1 [L210] input_113 = __VERIFIER_nondet_uchar() [L211] input_113 = input_113 & mask_SORT_1 [L212] input_115 = __VERIFIER_nondet_uchar() [L213] input_115 = input_115 & mask_SORT_1 [L214] input_117 = __VERIFIER_nondet_uchar() [L215] input_117 = input_117 & mask_SORT_1 [L216] input_119 = __VERIFIER_nondet_uchar() [L217] input_119 = input_119 & mask_SORT_1 [L218] input_121 = __VERIFIER_nondet_uchar() [L219] input_121 = input_121 & mask_SORT_1 [L220] input_123 = __VERIFIER_nondet_uchar() [L221] input_123 = input_123 & mask_SORT_1 [L222] input_125 = __VERIFIER_nondet_uchar() [L223] input_125 = input_125 & mask_SORT_1 [L224] input_127 = __VERIFIER_nondet_uchar() [L225] input_127 = input_127 & mask_SORT_1 [L226] input_129 = __VERIFIER_nondet_uchar() [L227] input_129 = input_129 & mask_SORT_1 [L228] input_131 = __VERIFIER_nondet_uchar() [L229] input_131 = input_131 & mask_SORT_1 [L230] input_133 = __VERIFIER_nondet_uchar() [L231] input_133 = input_133 & mask_SORT_1 [L232] input_135 = __VERIFIER_nondet_uchar() [L233] input_135 = input_135 & mask_SORT_1 [L234] input_139 = __VERIFIER_nondet_uchar() [L235] input_148 = __VERIFIER_nondet_uchar() [L236] input_148 = input_148 & mask_SORT_1 [L237] input_158 = __VERIFIER_nondet_uchar() [L238] input_158 = input_158 & mask_SORT_1 [L239] input_162 = __VERIFIER_nondet_uchar() [L240] input_162 = input_162 & mask_SORT_1 [L241] input_165 = __VERIFIER_nondet_uchar() [L242] input_177 = __VERIFIER_nondet_uchar() [L243] input_177 = input_177 & mask_SORT_1 [L244] input_180 = __VERIFIER_nondet_uchar() [L245] input_180 = input_180 & mask_SORT_1 [L246] input_204 = __VERIFIER_nondet_uchar() [L247] input_204 = input_204 & mask_SORT_1 [L248] input_214 = __VERIFIER_nondet_uchar() [L249] input_214 = input_214 & mask_SORT_1 [L250] input_224 = __VERIFIER_nondet_uchar() [L251] input_224 = input_224 & mask_SORT_1 [L252] input_232 = __VERIFIER_nondet_uchar() [L253] input_232 = input_232 & mask_SORT_1 [L254] input_244 = __VERIFIER_nondet_uchar() [L255] input_244 = input_244 & mask_SORT_1 [L256] input_247 = __VERIFIER_nondet_uchar() [L257] input_260 = __VERIFIER_nondet_uchar() [L258] input_267 = __VERIFIER_nondet_uchar() [L259] input_271 = __VERIFIER_nondet_uchar() [L260] input_275 = __VERIFIER_nondet_uchar() [L261] input_281 = __VERIFIER_nondet_uchar() [L262] input_284 = __VERIFIER_nondet_uchar() [L263] input_288 = __VERIFIER_nondet_uchar() [L264] input_292 = __VERIFIER_nondet_uchar() [L265] input_292 = input_292 & mask_SORT_1 [L266] input_296 = __VERIFIER_nondet_uchar() [L267] input_299 = __VERIFIER_nondet_uchar() [L268] input_314 = __VERIFIER_nondet_uchar() [L269] input_319 = __VERIFIER_nondet_uchar() [L270] input_325 = __VERIFIER_nondet_uchar() [L273] SORT_1 var_59_arg_0 = ~state_15; [L274] var_59_arg_0 = var_59_arg_0 & mask_SORT_1 [L275] SORT_1 var_59_arg_1 = ~state_17; [L276] var_59_arg_1 = var_59_arg_1 & mask_SORT_1 [L277] SORT_1 var_59 = var_59_arg_0 & var_59_arg_1; [L278] SORT_1 var_60_arg_0 = var_59; [L279] SORT_1 var_60_arg_1 = ~state_19; [L280] var_60_arg_1 = var_60_arg_1 & mask_SORT_1 [L281] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L282] SORT_1 var_61_arg_0 = var_60; [L283] SORT_1 var_61_arg_1 = state_21; [L284] SORT_1 var_61 = var_61_arg_0 & var_61_arg_1; [L285] SORT_1 var_62_arg_0 = var_61; [L286] SORT_1 var_62_arg_1 = ~state_23; [L287] var_62_arg_1 = var_62_arg_1 & mask_SORT_1 [L288] SORT_1 var_62 = var_62_arg_0 & var_62_arg_1; [L289] SORT_1 var_63_arg_0 = var_62; [L290] SORT_1 var_63_arg_1 = ~state_25; [L291] var_63_arg_1 = var_63_arg_1 & mask_SORT_1 [L292] SORT_1 var_63 = var_63_arg_0 & var_63_arg_1; [L293] SORT_1 var_64_arg_0 = var_63; [L294] SORT_1 var_64_arg_1 = ~state_27; [L295] var_64_arg_1 = var_64_arg_1 & mask_SORT_1 [L296] SORT_1 var_64 = var_64_arg_0 & var_64_arg_1; [L297] SORT_1 var_65_arg_0 = var_64; [L298] SORT_1 var_65_arg_1 = ~state_29; [L299] var_65_arg_1 = var_65_arg_1 & mask_SORT_1 [L300] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L301] SORT_1 var_66_arg_0 = var_65; [L302] SORT_1 var_66_arg_1 = ~state_31; [L303] var_66_arg_1 = var_66_arg_1 & mask_SORT_1 [L304] SORT_1 var_66 = var_66_arg_0 & var_66_arg_1; [L305] SORT_1 var_67_arg_0 = var_66; [L306] SORT_1 var_67_arg_1 = ~state_33; [L307] var_67_arg_1 = var_67_arg_1 & mask_SORT_1 [L308] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L309] SORT_1 var_68_arg_0 = var_67; [L310] SORT_1 var_68_arg_1 = ~state_35; [L311] var_68_arg_1 = var_68_arg_1 & mask_SORT_1 [L312] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L313] SORT_1 var_69_arg_0 = var_68; [L314] SORT_1 var_69_arg_1 = state_37; [L315] SORT_1 var_69 = var_69_arg_0 & var_69_arg_1; [L316] SORT_1 var_70_arg_0 = var_69; [L317] SORT_1 var_70_arg_1 = ~state_39; [L318] var_70_arg_1 = var_70_arg_1 & mask_SORT_1 [L319] SORT_1 var_70 = var_70_arg_0 & var_70_arg_1; [L320] SORT_1 var_71_arg_0 = var_70; [L321] SORT_1 var_71_arg_1 = ~state_41; [L322] var_71_arg_1 = var_71_arg_1 & mask_SORT_1 [L323] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L324] SORT_1 var_72_arg_0 = var_71; [L325] SORT_1 var_72_arg_1 = ~state_43; [L326] var_72_arg_1 = var_72_arg_1 & mask_SORT_1 [L327] SORT_1 var_72 = var_72_arg_0 & var_72_arg_1; [L328] SORT_1 var_73_arg_0 = var_72; [L329] SORT_1 var_73_arg_1 = ~state_45; [L330] var_73_arg_1 = var_73_arg_1 & mask_SORT_1 [L331] SORT_1 var_73 = var_73_arg_0 & var_73_arg_1; [L332] SORT_1 var_74_arg_0 = var_73; [L333] SORT_1 var_74_arg_1 = ~state_47; [L334] var_74_arg_1 = var_74_arg_1 & mask_SORT_1 [L335] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L336] SORT_1 var_75_arg_0 = var_74; [L337] SORT_1 var_75_arg_1 = ~state_49; [L338] var_75_arg_1 = var_75_arg_1 & mask_SORT_1 [L339] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L340] SORT_1 var_76_arg_0 = var_75; [L341] SORT_1 var_76_arg_1 = state_51; [L342] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L343] SORT_1 var_77_arg_0 = var_76; [L344] SORT_1 var_77_arg_1 = ~state_53; [L345] var_77_arg_1 = var_77_arg_1 & mask_SORT_1 [L346] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L347] SORT_3 var_79_arg_0 = var_78; [L348] SORT_3 var_79_arg_1 = state_6; [L349] SORT_1 var_79 = var_79_arg_0 == var_79_arg_1; [L350] SORT_1 var_80_arg_0 = var_77; [L351] SORT_1 var_80_arg_1 = var_79; [L352] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L353] SORT_3 var_81_arg_0 = var_78; [L354] SORT_3 var_81_arg_1 = state_8; [L355] SORT_1 var_81 = var_81_arg_0 == var_81_arg_1; [L356] SORT_1 var_82_arg_0 = var_80; [L357] SORT_1 var_82_arg_1 = var_81; [L358] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L359] SORT_3 var_83_arg_0 = var_78; [L360] SORT_3 var_83_arg_1 = state_10; [L361] SORT_1 var_83 = var_83_arg_0 == var_83_arg_1; [L362] SORT_1 var_84_arg_0 = var_82; [L363] SORT_1 var_84_arg_1 = var_83; [L364] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L365] SORT_3 var_85_arg_0 = var_78; [L366] SORT_3 var_85_arg_1 = state_12; [L367] SORT_1 var_85 = var_85_arg_0 == var_85_arg_1; [L368] SORT_1 var_86_arg_0 = var_84; [L369] SORT_1 var_86_arg_1 = var_85; [L370] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L371] SORT_1 var_87_arg_0 = state_57; [L372] SORT_1 var_87_arg_1 = var_86; [L373] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L374] var_87 = var_87 & mask_SORT_1 [L375] SORT_1 bad_88_arg_0 = var_87; [L376] CALL __VERIFIER_assert(!(bad_88_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L376] RET __VERIFIER_assert(!(bad_88_arg_0)) [L378] SORT_3 next_90_arg_1 = input_89; [L379] SORT_3 next_92_arg_1 = input_91; [L380] SORT_3 next_94_arg_1 = input_93; [L381] SORT_3 next_96_arg_1 = input_95; [L382] SORT_1 next_98_arg_1 = input_97; [L383] SORT_1 next_100_arg_1 = input_99; [L384] SORT_1 next_102_arg_1 = input_101; [L385] SORT_1 next_104_arg_1 = input_103; [L386] SORT_1 next_106_arg_1 = input_105; [L387] SORT_1 next_108_arg_1 = input_107; [L388] SORT_1 next_110_arg_1 = input_109; [L389] SORT_1 next_112_arg_1 = input_111; [L390] SORT_1 next_114_arg_1 = input_113; [L391] SORT_1 next_116_arg_1 = input_115; [L392] SORT_1 next_118_arg_1 = input_117; [L393] SORT_1 next_120_arg_1 = input_119; [L394] SORT_1 next_122_arg_1 = input_121; [L395] SORT_1 next_124_arg_1 = input_123; [L396] SORT_1 next_126_arg_1 = input_125; [L397] SORT_1 next_128_arg_1 = input_127; [L398] SORT_1 next_130_arg_1 = input_129; [L399] SORT_1 next_132_arg_1 = input_131; [L400] SORT_1 next_134_arg_1 = input_133; [L401] SORT_1 next_136_arg_1 = input_135; [L402] SORT_1 next_138_arg_1 = var_137; [L403] SORT_3 var_142_arg_0 = input_89; [L404] SORT_3 var_142_arg_1 = var_141; [L405] SORT_4 var_142 = ((SORT_4)var_142_arg_0 << 16) | var_142_arg_1; [L406] SORT_4 var_144_arg_0 = var_142; [L407] EXPR (var_144_arg_0 & msb_SORT_4) ? (var_144_arg_0 | ~mask_SORT_4) : (var_144_arg_0 & mask_SORT_4) [L407] var_144_arg_0 = (var_144_arg_0 & msb_SORT_4) ? (var_144_arg_0 | ~mask_SORT_4) : (var_144_arg_0 & mask_SORT_4) [L408] SORT_4 var_144_arg_1 = var_143; [L409] SORT_4 var_144 = (int)var_144_arg_0 >> var_144_arg_1; [L410] EXPR (var_144_arg_0 & msb_SORT_4) ? (var_144 | ~(mask_SORT_4 >> var_144_arg_1)) : var_144 [L410] var_144 = (var_144_arg_0 & msb_SORT_4) ? (var_144 | ~(mask_SORT_4 >> var_144_arg_1)) : var_144 [L411] var_144 = var_144 & mask_SORT_4 [L412] SORT_4 var_145_arg_0 = var_140; [L413] SORT_4 var_145_arg_1 = var_144; [L414] SORT_1 var_145 = var_145_arg_0 == var_145_arg_1; [L415] SORT_1 var_146_arg_0 = input_99; [L416] SORT_1 var_146_arg_1 = var_145; [L417] SORT_1 var_146 = var_146_arg_0 & var_146_arg_1; [L418] SORT_1 var_147_arg_0 = ~input_139; [L419] var_147_arg_0 = var_147_arg_0 & mask_SORT_1 [L420] SORT_1 var_147_arg_1 = var_146; [L421] SORT_1 var_147 = var_147_arg_0 | var_147_arg_1; [L422] SORT_1 var_149_arg_0 = input_97; [L423] SORT_1 var_149_arg_1 = input_139; [L424] SORT_1 var_149 = var_149_arg_0 | var_149_arg_1; [L425] SORT_3 var_151_arg_0 = input_91; [L426] SORT_3 var_151_arg_1 = var_141; [L427] SORT_4 var_151 = ((SORT_4)var_151_arg_0 << 16) | var_151_arg_1; [L428] SORT_4 var_152_arg_0 = var_151; [L429] EXPR (var_152_arg_0 & msb_SORT_4) ? (var_152_arg_0 | ~mask_SORT_4) : (var_152_arg_0 & mask_SORT_4) [L429] var_152_arg_0 = (var_152_arg_0 & msb_SORT_4) ? (var_152_arg_0 | ~mask_SORT_4) : (var_152_arg_0 & mask_SORT_4) [L430] SORT_4 var_152_arg_1 = var_143; [L431] SORT_4 var_152 = (int)var_152_arg_0 >> var_152_arg_1; [L432] EXPR (var_152_arg_0 & msb_SORT_4) ? (var_152 | ~(mask_SORT_4 >> var_152_arg_1)) : var_152 [L432] var_152 = (var_152_arg_0 & msb_SORT_4) ? (var_152 | ~(mask_SORT_4 >> var_152_arg_1)) : var_152 [L433] var_152 = var_152 & mask_SORT_4 [L434] SORT_4 var_153_arg_0 = var_150; [L435] SORT_4 var_153_arg_1 = var_152; [L436] SORT_1 var_153 = var_153_arg_0 <= var_153_arg_1; [L437] SORT_1 var_154_arg_0 = var_145; [L438] SORT_1 var_154_arg_1 = ~var_153; [L439] var_154_arg_1 = var_154_arg_1 & mask_SORT_1 [L440] SORT_1 var_154 = var_154_arg_0 & var_154_arg_1; [L441] SORT_1 var_155_arg_0 = var_149; [L442] SORT_1 var_155_arg_1 = var_154; [L443] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L444] SORT_1 var_156_arg_0 = ~input_148; [L445] var_156_arg_0 = var_156_arg_0 & mask_SORT_1 [L446] SORT_1 var_156_arg_1 = var_155; [L447] SORT_1 var_156 = var_156_arg_0 | var_156_arg_1; [L448] SORT_1 var_157_arg_0 = var_147; [L449] SORT_1 var_157_arg_1 = var_156; [L450] SORT_1 var_157 = var_157_arg_0 & var_157_arg_1; [L451] SORT_1 var_159_arg_0 = input_101; [L452] SORT_1 var_159_arg_1 = ~input_158; [L453] var_159_arg_1 = var_159_arg_1 & mask_SORT_1 [L454] SORT_1 var_159 = var_159_arg_0 | var_159_arg_1; [L455] SORT_1 var_160_arg_0 = var_157; [L456] SORT_1 var_160_arg_1 = var_159; [L457] SORT_1 var_160 = var_160_arg_0 & var_160_arg_1; [L458] SORT_1 var_161_arg_0 = var_149; [L459] SORT_1 var_161_arg_1 = input_158; [L460] SORT_1 var_161 = var_161_arg_0 | var_161_arg_1; [L461] SORT_1 var_163_arg_0 = var_161; [L462] SORT_1 var_163_arg_1 = ~input_162; [L463] var_163_arg_1 = var_163_arg_1 & mask_SORT_1 [L464] SORT_1 var_163 = var_163_arg_0 | var_163_arg_1; [L465] SORT_1 var_164_arg_0 = var_160; [L466] SORT_1 var_164_arg_1 = var_163; [L467] SORT_1 var_164 = var_164_arg_0 & var_164_arg_1; [L468] SORT_1 var_166_arg_0 = input_99; [L469] SORT_1 var_166_arg_1 = ~input_139; [L470] var_166_arg_1 = var_166_arg_1 & mask_SORT_1 [L471] SORT_1 var_166 = var_166_arg_0 & var_166_arg_1; [L472] SORT_1 var_169_arg_0 = input_158; [L473] SORT_3 var_169_arg_1 = var_168; [L474] SORT_3 var_169_arg_2 = input_89; [L475] EXPR var_169_arg_0 ? var_169_arg_1 : var_169_arg_2 [L475] SORT_3 var_169 = var_169_arg_0 ? var_169_arg_1 : var_169_arg_2; [L476] SORT_1 var_170_arg_0 = input_162; [L477] SORT_3 var_170_arg_1 = var_78; [L478] SORT_3 var_170_arg_2 = var_169; [L479] EXPR var_170_arg_0 ? var_170_arg_1 : var_170_arg_2 [L479] SORT_3 var_170 = var_170_arg_0 ? var_170_arg_1 : var_170_arg_2; [L480] SORT_3 var_171_arg_0 = var_170; [L481] SORT_3 var_171_arg_1 = var_141; [L482] SORT_4 var_171 = ((SORT_4)var_171_arg_0 << 16) | var_171_arg_1; [L483] SORT_4 var_172_arg_0 = var_171; [L484] EXPR (var_172_arg_0 & msb_SORT_4) ? (var_172_arg_0 | ~mask_SORT_4) : (var_172_arg_0 & mask_SORT_4) [L484] var_172_arg_0 = (var_172_arg_0 & msb_SORT_4) ? (var_172_arg_0 | ~mask_SORT_4) : (var_172_arg_0 & mask_SORT_4) [L485] SORT_4 var_172_arg_1 = var_143; [L486] SORT_4 var_172 = (int)var_172_arg_0 >> var_172_arg_1; [L487] EXPR (var_172_arg_0 & msb_SORT_4) ? (var_172 | ~(mask_SORT_4 >> var_172_arg_1)) : var_172 [L487] var_172 = (var_172_arg_0 & msb_SORT_4) ? (var_172 | ~(mask_SORT_4 >> var_172_arg_1)) : var_172 [L488] var_172 = var_172 & mask_SORT_4 [L489] SORT_4 var_173_arg_0 = var_167; [L490] SORT_4 var_173_arg_1 = var_172; [L491] SORT_1 var_173 = var_173_arg_0 == var_173_arg_1; [L492] SORT_1 var_174_arg_0 = var_166; [L493] SORT_1 var_174_arg_1 = var_173; [L494] SORT_1 var_174 = var_174_arg_0 & var_174_arg_1; [L495] SORT_1 var_175_arg_0 = ~input_165; [L496] var_175_arg_0 = var_175_arg_0 & mask_SORT_1 [L497] SORT_1 var_175_arg_1 = var_174; [L498] SORT_1 var_175 = var_175_arg_0 | var_175_arg_1; [L499] SORT_1 var_176_arg_0 = var_164; [L500] SORT_1 var_176_arg_1 = var_175; [L501] SORT_1 var_176 = var_176_arg_0 & var_176_arg_1; [L502] SORT_1 var_178_arg_0 = input_103; [L503] SORT_1 var_178_arg_1 = ~input_177; [L504] var_178_arg_1 = var_178_arg_1 & mask_SORT_1 [L505] SORT_1 var_178 = var_178_arg_0 | var_178_arg_1; [L506] SORT_1 var_179_arg_0 = var_176; [L507] SORT_1 var_179_arg_1 = var_178; [L508] SORT_1 var_179 = var_179_arg_0 & var_179_arg_1; [L509] SORT_4 var_181_arg_0 = var_140; [L510] SORT_4 var_181_arg_1 = var_152; [L511] SORT_4 var_181 = var_181_arg_0 + var_181_arg_1; [L512] SORT_4 var_182_arg_0 = var_181; [L513] SORT_3 var_182 = var_182_arg_0 >> 0; [L514] SORT_1 var_183_arg_0 = input_148; [L515] SORT_3 var_183_arg_1 = var_182; [L516] SORT_3 var_183_arg_2 = input_91; [L517] EXPR var_183_arg_0 ? var_183_arg_1 : var_183_arg_2 [L517] SORT_3 var_183 = var_183_arg_0 ? var_183_arg_1 : var_183_arg_2; [L518] SORT_3 var_184_arg_0 = var_183; [L519] SORT_3 var_184_arg_1 = var_141; [L520] SORT_4 var_184 = ((SORT_4)var_184_arg_0 << 16) | var_184_arg_1; [L521] SORT_4 var_185_arg_0 = var_184; [L522] EXPR (var_185_arg_0 & msb_SORT_4) ? (var_185_arg_0 | ~mask_SORT_4) : (var_185_arg_0 & mask_SORT_4) [L522] var_185_arg_0 = (var_185_arg_0 & msb_SORT_4) ? (var_185_arg_0 | ~mask_SORT_4) : (var_185_arg_0 & mask_SORT_4) [L523] SORT_4 var_185_arg_1 = var_143; [L524] SORT_4 var_185 = (int)var_185_arg_0 >> var_185_arg_1; [L525] EXPR (var_185_arg_0 & msb_SORT_4) ? (var_185 | ~(mask_SORT_4 >> var_185_arg_1)) : var_185 [L525] var_185 = (var_185_arg_0 & msb_SORT_4) ? (var_185 | ~(mask_SORT_4 >> var_185_arg_1)) : var_185 [L526] SORT_4 var_186_arg_0 = var_185; [L527] SORT_4 var_186_arg_1 = var_140; [L528] SORT_4 var_186 = var_186_arg_0 - var_186_arg_1; [L529] SORT_4 var_187_arg_0 = var_186; [L530] SORT_3 var_187 = var_187_arg_0 >> 0; [L531] SORT_1 var_188_arg_0 = input_158; [L532] SORT_3 var_188_arg_1 = var_187; [L533] SORT_3 var_188_arg_2 = var_183; [L534] EXPR var_188_arg_0 ? var_188_arg_1 : var_188_arg_2 [L534] SORT_3 var_188 = var_188_arg_0 ? var_188_arg_1 : var_188_arg_2; [L535] SORT_3 var_189_arg_0 = var_188; [L536] SORT_3 var_189_arg_1 = var_141; [L537] SORT_4 var_189 = ((SORT_4)var_189_arg_0 << 16) | var_189_arg_1; [L538] SORT_4 var_190_arg_0 = var_189; [L539] EXPR (var_190_arg_0 & msb_SORT_4) ? (var_190_arg_0 | ~mask_SORT_4) : (var_190_arg_0 & mask_SORT_4) [L539] var_190_arg_0 = (var_190_arg_0 & msb_SORT_4) ? (var_190_arg_0 | ~mask_SORT_4) : (var_190_arg_0 & mask_SORT_4) [L540] SORT_4 var_190_arg_1 = var_143; [L541] SORT_4 var_190 = (int)var_190_arg_0 >> var_190_arg_1; [L542] EXPR (var_190_arg_0 & msb_SORT_4) ? (var_190 | ~(mask_SORT_4 >> var_190_arg_1)) : var_190 [L542] var_190 = (var_190_arg_0 & msb_SORT_4) ? (var_190 | ~(mask_SORT_4 >> var_190_arg_1)) : var_190 [L543] SORT_4 var_191_arg_0 = var_190; [L544] SORT_4 var_191_arg_1 = var_140; [L545] SORT_4 var_191 = var_191_arg_0 - var_191_arg_1; [L546] SORT_4 var_192_arg_0 = var_191; [L547] SORT_3 var_192 = var_192_arg_0 >> 0; [L548] SORT_1 var_193_arg_0 = input_162; [L549] SORT_3 var_193_arg_1 = var_192; [L550] SORT_3 var_193_arg_2 = var_188; [L551] EXPR var_193_arg_0 ? var_193_arg_1 : var_193_arg_2 [L551] SORT_3 var_193 = var_193_arg_0 ? var_193_arg_1 : var_193_arg_2; [L552] SORT_3 var_194_arg_0 = var_193; [L553] SORT_3 var_194_arg_1 = var_141; [L554] SORT_4 var_194 = ((SORT_4)var_194_arg_0 << 16) | var_194_arg_1; [L555] SORT_4 var_195_arg_0 = var_194; [L556] EXPR (var_195_arg_0 & msb_SORT_4) ? (var_195_arg_0 | ~mask_SORT_4) : (var_195_arg_0 & mask_SORT_4) [L556] var_195_arg_0 = (var_195_arg_0 & msb_SORT_4) ? (var_195_arg_0 | ~mask_SORT_4) : (var_195_arg_0 & mask_SORT_4) [L557] SORT_4 var_195_arg_1 = var_143; [L558] SORT_4 var_195 = (int)var_195_arg_0 >> var_195_arg_1; [L559] EXPR (var_195_arg_0 & msb_SORT_4) ? (var_195 | ~(mask_SORT_4 >> var_195_arg_1)) : var_195 [L559] var_195 = (var_195_arg_0 & msb_SORT_4) ? (var_195 | ~(mask_SORT_4 >> var_195_arg_1)) : var_195 [L560] var_195 = var_195 & mask_SORT_4 [L561] SORT_4 var_197_arg_0 = var_195; [L562] SORT_4 var_197_arg_1 = var_196; [L563] SORT_1 var_197 = var_197_arg_0 <= var_197_arg_1; [L564] SORT_4 var_199_arg_0 = var_198; [L565] SORT_4 var_199_arg_1 = var_195; [L566] SORT_1 var_199 = var_199_arg_0 <= var_199_arg_1; [L567] SORT_1 var_200_arg_0 = ~var_197; [L568] var_200_arg_0 = var_200_arg_0 & mask_SORT_1 [L569] SORT_1 var_200_arg_1 = ~var_199; [L570] var_200_arg_1 = var_200_arg_1 & mask_SORT_1 [L571] SORT_1 var_200 = var_200_arg_0 & var_200_arg_1; [L572] SORT_1 var_201_arg_0 = input_105; [L573] SORT_1 var_201_arg_1 = var_200; [L574] SORT_1 var_201 = var_201_arg_0 & var_201_arg_1; [L575] SORT_1 var_202_arg_0 = ~input_180; [L576] var_202_arg_0 = var_202_arg_0 & mask_SORT_1 [L577] SORT_1 var_202_arg_1 = var_201; [L578] SORT_1 var_202 = var_202_arg_0 | var_202_arg_1; [L579] SORT_1 var_203_arg_0 = var_179; [L580] SORT_1 var_203_arg_1 = var_202; [L581] SORT_1 var_203 = var_203_arg_0 & var_203_arg_1; [L582] SORT_1 var_205_arg_0 = input_105; [L583] SORT_1 var_205_arg_1 = ~input_180; [L584] var_205_arg_1 = var_205_arg_1 & mask_SORT_1 [L585] SORT_1 var_205 = var_205_arg_0 & var_205_arg_1; [L586] SORT_1 var_207_arg_0 = input_180; [L587] SORT_3 var_207_arg_1 = var_78; [L588] SORT_3 var_207_arg_2 = var_193; [L589] EXPR var_207_arg_0 ? var_207_arg_1 : var_207_arg_2 [L589] SORT_3 var_207 = var_207_arg_0 ? var_207_arg_1 : var_207_arg_2; [L590] SORT_3 var_208_arg_0 = var_207; [L591] SORT_3 var_208_arg_1 = var_141; [L592] SORT_4 var_208 = ((SORT_4)var_208_arg_0 << 16) | var_208_arg_1; [L593] SORT_4 var_209_arg_0 = var_208; [L594] EXPR (var_209_arg_0 & msb_SORT_4) ? (var_209_arg_0 | ~mask_SORT_4) : (var_209_arg_0 & mask_SORT_4) [L594] var_209_arg_0 = (var_209_arg_0 & msb_SORT_4) ? (var_209_arg_0 | ~mask_SORT_4) : (var_209_arg_0 & mask_SORT_4) [L595] SORT_4 var_209_arg_1 = var_143; [L596] SORT_4 var_209 = (int)var_209_arg_0 >> var_209_arg_1; [L597] EXPR (var_209_arg_0 & msb_SORT_4) ? (var_209 | ~(mask_SORT_4 >> var_209_arg_1)) : var_209 [L597] var_209 = (var_209_arg_0 & msb_SORT_4) ? (var_209 | ~(mask_SORT_4 >> var_209_arg_1)) : var_209 [L598] var_209 = var_209 & mask_SORT_4 [L599] SORT_4 var_210_arg_0 = var_206; [L600] SORT_4 var_210_arg_1 = var_209; [L601] SORT_1 var_210 = var_210_arg_0 <= var_210_arg_1; [L602] SORT_1 var_211_arg_0 = var_205; [L603] SORT_1 var_211_arg_1 = ~var_210; [L604] var_211_arg_1 = var_211_arg_1 & mask_SORT_1 [L605] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L606] SORT_1 var_212_arg_0 = ~input_204; [L607] var_212_arg_0 = var_212_arg_0 & mask_SORT_1 [L608] SORT_1 var_212_arg_1 = var_211; [L609] SORT_1 var_212 = var_212_arg_0 | var_212_arg_1; [L610] SORT_1 var_213_arg_0 = var_203; [L611] SORT_1 var_213_arg_1 = var_212; [L612] SORT_1 var_213 = var_213_arg_0 & var_213_arg_1; [L613] SORT_1 var_215_arg_0 = var_205; [L614] SORT_1 var_215_arg_1 = ~input_204; [L615] var_215_arg_1 = var_215_arg_1 & mask_SORT_1 [L616] SORT_1 var_215 = var_215_arg_0 & var_215_arg_1; [L617] SORT_1 var_216_arg_0 = input_204; [L618] SORT_3 var_216_arg_1 = var_78; [L619] SORT_3 var_216_arg_2 = var_207; [L620] EXPR var_216_arg_0 ? var_216_arg_1 : var_216_arg_2 [L620] SORT_3 var_216 = var_216_arg_0 ? var_216_arg_1 : var_216_arg_2; [L621] SORT_3 var_217_arg_0 = var_216; [L622] SORT_3 var_217_arg_1 = var_141; [L623] SORT_4 var_217 = ((SORT_4)var_217_arg_0 << 16) | var_217_arg_1; [L624] SORT_4 var_218_arg_0 = var_217; [L625] EXPR (var_218_arg_0 & msb_SORT_4) ? (var_218_arg_0 | ~mask_SORT_4) : (var_218_arg_0 & mask_SORT_4) [L625] var_218_arg_0 = (var_218_arg_0 & msb_SORT_4) ? (var_218_arg_0 | ~mask_SORT_4) : (var_218_arg_0 & mask_SORT_4) [L626] SORT_4 var_218_arg_1 = var_143; [L627] SORT_4 var_218 = (int)var_218_arg_0 >> var_218_arg_1; [L628] EXPR (var_218_arg_0 & msb_SORT_4) ? (var_218 | ~(mask_SORT_4 >> var_218_arg_1)) : var_218 [L628] var_218 = (var_218_arg_0 & msb_SORT_4) ? (var_218 | ~(mask_SORT_4 >> var_218_arg_1)) : var_218 [L629] var_218 = var_218 & mask_SORT_4 [L630] SORT_4 var_220_arg_0 = var_218; [L631] SORT_4 var_220_arg_1 = var_219; [L632] SORT_1 var_220 = var_220_arg_0 <= var_220_arg_1; [L633] SORT_1 var_221_arg_0 = var_215; [L634] SORT_1 var_221_arg_1 = ~var_220; [L635] var_221_arg_1 = var_221_arg_1 & mask_SORT_1 [L636] SORT_1 var_221 = var_221_arg_0 & var_221_arg_1; [L637] SORT_1 var_222_arg_0 = ~input_214; [L638] var_222_arg_0 = var_222_arg_0 & mask_SORT_1 [L639] SORT_1 var_222_arg_1 = var_221; [L640] SORT_1 var_222 = var_222_arg_0 | var_222_arg_1; [L641] SORT_1 var_223_arg_0 = var_213; [L642] SORT_1 var_223_arg_1 = var_222; [L643] SORT_1 var_223 = var_223_arg_0 & var_223_arg_1; [L644] SORT_1 var_225_arg_0 = input_109; [L645] SORT_1 var_225_arg_1 = input_204; [L646] SORT_1 var_225 = var_225_arg_0 | var_225_arg_1; [L647] SORT_3 var_226_arg_0 = input_95; [L648] SORT_3 var_226_arg_1 = var_141; [L649] SORT_4 var_226 = ((SORT_4)var_226_arg_0 << 16) | var_226_arg_1; [L650] SORT_4 var_227_arg_0 = var_226; [L651] EXPR (var_227_arg_0 & msb_SORT_4) ? (var_227_arg_0 | ~mask_SORT_4) : (var_227_arg_0 & mask_SORT_4) [L651] var_227_arg_0 = (var_227_arg_0 & msb_SORT_4) ? (var_227_arg_0 | ~mask_SORT_4) : (var_227_arg_0 & mask_SORT_4) [L652] SORT_4 var_227_arg_1 = var_143; [L653] SORT_4 var_227 = (int)var_227_arg_0 >> var_227_arg_1; [L654] EXPR (var_227_arg_0 & msb_SORT_4) ? (var_227 | ~(mask_SORT_4 >> var_227_arg_1)) : var_227 [L654] var_227 = (var_227_arg_0 & msb_SORT_4) ? (var_227 | ~(mask_SORT_4 >> var_227_arg_1)) : var_227 [L655] var_227 = var_227 & mask_SORT_4 [L656] SORT_4 var_228_arg_0 = var_227; [L657] SORT_4 var_228_arg_1 = var_167; [L658] SORT_1 var_228 = var_228_arg_0 <= var_228_arg_1; [L659] SORT_1 var_229_arg_0 = var_225; [L660] SORT_1 var_229_arg_1 = ~var_228; [L661] var_229_arg_1 = var_229_arg_1 & mask_SORT_1 [L662] SORT_1 var_229 = var_229_arg_0 & var_229_arg_1; [L663] SORT_1 var_230_arg_0 = ~input_224; [L664] var_230_arg_0 = var_230_arg_0 & mask_SORT_1 [L665] SORT_1 var_230_arg_1 = var_229; [L666] SORT_1 var_230 = var_230_arg_0 | var_230_arg_1; [L667] SORT_1 var_231_arg_0 = var_223; [L668] SORT_1 var_231_arg_1 = var_230; [L669] SORT_1 var_231 = var_231_arg_0 & var_231_arg_1; [L670] SORT_1 var_233_arg_0 = input_113; [L671] SORT_1 var_233_arg_1 = input_214; [L672] SORT_1 var_233 = var_233_arg_0 | var_233_arg_1; [L673] SORT_4 var_235_arg_0 = var_227; [L674] SORT_4 var_235_arg_1 = var_140; [L675] SORT_4 var_235 = var_235_arg_0 - var_235_arg_1; [L676] SORT_4 var_236_arg_0 = var_235; [L677] SORT_3 var_236 = var_236_arg_0 >> 0; [L678] SORT_1 var_237_arg_0 = input_224; [L679] SORT_3 var_237_arg_1 = var_236; [L680] SORT_3 var_237_arg_2 = input_95; [L681] EXPR var_237_arg_0 ? var_237_arg_1 : var_237_arg_2 [L681] SORT_3 var_237 = var_237_arg_0 ? var_237_arg_1 : var_237_arg_2; [L682] SORT_3 var_238_arg_0 = var_237; [L683] SORT_3 var_238_arg_1 = var_141; [L684] SORT_4 var_238 = ((SORT_4)var_238_arg_0 << 16) | var_238_arg_1; [L685] SORT_4 var_239_arg_0 = var_238; [L686] EXPR (var_239_arg_0 & msb_SORT_4) ? (var_239_arg_0 | ~mask_SORT_4) : (var_239_arg_0 & mask_SORT_4) [L686] var_239_arg_0 = (var_239_arg_0 & msb_SORT_4) ? (var_239_arg_0 | ~mask_SORT_4) : (var_239_arg_0 & mask_SORT_4) [L687] SORT_4 var_239_arg_1 = var_143; [L688] SORT_4 var_239 = (int)var_239_arg_0 >> var_239_arg_1; [L689] EXPR (var_239_arg_0 & msb_SORT_4) ? (var_239 | ~(mask_SORT_4 >> var_239_arg_1)) : var_239 [L689] var_239 = (var_239_arg_0 & msb_SORT_4) ? (var_239 | ~(mask_SORT_4 >> var_239_arg_1)) : var_239 [L690] var_239 = var_239 & mask_SORT_4 [L691] SORT_4 var_240_arg_0 = var_234; [L692] SORT_4 var_240_arg_1 = var_239; [L693] SORT_1 var_240 = var_240_arg_0 <= var_240_arg_1; [L694] SORT_1 var_241_arg_0 = var_233; [L695] SORT_1 var_241_arg_1 = ~var_240; [L696] var_241_arg_1 = var_241_arg_1 & mask_SORT_1 [L697] SORT_1 var_241 = var_241_arg_0 & var_241_arg_1; [L698] SORT_1 var_242_arg_0 = ~input_232; [L699] var_242_arg_0 = var_242_arg_0 & mask_SORT_1 [L700] SORT_1 var_242_arg_1 = var_241; [L701] SORT_1 var_242 = var_242_arg_0 | var_242_arg_1; [L702] SORT_1 var_243_arg_0 = var_231; [L703] SORT_1 var_243_arg_1 = var_242; [L704] SORT_1 var_243 = var_243_arg_0 & var_243_arg_1; [L705] SORT_1 var_245_arg_0 = input_119; [L706] SORT_1 var_245_arg_1 = ~input_244; [L707] var_245_arg_1 = var_245_arg_1 & mask_SORT_1 [L708] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L709] SORT_1 var_246_arg_0 = var_243; [L710] SORT_1 var_246_arg_1 = var_245; [L711] SORT_1 var_246 = var_246_arg_0 & var_246_arg_1; [L712] SORT_1 var_248_arg_0 = var_225; [L713] SORT_1 var_248_arg_1 = ~input_224; [L714] var_248_arg_1 = var_248_arg_1 & mask_SORT_1 [L715] SORT_1 var_248 = var_248_arg_0 & var_248_arg_1; [L716] SORT_4 var_250_arg_0 = var_140; [L717] SORT_4 var_250_arg_1 = var_239; [L718] SORT_4 var_250 = var_250_arg_0 + var_250_arg_1; [L719] SORT_4 var_251_arg_0 = var_250; [L720] SORT_3 var_251 = var_251_arg_0 >> 0; [L721] SORT_1 var_252_arg_0 = input_232; [L722] SORT_3 var_252_arg_1 = var_251; [L723] SORT_3 var_252_arg_2 = var_237; [L724] EXPR var_252_arg_0 ? var_252_arg_1 : var_252_arg_2 [L724] SORT_3 var_252 = var_252_arg_0 ? var_252_arg_1 : var_252_arg_2; [L725] SORT_1 var_253_arg_0 = input_244; [L726] SORT_3 var_253_arg_1 = var_249; [L727] SORT_3 var_253_arg_2 = var_252; [L728] EXPR var_253_arg_0 ? var_253_arg_1 : var_253_arg_2 [L728] SORT_3 var_253 = var_253_arg_0 ? var_253_arg_1 : var_253_arg_2; [L729] var_253 = var_253 & mask_SORT_3 [L730] SORT_3 var_254_arg_0 = var_253; [L731] SORT_3 var_254_arg_1 = var_141; [L732] SORT_4 var_254 = ((SORT_4)var_254_arg_0 << 16) | var_254_arg_1; [L733] SORT_4 var_255_arg_0 = var_254; [L734] EXPR (var_255_arg_0 & msb_SORT_4) ? (var_255_arg_0 | ~mask_SORT_4) : (var_255_arg_0 & mask_SORT_4) [L734] var_255_arg_0 = (var_255_arg_0 & msb_SORT_4) ? (var_255_arg_0 | ~mask_SORT_4) : (var_255_arg_0 & mask_SORT_4) [L735] SORT_4 var_255_arg_1 = var_143; [L736] SORT_4 var_255 = (int)var_255_arg_0 >> var_255_arg_1; [L737] EXPR (var_255_arg_0 & msb_SORT_4) ? (var_255 | ~(mask_SORT_4 >> var_255_arg_1)) : var_255 [L737] var_255 = (var_255_arg_0 & msb_SORT_4) ? (var_255 | ~(mask_SORT_4 >> var_255_arg_1)) : var_255 [L738] var_255 = var_255 & mask_SORT_4 [L739] SORT_4 var_256_arg_0 = var_167; [L740] SORT_4 var_256_arg_1 = var_255; [L741] SORT_1 var_256 = var_256_arg_0 == var_256_arg_1; [L742] SORT_1 var_257_arg_0 = var_248; [L743] SORT_1 var_257_arg_1 = var_256; [L744] SORT_1 var_257 = var_257_arg_0 & var_257_arg_1; [L745] SORT_1 var_258_arg_0 = ~input_247; [L746] var_258_arg_0 = var_258_arg_0 & mask_SORT_1 [L747] SORT_1 var_258_arg_1 = var_257; [L748] SORT_1 var_258 = var_258_arg_0 | var_258_arg_1; [L749] SORT_1 var_259_arg_0 = var_246; [L750] SORT_1 var_259_arg_1 = var_258; [L751] SORT_1 var_259 = var_259_arg_0 & var_259_arg_1; [L752] SORT_1 var_261_arg_0 = var_233; [L753] SORT_1 var_261_arg_1 = ~input_232; [L754] var_261_arg_1 = var_261_arg_1 & mask_SORT_1 [L755] SORT_1 var_261 = var_261_arg_0 & var_261_arg_1; [L756] SORT_4 var_262_arg_0 = var_234; [L757] SORT_4 var_262_arg_1 = var_255; [L758] SORT_1 var_262 = var_262_arg_0 == var_262_arg_1; [L759] SORT_1 var_263_arg_0 = var_261; [L760] SORT_1 var_263_arg_1 = var_262; [L761] SORT_1 var_263 = var_263_arg_0 & var_263_arg_1; [L762] SORT_1 var_264_arg_0 = ~input_260; [L763] var_264_arg_0 = var_264_arg_0 & mask_SORT_1 [L764] SORT_1 var_264_arg_1 = var_263; [L765] SORT_1 var_264 = var_264_arg_0 | var_264_arg_1; [L766] SORT_1 var_265_arg_0 = var_259; [L767] SORT_1 var_265_arg_1 = var_264; [L768] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L769] SORT_1 var_266_arg_0 = input_115; [L770] SORT_1 var_266_arg_1 = input_247; [L771] SORT_1 var_266 = var_266_arg_0 | var_266_arg_1; [L772] SORT_1 var_268_arg_0 = var_266; [L773] SORT_1 var_268_arg_1 = ~input_267; [L774] var_268_arg_1 = var_268_arg_1 & mask_SORT_1 [L775] SORT_1 var_268 = var_268_arg_0 | var_268_arg_1; [L776] SORT_1 var_269_arg_0 = var_265; [L777] SORT_1 var_269_arg_1 = var_268; [L778] SORT_1 var_269 = var_269_arg_0 & var_269_arg_1; [L779] SORT_1 var_270_arg_0 = input_117; [L780] SORT_1 var_270_arg_1 = input_260; [L781] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L782] SORT_1 var_272_arg_0 = var_270; [L783] SORT_1 var_272_arg_1 = ~input_271; [L784] var_272_arg_1 = var_272_arg_1 & mask_SORT_1 [L785] SORT_1 var_272 = var_272_arg_0 | var_272_arg_1; [L786] SORT_1 var_273_arg_0 = var_269; [L787] SORT_1 var_273_arg_1 = var_272; [L788] SORT_1 var_273 = var_273_arg_0 & var_273_arg_1; [L789] SORT_1 var_274_arg_0 = input_111; [L790] SORT_1 var_274_arg_1 = input_180; [L791] SORT_1 var_274 = var_274_arg_0 | var_274_arg_1; [L792] SORT_1 var_276_arg_0 = var_274; [L793] SORT_1 var_276_arg_1 = ~input_275; [L794] var_276_arg_1 = var_276_arg_1 & mask_SORT_1 [L795] SORT_1 var_276 = var_276_arg_0 | var_276_arg_1; [L796] SORT_1 var_277_arg_0 = var_273; [L797] SORT_1 var_277_arg_1 = var_276; [L798] SORT_1 var_277 = var_277_arg_0 & var_277_arg_1; [L799] SORT_1 var_278_arg_0 = input_121; [L800] SORT_1 var_278_arg_1 = input_267; [L801] SORT_1 var_278 = var_278_arg_0 | var_278_arg_1; [L802] SORT_1 var_279_arg_0 = var_278; [L803] SORT_1 var_279_arg_1 = input_271; [L804] SORT_1 var_279 = var_279_arg_0 | var_279_arg_1; [L805] SORT_1 var_280_arg_0 = var_279; [L806] SORT_1 var_280_arg_1 = input_275; [L807] SORT_1 var_280 = var_280_arg_0 | var_280_arg_1; [L808] SORT_1 var_282_arg_0 = var_280; [L809] SORT_1 var_282_arg_1 = ~input_281; [L810] var_282_arg_1 = var_282_arg_1 & mask_SORT_1 [L811] SORT_1 var_282 = var_282_arg_0 | var_282_arg_1; [L812] SORT_1 var_283_arg_0 = var_277; [L813] SORT_1 var_283_arg_1 = var_282; [L814] SORT_1 var_283 = var_283_arg_0 & var_283_arg_1; [L815] SORT_1 var_285_arg_0 = input_127; [L816] SORT_1 var_285_arg_1 = ~input_284; [L817] var_285_arg_1 = var_285_arg_1 & mask_SORT_1 [L818] SORT_1 var_285 = var_285_arg_0 | var_285_arg_1; [L819] SORT_1 var_286_arg_0 = var_283; [L820] SORT_1 var_286_arg_1 = var_285; [L821] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L822] SORT_1 var_287_arg_0 = input_127; [L823] SORT_1 var_287_arg_1 = ~input_284; [L824] var_287_arg_1 = var_287_arg_1 & mask_SORT_1 [L825] SORT_1 var_287 = var_287_arg_0 & var_287_arg_1; [L826] SORT_1 var_289_arg_0 = var_287; [L827] SORT_1 var_289_arg_1 = ~input_288; [L828] var_289_arg_1 = var_289_arg_1 & mask_SORT_1 [L829] SORT_1 var_289 = var_289_arg_0 | var_289_arg_1; [L830] SORT_1 var_290_arg_0 = var_286; [L831] SORT_1 var_290_arg_1 = var_289; [L832] SORT_1 var_290 = var_290_arg_0 & var_290_arg_1; [L833] SORT_1 var_291_arg_0 = input_129; [L834] SORT_1 var_291_arg_1 = input_284; [L835] SORT_1 var_291 = var_291_arg_0 | var_291_arg_1; [L836] SORT_1 var_293_arg_0 = var_291; [L837] SORT_1 var_293_arg_1 = ~input_292; [L838] var_293_arg_1 = var_293_arg_1 & mask_SORT_1 [L839] SORT_1 var_293 = var_293_arg_0 | var_293_arg_1; [L840] SORT_1 var_294_arg_0 = var_290; [L841] SORT_1 var_294_arg_1 = var_293; [L842] SORT_1 var_294 = var_294_arg_0 & var_294_arg_1; [L843] SORT_1 var_295_arg_0 = var_291; [L844] SORT_1 var_295_arg_1 = ~input_292; [L845] var_295_arg_1 = var_295_arg_1 & mask_SORT_1 [L846] SORT_1 var_295 = var_295_arg_0 & var_295_arg_1; [L847] SORT_1 var_297_arg_0 = var_295; [L848] SORT_1 var_297_arg_1 = ~input_296; [L849] var_297_arg_1 = var_297_arg_1 & mask_SORT_1 [L850] SORT_1 var_297 = var_297_arg_0 | var_297_arg_1; [L851] SORT_1 var_298_arg_0 = var_294; [L852] SORT_1 var_298_arg_1 = var_297; [L853] SORT_1 var_298 = var_298_arg_0 & var_298_arg_1; [L854] SORT_1 var_300_arg_0 = var_161; [L855] SORT_1 var_300_arg_1 = ~input_162; [L856] var_300_arg_1 = var_300_arg_1 & mask_SORT_1 [L857] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L858] SORT_1 var_301_arg_0 = var_300; [L859] SORT_1 var_301_arg_1 = input_177; [L860] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L861] SORT_1 var_302_arg_0 = input_107; [L862] SORT_1 var_302_arg_1 = input_224; [L863] SORT_1 var_302 = var_302_arg_0 | var_302_arg_1; [L864] SORT_1 var_303_arg_0 = var_302; [L865] SORT_1 var_303_arg_1 = input_232; [L866] SORT_1 var_303 = var_303_arg_0 | var_303_arg_1; [L867] SORT_1 var_304_arg_0 = var_303; [L868] SORT_1 var_304_arg_1 = input_244; [L869] SORT_1 var_304 = var_304_arg_0 | var_304_arg_1; [L870] SORT_1 var_305_arg_0 = var_301; [L871] SORT_1 var_305_arg_1 = var_304; [L872] SORT_1 var_305 = var_305_arg_0 & var_305_arg_1; [L873] SORT_1 var_306_arg_0 = input_177; [L874] SORT_3 var_306_arg_1 = var_168; [L875] SORT_3 var_306_arg_2 = var_170; [L876] EXPR var_306_arg_0 ? var_306_arg_1 : var_306_arg_2 [L876] SORT_3 var_306 = var_306_arg_0 ? var_306_arg_1 : var_306_arg_2; [L877] SORT_1 var_307_arg_0 = input_292; [L878] SORT_3 var_307_arg_1 = var_168; [L879] SORT_3 var_307_arg_2 = var_306; [L880] EXPR var_307_arg_0 ? var_307_arg_1 : var_307_arg_2 [L880] SORT_3 var_307 = var_307_arg_0 ? var_307_arg_1 : var_307_arg_2; [L881] var_307 = var_307 & mask_SORT_3 [L882] SORT_3 var_308_arg_0 = var_307; [L883] SORT_3 var_308_arg_1 = var_141; [L884] SORT_4 var_308 = ((SORT_4)var_308_arg_0 << 16) | var_308_arg_1; [L885] SORT_4 var_309_arg_0 = var_308; [L886] EXPR (var_309_arg_0 & msb_SORT_4) ? (var_309_arg_0 | ~mask_SORT_4) : (var_309_arg_0 & mask_SORT_4) [L886] var_309_arg_0 = (var_309_arg_0 & msb_SORT_4) ? (var_309_arg_0 | ~mask_SORT_4) : (var_309_arg_0 & mask_SORT_4) [L887] SORT_4 var_309_arg_1 = var_143; [L888] SORT_4 var_309 = (int)var_309_arg_0 >> var_309_arg_1; [L889] EXPR (var_309_arg_0 & msb_SORT_4) ? (var_309 | ~(mask_SORT_4 >> var_309_arg_1)) : var_309 [L889] var_309 = (var_309_arg_0 & msb_SORT_4) ? (var_309 | ~(mask_SORT_4 >> var_309_arg_1)) : var_309 [L890] var_309 = var_309 & mask_SORT_4 [L891] SORT_4 var_310_arg_0 = var_140; [L892] SORT_4 var_310_arg_1 = var_309; [L893] SORT_1 var_310 = var_310_arg_0 == var_310_arg_1; [L894] SORT_1 var_311_arg_0 = var_305; [L895] SORT_1 var_311_arg_1 = var_310; [L896] SORT_1 var_311 = var_311_arg_0 & var_311_arg_1; [L897] SORT_1 var_312_arg_0 = ~input_299; [L898] var_312_arg_0 = var_312_arg_0 & mask_SORT_1 [L899] SORT_1 var_312_arg_1 = var_311; [L900] SORT_1 var_312 = var_312_arg_0 | var_312_arg_1; [L901] SORT_1 var_313_arg_0 = var_298; [L902] SORT_1 var_313_arg_1 = var_312; [L903] SORT_1 var_313 = var_313_arg_0 & var_313_arg_1; [L904] SORT_1 var_315_arg_0 = input_123; [L905] SORT_1 var_315_arg_1 = input_299; [L906] SORT_1 var_315 = var_315_arg_0 | var_315_arg_1; [L907] SORT_1 var_316_arg_0 = input_133; [L908] SORT_1 var_316_arg_1 = var_315; [L909] SORT_1 var_316 = var_316_arg_0 & var_316_arg_1; [L910] SORT_1 var_317_arg_0 = ~input_314; [L911] var_317_arg_0 = var_317_arg_0 & mask_SORT_1 [L912] SORT_1 var_317_arg_1 = var_316; [L913] SORT_1 var_317 = var_317_arg_0 | var_317_arg_1; [L914] SORT_1 var_318_arg_0 = var_313; [L915] SORT_1 var_318_arg_1 = var_317; [L916] SORT_1 var_318 = var_318_arg_0 & var_318_arg_1; [L917] SORT_1 var_320_arg_0 = input_135; [L918] SORT_1 var_320_arg_1 = input_292; [L919] SORT_1 var_320 = var_320_arg_0 | var_320_arg_1; [L920] SORT_1 var_321_arg_0 = input_125; [L921] SORT_1 var_321_arg_1 = input_314; [L922] SORT_1 var_321 = var_321_arg_0 | var_321_arg_1; [L923] SORT_1 var_322_arg_0 = var_320; [L924] SORT_1 var_322_arg_1 = var_321; [L925] SORT_1 var_322 = var_322_arg_0 & var_322_arg_1; [L926] SORT_1 var_323_arg_0 = ~input_319; [L927] var_323_arg_0 = var_323_arg_0 & mask_SORT_1 [L928] SORT_1 var_323_arg_1 = var_322; [L929] SORT_1 var_323 = var_323_arg_0 | var_323_arg_1; [L930] SORT_1 var_324_arg_0 = var_318; [L931] SORT_1 var_324_arg_1 = var_323; [L932] SORT_1 var_324 = var_324_arg_0 & var_324_arg_1; [L933] SORT_1 var_326_arg_0 = input_131; [L934] SORT_1 var_326_arg_1 = input_288; [L935] SORT_1 var_326 = var_326_arg_0 | var_326_arg_1; [L936] SORT_1 var_327_arg_0 = var_326; [L937] SORT_1 var_327_arg_1 = input_296; [L938] SORT_1 var_327 = var_327_arg_0 | var_327_arg_1; [L939] SORT_1 var_328_arg_0 = var_321; [L940] SORT_1 var_328_arg_1 = ~input_319; [L941] var_328_arg_1 = var_328_arg_1 & mask_SORT_1 [L942] SORT_1 var_328 = var_328_arg_0 & var_328_arg_1; [L943] SORT_1 var_329_arg_0 = var_327; [L944] SORT_1 var_329_arg_1 = var_328; [L945] SORT_1 var_329 = var_329_arg_0 & var_329_arg_1; [L946] SORT_1 var_330_arg_0 = ~input_325; [L947] var_330_arg_0 = var_330_arg_0 & mask_SORT_1 [L948] SORT_1 var_330_arg_1 = var_329; [L949] SORT_1 var_330 = var_330_arg_0 | var_330_arg_1; [L950] SORT_1 var_331_arg_0 = var_324; [L951] SORT_1 var_331_arg_1 = var_330; [L952] SORT_1 var_331 = var_331_arg_0 & var_331_arg_1; [L953] SORT_1 var_332_arg_0 = input_139; [L954] SORT_1 var_332_arg_1 = input_148; [L955] SORT_1 var_332 = var_332_arg_0 | var_332_arg_1; [L956] SORT_1 var_333_arg_0 = input_158; [L957] SORT_1 var_333_arg_1 = var_332; [L958] SORT_1 var_333 = var_333_arg_0 | var_333_arg_1; [L959] SORT_1 var_334_arg_0 = input_162; [L960] SORT_1 var_334_arg_1 = var_333; [L961] SORT_1 var_334 = var_334_arg_0 | var_334_arg_1; [L962] SORT_1 var_335_arg_0 = input_165; [L963] SORT_1 var_335_arg_1 = var_334; [L964] SORT_1 var_335 = var_335_arg_0 | var_335_arg_1; [L965] SORT_1 var_336_arg_0 = input_177; [L966] SORT_1 var_336_arg_1 = var_335; [L967] SORT_1 var_336 = var_336_arg_0 | var_336_arg_1; [L968] SORT_1 var_337_arg_0 = input_180; [L969] SORT_1 var_337_arg_1 = var_336; [L970] SORT_1 var_337 = var_337_arg_0 | var_337_arg_1; [L971] SORT_1 var_338_arg_0 = input_204; [L972] SORT_1 var_338_arg_1 = var_337; [L973] SORT_1 var_338 = var_338_arg_0 | var_338_arg_1; [L974] SORT_1 var_339_arg_0 = input_214; [L975] SORT_1 var_339_arg_1 = var_338; [L976] SORT_1 var_339 = var_339_arg_0 | var_339_arg_1; [L977] SORT_1 var_340_arg_0 = input_224; [L978] SORT_1 var_340_arg_1 = var_339; [L979] SORT_1 var_340 = var_340_arg_0 | var_340_arg_1; [L980] SORT_1 var_341_arg_0 = input_232; [L981] SORT_1 var_341_arg_1 = var_340; [L982] SORT_1 var_341 = var_341_arg_0 | var_341_arg_1; [L983] SORT_1 var_342_arg_0 = input_244; [L984] SORT_1 var_342_arg_1 = var_341; [L985] SORT_1 var_342 = var_342_arg_0 | var_342_arg_1; [L986] SORT_1 var_343_arg_0 = input_247; [L987] SORT_1 var_343_arg_1 = var_342; [L988] SORT_1 var_343 = var_343_arg_0 | var_343_arg_1; [L989] SORT_1 var_344_arg_0 = input_260; [L990] SORT_1 var_344_arg_1 = var_343; [L991] SORT_1 var_344 = var_344_arg_0 | var_344_arg_1; [L992] SORT_1 var_345_arg_0 = input_267; [L993] SORT_1 var_345_arg_1 = var_344; [L994] SORT_1 var_345 = var_345_arg_0 | var_345_arg_1; [L995] SORT_1 var_346_arg_0 = input_271; [L996] SORT_1 var_346_arg_1 = var_345; [L997] SORT_1 var_346 = var_346_arg_0 | var_346_arg_1; [L998] SORT_1 var_347_arg_0 = input_275; [L999] SORT_1 var_347_arg_1 = var_346; [L1000] SORT_1 var_347 = var_347_arg_0 | var_347_arg_1; [L1001] SORT_1 var_348_arg_0 = input_281; [L1002] SORT_1 var_348_arg_1 = var_347; [L1003] SORT_1 var_348 = var_348_arg_0 | var_348_arg_1; [L1004] SORT_1 var_349_arg_0 = input_284; [L1005] SORT_1 var_349_arg_1 = var_348; [L1006] SORT_1 var_349 = var_349_arg_0 | var_349_arg_1; [L1007] SORT_1 var_350_arg_0 = input_288; [L1008] SORT_1 var_350_arg_1 = var_349; [L1009] SORT_1 var_350 = var_350_arg_0 | var_350_arg_1; [L1010] SORT_1 var_351_arg_0 = input_292; [L1011] SORT_1 var_351_arg_1 = var_350; [L1012] SORT_1 var_351 = var_351_arg_0 | var_351_arg_1; [L1013] SORT_1 var_352_arg_0 = input_296; [L1014] SORT_1 var_352_arg_1 = var_351; [L1015] SORT_1 var_352 = var_352_arg_0 | var_352_arg_1; [L1016] SORT_1 var_353_arg_0 = input_299; [L1017] SORT_1 var_353_arg_1 = var_352; [L1018] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L1019] SORT_1 var_354_arg_0 = input_314; [L1020] SORT_1 var_354_arg_1 = var_353; [L1021] SORT_1 var_354 = var_354_arg_0 | var_354_arg_1; [L1022] SORT_1 var_355_arg_0 = input_319; [L1023] SORT_1 var_355_arg_1 = var_354; [L1024] SORT_1 var_355 = var_355_arg_0 | var_355_arg_1; [L1025] SORT_1 var_356_arg_0 = input_325; [L1026] SORT_1 var_356_arg_1 = var_355; [L1027] SORT_1 var_356 = var_356_arg_0 | var_356_arg_1; [L1028] SORT_1 var_357_arg_0 = var_331; [L1029] SORT_1 var_357_arg_1 = var_356; [L1030] SORT_1 var_357 = var_357_arg_0 & var_357_arg_1; [L1031] SORT_1 var_358_arg_0 = input_97; [L1032] SORT_1 var_358_arg_1 = input_99; [L1033] SORT_1 var_358 = var_358_arg_0 & var_358_arg_1; [L1034] SORT_1 var_359_arg_0 = input_97; [L1035] SORT_1 var_359_arg_1 = input_99; [L1036] SORT_1 var_359 = var_359_arg_0 | var_359_arg_1; [L1037] SORT_1 var_360_arg_0 = input_101; [L1038] SORT_1 var_360_arg_1 = var_359; [L1039] SORT_1 var_360 = var_360_arg_0 & var_360_arg_1; [L1040] SORT_1 var_361_arg_0 = var_358; [L1041] SORT_1 var_361_arg_1 = var_360; [L1042] SORT_1 var_361 = var_361_arg_0 | var_361_arg_1; [L1043] SORT_1 var_362_arg_0 = input_101; [L1044] SORT_1 var_362_arg_1 = var_359; [L1045] SORT_1 var_362 = var_362_arg_0 | var_362_arg_1; [L1046] SORT_1 var_363_arg_0 = input_103; [L1047] SORT_1 var_363_arg_1 = var_362; [L1048] SORT_1 var_363 = var_363_arg_0 & var_363_arg_1; [L1049] SORT_1 var_364_arg_0 = var_361; [L1050] SORT_1 var_364_arg_1 = var_363; [L1051] SORT_1 var_364 = var_364_arg_0 | var_364_arg_1; [L1052] SORT_1 var_365_arg_0 = input_103; [L1053] SORT_1 var_365_arg_1 = var_362; [L1054] SORT_1 var_365 = var_365_arg_0 | var_365_arg_1; [L1055] SORT_1 var_366_arg_0 = ~var_364; [L1056] var_366_arg_0 = var_366_arg_0 & mask_SORT_1 [L1057] SORT_1 var_366_arg_1 = var_365; [L1058] SORT_1 var_366 = var_366_arg_0 & var_366_arg_1; [L1059] SORT_1 var_367_arg_0 = input_105; [L1060] SORT_1 var_367_arg_1 = input_107; [L1061] SORT_1 var_367 = var_367_arg_0 & var_367_arg_1; [L1062] SORT_1 var_368_arg_0 = input_105; [L1063] SORT_1 var_368_arg_1 = input_107; [L1064] SORT_1 var_368 = var_368_arg_0 | var_368_arg_1; [L1065] SORT_1 var_369_arg_0 = input_109; [L1066] SORT_1 var_369_arg_1 = var_368; [L1067] SORT_1 var_369 = var_369_arg_0 & var_369_arg_1; [L1068] SORT_1 var_370_arg_0 = var_367; [L1069] SORT_1 var_370_arg_1 = var_369; [L1070] SORT_1 var_370 = var_370_arg_0 | var_370_arg_1; [L1071] SORT_1 var_371_arg_0 = input_109; [L1072] SORT_1 var_371_arg_1 = var_368; [L1073] SORT_1 var_371 = var_371_arg_0 | var_371_arg_1; [L1074] SORT_1 var_372_arg_0 = input_111; [L1075] SORT_1 var_372_arg_1 = var_371; [L1076] SORT_1 var_372 = var_372_arg_0 & var_372_arg_1; [L1077] SORT_1 var_373_arg_0 = var_370; [L1078] SORT_1 var_373_arg_1 = var_372; [L1079] SORT_1 var_373 = var_373_arg_0 | var_373_arg_1; [L1080] SORT_1 var_374_arg_0 = input_111; [L1081] SORT_1 var_374_arg_1 = var_371; [L1082] SORT_1 var_374 = var_374_arg_0 | var_374_arg_1; [L1083] SORT_1 var_375_arg_0 = input_113; [L1084] SORT_1 var_375_arg_1 = var_374; [L1085] SORT_1 var_375 = var_375_arg_0 & var_375_arg_1; [L1086] SORT_1 var_376_arg_0 = var_373; [L1087] SORT_1 var_376_arg_1 = var_375; [L1088] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L1089] SORT_1 var_377_arg_0 = input_113; [L1090] SORT_1 var_377_arg_1 = var_374; [L1091] SORT_1 var_377 = var_377_arg_0 | var_377_arg_1; [L1092] SORT_1 var_378_arg_0 = input_115; [L1093] SORT_1 var_378_arg_1 = var_377; [L1094] SORT_1 var_378 = var_378_arg_0 & var_378_arg_1; [L1095] SORT_1 var_379_arg_0 = var_376; [L1096] SORT_1 var_379_arg_1 = var_378; [L1097] SORT_1 var_379 = var_379_arg_0 | var_379_arg_1; [L1098] SORT_1 var_380_arg_0 = input_115; [L1099] SORT_1 var_380_arg_1 = var_377; [L1100] SORT_1 var_380 = var_380_arg_0 | var_380_arg_1; [L1101] SORT_1 var_381_arg_0 = input_117; [L1102] SORT_1 var_381_arg_1 = var_380; [L1103] SORT_1 var_381 = var_381_arg_0 & var_381_arg_1; [L1104] SORT_1 var_382_arg_0 = var_379; [L1105] SORT_1 var_382_arg_1 = var_381; [L1106] SORT_1 var_382 = var_382_arg_0 | var_382_arg_1; [L1107] SORT_1 var_383_arg_0 = input_117; [L1108] SORT_1 var_383_arg_1 = var_380; [L1109] SORT_1 var_383 = var_383_arg_0 | var_383_arg_1; [L1110] SORT_1 var_384_arg_0 = input_119; [L1111] SORT_1 var_384_arg_1 = var_383; [L1112] SORT_1 var_384 = var_384_arg_0 & var_384_arg_1; [L1113] SORT_1 var_385_arg_0 = var_382; [L1114] SORT_1 var_385_arg_1 = var_384; [L1115] SORT_1 var_385 = var_385_arg_0 | var_385_arg_1; [L1116] SORT_1 var_386_arg_0 = input_119; [L1117] SORT_1 var_386_arg_1 = var_383; [L1118] SORT_1 var_386 = var_386_arg_0 | var_386_arg_1; [L1119] SORT_1 var_387_arg_0 = input_121; [L1120] SORT_1 var_387_arg_1 = var_386; [L1121] SORT_1 var_387 = var_387_arg_0 & var_387_arg_1; [L1122] SORT_1 var_388_arg_0 = var_385; [L1123] SORT_1 var_388_arg_1 = var_387; [L1124] SORT_1 var_388 = var_388_arg_0 | var_388_arg_1; [L1125] SORT_1 var_389_arg_0 = input_121; [L1126] SORT_1 var_389_arg_1 = var_386; [L1127] SORT_1 var_389 = var_389_arg_0 | var_389_arg_1; [L1128] SORT_1 var_390_arg_0 = input_123; [L1129] SORT_1 var_390_arg_1 = var_389; [L1130] SORT_1 var_390 = var_390_arg_0 & var_390_arg_1; [L1131] SORT_1 var_391_arg_0 = var_388; [L1132] SORT_1 var_391_arg_1 = var_390; [L1133] SORT_1 var_391 = var_391_arg_0 | var_391_arg_1; [L1134] SORT_1 var_392_arg_0 = input_123; [L1135] SORT_1 var_392_arg_1 = var_389; [L1136] SORT_1 var_392 = var_392_arg_0 | var_392_arg_1; [L1137] SORT_1 var_393_arg_0 = input_125; [L1138] SORT_1 var_393_arg_1 = var_392; [L1139] SORT_1 var_393 = var_393_arg_0 & var_393_arg_1; [L1140] SORT_1 var_394_arg_0 = var_391; [L1141] SORT_1 var_394_arg_1 = var_393; [L1142] SORT_1 var_394 = var_394_arg_0 | var_394_arg_1; [L1143] SORT_1 var_395_arg_0 = var_366; [L1144] SORT_1 var_395_arg_1 = ~var_394; [L1145] var_395_arg_1 = var_395_arg_1 & mask_SORT_1 [L1146] SORT_1 var_395 = var_395_arg_0 & var_395_arg_1; [L1147] SORT_1 var_396_arg_0 = input_125; [L1148] SORT_1 var_396_arg_1 = var_392; [L1149] SORT_1 var_396 = var_396_arg_0 | var_396_arg_1; [L1150] SORT_1 var_397_arg_0 = var_395; [L1151] SORT_1 var_397_arg_1 = var_396; [L1152] SORT_1 var_397 = var_397_arg_0 & var_397_arg_1; [L1153] SORT_1 var_398_arg_0 = input_127; [L1154] SORT_1 var_398_arg_1 = input_129; [L1155] SORT_1 var_398 = var_398_arg_0 & var_398_arg_1; [L1156] SORT_1 var_399_arg_0 = input_127; [L1157] SORT_1 var_399_arg_1 = input_129; [L1158] SORT_1 var_399 = var_399_arg_0 | var_399_arg_1; [L1159] SORT_1 var_400_arg_0 = input_131; [L1160] SORT_1 var_400_arg_1 = var_399; [L1161] SORT_1 var_400 = var_400_arg_0 & var_400_arg_1; [L1162] SORT_1 var_401_arg_0 = var_398; [L1163] SORT_1 var_401_arg_1 = var_400; [L1164] SORT_1 var_401 = var_401_arg_0 | var_401_arg_1; [L1165] SORT_1 var_402_arg_0 = input_131; [L1166] SORT_1 var_402_arg_1 = var_399; [L1167] SORT_1 var_402 = var_402_arg_0 | var_402_arg_1; [L1168] SORT_1 var_403_arg_0 = input_133; [L1169] SORT_1 var_403_arg_1 = var_402; [L1170] SORT_1 var_403 = var_403_arg_0 & var_403_arg_1; [L1171] SORT_1 var_404_arg_0 = var_401; [L1172] SORT_1 var_404_arg_1 = var_403; [L1173] SORT_1 var_404 = var_404_arg_0 | var_404_arg_1; [L1174] SORT_1 var_405_arg_0 = input_133; [L1175] SORT_1 var_405_arg_1 = var_402; [L1176] SORT_1 var_405 = var_405_arg_0 | var_405_arg_1; [L1177] SORT_1 var_406_arg_0 = input_135; [L1178] SORT_1 var_406_arg_1 = var_405; [L1179] SORT_1 var_406 = var_406_arg_0 & var_406_arg_1; [L1180] SORT_1 var_407_arg_0 = var_404; [L1181] SORT_1 var_407_arg_1 = var_406; [L1182] SORT_1 var_407 = var_407_arg_0 | var_407_arg_1; [L1183] SORT_1 var_408_arg_0 = var_397; [L1184] SORT_1 var_408_arg_1 = ~var_407; [L1185] var_408_arg_1 = var_408_arg_1 & mask_SORT_1 [L1186] SORT_1 var_408 = var_408_arg_0 & var_408_arg_1; [L1187] SORT_1 var_409_arg_0 = input_135; [L1188] SORT_1 var_409_arg_1 = var_405; [L1189] SORT_1 var_409 = var_409_arg_0 | var_409_arg_1; [L1190] SORT_1 var_410_arg_0 = var_408; [L1191] SORT_1 var_410_arg_1 = var_409; [L1192] SORT_1 var_410 = var_410_arg_0 & var_410_arg_1; [L1193] SORT_1 var_411_arg_0 = var_357; [L1194] SORT_1 var_411_arg_1 = var_410; [L1195] SORT_1 var_411 = var_411_arg_0 & var_411_arg_1; [L1196] SORT_1 var_412_arg_0 = var_301; [L1197] SORT_1 var_412_arg_1 = ~input_299; [L1198] var_412_arg_1 = var_412_arg_1 & mask_SORT_1 [L1199] SORT_1 var_412 = var_412_arg_0 & var_412_arg_1; [L1200] var_412 = var_412 & mask_SORT_1 [L1201] SORT_1 var_413_arg_0 = var_166; [L1202] SORT_1 var_413_arg_1 = ~input_165; [L1203] var_413_arg_1 = var_413_arg_1 & mask_SORT_1 [L1204] SORT_1 var_413 = var_413_arg_0 & var_413_arg_1; [L1205] SORT_1 var_414_arg_0 = var_413; [L1206] SORT_1 var_414_arg_1 = input_299; [L1207] SORT_1 var_414 = var_414_arg_0 | var_414_arg_1; [L1208] var_414 = var_414 & mask_SORT_1 [L1209] SORT_1 var_415_arg_0 = var_412; [L1210] SORT_1 var_415_arg_1 = var_414; [L1211] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1212] SORT_1 var_416_arg_0 = input_101; [L1213] SORT_1 var_416_arg_1 = ~input_158; [L1214] var_416_arg_1 = var_416_arg_1 & mask_SORT_1 [L1215] SORT_1 var_416 = var_416_arg_0 & var_416_arg_1; [L1216] SORT_1 var_417_arg_0 = var_416; [L1217] SORT_1 var_417_arg_1 = input_162; [L1218] SORT_1 var_417 = var_417_arg_0 | var_417_arg_1; [L1219] SORT_1 var_418_arg_0 = var_417; [L1220] SORT_1 var_418_arg_1 = input_165; [L1221] SORT_1 var_418 = var_418_arg_0 | var_418_arg_1; [L1222] var_418 = var_418 & mask_SORT_1 [L1223] SORT_1 var_419_arg_0 = var_412; [L1224] SORT_1 var_419_arg_1 = var_414; [L1225] SORT_1 var_419 = var_419_arg_0 | var_419_arg_1; [L1226] SORT_1 var_420_arg_0 = var_418; [L1227] SORT_1 var_420_arg_1 = var_419; [L1228] SORT_1 var_420 = var_420_arg_0 & var_420_arg_1; [L1229] SORT_1 var_421_arg_0 = var_415; [L1230] SORT_1 var_421_arg_1 = var_420; [L1231] SORT_1 var_421 = var_421_arg_0 | var_421_arg_1; [L1232] SORT_1 var_422_arg_0 = input_103; [L1233] SORT_1 var_422_arg_1 = ~input_177; [L1234] var_422_arg_1 = var_422_arg_1 & mask_SORT_1 [L1235] SORT_1 var_422 = var_422_arg_0 & var_422_arg_1; [L1236] var_422 = var_422 & mask_SORT_1 [L1237] SORT_1 var_423_arg_0 = var_418; [L1238] SORT_1 var_423_arg_1 = var_419; [L1239] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1240] SORT_1 var_424_arg_0 = var_422; [L1241] SORT_1 var_424_arg_1 = var_423; [L1242] SORT_1 var_424 = var_424_arg_0 & var_424_arg_1; [L1243] SORT_1 var_425_arg_0 = var_421; [L1244] SORT_1 var_425_arg_1 = var_424; [L1245] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1246] SORT_1 var_426_arg_0 = var_422; [L1247] SORT_1 var_426_arg_1 = var_423; [L1248] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1249] SORT_1 var_427_arg_0 = ~var_425; [L1250] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L1251] SORT_1 var_427_arg_1 = var_426; [L1252] SORT_1 var_427 = var_427_arg_0 & var_427_arg_1; [L1253] SORT_1 var_428_arg_0 = var_304; [L1254] SORT_1 var_428_arg_1 = ~input_299; [L1255] var_428_arg_1 = var_428_arg_1 & mask_SORT_1 [L1256] SORT_1 var_428 = var_428_arg_0 & var_428_arg_1; [L1257] var_428 = var_428 & mask_SORT_1 [L1258] SORT_1 var_429_arg_0 = var_215; [L1259] SORT_1 var_429_arg_1 = ~input_214; [L1260] var_429_arg_1 = var_429_arg_1 & mask_SORT_1 [L1261] SORT_1 var_429 = var_429_arg_0 & var_429_arg_1; [L1262] SORT_1 var_430_arg_0 = var_429; [L1263] SORT_1 var_430_arg_1 = input_319; [L1264] SORT_1 var_430 = var_430_arg_0 | var_430_arg_1; [L1265] var_430 = var_430 & mask_SORT_1 [L1266] SORT_1 var_431_arg_0 = var_428; [L1267] SORT_1 var_431_arg_1 = var_430; [L1268] SORT_1 var_431 = var_431_arg_0 & var_431_arg_1; [L1269] SORT_1 var_432_arg_0 = var_248; [L1270] SORT_1 var_432_arg_1 = ~input_247; [L1271] var_432_arg_1 = var_432_arg_1 & mask_SORT_1 [L1272] SORT_1 var_432 = var_432_arg_0 & var_432_arg_1; [L1273] var_432 = var_432 & mask_SORT_1 [L1274] SORT_1 var_433_arg_0 = var_428; [L1275] SORT_1 var_433_arg_1 = var_430; [L1276] SORT_1 var_433 = var_433_arg_0 | var_433_arg_1; [L1277] SORT_1 var_434_arg_0 = var_432; [L1278] SORT_1 var_434_arg_1 = var_433; [L1279] SORT_1 var_434 = var_434_arg_0 & var_434_arg_1; [L1280] SORT_1 var_435_arg_0 = var_431; [L1281] SORT_1 var_435_arg_1 = var_434; [L1282] SORT_1 var_435 = var_435_arg_0 | var_435_arg_1; [L1283] SORT_1 var_436_arg_0 = var_274; [L1284] SORT_1 var_436_arg_1 = ~input_275; [L1285] var_436_arg_1 = var_436_arg_1 & mask_SORT_1 [L1286] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1287] var_436 = var_436 & mask_SORT_1 [L1288] SORT_1 var_437_arg_0 = var_432; [L1289] SORT_1 var_437_arg_1 = var_433; [L1290] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1291] SORT_1 var_438_arg_0 = var_436; [L1292] SORT_1 var_438_arg_1 = var_437; [L1293] SORT_1 var_438 = var_438_arg_0 & var_438_arg_1; [L1294] SORT_1 var_439_arg_0 = var_435; [L1295] SORT_1 var_439_arg_1 = var_438; [L1296] SORT_1 var_439 = var_439_arg_0 | var_439_arg_1; [L1297] SORT_1 var_440_arg_0 = var_261; [L1298] SORT_1 var_440_arg_1 = ~input_260; [L1299] var_440_arg_1 = var_440_arg_1 & mask_SORT_1 [L1300] SORT_1 var_440 = var_440_arg_0 & var_440_arg_1; [L1301] SORT_1 var_441_arg_0 = var_440; [L1302] SORT_1 var_441_arg_1 = input_325; [L1303] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1304] var_441 = var_441 & mask_SORT_1 [L1305] SORT_1 var_442_arg_0 = var_436; [L1306] SORT_1 var_442_arg_1 = var_437; [L1307] SORT_1 var_442 = var_442_arg_0 | var_442_arg_1; [L1308] SORT_1 var_443_arg_0 = var_441; [L1309] SORT_1 var_443_arg_1 = var_442; [L1310] SORT_1 var_443 = var_443_arg_0 & var_443_arg_1; [L1311] SORT_1 var_444_arg_0 = var_439; [L1312] SORT_1 var_444_arg_1 = var_443; [L1313] SORT_1 var_444 = var_444_arg_0 | var_444_arg_1; [L1314] SORT_1 var_445_arg_0 = var_266; [L1315] SORT_1 var_445_arg_1 = ~input_267; [L1316] var_445_arg_1 = var_445_arg_1 & mask_SORT_1 [L1317] SORT_1 var_445 = var_445_arg_0 & var_445_arg_1; [L1318] var_445 = var_445 & mask_SORT_1 [L1319] SORT_1 var_446_arg_0 = var_441; [L1320] SORT_1 var_446_arg_1 = var_442; [L1321] SORT_1 var_446 = var_446_arg_0 | var_446_arg_1; [L1322] SORT_1 var_447_arg_0 = var_445; [L1323] SORT_1 var_447_arg_1 = var_446; [L1324] SORT_1 var_447 = var_447_arg_0 & var_447_arg_1; [L1325] SORT_1 var_448_arg_0 = var_444; [L1326] SORT_1 var_448_arg_1 = var_447; [L1327] SORT_1 var_448 = var_448_arg_0 | var_448_arg_1; [L1328] SORT_1 var_449_arg_0 = var_270; [L1329] SORT_1 var_449_arg_1 = ~input_271; [L1330] var_449_arg_1 = var_449_arg_1 & mask_SORT_1 [L1331] SORT_1 var_449 = var_449_arg_0 & var_449_arg_1; [L1332] var_449 = var_449 & mask_SORT_1 [L1333] SORT_1 var_450_arg_0 = var_445; [L1334] SORT_1 var_450_arg_1 = var_446; [L1335] SORT_1 var_450 = var_450_arg_0 | var_450_arg_1; [L1336] SORT_1 var_451_arg_0 = var_449; [L1337] SORT_1 var_451_arg_1 = var_450; [L1338] SORT_1 var_451 = var_451_arg_0 & var_451_arg_1; [L1339] SORT_1 var_452_arg_0 = var_448; [L1340] SORT_1 var_452_arg_1 = var_451; [L1341] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1342] SORT_1 var_453_arg_0 = input_119; [L1343] SORT_1 var_453_arg_1 = ~input_244; [L1344] var_453_arg_1 = var_453_arg_1 & mask_SORT_1 [L1345] SORT_1 var_453 = var_453_arg_0 & var_453_arg_1; [L1346] SORT_1 var_454_arg_0 = var_453; [L1347] SORT_1 var_454_arg_1 = input_281; [L1348] SORT_1 var_454 = var_454_arg_0 | var_454_arg_1; [L1349] var_454 = var_454 & mask_SORT_1 [L1350] SORT_1 var_455_arg_0 = var_449; [L1351] SORT_1 var_455_arg_1 = var_450; [L1352] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1353] SORT_1 var_456_arg_0 = var_454; [L1354] SORT_1 var_456_arg_1 = var_455; [L1355] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1356] SORT_1 var_457_arg_0 = var_452; [L1357] SORT_1 var_457_arg_1 = var_456; [L1358] SORT_1 var_457 = var_457_arg_0 | var_457_arg_1; [L1359] SORT_1 var_458_arg_0 = var_280; [L1360] SORT_1 var_458_arg_1 = ~input_281; [L1361] var_458_arg_1 = var_458_arg_1 & mask_SORT_1 [L1362] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1363] var_458 = var_458 & mask_SORT_1 [L1364] SORT_1 var_459_arg_0 = var_454; [L1365] SORT_1 var_459_arg_1 = var_455; [L1366] SORT_1 var_459 = var_459_arg_0 | var_459_arg_1; [L1367] SORT_1 var_460_arg_0 = var_458; [L1368] SORT_1 var_460_arg_1 = var_459; [L1369] SORT_1 var_460 = var_460_arg_0 & var_460_arg_1; [L1370] SORT_1 var_461_arg_0 = var_457; [L1371] SORT_1 var_461_arg_1 = var_460; [L1372] SORT_1 var_461 = var_461_arg_0 | var_461_arg_1; [L1373] SORT_1 var_462_arg_0 = var_315; [L1374] SORT_1 var_462_arg_1 = ~input_314; [L1375] var_462_arg_1 = var_462_arg_1 & mask_SORT_1 [L1376] SORT_1 var_462 = var_462_arg_0 & var_462_arg_1; [L1377] var_462 = var_462 & mask_SORT_1 [L1378] SORT_1 var_463_arg_0 = var_458; [L1379] SORT_1 var_463_arg_1 = var_459; [L1380] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1381] SORT_1 var_464_arg_0 = var_462; [L1382] SORT_1 var_464_arg_1 = var_463; [L1383] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1384] SORT_1 var_465_arg_0 = var_461; [L1385] SORT_1 var_465_arg_1 = var_464; [L1386] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1387] SORT_1 var_466_arg_0 = var_328; [L1388] SORT_1 var_466_arg_1 = ~input_325; [L1389] var_466_arg_1 = var_466_arg_1 & mask_SORT_1 [L1390] SORT_1 var_466 = var_466_arg_0 & var_466_arg_1; [L1391] var_466 = var_466 & mask_SORT_1 [L1392] SORT_1 var_467_arg_0 = var_462; [L1393] SORT_1 var_467_arg_1 = var_463; [L1394] SORT_1 var_467 = var_467_arg_0 | var_467_arg_1; [L1395] SORT_1 var_468_arg_0 = var_466; [L1396] SORT_1 var_468_arg_1 = var_467; [L1397] SORT_1 var_468 = var_468_arg_0 & var_468_arg_1; [L1398] SORT_1 var_469_arg_0 = var_465; [L1399] SORT_1 var_469_arg_1 = var_468; [L1400] SORT_1 var_469 = var_469_arg_0 | var_469_arg_1; [L1401] SORT_1 var_470_arg_0 = var_427; [L1402] SORT_1 var_470_arg_1 = ~var_469; [L1403] var_470_arg_1 = var_470_arg_1 & mask_SORT_1 [L1404] SORT_1 var_470 = var_470_arg_0 & var_470_arg_1; [L1405] SORT_1 var_471_arg_0 = var_466; [L1406] SORT_1 var_471_arg_1 = var_467; [L1407] SORT_1 var_471 = var_471_arg_0 | var_471_arg_1; [L1408] SORT_1 var_472_arg_0 = var_470; [L1409] SORT_1 var_472_arg_1 = var_471; [L1410] SORT_1 var_472 = var_472_arg_0 & var_472_arg_1; [L1411] SORT_1 var_473_arg_0 = var_295; [L1412] SORT_1 var_473_arg_1 = ~input_296; [L1413] var_473_arg_1 = var_473_arg_1 & mask_SORT_1 [L1414] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1415] var_473 = var_473 & mask_SORT_1 [L1416] SORT_1 var_474_arg_0 = var_287; [L1417] SORT_1 var_474_arg_1 = ~input_288; [L1418] var_474_arg_1 = var_474_arg_1 & mask_SORT_1 [L1419] SORT_1 var_474 = var_474_arg_0 & var_474_arg_1; [L1420] SORT_1 var_475_arg_0 = var_474; [L1421] SORT_1 var_475_arg_1 = input_314; [L1422] SORT_1 var_475 = var_475_arg_0 | var_475_arg_1; [L1423] var_475 = var_475 & mask_SORT_1 [L1424] SORT_1 var_476_arg_0 = var_473; [L1425] SORT_1 var_476_arg_1 = var_475; [L1426] SORT_1 var_476 = var_476_arg_0 & var_476_arg_1; [L1427] SORT_1 var_477_arg_0 = var_327; [L1428] SORT_1 var_477_arg_1 = ~input_325; [L1429] var_477_arg_1 = var_477_arg_1 & mask_SORT_1 [L1430] SORT_1 var_477 = var_477_arg_0 & var_477_arg_1; [L1431] var_477 = var_477 & mask_SORT_1 [L1432] SORT_1 var_478_arg_0 = var_473; [L1433] SORT_1 var_478_arg_1 = var_475; [L1434] SORT_1 var_478 = var_478_arg_0 | var_478_arg_1; [L1435] SORT_1 var_479_arg_0 = var_477; [L1436] SORT_1 var_479_arg_1 = var_478; [L1437] SORT_1 var_479 = var_479_arg_0 & var_479_arg_1; [L1438] SORT_1 var_480_arg_0 = var_476; [L1439] SORT_1 var_480_arg_1 = var_479; [L1440] SORT_1 var_480 = var_480_arg_0 | var_480_arg_1; [L1441] SORT_1 var_481_arg_0 = input_133; [L1442] SORT_1 var_481_arg_1 = ~input_314; [L1443] var_481_arg_1 = var_481_arg_1 & mask_SORT_1 [L1444] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1445] SORT_1 var_482_arg_0 = var_481; [L1446] SORT_1 var_482_arg_1 = input_319; [L1447] SORT_1 var_482 = var_482_arg_0 | var_482_arg_1; [L1448] SORT_1 var_483_arg_0 = var_482; [L1449] SORT_1 var_483_arg_1 = input_325; [L1450] SORT_1 var_483 = var_483_arg_0 | var_483_arg_1; [L1451] var_483 = var_483 & mask_SORT_1 [L1452] SORT_1 var_484_arg_0 = var_477; [L1453] SORT_1 var_484_arg_1 = var_478; [L1454] SORT_1 var_484 = var_484_arg_0 | var_484_arg_1; [L1455] SORT_1 var_485_arg_0 = var_483; [L1456] SORT_1 var_485_arg_1 = var_484; [L1457] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1458] SORT_1 var_486_arg_0 = var_480; [L1459] SORT_1 var_486_arg_1 = var_485; [L1460] SORT_1 var_486 = var_486_arg_0 | var_486_arg_1; [L1461] SORT_1 var_487_arg_0 = var_320; [L1462] SORT_1 var_487_arg_1 = ~input_319; [L1463] var_487_arg_1 = var_487_arg_1 & mask_SORT_1 [L1464] SORT_1 var_487 = var_487_arg_0 & var_487_arg_1; [L1465] var_487 = var_487 & mask_SORT_1 [L1466] SORT_1 var_488_arg_0 = var_483; [L1467] SORT_1 var_488_arg_1 = var_484; [L1468] SORT_1 var_488 = var_488_arg_0 | var_488_arg_1; [L1469] SORT_1 var_489_arg_0 = var_487; [L1470] SORT_1 var_489_arg_1 = var_488; [L1471] SORT_1 var_489 = var_489_arg_0 & var_489_arg_1; [L1472] SORT_1 var_490_arg_0 = var_486; [L1473] SORT_1 var_490_arg_1 = var_489; [L1474] SORT_1 var_490 = var_490_arg_0 | var_490_arg_1; [L1475] SORT_1 var_491_arg_0 = var_472; [L1476] SORT_1 var_491_arg_1 = ~var_490; [L1477] var_491_arg_1 = var_491_arg_1 & mask_SORT_1 [L1478] SORT_1 var_491 = var_491_arg_0 & var_491_arg_1; [L1479] SORT_1 var_492_arg_0 = var_487; [L1480] SORT_1 var_492_arg_1 = var_488; [L1481] SORT_1 var_492 = var_492_arg_0 | var_492_arg_1; [L1482] SORT_1 var_493_arg_0 = var_491; [L1483] SORT_1 var_493_arg_1 = var_492; [L1484] SORT_1 var_493 = var_493_arg_0 & var_493_arg_1; [L1485] SORT_1 var_494_arg_0 = var_411; [L1486] SORT_1 var_494_arg_1 = var_493; [L1487] SORT_1 var_494 = var_494_arg_0 & var_494_arg_1; [L1488] SORT_3 var_495_arg_0 = var_307; [L1489] SORT_3 var_495_arg_1 = state_6; [L1490] SORT_1 var_495 = var_495_arg_0 == var_495_arg_1; [L1491] SORT_1 var_496_arg_0 = var_494; [L1492] SORT_1 var_496_arg_1 = var_495; [L1493] SORT_1 var_496 = var_496_arg_0 & var_496_arg_1; [L1494] SORT_1 var_497_arg_0 = input_214; [L1495] SORT_3 var_497_arg_1 = var_78; [L1496] SORT_3 var_497_arg_2 = var_216; [L1497] EXPR var_497_arg_0 ? var_497_arg_1 : var_497_arg_2 [L1497] SORT_3 var_497 = var_497_arg_0 ? var_497_arg_1 : var_497_arg_2; [L1498] var_497 = var_497 & mask_SORT_3 [L1499] SORT_3 var_498_arg_0 = var_497; [L1500] SORT_3 var_498_arg_1 = state_8; [L1501] SORT_1 var_498 = var_498_arg_0 == var_498_arg_1; [L1502] SORT_1 var_499_arg_0 = var_496; [L1503] SORT_1 var_499_arg_1 = var_498; [L1504] SORT_1 var_499 = var_499_arg_0 & var_499_arg_1; [L1505] SORT_3 var_500_arg_0 = input_93; [L1506] SORT_3 var_500_arg_1 = state_10; [L1507] SORT_1 var_500 = var_500_arg_0 == var_500_arg_1; [L1508] SORT_1 var_501_arg_0 = var_499; [L1509] SORT_1 var_501_arg_1 = var_500; [L1510] SORT_1 var_501 = var_501_arg_0 & var_501_arg_1; [L1511] SORT_3 var_502_arg_0 = var_253; [L1512] SORT_3 var_502_arg_1 = state_12; [L1513] SORT_1 var_502 = var_502_arg_0 == var_502_arg_1; [L1514] SORT_1 var_503_arg_0 = var_501; [L1515] SORT_1 var_503_arg_1 = var_502; [L1516] SORT_1 var_503 = var_503_arg_0 & var_503_arg_1; [L1517] SORT_1 var_504_arg_0 = var_412; [L1518] SORT_1 var_504_arg_1 = state_15; [L1519] SORT_1 var_504 = var_504_arg_0 == var_504_arg_1; [L1520] SORT_1 var_505_arg_0 = var_503; [L1521] SORT_1 var_505_arg_1 = var_504; [L1522] SORT_1 var_505 = var_505_arg_0 & var_505_arg_1; [L1523] SORT_1 var_506_arg_0 = var_414; [L1524] SORT_1 var_506_arg_1 = state_17; [L1525] SORT_1 var_506 = var_506_arg_0 == var_506_arg_1; [L1526] SORT_1 var_507_arg_0 = var_505; [L1527] SORT_1 var_507_arg_1 = var_506; [L1528] SORT_1 var_507 = var_507_arg_0 & var_507_arg_1; [L1529] SORT_1 var_508_arg_0 = var_418; [L1530] SORT_1 var_508_arg_1 = state_19; [L1531] SORT_1 var_508 = var_508_arg_0 == var_508_arg_1; [L1532] SORT_1 var_509_arg_0 = var_507; [L1533] SORT_1 var_509_arg_1 = var_508; [L1534] SORT_1 var_509 = var_509_arg_0 & var_509_arg_1; [L1535] SORT_1 var_510_arg_0 = var_422; [L1536] SORT_1 var_510_arg_1 = state_21; [L1537] SORT_1 var_510 = var_510_arg_0 == var_510_arg_1; [L1538] SORT_1 var_511_arg_0 = var_509; [L1539] SORT_1 var_511_arg_1 = var_510; [L1540] SORT_1 var_511 = var_511_arg_0 & var_511_arg_1; [L1541] SORT_1 var_512_arg_0 = var_430; [L1542] SORT_1 var_512_arg_1 = state_23; [L1543] SORT_1 var_512 = var_512_arg_0 == var_512_arg_1; [L1544] SORT_1 var_513_arg_0 = var_511; [L1545] SORT_1 var_513_arg_1 = var_512; [L1546] SORT_1 var_513 = var_513_arg_0 & var_513_arg_1; [L1547] SORT_1 var_514_arg_0 = var_428; [L1548] SORT_1 var_514_arg_1 = state_25; [L1549] SORT_1 var_514 = var_514_arg_0 == var_514_arg_1; [L1550] SORT_1 var_515_arg_0 = var_513; [L1551] SORT_1 var_515_arg_1 = var_514; [L1552] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1553] SORT_1 var_516_arg_0 = var_432; [L1554] SORT_1 var_516_arg_1 = state_27; [L1555] SORT_1 var_516 = var_516_arg_0 == var_516_arg_1; [L1556] SORT_1 var_517_arg_0 = var_515; [L1557] SORT_1 var_517_arg_1 = var_516; [L1558] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L1559] SORT_1 var_518_arg_0 = var_436; [L1560] SORT_1 var_518_arg_1 = state_29; [L1561] SORT_1 var_518 = var_518_arg_0 == var_518_arg_1; [L1562] SORT_1 var_519_arg_0 = var_517; [L1563] SORT_1 var_519_arg_1 = var_518; [L1564] SORT_1 var_519 = var_519_arg_0 & var_519_arg_1; [L1565] SORT_1 var_520_arg_0 = var_441; [L1566] SORT_1 var_520_arg_1 = state_31; [L1567] SORT_1 var_520 = var_520_arg_0 == var_520_arg_1; [L1568] SORT_1 var_521_arg_0 = var_519; [L1569] SORT_1 var_521_arg_1 = var_520; [L1570] SORT_1 var_521 = var_521_arg_0 & var_521_arg_1; [L1571] SORT_1 var_522_arg_0 = var_445; [L1572] SORT_1 var_522_arg_1 = state_33; [L1573] SORT_1 var_522 = var_522_arg_0 == var_522_arg_1; [L1574] SORT_1 var_523_arg_0 = var_521; [L1575] SORT_1 var_523_arg_1 = var_522; [L1576] SORT_1 var_523 = var_523_arg_0 & var_523_arg_1; [L1577] SORT_1 var_524_arg_0 = var_449; [L1578] SORT_1 var_524_arg_1 = state_35; [L1579] SORT_1 var_524 = var_524_arg_0 == var_524_arg_1; [L1580] SORT_1 var_525_arg_0 = var_523; [L1581] SORT_1 var_525_arg_1 = var_524; [L1582] SORT_1 var_525 = var_525_arg_0 & var_525_arg_1; [L1583] SORT_1 var_526_arg_0 = var_454; [L1584] SORT_1 var_526_arg_1 = state_37; [L1585] SORT_1 var_526 = var_526_arg_0 == var_526_arg_1; [L1586] SORT_1 var_527_arg_0 = var_525; [L1587] SORT_1 var_527_arg_1 = var_526; [L1588] SORT_1 var_527 = var_527_arg_0 & var_527_arg_1; [L1589] SORT_1 var_528_arg_0 = var_458; [L1590] SORT_1 var_528_arg_1 = state_39; [L1591] SORT_1 var_528 = var_528_arg_0 == var_528_arg_1; [L1592] SORT_1 var_529_arg_0 = var_527; [L1593] SORT_1 var_529_arg_1 = var_528; [L1594] SORT_1 var_529 = var_529_arg_0 & var_529_arg_1; [L1595] SORT_1 var_530_arg_0 = var_462; [L1596] SORT_1 var_530_arg_1 = state_41; [L1597] SORT_1 var_530 = var_530_arg_0 == var_530_arg_1; [L1598] SORT_1 var_531_arg_0 = var_529; [L1599] SORT_1 var_531_arg_1 = var_530; [L1600] SORT_1 var_531 = var_531_arg_0 & var_531_arg_1; [L1601] SORT_1 var_532_arg_0 = var_466; [L1602] SORT_1 var_532_arg_1 = state_43; [L1603] SORT_1 var_532 = var_532_arg_0 == var_532_arg_1; [L1604] SORT_1 var_533_arg_0 = var_531; [L1605] SORT_1 var_533_arg_1 = var_532; [L1606] SORT_1 var_533 = var_533_arg_0 & var_533_arg_1; [L1607] SORT_1 var_534_arg_0 = var_475; [L1608] SORT_1 var_534_arg_1 = state_45; [L1609] SORT_1 var_534 = var_534_arg_0 == var_534_arg_1; [L1610] SORT_1 var_535_arg_0 = var_533; [L1611] SORT_1 var_535_arg_1 = var_534; [L1612] SORT_1 var_535 = var_535_arg_0 & var_535_arg_1; [L1613] SORT_1 var_536_arg_0 = var_473; [L1614] SORT_1 var_536_arg_1 = state_47; [L1615] SORT_1 var_536 = var_536_arg_0 == var_536_arg_1; [L1616] SORT_1 var_537_arg_0 = var_535; [L1617] SORT_1 var_537_arg_1 = var_536; [L1618] SORT_1 var_537 = var_537_arg_0 & var_537_arg_1; [L1619] SORT_1 var_538_arg_0 = var_477; [L1620] SORT_1 var_538_arg_1 = state_49; [L1621] SORT_1 var_538 = var_538_arg_0 == var_538_arg_1; [L1622] SORT_1 var_539_arg_0 = var_537; [L1623] SORT_1 var_539_arg_1 = var_538; [L1624] SORT_1 var_539 = var_539_arg_0 & var_539_arg_1; [L1625] SORT_1 var_540_arg_0 = var_483; [L1626] SORT_1 var_540_arg_1 = state_51; [L1627] SORT_1 var_540 = var_540_arg_0 == var_540_arg_1; [L1628] SORT_1 var_541_arg_0 = var_539; [L1629] SORT_1 var_541_arg_1 = var_540; [L1630] SORT_1 var_541 = var_541_arg_0 & var_541_arg_1; [L1631] SORT_1 var_542_arg_0 = var_487; [L1632] SORT_1 var_542_arg_1 = state_53; [L1633] SORT_1 var_542 = var_542_arg_0 == var_542_arg_1; [L1634] SORT_1 var_543_arg_0 = var_541; [L1635] SORT_1 var_543_arg_1 = var_542; [L1636] SORT_1 var_543 = var_543_arg_0 & var_543_arg_1; [L1637] SORT_1 var_544_arg_0 = var_543; [L1638] SORT_1 var_544_arg_1 = state_57; [L1639] SORT_1 var_544 = var_544_arg_0 & var_544_arg_1; [L1640] SORT_1 var_545_arg_0 = input_115; [L1641] SORT_4 var_545_arg_1 = var_140; [L1642] SORT_4 var_545_arg_2 = var_167; [L1643] EXPR var_545_arg_0 ? var_545_arg_1 : var_545_arg_2 [L1643] SORT_4 var_545 = var_545_arg_0 ? var_545_arg_1 : var_545_arg_2; [L1644] var_545 = var_545 & mask_SORT_4 [L1645] SORT_4 var_546_arg_0 = var_140; [L1646] SORT_4 var_546_arg_1 = var_545; [L1647] SORT_1 var_546 = var_546_arg_0 == var_546_arg_1; [L1648] SORT_4 var_547_arg_0 = var_167; [L1649] SORT_4 var_547_arg_1 = var_227; [L1650] SORT_1 var_547 = var_547_arg_0 == var_547_arg_1; [L1651] SORT_1 var_548_arg_0 = var_546; [L1652] SORT_1 var_548_arg_1 = ~var_547; [L1653] var_548_arg_1 = var_548_arg_1 & mask_SORT_1 [L1654] SORT_1 var_548 = var_548_arg_0 & var_548_arg_1; [L1655] SORT_1 var_549_arg_0 = state_55; [L1656] SORT_1 var_549_arg_1 = var_544; [L1657] SORT_1 var_549_arg_2 = var_548; [L1658] EXPR var_549_arg_0 ? var_549_arg_1 : var_549_arg_2 [L1658] SORT_1 var_549 = var_549_arg_0 ? var_549_arg_1 : var_549_arg_2; [L1659] SORT_1 next_550_arg_1 = var_549; [L1661] state_6 = next_90_arg_1 [L1662] state_8 = next_92_arg_1 [L1663] state_10 = next_94_arg_1 [L1664] state_12 = next_96_arg_1 [L1665] state_15 = next_98_arg_1 [L1666] state_17 = next_100_arg_1 [L1667] state_19 = next_102_arg_1 [L1668] state_21 = next_104_arg_1 [L1669] state_23 = next_106_arg_1 [L1670] state_25 = next_108_arg_1 [L1671] state_27 = next_110_arg_1 [L1672] state_29 = next_112_arg_1 [L1673] state_31 = next_114_arg_1 [L1674] state_33 = next_116_arg_1 [L1675] state_35 = next_118_arg_1 [L1676] state_37 = next_120_arg_1 [L1677] state_39 = next_122_arg_1 [L1678] state_41 = next_124_arg_1 [L1679] state_43 = next_126_arg_1 [L1680] state_45 = next_128_arg_1 [L1681] state_47 = next_130_arg_1 [L1682] state_49 = next_132_arg_1 [L1683] state_51 = next_134_arg_1 [L1684] state_53 = next_136_arg_1 [L1685] state_55 = next_138_arg_1 [L1686] state_57 = next_550_arg_1 VAL [bad_88_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_16_arg_1=0, init_18_arg_1=0, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_101=0, input_103=1, input_105=1, input_107=1, input_109=1, input_111=1, input_113=1, input_115=1, input_117=0, input_119=1, input_121=1, input_123=1, input_125=0, input_127=1, input_129=0, input_131=1, input_133=1, input_135=0, input_139=2, input_148=1, input_158=1, input_162=0, input_165=2, input_177=0, input_180=0, input_204=0, input_214=0, input_224=1, input_232=1, input_244=0, input_247=7, input_260=2, input_267=251, input_271=0, input_275=2, input_281=3, input_284=1, input_288=2, input_292=1, input_296=0, input_299=2, input_314=248, input_319=248, input_325=15, input_89=0, input_91=0, input_93=0, input_95=0, input_97=1, input_99=1, mask_SORT_1=1, mask_SORT_2=31, mask_SORT_3=65535, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=16, msb_SORT_3=32768, msb_SORT_4=2147483648, next_100_arg_1=1, next_102_arg_1=0, next_104_arg_1=1, next_106_arg_1=1, next_108_arg_1=1, next_110_arg_1=1, next_112_arg_1=1, next_114_arg_1=1, next_116_arg_1=1, next_118_arg_1=0, next_120_arg_1=1, next_122_arg_1=1, next_124_arg_1=1, next_126_arg_1=0, next_128_arg_1=1, next_130_arg_1=0, next_132_arg_1=1, next_134_arg_1=1, next_136_arg_1=0, next_138_arg_1=1, next_550_arg_1=1, next_90_arg_1=0, next_92_arg_1=0, next_94_arg_1=0, next_96_arg_1=0, next_98_arg_1=1, state_10=0, state_12=0, state_15=1, state_17=1, state_19=0, state_21=1, state_23=1, state_25=1, state_27=1, state_29=1, state_31=1, state_33=1, state_35=0, state_37=1, state_39=1, state_41=1, state_43=0, state_45=1, state_47=0, state_49=1, state_51=1, state_53=0, state_55=1, state_57=1, state_6=0, state_8=0, var_137=1, var_14=0, var_140=1, var_141=0, var_142=0, var_142_arg_0=0, var_142_arg_1=0, var_143=16, var_144=1, var_144_arg_0=0, var_144_arg_1=16, var_145=1, var_145_arg_0=1, var_145_arg_1=1, var_146=1, var_146_arg_0=1, var_146_arg_1=1, var_147=1, var_147_arg_0=1, var_147_arg_1=1, var_149=73, var_149_arg_0=1, var_149_arg_1=2, var_150=6200, var_151=0, var_151_arg_0=0, var_151_arg_1=0, var_152=65545, var_152_arg_0=0, var_152_arg_1=16, var_153=1, var_153_arg_0=6200, var_153_arg_1=65545, var_154=1, var_154_arg_0=1, var_154_arg_1=1, var_155=1, var_155_arg_0=73, var_155_arg_1=1, var_156=1, var_156_arg_0=0, var_156_arg_1=1, var_157=1, var_157_arg_0=1, var_157_arg_1=1, var_159=1, var_159_arg_0=0, var_159_arg_1=1, var_160=1, var_160_arg_0=1, var_160_arg_1=1, var_161=30, var_161_arg_0=73, var_161_arg_1=1, var_163=30, var_163_arg_0=30, var_163_arg_1=0, var_164=0, var_164_arg_0=1, var_164_arg_1=30, var_166=1, var_166_arg_0=1, var_166_arg_1=1, var_167=0, var_168=1, var_169=1, var_169_arg_0=1, var_169_arg_1=1, var_169_arg_2=0, var_170=1, var_170_arg_0=0, var_170_arg_1=0, var_170_arg_2=1, var_171=0, var_171_arg_0=1, var_171_arg_1=0, var_172=4294967294, var_172_arg_0=2147483649, var_172_arg_1=16, var_173=0, var_173_arg_0=0, var_173_arg_1=4294967294, var_174=0, var_174_arg_0=1, var_174_arg_1=0, var_175=0, var_175_arg_0=0, var_175_arg_1=0, var_176=0, var_176_arg_0=0, var_176_arg_1=0, var_178=1, var_178_arg_0=1, var_178_arg_1=0, var_179=0, var_179_arg_0=0, var_179_arg_1=1, var_181=65546, var_181_arg_0=1, var_181_arg_1=65545, var_182=10, var_182_arg_0=65546, var_183=10, var_183_arg_0=1, var_183_arg_1=10, var_183_arg_2=0, var_184=655360, var_184_arg_0=10, var_184_arg_1=0, var_185=4294770728, var_185_arg_0=0, var_185_arg_1=16, var_186=4294770727, var_186_arg_0=4294770728, var_186_arg_1=1, var_187=39, var_187_arg_0=4294770727, var_188=39, var_188_arg_0=1, var_188_arg_1=39, var_188_arg_2=10, var_189=2555904, var_189_arg_0=39, var_189_arg_1=0, var_190=2050, var_190_arg_0=4294967295, var_190_arg_1=16, var_191=2049, var_191_arg_0=2050, var_191_arg_1=1, var_192=2049, var_192_arg_0=2049, var_193=39, var_193_arg_0=0, var_193_arg_1=2049, var_193_arg_2=39, var_194=1, var_194_arg_0=39, var_194_arg_1=0, var_195=0, var_195_arg_0=4294967295, var_195_arg_1=16, var_196=999, var_197=1, var_197_arg_0=0, var_197_arg_1=999, var_198=5999, var_199=0, var_199_arg_0=5999, var_199_arg_1=0, var_200=1, var_200_arg_0=1, var_200_arg_1=1, var_201=1, var_201_arg_0=1, var_201_arg_1=1, var_202=1, var_202_arg_0=1, var_202_arg_1=1, var_203=0, var_203_arg_0=0, var_203_arg_1=1, var_205=1, var_205_arg_0=1, var_205_arg_1=1, var_206=1000, var_207=39, var_207_arg_0=0, var_207_arg_1=0, var_207_arg_2=39, var_208=0, var_208_arg_0=39, var_208_arg_1=0, var_209=0, var_209_arg_0=0, var_209_arg_1=16, var_210=0, var_210_arg_0=1000, var_210_arg_1=0, var_211=0, var_211_arg_0=1, var_211_arg_1=0, var_212=0, var_212_arg_0=0, var_212_arg_1=0, var_213=0, var_213_arg_0=0, var_213_arg_1=0, var_215=1, var_215_arg_0=1, var_215_arg_1=1, var_216=39, var_216_arg_0=0, var_216_arg_1=0, var_216_arg_2=39, var_217=0, var_217_arg_0=39, var_217_arg_1=0, var_218=0, var_218_arg_0=0, var_218_arg_1=16, var_219=5800, var_220=1, var_220_arg_0=0, var_220_arg_1=5800, var_221=0, var_221_arg_0=1, var_221_arg_1=0, var_222=0, var_222_arg_0=0, var_222_arg_1=0, var_223=0, var_223_arg_0=0, var_223_arg_1=0, var_225=1, var_225_arg_0=1, var_225_arg_1=0, var_226=0, var_226_arg_0=0, var_226_arg_1=0, var_227=65536, var_227_arg_0=0, var_227_arg_1=16, var_228=0, var_228_arg_0=65536, var_228_arg_1=0, var_229=0, var_229_arg_0=1, var_229_arg_1=0, var_230=0, var_230_arg_0=0, var_230_arg_1=0, var_231=0, var_231_arg_0=0, var_231_arg_1=0, var_233=1, var_233_arg_0=1, var_233_arg_1=0, var_234=5, var_235=65535, var_235_arg_0=65536, var_235_arg_1=1, var_236=65535, var_236_arg_0=65535, var_237=65535, var_237_arg_0=1, var_237_arg_1=65535, var_237_arg_2=0, var_238=0, var_238_arg_0=65535, var_238_arg_1=0, var_239=131071, var_239_arg_0=0, var_239_arg_1=16, var_240=1, var_240_arg_0=5, var_240_arg_1=131071, var_241=0, var_241_arg_0=1, var_241_arg_1=0, var_242=1, var_242_arg_0=1, var_242_arg_1=0, var_243=0, var_243_arg_0=0, var_243_arg_1=1, var_245=1, var_245_arg_0=1, var_245_arg_1=1, var_246=0, var_246_arg_0=0, var_246_arg_1=1, var_248=1, var_248_arg_0=1, var_248_arg_1=1, var_249=3, var_250=131072, var_250_arg_0=1, var_250_arg_1=131071, var_251=0, var_251_arg_0=131072, var_252=0, var_252_arg_0=1, var_252_arg_1=0, var_252_arg_2=65535, var_253=0, var_253_arg_0=0, var_253_arg_1=3, var_253_arg_2=0, var_254=0, var_254_arg_0=0, var_254_arg_1=0, var_255=5, var_255_arg_0=0, var_255_arg_1=16, var_256=0, var_256_arg_0=0, var_256_arg_1=5, var_257=0, var_257_arg_0=1, var_257_arg_1=0, var_258=1, var_258_arg_0=1, var_258_arg_1=0, var_259=0, var_259_arg_0=0, var_259_arg_1=1, var_261=0, var_261_arg_0=1, var_261_arg_1=0, var_262=1, var_262_arg_0=5, var_262_arg_1=5, var_263=0, var_263_arg_0=0, var_263_arg_1=1, var_264=1, var_264_arg_0=1, var_264_arg_1=0, var_265=0, var_265_arg_0=0, var_265_arg_1=1, var_266=0, var_266_arg_0=1, var_266_arg_1=7, var_268=1, var_268_arg_0=0, var_268_arg_1=1, var_269=0, var_269_arg_0=0, var_269_arg_1=1, var_270=2, var_270_arg_0=0, var_270_arg_1=2, var_272=1, var_272_arg_0=2, var_272_arg_1=1, var_273=0, var_273_arg_0=0, var_273_arg_1=1, var_274=1, var_274_arg_0=1, var_274_arg_1=0, var_276=1, var_276_arg_0=1, var_276_arg_1=0, var_277=0, var_277_arg_0=0, var_277_arg_1=1, var_278=13, var_278_arg_0=1, var_278_arg_1=251, var_279=0, var_279_arg_0=13, var_279_arg_1=0, var_280=16, var_280_arg_0=0, var_280_arg_1=2, var_282=52, var_282_arg_0=16, var_282_arg_1=1, var_283=0, var_283_arg_0=0, var_283_arg_1=52, var_285=1, var_285_arg_0=1, var_285_arg_1=0, var_286=0, var_286_arg_0=0, var_286_arg_1=1, var_287=1, var_287_arg_0=1, var_287_arg_1=1, var_289=1, var_289_arg_0=1, var_289_arg_1=1, var_290=0, var_290_arg_0=0, var_290_arg_1=1, var_291=1, var_291_arg_0=0, var_291_arg_1=1, var_293=1, var_293_arg_0=1, var_293_arg_1=1, var_294=0, var_294_arg_0=0, var_294_arg_1=1, var_295=1, var_295_arg_0=1, var_295_arg_1=1, var_297=1, var_297_arg_0=1, var_297_arg_1=1, var_298=0, var_298_arg_0=0, var_298_arg_1=1, var_300=0, var_300_arg_0=30, var_300_arg_1=1, var_301=0, var_301_arg_0=0, var_301_arg_1=0, var_302=1, var_302_arg_0=1, var_302_arg_1=1, var_303=1, var_303_arg_0=1, var_303_arg_1=1, var_304=1, var_304_arg_0=1, var_304_arg_1=0, var_305=0, var_305_arg_0=0, var_305_arg_1=1, var_306=1, var_306_arg_0=0, var_306_arg_1=1, var_306_arg_2=1, var_307=1, var_307_arg_0=1, var_307_arg_1=1, var_307_arg_2=1, var_308=0, var_308_arg_0=1, var_308_arg_1=0, var_309=0, var_309_arg_0=0, var_309_arg_1=16, var_310=0, var_310_arg_0=1, var_310_arg_1=0, var_311=0, var_311_arg_0=0, var_311_arg_1=0, var_312=0, var_312_arg_0=0, var_312_arg_1=0, var_313=0, var_313_arg_0=0, var_313_arg_1=0, var_315=1, var_315_arg_0=1, var_315_arg_1=2, var_316=1, var_316_arg_0=1, var_316_arg_1=1, var_317=1, var_317_arg_0=0, var_317_arg_1=1, var_318=0, var_318_arg_0=0, var_318_arg_1=1, var_320=1, var_320_arg_0=0, var_320_arg_1=1, var_321=248, var_321_arg_0=0, var_321_arg_1=248, var_322=0, var_322_arg_0=1, var_322_arg_1=248, var_323=1, var_323_arg_0=1, var_323_arg_1=0, var_324=0, var_324_arg_0=0, var_324_arg_1=1, var_326=1, var_326_arg_0=1, var_326_arg_1=2, var_327=1, var_327_arg_0=1, var_327_arg_1=0, var_328=0, var_328_arg_0=248, var_328_arg_1=1, var_329=0, var_329_arg_0=1, var_329_arg_1=0, var_330=0, var_330_arg_0=0, var_330_arg_1=0, var_331=0, var_331_arg_0=0, var_331_arg_1=0, var_332=2, var_332_arg_0=2, var_332_arg_1=1, var_333=2, var_333_arg_0=1, var_333_arg_1=2, var_334=1, var_334_arg_0=0, var_334_arg_1=2, var_335=49, var_335_arg_0=2, var_335_arg_1=1, var_336=19, var_336_arg_0=0, var_336_arg_1=49, var_337=17, var_337_arg_0=0, var_337_arg_1=19, var_338=1, var_338_arg_0=0, var_338_arg_1=17, var_339=1, var_339_arg_0=0, var_339_arg_1=1, var_340=1, var_340_arg_0=1, var_340_arg_1=1, var_341=1, var_341_arg_0=1, var_341_arg_1=1, var_342=1, var_342_arg_0=0, var_342_arg_1=1, var_343=0, var_343_arg_0=7, var_343_arg_1=1, var_344=1, var_344_arg_0=2, var_344_arg_1=0, var_345=251, var_345_arg_0=251, var_345_arg_1=1, var_346=23, var_346_arg_0=0, var_346_arg_1=251, var_347=1, var_347_arg_0=2, var_347_arg_1=23, var_348=21, var_348_arg_0=3, var_348_arg_1=1, var_349=1, var_349_arg_0=1, var_349_arg_1=21, var_350=2, var_350_arg_0=2, var_350_arg_1=1, var_351=2, var_351_arg_0=1, var_351_arg_1=2, var_352=2, var_352_arg_0=0, var_352_arg_1=2, var_353=29, var_353_arg_0=2, var_353_arg_1=2, var_354=248, var_354_arg_0=248, var_354_arg_1=29, var_355=248, var_355_arg_0=248, var_355_arg_1=248, var_356=0, var_356_arg_0=15, var_356_arg_1=248, var_357=0, var_357_arg_0=0, var_357_arg_1=0, var_358=1, var_358_arg_0=1, var_358_arg_1=1, var_359=1, var_359_arg_0=1, var_359_arg_1=1, var_360=0, var_360_arg_0=0, var_360_arg_1=1, var_361=1, var_361_arg_0=1, var_361_arg_1=0, var_362=1, var_362_arg_0=0, var_362_arg_1=1, var_363=1, var_363_arg_0=1, var_363_arg_1=1, var_364=1, var_364_arg_0=1, var_364_arg_1=1, var_365=1, var_365_arg_0=1, var_365_arg_1=1, var_366=1, var_366_arg_0=1, var_366_arg_1=1, var_367=1, var_367_arg_0=1, var_367_arg_1=1, var_368=1, var_368_arg_0=1, var_368_arg_1=1, var_369=1, var_369_arg_0=1, var_369_arg_1=1, var_370=1, var_370_arg_0=1, var_370_arg_1=1, var_371=1, var_371_arg_0=1, var_371_arg_1=1, var_372=1, var_372_arg_0=1, var_372_arg_1=1, var_373=1, var_373_arg_0=1, var_373_arg_1=1, var_374=1, var_374_arg_0=1, var_374_arg_1=1, var_375=1, var_375_arg_0=1, var_375_arg_1=1, var_376=1, var_376_arg_0=1, var_376_arg_1=1, var_377=1, var_377_arg_0=1, var_377_arg_1=1, var_378=1, var_378_arg_0=1, var_378_arg_1=1, var_379=1, var_379_arg_0=1, var_379_arg_1=1, var_380=1, var_380_arg_0=1, var_380_arg_1=1, var_381=0, var_381_arg_0=0, var_381_arg_1=1, var_382=1, var_382_arg_0=1, var_382_arg_1=0, var_383=1, var_383_arg_0=0, var_383_arg_1=1, var_384=1, var_384_arg_0=1, var_384_arg_1=1, var_385=1, var_385_arg_0=1, var_385_arg_1=1, var_386=1, var_386_arg_0=1, var_386_arg_1=1, var_387=1, var_387_arg_0=1, var_387_arg_1=1, var_388=1, var_388_arg_0=1, var_388_arg_1=1, var_389=1, var_389_arg_0=1, var_389_arg_1=1, var_390=1, var_390_arg_0=1, var_390_arg_1=1, var_391=1, var_391_arg_0=1, var_391_arg_1=1, var_392=1, var_392_arg_0=1, var_392_arg_1=1, var_393=0, var_393_arg_0=0, var_393_arg_1=1, var_394=1, var_394_arg_0=1, var_394_arg_1=0, var_395=1, var_395_arg_0=1, var_395_arg_1=1, var_396=1, var_396_arg_0=0, var_396_arg_1=1, var_397=1, var_397_arg_0=1, var_397_arg_1=1, var_398=0, var_398_arg_0=1, var_398_arg_1=0, var_399=1, var_399_arg_0=1, var_399_arg_1=0, var_400=1, var_400_arg_0=1, var_400_arg_1=1, var_401=1, var_401_arg_0=0, var_401_arg_1=1, var_402=1, var_402_arg_0=1, var_402_arg_1=1, var_403=1, var_403_arg_0=1, var_403_arg_1=1, var_404=1, var_404_arg_0=1, var_404_arg_1=1, var_405=1, var_405_arg_0=1, var_405_arg_1=1, var_406=0, var_406_arg_0=0, var_406_arg_1=1, var_407=1, var_407_arg_0=1, var_407_arg_1=0, var_408=0, var_408_arg_0=1, var_408_arg_1=0, var_409=1, var_409_arg_0=0, var_409_arg_1=1, var_410=0, var_410_arg_0=0, var_410_arg_1=1, var_411=0, var_411_arg_0=0, var_411_arg_1=0, var_412=0, var_412_arg_0=0, var_412_arg_1=1, var_413=1, var_413_arg_0=1, var_413_arg_1=1, var_414=0, var_414_arg_0=1, var_414_arg_1=2, var_415=0, var_415_arg_0=0, var_415_arg_1=0, var_416=0, var_416_arg_0=0, var_416_arg_1=1, var_417=0, var_417_arg_0=0, var_417_arg_1=0, var_418=1, var_418_arg_0=0, var_418_arg_1=2, var_419=0, var_419_arg_0=0, var_419_arg_1=0, var_420=0, var_420_arg_0=1, var_420_arg_1=0, var_421=0, var_421_arg_0=0, var_421_arg_1=0, var_422=1, var_422_arg_0=1, var_422_arg_1=1, var_423=1, var_423_arg_0=1, var_423_arg_1=0, var_424=1, var_424_arg_0=1, var_424_arg_1=1, var_425=1, var_425_arg_0=0, var_425_arg_1=1, var_426=1, var_426_arg_0=1, var_426_arg_1=1, var_427=1, var_427_arg_0=1, var_427_arg_1=1, var_428=0, var_428_arg_0=1, var_428_arg_1=0, var_429=0, var_429_arg_0=1, var_429_arg_1=0, var_430=0, var_430_arg_0=0, var_430_arg_1=248, var_431=0, var_431_arg_0=0, var_431_arg_1=0, var_432=1, var_432_arg_0=1, var_432_arg_1=1, var_433=0, var_433_arg_0=0, var_433_arg_1=0, var_434=0, var_434_arg_0=1, var_434_arg_1=0, var_435=0, var_435_arg_0=0, var_435_arg_1=0, var_436=0, var_436_arg_0=1, var_436_arg_1=0, var_437=1, var_437_arg_0=1, var_437_arg_1=0, var_438=0, var_438_arg_0=0, var_438_arg_1=1, var_439=0, var_439_arg_0=0, var_439_arg_1=0, var_440=0, var_440_arg_0=0, var_440_arg_1=1, var_441=0, var_441_arg_0=0, var_441_arg_1=15, var_442=1, var_442_arg_0=0, var_442_arg_1=1, var_443=0, var_443_arg_0=0, var_443_arg_1=1, var_444=0, var_444_arg_0=0, var_444_arg_1=0, var_445=0, var_445_arg_0=0, var_445_arg_1=0, var_446=1, var_446_arg_0=0, var_446_arg_1=1, var_447=0, var_447_arg_0=0, var_447_arg_1=1, var_448=0, var_448_arg_0=0, var_448_arg_1=0, var_449=0, var_449_arg_0=2, var_449_arg_1=1, var_450=1, var_450_arg_0=0, var_450_arg_1=1, var_451=0, var_451_arg_0=0, var_451_arg_1=1, var_452=0, var_452_arg_0=0, var_452_arg_1=0, var_453=0, var_453_arg_0=1, var_453_arg_1=0, var_454=1, var_454_arg_0=0, var_454_arg_1=3, var_455=1, var_455_arg_0=0, var_455_arg_1=1, var_456=1, var_456_arg_0=1, var_456_arg_1=1, var_457=1, var_457_arg_0=0, var_457_arg_1=1, var_458=0, var_458_arg_0=16, var_458_arg_1=1, var_459=1, var_459_arg_0=1, var_459_arg_1=1, var_460=0, var_460_arg_0=0, var_460_arg_1=1, var_461=1, var_461_arg_0=1, var_461_arg_1=0, var_462=1, var_462_arg_0=1, var_462_arg_1=1, var_463=1, var_463_arg_0=0, var_463_arg_1=1, var_464=1, var_464_arg_0=1, var_464_arg_1=1, var_465=1, var_465_arg_0=1, var_465_arg_1=1, var_466=0, var_466_arg_0=0, var_466_arg_1=1, var_467=1, var_467_arg_0=1, var_467_arg_1=1, var_468=0, var_468_arg_0=0, var_468_arg_1=1, var_469=1, var_469_arg_0=1, var_469_arg_1=0, var_470=1, var_470_arg_0=1, var_470_arg_1=1, var_471=1, var_471_arg_0=0, var_471_arg_1=1, var_472=1, var_472_arg_0=1, var_472_arg_1=1, var_473=1, var_473_arg_0=1, var_473_arg_1=1, var_474=0, var_474_arg_0=1, var_474_arg_1=0, var_475=1, var_475_arg_0=0, var_475_arg_1=248, var_476=1, var_476_arg_0=1, var_476_arg_1=1, var_477=1, var_477_arg_0=1, var_477_arg_1=1, var_478=1, var_478_arg_0=1, var_478_arg_1=1, var_479=1, var_479_arg_0=1, var_479_arg_1=1, var_480=1, var_480_arg_0=1, var_480_arg_1=1, var_481=0, var_481_arg_0=1, var_481_arg_1=0, var_482=0, var_482_arg_0=0, var_482_arg_1=248, var_483=1, var_483_arg_0=0, var_483_arg_1=15, var_484=1, var_484_arg_0=1, var_484_arg_1=1, var_485=1, var_485_arg_0=1, var_485_arg_1=1, var_486=1, var_486_arg_0=1, var_486_arg_1=1, var_487=1, var_487_arg_0=1, var_487_arg_1=1, var_488=1, var_488_arg_0=1, var_488_arg_1=1, var_489=1, var_489_arg_0=1, var_489_arg_1=1, var_490=1, var_490_arg_0=1, var_490_arg_1=1, var_491=0, var_491_arg_0=1, var_491_arg_1=0, var_492=1, var_492_arg_0=1, var_492_arg_1=1, var_493=0, var_493_arg_0=0, var_493_arg_1=1, var_494=0, var_494_arg_0=0, var_494_arg_1=0, var_495=0, var_495_arg_0=1, var_495_arg_1=0, var_496=0, var_496_arg_0=0, var_496_arg_1=0, var_497=39, var_497_arg_0=0, var_497_arg_1=0, var_497_arg_2=39, var_498=0, var_498_arg_0=39, var_498_arg_1=0, var_499=0, var_499_arg_0=0, var_499_arg_1=0, var_5=0, var_500=1, var_500_arg_0=0, var_500_arg_1=0, var_501=0, var_501_arg_0=0, var_501_arg_1=1, var_502=1, var_502_arg_0=0, var_502_arg_1=0, var_503=0, var_503_arg_0=0, var_503_arg_1=1, var_504=1, var_504_arg_0=0, var_504_arg_1=0, var_505=0, var_505_arg_0=0, var_505_arg_1=1, var_506=1, var_506_arg_0=0, var_506_arg_1=0, var_507=0, var_507_arg_0=0, var_507_arg_1=1, var_508=0, var_508_arg_0=1, var_508_arg_1=0, var_509=0, var_509_arg_0=0, var_509_arg_1=0, var_510=0, var_510_arg_0=1, var_510_arg_1=0, var_511=0, var_511_arg_0=0, var_511_arg_1=0, var_512=1, var_512_arg_0=0, var_512_arg_1=0, var_513=0, var_513_arg_0=0, var_513_arg_1=1, var_514=1, var_514_arg_0=0, var_514_arg_1=0, var_515=0, var_515_arg_0=0, var_515_arg_1=1, var_516=0, var_516_arg_0=1, var_516_arg_1=0, var_517=0, var_517_arg_0=0, var_517_arg_1=0, var_518=1, var_518_arg_0=0, var_518_arg_1=0, var_519=0, var_519_arg_0=0, var_519_arg_1=1, var_520=1, var_520_arg_0=0, var_520_arg_1=0, var_521=0, var_521_arg_0=0, var_521_arg_1=1, var_522=1, var_522_arg_0=0, var_522_arg_1=0, var_523=0, var_523_arg_0=0, var_523_arg_1=1, var_524=1, var_524_arg_0=0, var_524_arg_1=0, var_525=0, var_525_arg_0=0, var_525_arg_1=1, var_526=0, var_526_arg_0=1, var_526_arg_1=0, var_527=0, var_527_arg_0=0, var_527_arg_1=0, var_528=1, var_528_arg_0=0, var_528_arg_1=0, var_529=0, var_529_arg_0=0, var_529_arg_1=1, var_530=0, var_530_arg_0=1, var_530_arg_1=0, var_531=0, var_531_arg_0=0, var_531_arg_1=0, var_532=1, var_532_arg_0=0, var_532_arg_1=0, var_533=0, var_533_arg_0=0, var_533_arg_1=1, var_534=0, var_534_arg_0=1, var_534_arg_1=0, var_535=0, var_535_arg_0=0, var_535_arg_1=0, var_536=0, var_536_arg_0=1, var_536_arg_1=0, var_537=0, var_537_arg_0=0, var_537_arg_1=0, var_538=0, var_538_arg_0=1, var_538_arg_1=0, var_539=0, var_539_arg_0=0, var_539_arg_1=0, var_540=0, var_540_arg_0=1, var_540_arg_1=0, var_541=0, var_541_arg_0=0, var_541_arg_1=0, var_542=0, var_542_arg_0=1, var_542_arg_1=0, var_543=0, var_543_arg_0=0, var_543_arg_1=0, var_544=0, var_544_arg_0=0, var_544_arg_1=0, var_545=1, var_545_arg_0=1, var_545_arg_1=1, var_545_arg_2=0, var_546=1, var_546_arg_0=1, var_546_arg_1=1, var_547=0, var_547_arg_0=0, var_547_arg_1=65536, var_548=1, var_548_arg_0=1, var_548_arg_1=1, var_549=1, var_549_arg_0=0, var_549_arg_1=0, var_549_arg_2=1, var_59=0, var_59_arg_0=1, var_59_arg_1=0, var_60=0, var_60_arg_0=0, var_60_arg_1=0, var_61=0, var_61_arg_0=0, var_61_arg_1=0, var_62=0, var_62_arg_0=0, var_62_arg_1=1, var_63=0, var_63_arg_0=0, var_63_arg_1=0, var_64=0, var_64_arg_0=0, var_64_arg_1=1, var_65=0, var_65_arg_0=0, var_65_arg_1=0, var_66=0, var_66_arg_0=0, var_66_arg_1=0, var_67=0, var_67_arg_0=0, var_67_arg_1=0, var_68=0, var_68_arg_0=0, var_68_arg_1=0, var_69=0, var_69_arg_0=0, var_69_arg_1=0, var_70=0, var_70_arg_0=0, var_70_arg_1=1, var_71=0, var_71_arg_0=0, var_71_arg_1=0, var_72=0, var_72_arg_0=0, var_72_arg_1=1, var_73=0, var_73_arg_0=0, var_73_arg_1=1, var_74=0, var_74_arg_0=0, var_74_arg_1=1, var_75=0, var_75_arg_0=0, var_75_arg_1=1, var_76=0, var_76_arg_0=0, var_76_arg_1=0, var_77=0, var_77_arg_0=0, var_77_arg_1=0, var_78=0, var_79=1, var_79_arg_0=0, var_79_arg_1=0, var_80=0, var_80_arg_0=0, var_80_arg_1=1, var_81=1, var_81_arg_0=0, var_81_arg_1=0, var_82=0, var_82_arg_0=0, var_82_arg_1=1, var_83=1, var_83_arg_0=0, var_83_arg_1=0, var_84=0, var_84_arg_0=0, var_84_arg_1=1, var_85=1, var_85_arg_0=0, var_85_arg_1=0, var_86=0, var_86_arg_0=0, var_86_arg_1=1, var_87=0, var_87_arg_0=0, var_87_arg_1=0] [L186] input_89 = __VERIFIER_nondet_ushort() [L187] input_89 = input_89 & mask_SORT_3 [L188] input_91 = __VERIFIER_nondet_ushort() [L189] input_91 = input_91 & mask_SORT_3 [L190] input_93 = __VERIFIER_nondet_ushort() [L191] input_93 = input_93 & mask_SORT_3 [L192] input_95 = __VERIFIER_nondet_ushort() [L193] input_95 = input_95 & mask_SORT_3 [L194] input_97 = __VERIFIER_nondet_uchar() [L195] input_97 = input_97 & mask_SORT_1 [L196] input_99 = __VERIFIER_nondet_uchar() [L197] input_99 = input_99 & mask_SORT_1 [L198] input_101 = __VERIFIER_nondet_uchar() [L199] input_101 = input_101 & mask_SORT_1 [L200] input_103 = __VERIFIER_nondet_uchar() [L201] input_103 = input_103 & mask_SORT_1 [L202] input_105 = __VERIFIER_nondet_uchar() [L203] input_105 = input_105 & mask_SORT_1 [L204] input_107 = __VERIFIER_nondet_uchar() [L205] input_107 = input_107 & mask_SORT_1 [L206] input_109 = __VERIFIER_nondet_uchar() [L207] input_109 = input_109 & mask_SORT_1 [L208] input_111 = __VERIFIER_nondet_uchar() [L209] input_111 = input_111 & mask_SORT_1 [L210] input_113 = __VERIFIER_nondet_uchar() [L211] input_113 = input_113 & mask_SORT_1 [L212] input_115 = __VERIFIER_nondet_uchar() [L213] input_115 = input_115 & mask_SORT_1 [L214] input_117 = __VERIFIER_nondet_uchar() [L215] input_117 = input_117 & mask_SORT_1 [L216] input_119 = __VERIFIER_nondet_uchar() [L217] input_119 = input_119 & mask_SORT_1 [L218] input_121 = __VERIFIER_nondet_uchar() [L219] input_121 = input_121 & mask_SORT_1 [L220] input_123 = __VERIFIER_nondet_uchar() [L221] input_123 = input_123 & mask_SORT_1 [L222] input_125 = __VERIFIER_nondet_uchar() [L223] input_125 = input_125 & mask_SORT_1 [L224] input_127 = __VERIFIER_nondet_uchar() [L225] input_127 = input_127 & mask_SORT_1 [L226] input_129 = __VERIFIER_nondet_uchar() [L227] input_129 = input_129 & mask_SORT_1 [L228] input_131 = __VERIFIER_nondet_uchar() [L229] input_131 = input_131 & mask_SORT_1 [L230] input_133 = __VERIFIER_nondet_uchar() [L231] input_133 = input_133 & mask_SORT_1 [L232] input_135 = __VERIFIER_nondet_uchar() [L233] input_135 = input_135 & mask_SORT_1 [L234] input_139 = __VERIFIER_nondet_uchar() [L235] input_148 = __VERIFIER_nondet_uchar() [L236] input_148 = input_148 & mask_SORT_1 [L237] input_158 = __VERIFIER_nondet_uchar() [L238] input_158 = input_158 & mask_SORT_1 [L239] input_162 = __VERIFIER_nondet_uchar() [L240] input_162 = input_162 & mask_SORT_1 [L241] input_165 = __VERIFIER_nondet_uchar() [L242] input_177 = __VERIFIER_nondet_uchar() [L243] input_177 = input_177 & mask_SORT_1 [L244] input_180 = __VERIFIER_nondet_uchar() [L245] input_180 = input_180 & mask_SORT_1 [L246] input_204 = __VERIFIER_nondet_uchar() [L247] input_204 = input_204 & mask_SORT_1 [L248] input_214 = __VERIFIER_nondet_uchar() [L249] input_214 = input_214 & mask_SORT_1 [L250] input_224 = __VERIFIER_nondet_uchar() [L251] input_224 = input_224 & mask_SORT_1 [L252] input_232 = __VERIFIER_nondet_uchar() [L253] input_232 = input_232 & mask_SORT_1 [L254] input_244 = __VERIFIER_nondet_uchar() [L255] input_244 = input_244 & mask_SORT_1 [L256] input_247 = __VERIFIER_nondet_uchar() [L257] input_260 = __VERIFIER_nondet_uchar() [L258] input_267 = __VERIFIER_nondet_uchar() [L259] input_271 = __VERIFIER_nondet_uchar() [L260] input_275 = __VERIFIER_nondet_uchar() [L261] input_281 = __VERIFIER_nondet_uchar() [L262] input_284 = __VERIFIER_nondet_uchar() [L263] input_288 = __VERIFIER_nondet_uchar() [L264] input_292 = __VERIFIER_nondet_uchar() [L265] input_292 = input_292 & mask_SORT_1 [L266] input_296 = __VERIFIER_nondet_uchar() [L267] input_299 = __VERIFIER_nondet_uchar() [L268] input_314 = __VERIFIER_nondet_uchar() [L269] input_319 = __VERIFIER_nondet_uchar() [L270] input_325 = __VERIFIER_nondet_uchar() [L273] SORT_1 var_59_arg_0 = ~state_15; [L274] var_59_arg_0 = var_59_arg_0 & mask_SORT_1 [L275] SORT_1 var_59_arg_1 = ~state_17; [L276] var_59_arg_1 = var_59_arg_1 & mask_SORT_1 [L277] SORT_1 var_59 = var_59_arg_0 & var_59_arg_1; [L278] SORT_1 var_60_arg_0 = var_59; [L279] SORT_1 var_60_arg_1 = ~state_19; [L280] var_60_arg_1 = var_60_arg_1 & mask_SORT_1 [L281] SORT_1 var_60 = var_60_arg_0 & var_60_arg_1; [L282] SORT_1 var_61_arg_0 = var_60; [L283] SORT_1 var_61_arg_1 = state_21; [L284] SORT_1 var_61 = var_61_arg_0 & var_61_arg_1; [L285] SORT_1 var_62_arg_0 = var_61; [L286] SORT_1 var_62_arg_1 = ~state_23; [L287] var_62_arg_1 = var_62_arg_1 & mask_SORT_1 [L288] SORT_1 var_62 = var_62_arg_0 & var_62_arg_1; [L289] SORT_1 var_63_arg_0 = var_62; [L290] SORT_1 var_63_arg_1 = ~state_25; [L291] var_63_arg_1 = var_63_arg_1 & mask_SORT_1 [L292] SORT_1 var_63 = var_63_arg_0 & var_63_arg_1; [L293] SORT_1 var_64_arg_0 = var_63; [L294] SORT_1 var_64_arg_1 = ~state_27; [L295] var_64_arg_1 = var_64_arg_1 & mask_SORT_1 [L296] SORT_1 var_64 = var_64_arg_0 & var_64_arg_1; [L297] SORT_1 var_65_arg_0 = var_64; [L298] SORT_1 var_65_arg_1 = ~state_29; [L299] var_65_arg_1 = var_65_arg_1 & mask_SORT_1 [L300] SORT_1 var_65 = var_65_arg_0 & var_65_arg_1; [L301] SORT_1 var_66_arg_0 = var_65; [L302] SORT_1 var_66_arg_1 = ~state_31; [L303] var_66_arg_1 = var_66_arg_1 & mask_SORT_1 [L304] SORT_1 var_66 = var_66_arg_0 & var_66_arg_1; [L305] SORT_1 var_67_arg_0 = var_66; [L306] SORT_1 var_67_arg_1 = ~state_33; [L307] var_67_arg_1 = var_67_arg_1 & mask_SORT_1 [L308] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L309] SORT_1 var_68_arg_0 = var_67; [L310] SORT_1 var_68_arg_1 = ~state_35; [L311] var_68_arg_1 = var_68_arg_1 & mask_SORT_1 [L312] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L313] SORT_1 var_69_arg_0 = var_68; [L314] SORT_1 var_69_arg_1 = state_37; [L315] SORT_1 var_69 = var_69_arg_0 & var_69_arg_1; [L316] SORT_1 var_70_arg_0 = var_69; [L317] SORT_1 var_70_arg_1 = ~state_39; [L318] var_70_arg_1 = var_70_arg_1 & mask_SORT_1 [L319] SORT_1 var_70 = var_70_arg_0 & var_70_arg_1; [L320] SORT_1 var_71_arg_0 = var_70; [L321] SORT_1 var_71_arg_1 = ~state_41; [L322] var_71_arg_1 = var_71_arg_1 & mask_SORT_1 [L323] SORT_1 var_71 = var_71_arg_0 & var_71_arg_1; [L324] SORT_1 var_72_arg_0 = var_71; [L325] SORT_1 var_72_arg_1 = ~state_43; [L326] var_72_arg_1 = var_72_arg_1 & mask_SORT_1 [L327] SORT_1 var_72 = var_72_arg_0 & var_72_arg_1; [L328] SORT_1 var_73_arg_0 = var_72; [L329] SORT_1 var_73_arg_1 = ~state_45; [L330] var_73_arg_1 = var_73_arg_1 & mask_SORT_1 [L331] SORT_1 var_73 = var_73_arg_0 & var_73_arg_1; [L332] SORT_1 var_74_arg_0 = var_73; [L333] SORT_1 var_74_arg_1 = ~state_47; [L334] var_74_arg_1 = var_74_arg_1 & mask_SORT_1 [L335] SORT_1 var_74 = var_74_arg_0 & var_74_arg_1; [L336] SORT_1 var_75_arg_0 = var_74; [L337] SORT_1 var_75_arg_1 = ~state_49; [L338] var_75_arg_1 = var_75_arg_1 & mask_SORT_1 [L339] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L340] SORT_1 var_76_arg_0 = var_75; [L341] SORT_1 var_76_arg_1 = state_51; [L342] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L343] SORT_1 var_77_arg_0 = var_76; [L344] SORT_1 var_77_arg_1 = ~state_53; [L345] var_77_arg_1 = var_77_arg_1 & mask_SORT_1 [L346] SORT_1 var_77 = var_77_arg_0 & var_77_arg_1; [L347] SORT_3 var_79_arg_0 = var_78; [L348] SORT_3 var_79_arg_1 = state_6; [L349] SORT_1 var_79 = var_79_arg_0 == var_79_arg_1; [L350] SORT_1 var_80_arg_0 = var_77; [L351] SORT_1 var_80_arg_1 = var_79; [L352] SORT_1 var_80 = var_80_arg_0 & var_80_arg_1; [L353] SORT_3 var_81_arg_0 = var_78; [L354] SORT_3 var_81_arg_1 = state_8; [L355] SORT_1 var_81 = var_81_arg_0 == var_81_arg_1; [L356] SORT_1 var_82_arg_0 = var_80; [L357] SORT_1 var_82_arg_1 = var_81; [L358] SORT_1 var_82 = var_82_arg_0 & var_82_arg_1; [L359] SORT_3 var_83_arg_0 = var_78; [L360] SORT_3 var_83_arg_1 = state_10; [L361] SORT_1 var_83 = var_83_arg_0 == var_83_arg_1; [L362] SORT_1 var_84_arg_0 = var_82; [L363] SORT_1 var_84_arg_1 = var_83; [L364] SORT_1 var_84 = var_84_arg_0 & var_84_arg_1; [L365] SORT_3 var_85_arg_0 = var_78; [L366] SORT_3 var_85_arg_1 = state_12; [L367] SORT_1 var_85 = var_85_arg_0 == var_85_arg_1; [L368] SORT_1 var_86_arg_0 = var_84; [L369] SORT_1 var_86_arg_1 = var_85; [L370] SORT_1 var_86 = var_86_arg_0 & var_86_arg_1; [L371] SORT_1 var_87_arg_0 = state_57; [L372] SORT_1 var_87_arg_1 = var_86; [L373] SORT_1 var_87 = var_87_arg_0 & var_87_arg_1; [L374] var_87 = var_87 & mask_SORT_1 [L375] SORT_1 bad_88_arg_0 = var_87; [L376] CALL __VERIFIER_assert(!(bad_88_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 555.7s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 4.1s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 1 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 4.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 3.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 7 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 7 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 260.9s SatisfiabilityAnalysisTime, 6.0s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 8 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 01:56:01,743 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash e0b3b6b781ffc688dafba255fdda5ddb1bc0b2a1529746a3260ac898e37a723c --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 01:56:04,729 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 01:56:04,733 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 01:56:04,783 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 01:56:04,783 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 01:56:04,788 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 01:56:04,791 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 01:56:04,797 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 01:56:04,804 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 01:56:04,811 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 01:56:04,812 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 01:56:04,814 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 01:56:04,815 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 01:56:04,818 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 01:56:04,820 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 01:56:04,822 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 01:56:04,824 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 01:56:04,825 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 01:56:04,830 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 01:56:04,837 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 01:56:04,839 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 01:56:04,847 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 01:56:04,849 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 01:56:04,851 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 01:56:04,856 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 01:56:04,856 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 01:56:04,856 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 01:56:04,858 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 01:56:04,858 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 01:56:04,860 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 01:56:04,860 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 01:56:04,861 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 01:56:04,862 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 01:56:04,863 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 01:56:04,865 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 01:56:04,865 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 01:56:04,866 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 01:56:04,866 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 01:56:04,867 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 01:56:04,868 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 01:56:04,869 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 01:56:04,870 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 01:56:04,910 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 01:56:04,911 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 01:56:04,912 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 01:56:04,913 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 01:56:04,914 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 01:56:04,914 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 01:56:04,914 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 01:56:04,915 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 01:56:04,915 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 01:56:04,915 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 01:56:04,916 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 01:56:04,917 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 01:56:04,918 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 01:56:04,919 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 01:56:04,919 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 01:56:04,919 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 01:56:04,919 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 01:56:04,920 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 01:56:04,920 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 01:56:04,920 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 01:56:04,920 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 01:56:04,921 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 01:56:04,921 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 01:56:04,921 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 01:56:04,921 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 01:56:04,922 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 01:56:04,922 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 01:56:04,922 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 01:56:04,923 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 01:56:04,923 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 01:56:04,923 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 01:56:04,923 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 01:56:04,924 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 01:56:04,924 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 01:56:04,924 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 01:56:04,925 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0b3b6b781ffc688dafba255fdda5ddb1bc0b2a1529746a3260ac898e37a723c [2022-11-03 01:56:05,362 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 01:56:05,390 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 01:56:05,393 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 01:56:05,395 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 01:56:05,396 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 01:56:05,398 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:56:05,489 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/1eec5eaec/c29eab71273541aeaba1131cafc9cc9a/FLAG2d2841126 [2022-11-03 01:56:06,364 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 01:56:06,365 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:56:06,407 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/1eec5eaec/c29eab71273541aeaba1131cafc9cc9a/FLAG2d2841126 [2022-11-03 01:56:06,428 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/data/1eec5eaec/c29eab71273541aeaba1131cafc9cc9a [2022-11-03 01:56:06,432 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 01:56:06,434 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 01:56:06,452 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 01:56:06,452 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 01:56:06,457 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 01:56:06,458 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 01:56:06" (1/1) ... [2022-11-03 01:56:06,459 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67fd776 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:06, skipping insertion in model container [2022-11-03 01:56:06,459 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 01:56:06" (1/1) ... [2022-11-03 01:56:06,470 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 01:56:06,575 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 01:56:06,813 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c[1014,1027] [2022-11-03 01:56:07,318 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 01:56:07,338 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 01:56:07,374 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop2-back-serstep.c[1014,1027] [2022-11-03 01:56:07,607 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 01:56:07,620 INFO L208 MainTranslator]: Completed translation [2022-11-03 01:56:07,621 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07 WrapperNode [2022-11-03 01:56:07,621 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 01:56:07,622 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 01:56:07,622 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 01:56:07,623 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 01:56:07,630 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,667 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,781 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1894 [2022-11-03 01:56:07,782 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 01:56:07,783 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 01:56:07,783 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 01:56:07,783 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 01:56:07,795 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,796 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,810 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,811 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,905 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,930 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,938 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,965 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,982 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 01:56:07,983 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 01:56:07,983 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 01:56:07,984 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 01:56:07,985 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (1/1) ... [2022-11-03 01:56:07,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 01:56:08,005 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:56:08,020 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 01:56:08,058 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 01:56:08,087 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 01:56:08,088 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 01:56:08,652 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 01:56:08,656 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 01:56:10,636 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 01:56:10,644 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 01:56:10,647 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 01:56:10,650 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 01:56:10 BoogieIcfgContainer [2022-11-03 01:56:10,651 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 01:56:10,656 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 01:56:10,657 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 01:56:10,661 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 01:56:10,661 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 01:56:06" (1/3) ... [2022-11-03 01:56:10,662 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70a4fb52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 01:56:10, skipping insertion in model container [2022-11-03 01:56:10,662 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 01:56:07" (2/3) ... [2022-11-03 01:56:10,663 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@70a4fb52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 01:56:10, skipping insertion in model container [2022-11-03 01:56:10,663 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 01:56:10" (3/3) ... [2022-11-03 01:56:10,664 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.resistance.1.prop2-back-serstep.c [2022-11-03 01:56:10,687 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 01:56:10,687 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 01:56:10,777 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 01:56:10,784 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@6ec9d499, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 01:56:10,784 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 01:56:10,789 INFO L276 IsEmpty]: Start isEmpty. Operand has 89 states, 87 states have (on average 1.4942528735632183) internal successors, (130), 88 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:10,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 01:56:10,796 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:10,797 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 01:56:10,797 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:10,802 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:10,803 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 01:56:10,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:10,819 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [235805285] [2022-11-03 01:56:10,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:10,820 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:10,820 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:10,825 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:10,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 01:56:11,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:11,418 INFO L263 TraceCheckSpWp]: Trace formula consists of 218 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 01:56:11,435 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:11,536 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:11,537 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:11,538 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:11,538 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [235805285] [2022-11-03 01:56:11,539 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [235805285] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:11,539 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:11,539 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 01:56:11,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181836320] [2022-11-03 01:56:11,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:11,549 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 01:56:11,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:11,585 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 01:56:11,586 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 01:56:11,589 INFO L87 Difference]: Start difference. First operand has 89 states, 87 states have (on average 1.4942528735632183) internal successors, (130), 88 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:12,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:12,081 INFO L93 Difference]: Finished difference Result 254 states and 381 transitions. [2022-11-03 01:56:12,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:56:12,086 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 01:56:12,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:12,101 INFO L225 Difference]: With dead ends: 254 [2022-11-03 01:56:12,101 INFO L226 Difference]: Without dead ends: 167 [2022-11-03 01:56:12,112 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:12,116 INFO L413 NwaCegarLoop]: 111 mSDtfsCounter, 238 mSDsluCounter, 230 mSDsCounter, 0 mSdLazyCounter, 31 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 238 SdHoareTripleChecker+Valid, 341 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 31 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:12,118 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [238 Valid, 341 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 31 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 01:56:12,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2022-11-03 01:56:12,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 87. [2022-11-03 01:56:12,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 86 states have (on average 1.4651162790697674) internal successors, (126), 86 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:12,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 126 transitions. [2022-11-03 01:56:12,170 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 126 transitions. Word has length 5 [2022-11-03 01:56:12,170 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:12,171 INFO L495 AbstractCegarLoop]: Abstraction has 87 states and 126 transitions. [2022-11-03 01:56:12,171 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:12,171 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 126 transitions. [2022-11-03 01:56:12,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:12,174 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:12,175 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:12,197 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:12,394 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:12,395 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:12,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:12,396 INFO L85 PathProgramCache]: Analyzing trace with hash -779517679, now seen corresponding path program 1 times [2022-11-03 01:56:12,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:12,400 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1678242003] [2022-11-03 01:56:12,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:12,401 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:12,402 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:12,403 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:12,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 01:56:13,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:13,659 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:56:13,670 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:13,842 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:13,842 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:13,842 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:13,842 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1678242003] [2022-11-03 01:56:13,843 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1678242003] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:13,843 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:13,843 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 01:56:13,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493089444] [2022-11-03 01:56:13,844 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:13,845 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:56:13,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:13,848 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:56:13,850 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:13,851 INFO L87 Difference]: Start difference. First operand 87 states and 126 transitions. Second operand has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:14,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:14,035 INFO L93 Difference]: Finished difference Result 175 states and 255 transitions. [2022-11-03 01:56:14,036 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:56:14,037 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:14,037 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:14,038 INFO L225 Difference]: With dead ends: 175 [2022-11-03 01:56:14,038 INFO L226 Difference]: Without dead ends: 92 [2022-11-03 01:56:14,038 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:14,040 INFO L413 NwaCegarLoop]: 120 mSDtfsCounter, 2 mSDsluCounter, 79 mSDsCounter, 0 mSdLazyCounter, 49 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 2 SdHoareTripleChecker+Valid, 199 SdHoareTripleChecker+Invalid, 57 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 49 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 8 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:14,041 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [2 Valid, 199 Invalid, 57 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 49 Invalid, 0 Unknown, 8 Unchecked, 0.2s Time] [2022-11-03 01:56:14,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2022-11-03 01:56:14,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 91. [2022-11-03 01:56:14,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 90 states have (on average 1.4555555555555555) internal successors, (131), 90 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:14,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 131 transitions. [2022-11-03 01:56:14,050 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 131 transitions. Word has length 86 [2022-11-03 01:56:14,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:14,051 INFO L495 AbstractCegarLoop]: Abstraction has 91 states and 131 transitions. [2022-11-03 01:56:14,051 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:14,052 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 131 transitions. [2022-11-03 01:56:14,053 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:14,054 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:14,054 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:14,090 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:14,278 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:14,279 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:14,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:14,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1019757425, now seen corresponding path program 1 times [2022-11-03 01:56:14,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:14,282 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1670317977] [2022-11-03 01:56:14,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:14,282 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:14,282 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:14,284 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:14,313 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 01:56:15,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:15,461 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:56:15,475 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:15,655 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:15,659 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:15,659 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:15,659 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1670317977] [2022-11-03 01:56:15,660 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1670317977] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:15,661 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:15,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 01:56:15,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139584253] [2022-11-03 01:56:15,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:15,666 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 01:56:15,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:15,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 01:56:15,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-03 01:56:15,669 INFO L87 Difference]: Start difference. First operand 91 states and 131 transitions. Second operand has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:16,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:16,424 INFO L93 Difference]: Finished difference Result 268 states and 391 transitions. [2022-11-03 01:56:16,426 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 01:56:16,426 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:16,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:16,429 INFO L225 Difference]: With dead ends: 268 [2022-11-03 01:56:16,429 INFO L226 Difference]: Without dead ends: 185 [2022-11-03 01:56:16,430 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2022-11-03 01:56:16,431 INFO L413 NwaCegarLoop]: 176 mSDtfsCounter, 229 mSDsluCounter, 414 mSDsCounter, 0 mSdLazyCounter, 271 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 229 SdHoareTripleChecker+Valid, 590 SdHoareTripleChecker+Invalid, 381 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 271 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 108 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:16,432 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [229 Valid, 590 Invalid, 381 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 271 Invalid, 0 Unknown, 108 Unchecked, 0.7s Time] [2022-11-03 01:56:16,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2022-11-03 01:56:16,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 174. [2022-11-03 01:56:16,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 173 states have (on average 1.4682080924855492) internal successors, (254), 173 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:16,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 254 transitions. [2022-11-03 01:56:16,447 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 254 transitions. Word has length 86 [2022-11-03 01:56:16,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:16,448 INFO L495 AbstractCegarLoop]: Abstraction has 174 states and 254 transitions. [2022-11-03 01:56:16,448 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:16,448 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 254 transitions. [2022-11-03 01:56:16,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:16,450 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:16,451 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:16,487 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:16,665 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:16,665 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:16,666 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:16,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1512383599, now seen corresponding path program 1 times [2022-11-03 01:56:16,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:16,668 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1070380854] [2022-11-03 01:56:16,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:16,669 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:16,669 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:16,671 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:16,674 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 01:56:17,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:17,713 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:56:17,724 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:18,073 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:18,074 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:18,074 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:18,075 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1070380854] [2022-11-03 01:56:18,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1070380854] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:18,075 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:18,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 01:56:18,076 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [46649417] [2022-11-03 01:56:18,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:18,077 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 01:56:18,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:18,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 01:56:18,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-03 01:56:18,078 INFO L87 Difference]: Start difference. First operand 174 states and 254 transitions. Second operand has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:18,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:18,895 INFO L93 Difference]: Finished difference Result 270 states and 393 transitions. [2022-11-03 01:56:18,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 01:56:18,896 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:18,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:18,898 INFO L225 Difference]: With dead ends: 270 [2022-11-03 01:56:18,898 INFO L226 Difference]: Without dead ends: 187 [2022-11-03 01:56:18,899 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-11-03 01:56:18,900 INFO L413 NwaCegarLoop]: 173 mSDtfsCounter, 229 mSDsluCounter, 554 mSDsCounter, 0 mSdLazyCounter, 269 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 229 SdHoareTripleChecker+Valid, 727 SdHoareTripleChecker+Invalid, 503 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 269 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 232 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:18,900 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [229 Valid, 727 Invalid, 503 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 269 Invalid, 0 Unknown, 232 Unchecked, 0.7s Time] [2022-11-03 01:56:18,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2022-11-03 01:56:18,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 176. [2022-11-03 01:56:18,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 175 states have (on average 1.4628571428571429) internal successors, (256), 175 states have internal predecessors, (256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:18,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 256 transitions. [2022-11-03 01:56:18,937 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 256 transitions. Word has length 86 [2022-11-03 01:56:18,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:18,937 INFO L495 AbstractCegarLoop]: Abstraction has 176 states and 256 transitions. [2022-11-03 01:56:18,938 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:18,938 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 256 transitions. [2022-11-03 01:56:18,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:18,952 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:18,952 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:18,990 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:19,153 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:19,153 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:19,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:19,154 INFO L85 PathProgramCache]: Analyzing trace with hash 1566429971, now seen corresponding path program 1 times [2022-11-03 01:56:19,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:19,156 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [465552964] [2022-11-03 01:56:19,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:19,156 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:19,156 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:19,158 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:19,160 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 01:56:20,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:20,310 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:56:20,335 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:20,745 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:20,745 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:20,745 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:20,746 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [465552964] [2022-11-03 01:56:20,746 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [465552964] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:20,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:20,746 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 01:56:20,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166152329] [2022-11-03 01:56:20,747 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:20,747 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 01:56:20,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:20,748 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 01:56:20,748 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-03 01:56:20,748 INFO L87 Difference]: Start difference. First operand 176 states and 256 transitions. Second operand has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:21,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:21,581 INFO L93 Difference]: Finished difference Result 586 states and 858 transitions. [2022-11-03 01:56:21,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 01:56:21,582 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:21,582 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:21,584 INFO L225 Difference]: With dead ends: 586 [2022-11-03 01:56:21,585 INFO L226 Difference]: Without dead ends: 418 [2022-11-03 01:56:21,586 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2022-11-03 01:56:21,587 INFO L413 NwaCegarLoop]: 154 mSDtfsCounter, 199 mSDsluCounter, 407 mSDsCounter, 0 mSdLazyCounter, 297 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 199 SdHoareTripleChecker+Valid, 561 SdHoareTripleChecker+Invalid, 375 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 297 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 76 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:21,588 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [199 Valid, 561 Invalid, 375 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 297 Invalid, 0 Unknown, 76 Unchecked, 0.7s Time] [2022-11-03 01:56:21,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 418 states. [2022-11-03 01:56:21,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 418 to 346. [2022-11-03 01:56:21,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 346 states, 345 states have (on average 1.4666666666666666) internal successors, (506), 345 states have internal predecessors, (506), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:21,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 346 states to 346 states and 506 transitions. [2022-11-03 01:56:21,610 INFO L78 Accepts]: Start accepts. Automaton has 346 states and 506 transitions. Word has length 86 [2022-11-03 01:56:21,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:21,610 INFO L495 AbstractCegarLoop]: Abstraction has 346 states and 506 transitions. [2022-11-03 01:56:21,611 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:21,611 INFO L276 IsEmpty]: Start isEmpty. Operand 346 states and 506 transitions. [2022-11-03 01:56:21,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:21,615 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:21,615 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:21,663 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:21,838 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:21,838 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:21,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:21,839 INFO L85 PathProgramCache]: Analyzing trace with hash -278937195, now seen corresponding path program 1 times [2022-11-03 01:56:21,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:21,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1855056995] [2022-11-03 01:56:21,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:21,841 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:21,841 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:21,842 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:21,843 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 01:56:22,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:22,916 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:56:22,925 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:23,346 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:23,346 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:23,347 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:23,347 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1855056995] [2022-11-03 01:56:23,347 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1855056995] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:23,347 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:23,347 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 01:56:23,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035772007] [2022-11-03 01:56:23,348 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:23,348 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 01:56:23,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:23,349 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 01:56:23,349 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2022-11-03 01:56:23,350 INFO L87 Difference]: Start difference. First operand 346 states and 506 transitions. Second operand has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:24,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:24,107 INFO L93 Difference]: Finished difference Result 590 states and 862 transitions. [2022-11-03 01:56:24,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 01:56:24,108 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:24,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:24,109 INFO L225 Difference]: With dead ends: 590 [2022-11-03 01:56:24,110 INFO L226 Difference]: Without dead ends: 422 [2022-11-03 01:56:24,110 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-11-03 01:56:24,111 INFO L413 NwaCegarLoop]: 151 mSDtfsCounter, 199 mSDsluCounter, 539 mSDsCounter, 0 mSdLazyCounter, 295 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 199 SdHoareTripleChecker+Valid, 690 SdHoareTripleChecker+Invalid, 509 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 295 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 212 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:24,112 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [199 Valid, 690 Invalid, 509 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 295 Invalid, 0 Unknown, 212 Unchecked, 0.7s Time] [2022-11-03 01:56:24,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 422 states. [2022-11-03 01:56:24,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 422 to 350. [2022-11-03 01:56:24,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 350 states, 349 states have (on average 1.4613180515759312) internal successors, (510), 349 states have internal predecessors, (510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:24,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 510 transitions. [2022-11-03 01:56:24,126 INFO L78 Accepts]: Start accepts. Automaton has 350 states and 510 transitions. Word has length 86 [2022-11-03 01:56:24,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:24,127 INFO L495 AbstractCegarLoop]: Abstraction has 350 states and 510 transitions. [2022-11-03 01:56:24,127 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 12.285714285714286) internal successors, (86), 7 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:24,127 INFO L276 IsEmpty]: Start isEmpty. Operand 350 states and 510 transitions. [2022-11-03 01:56:24,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:24,129 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:24,130 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:24,158 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:24,354 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:24,355 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:24,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:24,355 INFO L85 PathProgramCache]: Analyzing trace with hash 380594327, now seen corresponding path program 1 times [2022-11-03 01:56:24,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:24,357 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [463086] [2022-11-03 01:56:24,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:24,358 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:24,358 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:24,359 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:24,370 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 01:56:25,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:25,387 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:56:25,396 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:25,644 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:25,647 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:25,648 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:25,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [463086] [2022-11-03 01:56:25,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [463086] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:25,648 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:25,649 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 01:56:25,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [159843810] [2022-11-03 01:56:25,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:25,650 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:56:25,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:25,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:56:25,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:25,651 INFO L87 Difference]: Start difference. First operand 350 states and 510 transitions. Second operand has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:25,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:25,865 INFO L93 Difference]: Finished difference Result 804 states and 1171 transitions. [2022-11-03 01:56:25,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:56:25,866 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:25,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:25,868 INFO L225 Difference]: With dead ends: 804 [2022-11-03 01:56:25,868 INFO L226 Difference]: Without dead ends: 462 [2022-11-03 01:56:25,869 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 82 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:25,870 INFO L413 NwaCegarLoop]: 88 mSDtfsCounter, 25 mSDsluCounter, 221 mSDsCounter, 0 mSdLazyCounter, 81 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 309 SdHoareTripleChecker+Invalid, 215 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 81 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 134 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:25,871 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [25 Valid, 309 Invalid, 215 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 81 Invalid, 0 Unknown, 134 Unchecked, 0.2s Time] [2022-11-03 01:56:25,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2022-11-03 01:56:25,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 458. [2022-11-03 01:56:25,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 458 states, 457 states have (on average 1.4485776805251642) internal successors, (662), 457 states have internal predecessors, (662), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:25,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 662 transitions. [2022-11-03 01:56:25,889 INFO L78 Accepts]: Start accepts. Automaton has 458 states and 662 transitions. Word has length 86 [2022-11-03 01:56:25,890 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:25,890 INFO L495 AbstractCegarLoop]: Abstraction has 458 states and 662 transitions. [2022-11-03 01:56:25,891 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 17.2) internal successors, (86), 5 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:25,891 INFO L276 IsEmpty]: Start isEmpty. Operand 458 states and 662 transitions. [2022-11-03 01:56:25,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:25,893 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:25,893 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:25,933 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:26,118 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:26,119 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:26,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:26,119 INFO L85 PathProgramCache]: Analyzing trace with hash 452980885, now seen corresponding path program 1 times [2022-11-03 01:56:26,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:26,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2021464227] [2022-11-03 01:56:26,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:26,121 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:26,121 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:26,122 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:26,127 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 01:56:27,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:27,153 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:56:27,166 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:27,593 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:27,594 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:27,594 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:27,594 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2021464227] [2022-11-03 01:56:27,595 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2021464227] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:27,595 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:27,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 01:56:27,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435205145] [2022-11-03 01:56:27,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:27,596 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 01:56:27,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:27,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 01:56:27,597 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-03 01:56:27,598 INFO L87 Difference]: Start difference. First operand 458 states and 662 transitions. Second operand has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:28,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:28,252 INFO L93 Difference]: Finished difference Result 1194 states and 1740 transitions. [2022-11-03 01:56:28,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 01:56:28,254 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:28,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:28,257 INFO L225 Difference]: With dead ends: 1194 [2022-11-03 01:56:28,257 INFO L226 Difference]: Without dead ends: 852 [2022-11-03 01:56:28,258 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 81 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=47, Unknown=0, NotChecked=0, Total=72 [2022-11-03 01:56:28,259 INFO L413 NwaCegarLoop]: 149 mSDtfsCounter, 181 mSDsluCounter, 430 mSDsCounter, 0 mSdLazyCounter, 288 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 181 SdHoareTripleChecker+Valid, 579 SdHoareTripleChecker+Invalid, 386 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 288 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 96 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:28,260 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [181 Valid, 579 Invalid, 386 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 288 Invalid, 0 Unknown, 96 Unchecked, 0.6s Time] [2022-11-03 01:56:28,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 852 states. [2022-11-03 01:56:28,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 852 to 806. [2022-11-03 01:56:28,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 806 states, 805 states have (on average 1.453416149068323) internal successors, (1170), 805 states have internal predecessors, (1170), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:28,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 806 states to 806 states and 1170 transitions. [2022-11-03 01:56:28,291 INFO L78 Accepts]: Start accepts. Automaton has 806 states and 1170 transitions. Word has length 86 [2022-11-03 01:56:28,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:28,292 INFO L495 AbstractCegarLoop]: Abstraction has 806 states and 1170 transitions. [2022-11-03 01:56:28,292 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 14.333333333333334) internal successors, (86), 6 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:28,293 INFO L276 IsEmpty]: Start isEmpty. Operand 806 states and 1170 transitions. [2022-11-03 01:56:28,294 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:28,294 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:28,295 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:28,336 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:28,516 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:28,516 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:28,517 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:28,517 INFO L85 PathProgramCache]: Analyzing trace with hash 875682711, now seen corresponding path program 1 times [2022-11-03 01:56:28,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:28,518 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [896329856] [2022-11-03 01:56:28,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:28,519 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:28,519 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:28,521 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:28,525 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Waiting until timeout for monitored process [2022-11-03 01:56:29,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:29,479 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:56:29,488 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:31,834 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:31,834 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:31,834 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:31,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [896329856] [2022-11-03 01:56:31,835 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [896329856] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:31,835 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:31,835 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 01:56:31,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020062051] [2022-11-03 01:56:31,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:31,836 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 01:56:31,837 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:31,837 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 01:56:31,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=41, Unknown=1, NotChecked=0, Total=56 [2022-11-03 01:56:31,838 INFO L87 Difference]: Start difference. First operand 806 states and 1170 transitions. Second operand has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:32,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:32,501 INFO L93 Difference]: Finished difference Result 1202 states and 1748 transitions. [2022-11-03 01:56:32,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 01:56:32,502 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:32,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:32,506 INFO L225 Difference]: With dead ends: 1202 [2022-11-03 01:56:32,506 INFO L226 Difference]: Without dead ends: 860 [2022-11-03 01:56:32,507 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=31, Invalid=78, Unknown=1, NotChecked=0, Total=110 [2022-11-03 01:56:32,508 INFO L413 NwaCegarLoop]: 146 mSDtfsCounter, 181 mSDsluCounter, 572 mSDsCounter, 0 mSdLazyCounter, 286 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 181 SdHoareTripleChecker+Valid, 718 SdHoareTripleChecker+Invalid, 486 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 286 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 198 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:32,508 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [181 Valid, 718 Invalid, 486 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 286 Invalid, 0 Unknown, 198 Unchecked, 0.6s Time] [2022-11-03 01:56:32,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 860 states. [2022-11-03 01:56:32,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 860 to 814. [2022-11-03 01:56:32,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 814 states, 813 states have (on average 1.4489544895448954) internal successors, (1178), 813 states have internal predecessors, (1178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:32,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 814 states to 814 states and 1178 transitions. [2022-11-03 01:56:32,537 INFO L78 Accepts]: Start accepts. Automaton has 814 states and 1178 transitions. Word has length 86 [2022-11-03 01:56:32,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:32,538 INFO L495 AbstractCegarLoop]: Abstraction has 814 states and 1178 transitions. [2022-11-03 01:56:32,538 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:32,538 INFO L276 IsEmpty]: Start isEmpty. Operand 814 states and 1178 transitions. [2022-11-03 01:56:32,539 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:32,539 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:32,540 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:32,569 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:32,754 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:32,755 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:32,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:32,755 INFO L85 PathProgramCache]: Analyzing trace with hash -813261031, now seen corresponding path program 1 times [2022-11-03 01:56:32,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:32,757 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [237736488] [2022-11-03 01:56:32,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:32,758 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:32,758 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:32,760 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:32,807 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-03 01:56:33,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:33,804 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 01:56:33,829 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:34,278 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:34,278 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:34,278 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:34,279 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [237736488] [2022-11-03 01:56:34,279 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [237736488] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:34,279 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:34,279 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 01:56:34,280 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858990670] [2022-11-03 01:56:34,280 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:34,280 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 01:56:34,280 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:34,281 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 01:56:34,281 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 01:56:34,282 INFO L87 Difference]: Start difference. First operand 814 states and 1178 transitions. Second operand has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:35,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:35,366 INFO L93 Difference]: Finished difference Result 3036 states and 4401 transitions. [2022-11-03 01:56:35,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 01:56:35,367 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:35,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:35,376 INFO L225 Difference]: With dead ends: 3036 [2022-11-03 01:56:35,376 INFO L226 Difference]: Without dead ends: 2338 [2022-11-03 01:56:35,378 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=128, Unknown=0, NotChecked=0, Total=182 [2022-11-03 01:56:35,379 INFO L413 NwaCegarLoop]: 139 mSDtfsCounter, 430 mSDsluCounter, 683 mSDsCounter, 0 mSdLazyCounter, 514 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 430 SdHoareTripleChecker+Valid, 822 SdHoareTripleChecker+Invalid, 628 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 514 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 108 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:35,379 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [430 Valid, 822 Invalid, 628 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 514 Invalid, 0 Unknown, 108 Unchecked, 0.9s Time] [2022-11-03 01:56:35,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2338 states. [2022-11-03 01:56:35,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2338 to 1542. [2022-11-03 01:56:35,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1542 states, 1541 states have (on average 1.4497079818299805) internal successors, (2234), 1541 states have internal predecessors, (2234), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:35,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1542 states to 1542 states and 2234 transitions. [2022-11-03 01:56:35,434 INFO L78 Accepts]: Start accepts. Automaton has 1542 states and 2234 transitions. Word has length 86 [2022-11-03 01:56:35,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:35,434 INFO L495 AbstractCegarLoop]: Abstraction has 1542 states and 2234 transitions. [2022-11-03 01:56:35,435 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 10.75) internal successors, (86), 8 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:35,435 INFO L276 IsEmpty]: Start isEmpty. Operand 1542 states and 2234 transitions. [2022-11-03 01:56:35,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:35,436 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:35,437 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:35,475 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:35,661 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:35,661 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:35,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:35,662 INFO L85 PathProgramCache]: Analyzing trace with hash -1400067045, now seen corresponding path program 1 times [2022-11-03 01:56:35,663 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:35,663 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [854274572] [2022-11-03 01:56:35,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:35,663 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:35,664 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:35,665 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:35,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 01:56:36,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:36,654 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 01:56:36,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:39,171 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:39,171 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:39,171 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:39,171 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [854274572] [2022-11-03 01:56:39,172 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [854274572] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:39,172 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:39,172 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2022-11-03 01:56:39,172 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586603996] [2022-11-03 01:56:39,172 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:39,172 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-03 01:56:39,173 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:39,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-03 01:56:39,173 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=71, Unknown=1, NotChecked=0, Total=90 [2022-11-03 01:56:39,173 INFO L87 Difference]: Start difference. First operand 1542 states and 2234 transitions. Second operand has 10 states, 10 states have (on average 8.6) internal successors, (86), 10 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:40,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:40,227 INFO L93 Difference]: Finished difference Result 3052 states and 4417 transitions. [2022-11-03 01:56:40,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 01:56:40,227 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 8.6) internal successors, (86), 10 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:40,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:40,235 INFO L225 Difference]: With dead ends: 3052 [2022-11-03 01:56:40,235 INFO L226 Difference]: Without dead ends: 2354 [2022-11-03 01:56:40,237 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=60, Invalid=179, Unknown=1, NotChecked=0, Total=240 [2022-11-03 01:56:40,238 INFO L413 NwaCegarLoop]: 136 mSDtfsCounter, 430 mSDsluCounter, 947 mSDsCounter, 0 mSdLazyCounter, 510 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 430 SdHoareTripleChecker+Valid, 1083 SdHoareTripleChecker+Invalid, 833 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 510 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 317 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:40,238 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [430 Valid, 1083 Invalid, 833 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 510 Invalid, 0 Unknown, 317 Unchecked, 0.9s Time] [2022-11-03 01:56:40,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2354 states. [2022-11-03 01:56:40,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2354 to 1558. [2022-11-03 01:56:40,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1558 states, 1557 states have (on average 1.4450867052023122) internal successors, (2250), 1557 states have internal predecessors, (2250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:40,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 1558 states and 2250 transitions. [2022-11-03 01:56:40,280 INFO L78 Accepts]: Start accepts. Automaton has 1558 states and 2250 transitions. Word has length 86 [2022-11-03 01:56:40,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:40,281 INFO L495 AbstractCegarLoop]: Abstraction has 1558 states and 2250 transitions. [2022-11-03 01:56:40,281 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 8.6) internal successors, (86), 10 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:40,281 INFO L276 IsEmpty]: Start isEmpty. Operand 1558 states and 2250 transitions. [2022-11-03 01:56:40,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:40,283 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:40,283 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:40,318 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:40,494 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:40,494 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:40,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:40,495 INFO L85 PathProgramCache]: Analyzing trace with hash -699002467, now seen corresponding path program 1 times [2022-11-03 01:56:40,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:40,496 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1611785157] [2022-11-03 01:56:40,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:40,497 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:40,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:40,498 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:40,501 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 01:56:41,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:41,437 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:56:41,443 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:41,620 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:41,620 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:56:41,621 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:41,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1611785157] [2022-11-03 01:56:41,621 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1611785157] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:56:41,621 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:56:41,621 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 01:56:41,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516652810] [2022-11-03 01:56:41,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:56:41,622 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 01:56:41,622 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:41,622 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 01:56:41,622 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 01:56:41,623 INFO L87 Difference]: Start difference. First operand 1558 states and 2250 transitions. Second operand has 4 states, 4 states have (on average 21.5) internal successors, (86), 4 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:41,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:41,692 INFO L93 Difference]: Finished difference Result 4754 states and 6856 transitions. [2022-11-03 01:56:41,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:56:41,693 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 21.5) internal successors, (86), 4 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:41,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:41,703 INFO L225 Difference]: With dead ends: 4754 [2022-11-03 01:56:41,704 INFO L226 Difference]: Without dead ends: 3312 [2022-11-03 01:56:41,706 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:56:41,707 INFO L413 NwaCegarLoop]: 239 mSDtfsCounter, 161 mSDsluCounter, 241 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 161 SdHoareTripleChecker+Valid, 480 SdHoareTripleChecker+Invalid, 8 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:41,707 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [161 Valid, 480 Invalid, 8 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-03 01:56:41,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3312 states. [2022-11-03 01:56:41,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3312 to 1870. [2022-11-03 01:56:41,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1870 states, 1869 states have (on average 1.4328517924023543) internal successors, (2678), 1869 states have internal predecessors, (2678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:41,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1870 states to 1870 states and 2678 transitions. [2022-11-03 01:56:41,772 INFO L78 Accepts]: Start accepts. Automaton has 1870 states and 2678 transitions. Word has length 86 [2022-11-03 01:56:41,772 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:41,772 INFO L495 AbstractCegarLoop]: Abstraction has 1870 states and 2678 transitions. [2022-11-03 01:56:41,772 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 21.5) internal successors, (86), 4 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:41,773 INFO L276 IsEmpty]: Start isEmpty. Operand 1870 states and 2678 transitions. [2022-11-03 01:56:41,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:41,777 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:41,778 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:41,810 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:41,993 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:56:41,993 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:41,993 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:41,994 INFO L85 PathProgramCache]: Analyzing trace with hash -697155425, now seen corresponding path program 1 times [2022-11-03 01:56:41,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:41,997 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [50592099] [2022-11-03 01:56:41,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:41,997 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:41,997 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:41,998 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:42,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 01:56:42,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:43,004 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 26 conjunts are in the unsatisfiable core [2022-11-03 01:56:43,010 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:44,082 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:44,082 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:56:45,289 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:45,289 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:45,289 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [50592099] [2022-11-03 01:56:45,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [50592099] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:56:45,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [355412428] [2022-11-03 01:56:45,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:45,290 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:56:45,291 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:56:45,298 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:56:45,314 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (15)] Waiting until timeout for monitored process [2022-11-03 01:56:46,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:47,039 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-03 01:56:47,047 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:48,231 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:48,232 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:56:51,459 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:51,460 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [355412428] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:56:51,460 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1139028583] [2022-11-03 01:56:51,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:51,461 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:56:51,461 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:56:51,466 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:56:51,486 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2022-11-03 01:56:52,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:52,228 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-03 01:56:52,233 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:53,331 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:53,331 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:56:55,466 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:55,467 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1139028583] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:56:55,467 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:56:55,469 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 9, 9, 10, 10] total 26 [2022-11-03 01:56:55,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1204792852] [2022-11-03 01:56:55,469 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:56:55,470 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-11-03 01:56:55,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:56:55,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-03 01:56:55,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=554, Unknown=0, NotChecked=0, Total=650 [2022-11-03 01:56:55,473 INFO L87 Difference]: Start difference. First operand 1870 states and 2678 transitions. Second operand has 26 states, 26 states have (on average 13.076923076923077) internal successors, (340), 26 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:56,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:56:56,144 INFO L93 Difference]: Finished difference Result 3762 states and 5376 transitions. [2022-11-03 01:56:56,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2022-11-03 01:56:56,145 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 13.076923076923077) internal successors, (340), 26 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:56:56,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:56:56,157 INFO L225 Difference]: With dead ends: 3762 [2022-11-03 01:56:56,158 INFO L226 Difference]: Without dead ends: 3760 [2022-11-03 01:56:56,160 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 520 GetRequests, 486 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 248 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=180, Invalid=942, Unknown=0, NotChecked=0, Total=1122 [2022-11-03 01:56:56,161 INFO L413 NwaCegarLoop]: 104 mSDtfsCounter, 759 mSDsluCounter, 1581 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 759 SdHoareTripleChecker+Valid, 1685 SdHoareTripleChecker+Invalid, 456 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 453 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 01:56:56,161 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [759 Valid, 1685 Invalid, 456 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 453 Unchecked, 0.0s Time] [2022-11-03 01:56:56,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3760 states. [2022-11-03 01:56:56,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3760 to 3728. [2022-11-03 01:56:56,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3728 states, 3727 states have (on average 1.4292997048564529) internal successors, (5327), 3727 states have internal predecessors, (5327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:56,306 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3728 states to 3728 states and 5327 transitions. [2022-11-03 01:56:56,306 INFO L78 Accepts]: Start accepts. Automaton has 3728 states and 5327 transitions. Word has length 86 [2022-11-03 01:56:56,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:56:56,307 INFO L495 AbstractCegarLoop]: Abstraction has 3728 states and 5327 transitions. [2022-11-03 01:56:56,307 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 13.076923076923077) internal successors, (340), 26 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:56:56,308 INFO L276 IsEmpty]: Start isEmpty. Operand 3728 states and 5327 transitions. [2022-11-03 01:56:56,311 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:56:56,311 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:56:56,311 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:56:56,350 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:56,568 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (15)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:56,767 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2022-11-03 01:56:56,934 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:56:56,935 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:56:56,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:56:56,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1077851937, now seen corresponding path program 1 times [2022-11-03 01:56:56,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:56:56,937 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [996947240] [2022-11-03 01:56:56,937 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:56,937 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:56:56,937 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:56:56,938 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:56:56,939 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Waiting until timeout for monitored process [2022-11-03 01:56:57,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:56:57,958 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-03 01:56:57,964 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:56:58,810 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:58,810 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:56:59,870 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:56:59,871 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:56:59,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [996947240] [2022-11-03 01:56:59,871 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [996947240] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:56:59,871 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [544476628] [2022-11-03 01:56:59,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:56:59,871 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:56:59,871 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:56:59,875 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:56:59,890 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (18)] Waiting until timeout for monitored process [2022-11-03 01:57:01,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:01,606 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 22 conjunts are in the unsatisfiable core [2022-11-03 01:57:01,611 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:02,329 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:02,329 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:03,144 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:03,145 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [544476628] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:03,145 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [808134002] [2022-11-03 01:57:03,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:03,145 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:03,146 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:57:03,147 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:57:03,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2022-11-03 01:57:03,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:03,915 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 25 conjunts are in the unsatisfiable core [2022-11-03 01:57:03,920 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:04,603 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:04,603 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:05,388 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:05,388 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [808134002] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:05,388 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:57:05,388 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 10, 10] total 18 [2022-11-03 01:57:05,392 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [975803768] [2022-11-03 01:57:05,392 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:57:05,393 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-03 01:57:05,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:05,394 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-03 01:57:05,394 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=261, Unknown=0, NotChecked=0, Total=306 [2022-11-03 01:57:05,395 INFO L87 Difference]: Start difference. First operand 3728 states and 5327 transitions. Second operand has 18 states, 18 states have (on average 9.666666666666666) internal successors, (174), 18 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:06,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:06,833 INFO L93 Difference]: Finished difference Result 5284 states and 7545 transitions. [2022-11-03 01:57:06,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-03 01:57:06,834 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 9.666666666666666) internal successors, (174), 18 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:57:06,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:06,842 INFO L225 Difference]: With dead ends: 5284 [2022-11-03 01:57:06,842 INFO L226 Difference]: Without dead ends: 5282 [2022-11-03 01:57:06,844 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 519 GetRequests, 490 SyntacticMatches, 4 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 90 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=173, Invalid=529, Unknown=0, NotChecked=0, Total=702 [2022-11-03 01:57:06,844 INFO L413 NwaCegarLoop]: 307 mSDtfsCounter, 479 mSDsluCounter, 2133 mSDsCounter, 0 mSdLazyCounter, 232 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 479 SdHoareTripleChecker+Valid, 2440 SdHoareTripleChecker+Invalid, 345 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 232 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 107 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:06,845 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [479 Valid, 2440 Invalid, 345 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 232 Invalid, 0 Unknown, 107 Unchecked, 1.0s Time] [2022-11-03 01:57:06,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5282 states. [2022-11-03 01:57:06,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5282 to 3840. [2022-11-03 01:57:06,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3840 states, 3839 states have (on average 1.4209429538942433) internal successors, (5455), 3839 states have internal predecessors, (5455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:06,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3840 states to 3840 states and 5455 transitions. [2022-11-03 01:57:06,965 INFO L78 Accepts]: Start accepts. Automaton has 3840 states and 5455 transitions. Word has length 86 [2022-11-03 01:57:06,966 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:06,966 INFO L495 AbstractCegarLoop]: Abstraction has 3840 states and 5455 transitions. [2022-11-03 01:57:06,966 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 9.666666666666666) internal successors, (174), 18 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:06,966 INFO L276 IsEmpty]: Start isEmpty. Operand 3840 states and 5455 transitions. [2022-11-03 01:57:06,969 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2022-11-03 01:57:06,969 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:06,969 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:06,994 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (17)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:07,193 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (18)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:07,411 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:07,582 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:07,583 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:07,583 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:07,583 INFO L85 PathProgramCache]: Analyzing trace with hash -1514753757, now seen corresponding path program 1 times [2022-11-03 01:57:07,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:07,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1417064403] [2022-11-03 01:57:07,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:07,585 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:07,585 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:07,586 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:07,590 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (20)] Waiting until timeout for monitored process [2022-11-03 01:57:08,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:08,466 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 24 conjunts are in the unsatisfiable core [2022-11-03 01:57:08,471 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:09,303 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:09,303 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:10,454 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:10,454 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:10,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1417064403] [2022-11-03 01:57:10,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1417064403] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:10,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [808931987] [2022-11-03 01:57:10,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:10,456 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:57:10,456 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:57:10,459 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:57:10,467 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (21)] Waiting until timeout for monitored process [2022-11-03 01:57:12,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:12,103 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 42 conjunts are in the unsatisfiable core [2022-11-03 01:57:12,108 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:13,147 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:13,148 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:16,051 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:16,051 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [808931987] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:16,051 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [18818980] [2022-11-03 01:57:16,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:16,051 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:16,052 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:57:16,053 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:57:16,062 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2022-11-03 01:57:16,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:16,759 INFO L263 TraceCheckSpWp]: Trace formula consists of 1639 conjuncts, 45 conjunts are in the unsatisfiable core [2022-11-03 01:57:16,764 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:17,601 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:17,602 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:19,696 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:57:19,696 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [18818980] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:19,696 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:57:19,696 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 9, 9, 10, 10] total 28 [2022-11-03 01:57:19,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078278139] [2022-11-03 01:57:19,697 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:57:19,698 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 28 states [2022-11-03 01:57:19,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:19,699 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2022-11-03 01:57:19,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=649, Unknown=0, NotChecked=0, Total=756 [2022-11-03 01:57:19,699 INFO L87 Difference]: Start difference. First operand 3840 states and 5455 transitions. Second operand has 28 states, 28 states have (on average 12.142857142857142) internal successors, (340), 28 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:21,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:21,144 INFO L93 Difference]: Finished difference Result 7332 states and 10383 transitions. [2022-11-03 01:57:21,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-03 01:57:21,145 INFO L78 Accepts]: Start accepts. Automaton has has 28 states, 28 states have (on average 12.142857142857142) internal successors, (340), 28 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 86 [2022-11-03 01:57:21,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:21,166 INFO L225 Difference]: With dead ends: 7332 [2022-11-03 01:57:21,166 INFO L226 Difference]: Without dead ends: 7330 [2022-11-03 01:57:21,168 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 526 GetRequests, 484 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 316 ImplicationChecksByTransitivity, 3.8s TimeCoverageRelationStatistics Valid=377, Invalid=1345, Unknown=0, NotChecked=0, Total=1722 [2022-11-03 01:57:21,169 INFO L413 NwaCegarLoop]: 172 mSDtfsCounter, 1486 mSDsluCounter, 2247 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1486 SdHoareTripleChecker+Valid, 2419 SdHoareTripleChecker+Invalid, 1791 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 1773 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:21,170 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1486 Valid, 2419 Invalid, 1791 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 1773 Unchecked, 0.2s Time] [2022-11-03 01:57:21,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7330 states. [2022-11-03 01:57:21,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7330 to 6624. [2022-11-03 01:57:21,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6624 states, 6623 states have (on average 1.4300166087875585) internal successors, (9471), 6623 states have internal predecessors, (9471), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:21,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6624 states to 6624 states and 9471 transitions. [2022-11-03 01:57:21,408 INFO L78 Accepts]: Start accepts. Automaton has 6624 states and 9471 transitions. Word has length 86 [2022-11-03 01:57:21,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:21,408 INFO L495 AbstractCegarLoop]: Abstraction has 6624 states and 9471 transitions. [2022-11-03 01:57:21,409 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 28 states, 28 states have (on average 12.142857142857142) internal successors, (340), 28 states have internal predecessors, (340), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:21,409 INFO L276 IsEmpty]: Start isEmpty. Operand 6624 states and 9471 transitions. [2022-11-03 01:57:21,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:57:21,425 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:21,425 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:21,445 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (21)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:21,669 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:21,861 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (20)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:22,038 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:57:22,039 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:22,039 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:22,039 INFO L85 PathProgramCache]: Analyzing trace with hash -707543491, now seen corresponding path program 1 times [2022-11-03 01:57:22,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:22,042 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1529817050] [2022-11-03 01:57:22,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:22,042 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:22,042 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:22,043 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:22,044 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (23)] Waiting until timeout for monitored process [2022-11-03 01:57:23,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:23,508 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:57:23,514 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:23,748 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 81 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-11-03 01:57:23,748 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:57:23,749 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:23,749 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1529817050] [2022-11-03 01:57:23,749 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1529817050] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:57:23,749 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:57:23,749 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 01:57:23,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1410605277] [2022-11-03 01:57:23,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:57:23,750 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:57:23,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:23,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:57:23,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:57:23,751 INFO L87 Difference]: Start difference. First operand 6624 states and 9471 transitions. Second operand has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:23,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:23,918 INFO L93 Difference]: Finished difference Result 9618 states and 13776 transitions. [2022-11-03 01:57:23,919 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:57:23,919 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:57:23,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:23,933 INFO L225 Difference]: With dead ends: 9618 [2022-11-03 01:57:23,933 INFO L226 Difference]: Without dead ends: 6656 [2022-11-03 01:57:23,938 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:57:23,939 INFO L413 NwaCegarLoop]: 75 mSDtfsCounter, 41 mSDsluCounter, 147 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 222 SdHoareTripleChecker+Invalid, 145 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 98 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:23,939 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 222 Invalid, 145 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 47 Invalid, 0 Unknown, 98 Unchecked, 0.1s Time] [2022-11-03 01:57:23,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6656 states. [2022-11-03 01:57:24,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6656 to 6656. [2022-11-03 01:57:24,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6656 states, 6655 states have (on average 1.4255447032306536) internal successors, (9487), 6655 states have internal predecessors, (9487), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:24,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6656 states to 6656 states and 9487 transitions. [2022-11-03 01:57:24,121 INFO L78 Accepts]: Start accepts. Automaton has 6656 states and 9487 transitions. Word has length 167 [2022-11-03 01:57:24,122 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:24,122 INFO L495 AbstractCegarLoop]: Abstraction has 6656 states and 9487 transitions. [2022-11-03 01:57:24,122 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:24,123 INFO L276 IsEmpty]: Start isEmpty. Operand 6656 states and 9487 transitions. [2022-11-03 01:57:24,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:57:24,139 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:24,140 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:24,199 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (23)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:24,366 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:57:24,366 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:24,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:24,367 INFO L85 PathProgramCache]: Analyzing trace with hash -947783237, now seen corresponding path program 1 times [2022-11-03 01:57:24,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:24,369 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1654184803] [2022-11-03 01:57:24,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:24,369 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:24,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:24,370 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:24,371 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Waiting until timeout for monitored process [2022-11-03 01:57:25,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:25,860 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:57:25,866 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:26,395 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:26,395 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:26,930 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:26,930 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:26,930 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1654184803] [2022-11-03 01:57:26,930 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1654184803] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:26,931 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1141079155] [2022-11-03 01:57:26,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:26,931 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:57:26,931 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:57:26,932 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:57:26,934 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Waiting until timeout for monitored process [2022-11-03 01:57:29,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:29,730 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:57:29,737 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:30,192 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:30,192 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:30,561 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:30,562 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1141079155] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:30,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1431088799] [2022-11-03 01:57:30,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:30,563 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:30,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:57:30,564 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:57:30,565 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-03 01:57:31,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:31,595 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:57:31,601 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:32,078 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:32,078 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:32,589 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 69 proven. 3 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:32,589 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1431088799] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:32,589 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:57:32,590 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6, 6] total 10 [2022-11-03 01:57:32,590 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499632406] [2022-11-03 01:57:32,591 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:57:32,592 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-03 01:57:32,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:32,593 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-03 01:57:32,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2022-11-03 01:57:32,594 INFO L87 Difference]: Start difference. First operand 6656 states and 9487 transitions. Second operand has 10 states, 10 states have (on average 24.1) internal successors, (241), 10 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:33,415 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:33,415 INFO L93 Difference]: Finished difference Result 15900 states and 22705 transitions. [2022-11-03 01:57:33,416 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 01:57:33,417 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 24.1) internal successors, (241), 10 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:57:33,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:33,446 INFO L225 Difference]: With dead ends: 15900 [2022-11-03 01:57:33,446 INFO L226 Difference]: Without dead ends: 13074 [2022-11-03 01:57:33,453 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1002 GetRequests, 986 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2022-11-03 01:57:33,454 INFO L413 NwaCegarLoop]: 81 mSDtfsCounter, 191 mSDsluCounter, 382 mSDsCounter, 0 mSdLazyCounter, 189 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 191 SdHoareTripleChecker+Valid, 463 SdHoareTripleChecker+Invalid, 427 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 189 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 237 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:33,455 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [191 Valid, 463 Invalid, 427 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 189 Invalid, 0 Unknown, 237 Unchecked, 0.5s Time] [2022-11-03 01:57:33,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13074 states. [2022-11-03 01:57:33,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13074 to 6720. [2022-11-03 01:57:33,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6720 states, 6719 states have (on average 1.4214912933472243) internal successors, (9551), 6719 states have internal predecessors, (9551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:33,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6720 states to 6720 states and 9551 transitions. [2022-11-03 01:57:33,698 INFO L78 Accepts]: Start accepts. Automaton has 6720 states and 9551 transitions. Word has length 167 [2022-11-03 01:57:33,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:33,699 INFO L495 AbstractCegarLoop]: Abstraction has 6720 states and 9551 transitions. [2022-11-03 01:57:33,700 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 24.1) internal successors, (241), 10 states have internal predecessors, (241), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:33,700 INFO L276 IsEmpty]: Start isEmpty. Operand 6720 states and 9551 transitions. [2022-11-03 01:57:33,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:57:33,717 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:33,718 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:33,779 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:33,973 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:34,162 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:34,342 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt [2022-11-03 01:57:34,343 INFO L420 AbstractCegarLoop]: === Iteration 18 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:34,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:34,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1440409411, now seen corresponding path program 1 times [2022-11-03 01:57:34,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:34,346 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1120772302] [2022-11-03 01:57:34,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:34,346 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:34,346 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:34,347 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:34,349 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-03 01:57:35,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:35,860 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:57:35,867 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:36,441 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 67 proven. 5 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:36,442 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:37,052 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 67 proven. 5 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:37,052 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:37,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1120772302] [2022-11-03 01:57:37,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1120772302] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:37,053 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [2123431193] [2022-11-03 01:57:37,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:37,053 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:57:37,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:57:37,054 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:57:37,058 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Waiting until timeout for monitored process [2022-11-03 01:57:39,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:39,943 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:57:40,027 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:40,519 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 67 proven. 5 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:40,520 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:40,974 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 67 proven. 5 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2022-11-03 01:57:40,975 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [2123431193] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:40,975 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2116490874] [2022-11-03 01:57:40,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:40,975 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:40,975 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:57:40,976 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:57:40,979 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-03 01:57:42,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:42,107 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:57:42,114 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:42,868 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 39 proven. 3 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:42,869 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:43,560 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 39 proven. 3 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:43,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2116490874] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:43,560 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:57:43,560 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 6, 6] total 18 [2022-11-03 01:57:43,560 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1413474460] [2022-11-03 01:57:43,561 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:57:43,562 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-11-03 01:57:43,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:43,563 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-11-03 01:57:43,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2022-11-03 01:57:43,563 INFO L87 Difference]: Start difference. First operand 6720 states and 9551 transitions. Second operand has 18 states, 18 states have (on average 14.055555555555555) internal successors, (253), 18 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:45,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:45,366 INFO L93 Difference]: Finished difference Result 19420 states and 27531 transitions. [2022-11-03 01:57:45,371 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-03 01:57:45,371 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 14.055555555555555) internal successors, (253), 18 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:57:45,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:45,395 INFO L225 Difference]: With dead ends: 19420 [2022-11-03 01:57:45,395 INFO L226 Difference]: Without dead ends: 15086 [2022-11-03 01:57:45,404 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1010 GetRequests, 974 SyntacticMatches, 6 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=160, Invalid=832, Unknown=0, NotChecked=0, Total=992 [2022-11-03 01:57:45,405 INFO L413 NwaCegarLoop]: 168 mSDtfsCounter, 381 mSDsluCounter, 1635 mSDsCounter, 0 mSdLazyCounter, 597 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 381 SdHoareTripleChecker+Valid, 1803 SdHoareTripleChecker+Invalid, 1388 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 597 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 788 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:45,405 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [381 Valid, 1803 Invalid, 1388 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 597 Invalid, 0 Unknown, 788 Unchecked, 1.1s Time] [2022-11-03 01:57:45,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15086 states. [2022-11-03 01:57:45,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15086 to 3444. [2022-11-03 01:57:45,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3444 states, 3443 states have (on average 1.413011908219576) internal successors, (4865), 3443 states have internal predecessors, (4865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:45,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3444 states to 3444 states and 4865 transitions. [2022-11-03 01:57:45,623 INFO L78 Accepts]: Start accepts. Automaton has 3444 states and 4865 transitions. Word has length 167 [2022-11-03 01:57:45,623 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:45,623 INFO L495 AbstractCegarLoop]: Abstraction has 3444 states and 4865 transitions. [2022-11-03 01:57:45,623 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 14.055555555555555) internal successors, (253), 18 states have internal predecessors, (253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:45,624 INFO L276 IsEmpty]: Start isEmpty. Operand 3444 states and 4865 transitions. [2022-11-03 01:57:45,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:57:45,631 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:45,632 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:45,662 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:45,888 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:46,090 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:46,249 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:57:46,249 INFO L420 AbstractCegarLoop]: === Iteration 19 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:46,249 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:46,250 INFO L85 PathProgramCache]: Analyzing trace with hash -206963007, now seen corresponding path program 1 times [2022-11-03 01:57:46,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:46,252 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [89744631] [2022-11-03 01:57:46,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:46,252 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:46,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:46,254 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:46,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Waiting until timeout for monitored process [2022-11-03 01:57:47,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:47,822 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:57:47,828 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:48,511 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:48,511 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:49,211 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:49,211 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:49,211 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [89744631] [2022-11-03 01:57:49,211 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [89744631] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:49,212 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [727736751] [2022-11-03 01:57:49,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:49,212 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:57:49,212 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:57:49,213 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:57:49,215 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Waiting until timeout for monitored process [2022-11-03 01:57:51,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:52,064 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:57:52,070 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:52,674 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:52,674 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:53,254 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:53,254 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [727736751] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:53,255 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [887921365] [2022-11-03 01:57:53,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:53,255 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:53,255 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:57:53,259 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:57:53,265 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2022-11-03 01:57:54,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:54,417 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:57:54,424 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:55,067 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:55,068 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:57:55,614 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 37 proven. 5 refuted. 0 times theorem prover too weak. 43 trivial. 0 not checked. [2022-11-03 01:57:55,615 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [887921365] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:57:55,615 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:57:55,615 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7, 7] total 12 [2022-11-03 01:57:55,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502933423] [2022-11-03 01:57:55,616 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:57:55,617 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-11-03 01:57:55,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:55,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-11-03 01:57:55,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=106, Unknown=0, NotChecked=0, Total=132 [2022-11-03 01:57:55,618 INFO L87 Difference]: Start difference. First operand 3444 states and 4865 transitions. Second operand has 12 states, 12 states have (on average 17.75) internal successors, (213), 12 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:57,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:57,029 INFO L93 Difference]: Finished difference Result 10888 states and 15437 transitions. [2022-11-03 01:57:57,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-03 01:57:57,030 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 17.75) internal successors, (213), 12 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:57:57,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:57,041 INFO L225 Difference]: With dead ends: 10888 [2022-11-03 01:57:57,041 INFO L226 Difference]: Without dead ends: 9410 [2022-11-03 01:57:57,045 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1004 GetRequests, 978 SyntacticMatches, 8 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=93, Invalid=287, Unknown=0, NotChecked=0, Total=380 [2022-11-03 01:57:57,046 INFO L413 NwaCegarLoop]: 200 mSDtfsCounter, 391 mSDsluCounter, 1187 mSDsCounter, 0 mSdLazyCounter, 514 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 391 SdHoareTripleChecker+Valid, 1387 SdHoareTripleChecker+Invalid, 1187 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 514 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 669 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:57,046 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [391 Valid, 1387 Invalid, 1187 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 514 Invalid, 0 Unknown, 669 Unchecked, 1.1s Time] [2022-11-03 01:57:57,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9410 states. [2022-11-03 01:57:57,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9410 to 1792. [2022-11-03 01:57:57,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1792 states, 1791 states have (on average 1.4087102177554438) internal successors, (2523), 1791 states have internal predecessors, (2523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:57,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1792 states to 1792 states and 2523 transitions. [2022-11-03 01:57:57,142 INFO L78 Accepts]: Start accepts. Automaton has 1792 states and 2523 transitions. Word has length 167 [2022-11-03 01:57:57,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:57:57,142 INFO L495 AbstractCegarLoop]: Abstraction has 1792 states and 2523 transitions. [2022-11-03 01:57:57,143 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 17.75) internal successors, (213), 12 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:57,143 INFO L276 IsEmpty]: Start isEmpty. Operand 1792 states and 2523 transitions. [2022-11-03 01:57:57,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:57:57,147 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:57:57,148 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:57:57,211 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (30)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:57,404 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (31)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:57,613 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Forceful destruction successful, exit code 0 [2022-11-03 01:57:57,774 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 30 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,31 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,32 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:57:57,775 INFO L420 AbstractCegarLoop]: === Iteration 20 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:57:57,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:57:57,775 INFO L85 PathProgramCache]: Analyzing trace with hash 452568515, now seen corresponding path program 1 times [2022-11-03 01:57:57,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:57:57,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [312253161] [2022-11-03 01:57:57,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:57:57,778 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:57:57,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:57:57,779 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:57:57,781 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Waiting until timeout for monitored process [2022-11-03 01:57:59,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:57:59,383 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:57:59,392 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:57:59,745 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 35 proven. 0 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2022-11-03 01:57:59,745 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:57:59,745 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:57:59,745 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [312253161] [2022-11-03 01:57:59,745 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [312253161] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:57:59,746 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 01:57:59,746 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 01:57:59,746 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530575635] [2022-11-03 01:57:59,746 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:57:59,747 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:57:59,747 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:57:59,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:57:59,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:57:59,747 INFO L87 Difference]: Start difference. First operand 1792 states and 2523 transitions. Second operand has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:57:59,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:57:59,887 INFO L93 Difference]: Finished difference Result 3334 states and 4708 transitions. [2022-11-03 01:57:59,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:57:59,888 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:57:59,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:57:59,890 INFO L225 Difference]: With dead ends: 3334 [2022-11-03 01:57:59,890 INFO L226 Difference]: Without dead ends: 1824 [2022-11-03 01:57:59,933 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 163 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 01:57:59,934 INFO L413 NwaCegarLoop]: 75 mSDtfsCounter, 41 mSDsluCounter, 146 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 221 SdHoareTripleChecker+Invalid, 145 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 98 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:57:59,934 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 221 Invalid, 145 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 47 Invalid, 0 Unknown, 98 Unchecked, 0.1s Time] [2022-11-03 01:57:59,936 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1824 states. [2022-11-03 01:58:00,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1824 to 1824. [2022-11-03 01:58:00,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1824 states, 1823 states have (on average 1.401535929786067) internal successors, (2555), 1823 states have internal predecessors, (2555), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:00,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1824 states to 1824 states and 2555 transitions. [2022-11-03 01:58:00,007 INFO L78 Accepts]: Start accepts. Automaton has 1824 states and 2555 transitions. Word has length 167 [2022-11-03 01:58:00,007 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:58:00,008 INFO L495 AbstractCegarLoop]: Abstraction has 1824 states and 2555 transitions. [2022-11-03 01:58:00,008 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 23.6) internal successors, (118), 5 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:00,008 INFO L276 IsEmpty]: Start isEmpty. Operand 1824 states and 2555 transitions. [2022-11-03 01:58:00,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:58:00,012 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:58:00,012 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:58:00,061 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (33)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:00,226 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 33 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:58:00,226 INFO L420 AbstractCegarLoop]: === Iteration 21 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:58:00,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:58:00,227 INFO L85 PathProgramCache]: Analyzing trace with hash 524955073, now seen corresponding path program 1 times [2022-11-03 01:58:00,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:58:00,230 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [436990139] [2022-11-03 01:58:00,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:00,230 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:58:00,230 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:58:00,231 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:58:00,233 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (34)] Waiting until timeout for monitored process [2022-11-03 01:58:01,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:01,808 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:58:01,816 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:02,546 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:02,547 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:03,295 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:03,295 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:58:03,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [436990139] [2022-11-03 01:58:03,296 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [436990139] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:03,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1205775077] [2022-11-03 01:58:03,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:03,296 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:58:03,296 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:58:03,297 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:58:03,299 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (35)] Waiting until timeout for monitored process [2022-11-03 01:58:05,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:06,041 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:58:06,048 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:06,885 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:06,885 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:07,685 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:07,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1205775077] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:07,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [428771905] [2022-11-03 01:58:07,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:07,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:58:07,687 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:58:07,696 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:58:07,722 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2022-11-03 01:58:08,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:08,987 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 9 conjunts are in the unsatisfiable core [2022-11-03 01:58:08,995 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:09,668 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:09,668 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:10,398 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 3 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:10,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [428771905] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:10,399 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:58:10,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6, 6] total 10 [2022-11-03 01:58:10,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1478662263] [2022-11-03 01:58:10,399 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:58:10,400 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-11-03 01:58:10,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:58:10,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-11-03 01:58:10,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2022-11-03 01:58:10,401 INFO L87 Difference]: Start difference. First operand 1824 states and 2555 transitions. Second operand has 10 states, 10 states have (on average 19.3) internal successors, (193), 10 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:11,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:58:11,234 INFO L93 Difference]: Finished difference Result 7102 states and 9979 transitions. [2022-11-03 01:58:11,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 01:58:11,239 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 19.3) internal successors, (193), 10 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:58:11,239 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:58:11,245 INFO L225 Difference]: With dead ends: 7102 [2022-11-03 01:58:11,245 INFO L226 Difference]: Without dead ends: 6346 [2022-11-03 01:58:11,248 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1002 GetRequests, 986 SyntacticMatches, 2 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=70, Invalid=170, Unknown=0, NotChecked=0, Total=240 [2022-11-03 01:58:11,249 INFO L413 NwaCegarLoop]: 265 mSDtfsCounter, 403 mSDsluCounter, 666 mSDsCounter, 0 mSdLazyCounter, 286 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 403 SdHoareTripleChecker+Valid, 931 SdHoareTripleChecker+Invalid, 657 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 286 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 370 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-03 01:58:11,249 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [403 Valid, 931 Invalid, 657 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 286 Invalid, 0 Unknown, 370 Unchecked, 0.6s Time] [2022-11-03 01:58:11,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6346 states. [2022-11-03 01:58:11,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6346 to 1840. [2022-11-03 01:58:11,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1840 states, 1839 states have (on average 1.398042414355628) internal successors, (2571), 1839 states have internal predecessors, (2571), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:11,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1840 states to 1840 states and 2571 transitions. [2022-11-03 01:58:11,329 INFO L78 Accepts]: Start accepts. Automaton has 1840 states and 2571 transitions. Word has length 167 [2022-11-03 01:58:11,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:58:11,329 INFO L495 AbstractCegarLoop]: Abstraction has 1840 states and 2571 transitions. [2022-11-03 01:58:11,330 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 19.3) internal successors, (193), 10 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:11,330 INFO L276 IsEmpty]: Start isEmpty. Operand 1840 states and 2571 transitions. [2022-11-03 01:58:11,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:58:11,334 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:58:11,335 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:58:11,367 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (35)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:11,586 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:11,790 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (34)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:11,951 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 35 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,36 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,34 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:58:11,951 INFO L420 AbstractCegarLoop]: === Iteration 22 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:58:11,951 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:58:11,952 INFO L85 PathProgramCache]: Analyzing trace with hash 947656899, now seen corresponding path program 1 times [2022-11-03 01:58:11,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:58:11,954 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [972272979] [2022-11-03 01:58:11,954 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:11,954 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:58:11,955 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:58:11,955 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:58:11,957 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (37)] Waiting until timeout for monitored process [2022-11-03 01:58:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:13,544 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:58:13,549 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:16,603 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 19 proven. 5 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:16,603 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:17,578 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 19 proven. 5 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:17,579 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:58:17,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [972272979] [2022-11-03 01:58:17,579 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [972272979] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:17,579 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [55751688] [2022-11-03 01:58:17,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:17,579 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:58:17,579 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:58:17,580 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:58:17,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (38)] Waiting until timeout for monitored process [2022-11-03 01:58:20,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:20,508 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 01:58:20,515 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:21,199 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 19 proven. 5 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:21,199 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:21,987 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 19 proven. 5 refuted. 0 times theorem prover too weak. 61 trivial. 0 not checked. [2022-11-03 01:58:21,988 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [55751688] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:21,988 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1178671512] [2022-11-03 01:58:21,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:21,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:58:21,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:58:21,989 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:58:22,006 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2022-11-03 01:58:23,186 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:23,228 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:58:23,235 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:23,722 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 21 proven. 0 refuted. 0 times theorem prover too weak. 64 trivial. 0 not checked. [2022-11-03 01:58:23,722 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:58:23,722 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1178671512] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:58:23,722 INFO L184 FreeRefinementEngine]: Found 1 perfect and 4 imperfect interpolant sequences. [2022-11-03 01:58:23,722 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8, 7, 8, 7] total 16 [2022-11-03 01:58:23,723 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636097234] [2022-11-03 01:58:23,723 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:58:23,723 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:58:23,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:58:23,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:58:23,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=190, Unknown=1, NotChecked=0, Total=240 [2022-11-03 01:58:23,724 INFO L87 Difference]: Start difference. First operand 1840 states and 2571 transitions. Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:23,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:58:23,857 INFO L93 Difference]: Finished difference Result 2553 states and 3563 transitions. [2022-11-03 01:58:23,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:58:23,863 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:58:23,863 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:58:23,866 INFO L225 Difference]: With dead ends: 2553 [2022-11-03 01:58:23,866 INFO L226 Difference]: Without dead ends: 2121 [2022-11-03 01:58:23,868 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 830 GetRequests, 813 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=49, Invalid=190, Unknown=1, NotChecked=0, Total=240 [2022-11-03 01:58:23,869 INFO L413 NwaCegarLoop]: 84 mSDtfsCounter, 17 mSDsluCounter, 227 mSDsCounter, 0 mSdLazyCounter, 44 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 17 SdHoareTripleChecker+Valid, 311 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 44 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 105 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:58:23,870 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [17 Valid, 311 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 44 Invalid, 0 Unknown, 105 Unchecked, 0.1s Time] [2022-11-03 01:58:23,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2121 states. [2022-11-03 01:58:23,936 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2121 to 2117. [2022-11-03 01:58:23,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2117 states, 2116 states have (on average 1.3969754253308129) internal successors, (2956), 2116 states have internal predecessors, (2956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:23,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2117 states to 2117 states and 2956 transitions. [2022-11-03 01:58:23,943 INFO L78 Accepts]: Start accepts. Automaton has 2117 states and 2956 transitions. Word has length 167 [2022-11-03 01:58:23,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:58:23,944 INFO L495 AbstractCegarLoop]: Abstraction has 2117 states and 2956 transitions. [2022-11-03 01:58:23,944 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:23,945 INFO L276 IsEmpty]: Start isEmpty. Operand 2117 states and 2956 transitions. [2022-11-03 01:58:23,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:58:23,949 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:58:23,949 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:58:24,013 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:24,204 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (38)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:24,436 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (37)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:24,574 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 39 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,38 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,37 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:58:24,575 INFO L420 AbstractCegarLoop]: === Iteration 23 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:58:24,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:58:24,575 INFO L85 PathProgramCache]: Analyzing trace with hash -741286843, now seen corresponding path program 1 times [2022-11-03 01:58:24,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:58:24,579 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [720687376] [2022-11-03 01:58:24,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:24,579 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:58:24,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:58:24,581 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:58:24,587 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (40)] Waiting until timeout for monitored process [2022-11-03 01:58:26,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:26,214 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 01:58:26,220 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:27,161 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:27,162 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:28,188 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:28,189 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:58:28,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [720687376] [2022-11-03 01:58:28,189 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [720687376] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:28,189 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1896942690] [2022-11-03 01:58:28,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:28,189 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:58:28,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:58:28,191 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:58:28,207 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (41)] Waiting until timeout for monitored process [2022-11-03 01:58:30,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:31,021 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 01:58:31,027 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:31,761 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:31,762 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:32,620 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:32,621 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1896942690] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:32,621 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [692170227] [2022-11-03 01:58:32,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:32,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:58:32,622 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:58:32,623 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:58:32,626 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2022-11-03 01:58:33,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:33,790 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 01:58:33,797 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:34,654 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:34,654 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:35,689 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 5 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:35,689 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [692170227] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:35,689 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 01:58:35,690 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 14 [2022-11-03 01:58:35,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489641255] [2022-11-03 01:58:35,690 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 01:58:35,691 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-03 01:58:35,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:58:35,691 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-03 01:58:35,691 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2022-11-03 01:58:35,692 INFO L87 Difference]: Start difference. First operand 2117 states and 2956 transitions. Second operand has 14 states, 14 states have (on average 13.5) internal successors, (189), 14 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:36,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:58:36,355 INFO L93 Difference]: Finished difference Result 4188 states and 5856 transitions. [2022-11-03 01:58:36,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 01:58:36,356 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 13.5) internal successors, (189), 14 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:58:36,356 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:58:36,359 INFO L225 Difference]: With dead ends: 4188 [2022-11-03 01:58:36,359 INFO L226 Difference]: Without dead ends: 3432 [2022-11-03 01:58:36,360 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1001 GetRequests, 982 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=76, Invalid=266, Unknown=0, NotChecked=0, Total=342 [2022-11-03 01:58:36,361 INFO L413 NwaCegarLoop]: 136 mSDtfsCounter, 280 mSDsluCounter, 940 mSDsCounter, 0 mSdLazyCounter, 256 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 280 SdHoareTripleChecker+Valid, 1076 SdHoareTripleChecker+Invalid, 584 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 256 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 326 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 01:58:36,362 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [280 Valid, 1076 Invalid, 584 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 256 Invalid, 0 Unknown, 326 Unchecked, 0.5s Time] [2022-11-03 01:58:36,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3432 states. [2022-11-03 01:58:36,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3432 to 2157. [2022-11-03 01:58:36,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2157 states, 2156 states have (on average 1.3942486085343229) internal successors, (3006), 2156 states have internal predecessors, (3006), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:36,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2157 states to 2157 states and 3006 transitions. [2022-11-03 01:58:36,428 INFO L78 Accepts]: Start accepts. Automaton has 2157 states and 3006 transitions. Word has length 167 [2022-11-03 01:58:36,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:58:36,428 INFO L495 AbstractCegarLoop]: Abstraction has 2157 states and 3006 transitions. [2022-11-03 01:58:36,428 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 13.5) internal successors, (189), 14 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:36,429 INFO L276 IsEmpty]: Start isEmpty. Operand 2157 states and 3006 transitions. [2022-11-03 01:58:36,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:58:36,432 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:58:36,433 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:58:36,486 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (40)] Ended with exit code 0 [2022-11-03 01:58:36,666 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (41)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:36,887 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:37,049 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 40 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,41 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,42 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:58:37,049 INFO L420 AbstractCegarLoop]: === Iteration 24 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:58:37,050 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:58:37,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1328092857, now seen corresponding path program 1 times [2022-11-03 01:58:37,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:58:37,053 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1130125114] [2022-11-03 01:58:37,053 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:37,053 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:58:37,053 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:58:37,055 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:58:37,071 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (43)] Waiting until timeout for monitored process [2022-11-03 01:58:38,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:38,684 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 01:58:38,690 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:41,597 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 11 proven. 7 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:41,597 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:42,721 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 11 proven. 7 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:42,721 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 01:58:42,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1130125114] [2022-11-03 01:58:42,721 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1130125114] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:42,721 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1937978574] [2022-11-03 01:58:42,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:42,721 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 01:58:42,722 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 01:58:42,723 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 01:58:42,725 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (44)] Waiting until timeout for monitored process [2022-11-03 01:58:45,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:45,681 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 14 conjunts are in the unsatisfiable core [2022-11-03 01:58:45,687 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:46,556 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 11 proven. 7 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:46,557 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 01:58:47,475 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 11 proven. 7 refuted. 0 times theorem prover too weak. 67 trivial. 0 not checked. [2022-11-03 01:58:47,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1937978574] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 01:58:47,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [298844235] [2022-11-03 01:58:47,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:47,475 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 01:58:47,476 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 01:58:47,476 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 01:58:47,478 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2022-11-03 01:58:48,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:48,642 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 01:58:48,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:49,214 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2022-11-03 01:58:49,214 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 01:58:49,214 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [298844235] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 01:58:49,214 INFO L184 FreeRefinementEngine]: Found 1 perfect and 4 imperfect interpolant sequences. [2022-11-03 01:58:49,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [10, 9, 10, 9] total 20 [2022-11-03 01:58:49,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14187863] [2022-11-03 01:58:49,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 01:58:49,215 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 01:58:49,215 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 01:58:49,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 01:58:49,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=318, Unknown=1, NotChecked=0, Total=380 [2022-11-03 01:58:49,216 INFO L87 Difference]: Start difference. First operand 2157 states and 3006 transitions. Second operand has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:49,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 01:58:49,359 INFO L93 Difference]: Finished difference Result 2989 states and 4171 transitions. [2022-11-03 01:58:49,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 01:58:49,360 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 167 [2022-11-03 01:58:49,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 01:58:49,362 INFO L225 Difference]: With dead ends: 2989 [2022-11-03 01:58:49,362 INFO L226 Difference]: Without dead ends: 2173 [2022-11-03 01:58:49,363 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 830 GetRequests, 809 SyntacticMatches, 3 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 58 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=61, Invalid=318, Unknown=1, NotChecked=0, Total=380 [2022-11-03 01:58:49,363 INFO L413 NwaCegarLoop]: 75 mSDtfsCounter, 41 mSDsluCounter, 148 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 41 SdHoareTripleChecker+Valid, 223 SdHoareTripleChecker+Invalid, 145 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 98 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 01:58:49,364 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [41 Valid, 223 Invalid, 145 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 47 Invalid, 0 Unknown, 98 Unchecked, 0.1s Time] [2022-11-03 01:58:49,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2173 states. [2022-11-03 01:58:49,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2173 to 1333. [2022-11-03 01:58:49,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1333 states, 1332 states have (on average 1.3881381381381381) internal successors, (1849), 1332 states have internal predecessors, (1849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:49,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1333 states to 1333 states and 1849 transitions. [2022-11-03 01:58:49,401 INFO L78 Accepts]: Start accepts. Automaton has 1333 states and 1849 transitions. Word has length 167 [2022-11-03 01:58:49,401 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 01:58:49,401 INFO L495 AbstractCegarLoop]: Abstraction has 1333 states and 1849 transitions. [2022-11-03 01:58:49,402 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 19.2) internal successors, (96), 5 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 01:58:49,402 INFO L276 IsEmpty]: Start isEmpty. Operand 1333 states and 1849 transitions. [2022-11-03 01:58:49,404 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2022-11-03 01:58:49,404 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 01:58:49,405 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 01:58:49,434 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (44)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:49,667 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:49,869 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (43)] Forceful destruction successful, exit code 0 [2022-11-03 01:58:50,028 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 44 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,45 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,43 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 01:58:50,028 INFO L420 AbstractCegarLoop]: === Iteration 25 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 01:58:50,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 01:58:50,029 INFO L85 PathProgramCache]: Analyzing trace with hash -627028279, now seen corresponding path program 1 times [2022-11-03 01:58:50,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 01:58:50,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1395545607] [2022-11-03 01:58:50,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 01:58:50,031 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 01:58:50,031 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 01:58:50,033 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 01:58:50,037 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f3aac3e8-cf51-4410-b322-ca2c3eec7604/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (46)] Waiting until timeout for monitored process [2022-11-03 01:58:51,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 01:58:51,602 INFO L263 TraceCheckSpWp]: Trace formula consists of 3060 conjuncts, 79 conjunts are in the unsatisfiable core [2022-11-03 01:58:51,610 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 01:58:53,390 INFO L134 CoverageAnalysis]: Checked inductivity of 85 backedges. 0 proven. 85 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 01:58:53,391 INFO L328 TraceCheckSpWp]: Computing backward predicates...