./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 32680cd5468fc7b83afae376e65e08c96334765648dec339f78f485e369894d8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 03:46:45,074 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 03:46:45,077 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 03:46:45,116 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 03:46:45,117 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 03:46:45,118 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 03:46:45,120 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 03:46:45,122 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 03:46:45,124 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 03:46:45,126 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 03:46:45,127 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 03:46:45,129 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 03:46:45,129 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 03:46:45,131 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 03:46:45,133 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 03:46:45,135 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 03:46:45,136 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 03:46:45,137 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 03:46:45,140 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 03:46:45,143 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 03:46:45,145 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 03:46:45,147 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 03:46:45,149 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 03:46:45,150 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 03:46:45,156 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 03:46:45,157 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 03:46:45,157 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 03:46:45,159 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 03:46:45,160 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 03:46:45,161 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 03:46:45,161 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 03:46:45,163 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 03:46:45,164 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 03:46:45,165 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 03:46:45,166 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 03:46:45,167 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 03:46:45,168 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 03:46:45,168 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 03:46:45,168 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 03:46:45,170 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 03:46:45,171 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 03:46:45,176 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 03:46:45,219 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 03:46:45,224 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 03:46:45,225 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 03:46:45,225 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 03:46:45,226 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 03:46:45,227 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 03:46:45,227 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 03:46:45,227 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 03:46:45,228 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 03:46:45,228 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 03:46:45,229 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 03:46:45,229 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 03:46:45,230 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 03:46:45,230 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 03:46:45,230 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 03:46:45,230 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 03:46:45,231 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 03:46:45,231 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 03:46:45,232 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 03:46:45,232 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 03:46:45,232 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 03:46:45,233 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 03:46:45,233 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 03:46:45,233 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 03:46:45,233 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 03:46:45,234 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 03:46:45,234 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 03:46:45,234 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 03:46:45,234 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 03:46:45,235 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:46:45,236 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 03:46:45,236 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 03:46:45,236 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 03:46:45,237 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 03:46:45,237 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 03:46:45,237 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 03:46:45,237 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 03:46:45,238 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 03:46:45,238 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32680cd5468fc7b83afae376e65e08c96334765648dec339f78f485e369894d8 [2022-11-03 03:46:45,600 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 03:46:45,626 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 03:46:45,630 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 03:46:45,631 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 03:46:45,632 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 03:46:45,634 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:46:45,725 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/425060220/c50b5965a09a419d89be11d6f4d9c8bb/FLAGadae0fdcf [2022-11-03 03:46:46,471 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 03:46:46,472 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:46:46,491 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/425060220/c50b5965a09a419d89be11d6f4d9c8bb/FLAGadae0fdcf [2022-11-03 03:46:46,696 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/425060220/c50b5965a09a419d89be11d6f4d9c8bb [2022-11-03 03:46:46,700 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 03:46:46,705 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 03:46:46,708 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 03:46:46,708 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 03:46:46,712 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 03:46:46,713 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:46:46" (1/1) ... [2022-11-03 03:46:46,715 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6cdc69e7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:46, skipping insertion in model container [2022-11-03 03:46:46,715 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:46:46" (1/1) ... [2022-11-03 03:46:46,725 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 03:46:46,781 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 03:46:47,074 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c[1014,1027] [2022-11-03 03:46:47,477 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:46:47,481 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 03:46:47,493 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c[1014,1027] [2022-11-03 03:46:47,692 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:46:47,738 INFO L208 MainTranslator]: Completed translation [2022-11-03 03:46:47,752 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47 WrapperNode [2022-11-03 03:46:47,752 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 03:46:47,753 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 03:46:47,754 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 03:46:47,754 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 03:46:47,776 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:47,874 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,135 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1526 [2022-11-03 03:46:48,135 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 03:46:48,136 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 03:46:48,137 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 03:46:48,137 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 03:46:48,147 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,147 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,171 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,171 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,279 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,286 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,305 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,323 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,365 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 03:46:48,366 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 03:46:48,367 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 03:46:48,367 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 03:46:48,368 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (1/1) ... [2022-11-03 03:46:48,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:46:48,385 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:46:48,398 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 03:46:48,422 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 03:46:48,445 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 03:46:48,447 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 03:46:48,945 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 03:46:48,947 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 03:48:32,390 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 03:48:45,550 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 03:48:45,550 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 03:48:45,553 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:48:45 BoogieIcfgContainer [2022-11-03 03:48:45,553 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 03:48:45,557 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 03:48:45,557 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 03:48:45,561 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 03:48:45,562 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 03:46:46" (1/3) ... [2022-11-03 03:48:45,563 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f604bac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:48:45, skipping insertion in model container [2022-11-03 03:48:45,563 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:46:47" (2/3) ... [2022-11-03 03:48:45,564 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6f604bac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:48:45, skipping insertion in model container [2022-11-03 03:48:45,564 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:48:45" (3/3) ... [2022-11-03 03:48:45,566 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:48:45,590 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 03:48:45,590 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 03:48:45,649 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 03:48:45,658 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@ccdaecb, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 03:48:45,659 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 03:48:45,664 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:48:45,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 03:48:45,671 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:48:45,672 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 03:48:45,673 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:48:45,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:48:45,680 INFO L85 PathProgramCache]: Analyzing trace with hash 6204345, now seen corresponding path program 1 times [2022-11-03 03:48:45,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 03:48:45,693 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386670465] [2022-11-03 03:48:45,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:48:45,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 03:48:46,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:48:49,300 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:48:49,301 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 03:48:49,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386670465] [2022-11-03 03:48:49,304 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386670465] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:48:49,304 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:48:49,304 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 03:48:49,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369771585] [2022-11-03 03:48:49,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:48:49,314 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:48:49,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 03:48:49,356 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:48:49,357 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:48:49,360 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:48:51,719 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.23s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 03:48:51,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:48:51,915 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 03:48:51,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:48:51,918 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 03:48:51,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:48:51,927 INFO L225 Difference]: With dead ends: 15 [2022-11-03 03:48:51,927 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 03:48:51,929 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:48:51,933 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.5s IncrementalHoareTripleChecker+Time [2022-11-03 03:48:51,935 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 1 Unknown, 0 Unchecked, 2.5s Time] [2022-11-03 03:48:51,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 03:48:51,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 03:48:51,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:48:51,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 03:48:51,971 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 03:48:51,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:48:51,971 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 03:48:51,972 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:48:51,972 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 03:48:51,972 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 03:48:51,973 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:48:51,973 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 03:48:51,974 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 03:48:51,974 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:48:51,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:48:51,975 INFO L85 PathProgramCache]: Analyzing trace with hash 160750953, now seen corresponding path program 1 times [2022-11-03 03:48:51,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 03:48:51,977 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430303842] [2022-11-03 03:48:51,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:48:51,978 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 03:50:54,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 03:50:54,125 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 03:53:05,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 03:53:05,832 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 03:53:05,833 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 03:53:05,835 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 03:53:05,838 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 03:53:05,843 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 03:53:05,848 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 03:53:06,017 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:53:06,018 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:53:06,086 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 03:53:06 BoogieIcfgContainer [2022-11-03 03:53:06,086 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 03:53:06,088 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 03:53:06,089 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 03:53:06,089 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 03:53:06,090 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:48:45" (3/4) ... [2022-11-03 03:53:06,094 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 03:53:06,094 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 03:53:06,095 INFO L158 Benchmark]: Toolchain (without parser) took 379389.90ms. Allocated memory was 104.9MB in the beginning and 3.0GB in the end (delta: 2.9GB). Free memory was 65.2MB in the beginning and 2.7GB in the end (delta: -2.6GB). Peak memory consumption was 263.3MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,097 INFO L158 Benchmark]: CDTParser took 0.33ms. Allocated memory is still 104.9MB. Free memory was 84.1MB in the beginning and 84.0MB in the end (delta: 91.0kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 03:53:06,103 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1044.78ms. Allocated memory is still 104.9MB. Free memory was 65.0MB in the beginning and 67.3MB in the end (delta: -2.3MB). Peak memory consumption was 25.4MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,105 INFO L158 Benchmark]: Boogie Procedure Inliner took 382.12ms. Allocated memory was 104.9MB in the beginning and 155.2MB in the end (delta: 50.3MB). Free memory was 66.8MB in the beginning and 95.6MB in the end (delta: -28.8MB). Peak memory consumption was 38.1MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,105 INFO L158 Benchmark]: Boogie Preprocessor took 229.69ms. Allocated memory is still 155.2MB. Free memory was 95.6MB in the beginning and 78.2MB in the end (delta: 17.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,106 INFO L158 Benchmark]: RCFGBuilder took 117186.65ms. Allocated memory was 155.2MB in the beginning and 2.1GB in the end (delta: 1.9GB). Free memory was 78.2MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 862.3MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,107 INFO L158 Benchmark]: TraceAbstraction took 260529.92ms. Allocated memory was 2.1GB in the beginning and 3.0GB in the end (delta: 876.6MB). Free memory was 1.5GB in the beginning and 2.7GB in the end (delta: -1.2GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. [2022-11-03 03:53:06,111 INFO L158 Benchmark]: Witness Printer took 5.78ms. Allocated memory is still 3.0GB. Free memory was 2.7GB in the beginning and 2.7GB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-03 03:53:06,118 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.33ms. Allocated memory is still 104.9MB. Free memory was 84.1MB in the beginning and 84.0MB in the end (delta: 91.0kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1044.78ms. Allocated memory is still 104.9MB. Free memory was 65.0MB in the beginning and 67.3MB in the end (delta: -2.3MB). Peak memory consumption was 25.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 382.12ms. Allocated memory was 104.9MB in the beginning and 155.2MB in the end (delta: 50.3MB). Free memory was 66.8MB in the beginning and 95.6MB in the end (delta: -28.8MB). Peak memory consumption was 38.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 229.69ms. Allocated memory is still 155.2MB. Free memory was 95.6MB in the beginning and 78.2MB in the end (delta: 17.4MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * RCFGBuilder took 117186.65ms. Allocated memory was 155.2MB in the beginning and 2.1GB in the end (delta: 1.9GB). Free memory was 78.2MB in the beginning and 1.5GB in the end (delta: -1.4GB). Peak memory consumption was 862.3MB. Max. memory is 16.1GB. * TraceAbstraction took 260529.92ms. Allocated memory was 2.1GB in the beginning and 3.0GB in the end (delta: 876.6MB). Free memory was 1.5GB in the beginning and 2.7GB in the end (delta: -1.2GB). Peak memory consumption was 1.3GB. Max. memory is 16.1GB. * Witness Printer took 5.78ms. Allocated memory is still 3.0GB. Free memory was 2.7GB in the beginning and 2.7GB in the end (delta: 1.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseOr at line 199, overapproximation of shiftRight at line 203, overapproximation of bitwiseAnd at line 159, overapproximation of bitwiseComplement at line 201. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 5); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (5 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_3 var_5 = 0; [L38] const SORT_1 var_14 = 0; [L39] const SORT_4 var_57 = 5; [L40] const SORT_3 var_58 = 0; [L41] const SORT_4 var_60 = 16; [L42] const SORT_4 var_63 = 1; [L43] const SORT_4 var_64 = 0; [L44] const SORT_3 var_71 = 1; [L45] const SORT_3 var_74 = 0; [L46] const SORT_3 var_100 = 3; [L47] const SORT_4 var_209 = 6200; [L48] const SORT_4 var_225 = 999; [L49] const SORT_4 var_227 = 5999; [L50] const SORT_4 var_233 = 1000; [L51] const SORT_4 var_238 = 5800; [L53] SORT_1 input_70; [L54] SORT_1 input_72; [L55] SORT_1 input_73; [L56] SORT_1 input_75; [L57] SORT_1 input_81; [L58] SORT_1 input_82; [L59] SORT_1 input_83; [L60] SORT_1 input_88; [L61] SORT_1 input_99; [L62] SORT_1 input_101; [L63] SORT_1 input_104; [L64] SORT_1 input_111; [L65] SORT_1 input_116; [L66] SORT_1 input_120; [L67] SORT_1 input_133; [L68] SORT_1 input_143; [L69] SORT_1 input_147; [L70] SORT_1 input_152; [L71] SORT_1 input_154; [L72] SORT_1 input_158; [L73] SORT_1 input_162; [L74] SORT_1 input_166; [L75] SORT_1 input_175; [L76] SORT_1 input_182; [L77] SORT_1 input_184; [L78] SORT_1 input_190; [L80] SORT_3 state_6 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L81] SORT_3 state_8 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L82] SORT_3 state_10 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L83] SORT_3 state_12 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L84] SORT_1 state_15 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] SORT_1 state_17 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] SORT_1 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L87] SORT_1 state_21 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L88] SORT_1 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] SORT_1 state_25 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] SORT_1 state_27 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] SORT_1 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L97] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L99] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L100] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L101] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L102] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L103] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L104] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L106] SORT_3 init_7_arg_1 = var_5; [L107] state_6 = init_7_arg_1 [L108] SORT_3 init_9_arg_1 = var_5; [L109] state_8 = init_9_arg_1 [L110] SORT_3 init_11_arg_1 = var_5; [L111] state_10 = init_11_arg_1 [L112] SORT_3 init_13_arg_1 = var_5; [L113] state_12 = init_13_arg_1 [L114] SORT_1 init_16_arg_1 = var_14; [L115] state_15 = init_16_arg_1 [L116] SORT_1 init_18_arg_1 = var_14; [L117] state_17 = init_18_arg_1 [L118] SORT_1 init_20_arg_1 = var_14; [L119] state_19 = init_20_arg_1 [L120] SORT_1 init_22_arg_1 = var_14; [L121] state_21 = init_22_arg_1 [L122] SORT_1 init_24_arg_1 = var_14; [L123] state_23 = init_24_arg_1 [L124] SORT_1 init_26_arg_1 = var_14; [L125] state_25 = init_26_arg_1 [L126] SORT_1 init_28_arg_1 = var_14; [L127] state_27 = init_28_arg_1 [L128] SORT_1 init_30_arg_1 = var_14; [L129] state_29 = init_30_arg_1 [L130] SORT_1 init_32_arg_1 = var_14; [L131] state_31 = init_32_arg_1 [L132] SORT_1 init_34_arg_1 = var_14; [L133] state_33 = init_34_arg_1 [L134] SORT_1 init_36_arg_1 = var_14; [L135] state_35 = init_36_arg_1 [L136] SORT_1 init_38_arg_1 = var_14; [L137] state_37 = init_38_arg_1 [L138] SORT_1 init_40_arg_1 = var_14; [L139] state_39 = init_40_arg_1 [L140] SORT_1 init_42_arg_1 = var_14; [L141] state_41 = init_42_arg_1 [L142] SORT_1 init_44_arg_1 = var_14; [L143] state_43 = init_44_arg_1 [L144] SORT_1 init_46_arg_1 = var_14; [L145] state_45 = init_46_arg_1 [L146] SORT_1 init_48_arg_1 = var_14; [L147] state_47 = init_48_arg_1 [L148] SORT_1 init_50_arg_1 = var_14; [L149] state_49 = init_50_arg_1 [L150] SORT_1 init_52_arg_1 = var_14; [L151] state_51 = init_52_arg_1 [L152] SORT_1 init_54_arg_1 = var_14; [L153] state_53 = init_54_arg_1 [L154] SORT_1 init_56_arg_1 = var_14; [L155] state_55 = init_56_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_16_arg_1=0, init_18_arg_1=0, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=31, mask_SORT_3=65535, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=16, msb_SORT_3=32768, msb_SORT_4=2147483648, state_10=0, state_12=0, state_15=0, state_17=0, state_19=0, state_21=0, state_23=0, state_25=0, state_27=0, state_29=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_6=0, state_8=0, var_100=3, var_14=0, var_209=6200, var_225=999, var_227=5999, var_233=1000, var_238=5800, var_5=0, var_57=5, var_58=0, var_60=16, var_63=1, var_64=0, var_71=1, var_74=0] [L158] input_70 = __VERIFIER_nondet_uchar() [L159] input_70 = input_70 & mask_SORT_1 [L160] input_72 = __VERIFIER_nondet_uchar() [L161] input_72 = input_72 & mask_SORT_1 [L162] input_73 = __VERIFIER_nondet_uchar() [L163] input_73 = input_73 & mask_SORT_1 [L164] input_75 = __VERIFIER_nondet_uchar() [L165] input_75 = input_75 & mask_SORT_1 [L166] input_81 = __VERIFIER_nondet_uchar() [L167] input_81 = input_81 & mask_SORT_1 [L168] input_82 = __VERIFIER_nondet_uchar() [L169] input_82 = input_82 & mask_SORT_1 [L170] input_83 = __VERIFIER_nondet_uchar() [L171] input_83 = input_83 & mask_SORT_1 [L172] input_88 = __VERIFIER_nondet_uchar() [L173] input_88 = input_88 & mask_SORT_1 [L174] input_99 = __VERIFIER_nondet_uchar() [L175] input_99 = input_99 & mask_SORT_1 [L176] input_101 = __VERIFIER_nondet_uchar() [L177] input_101 = input_101 & mask_SORT_1 [L178] input_104 = __VERIFIER_nondet_uchar() [L179] input_104 = input_104 & mask_SORT_1 [L180] input_111 = __VERIFIER_nondet_uchar() [L181] input_116 = __VERIFIER_nondet_uchar() [L182] input_120 = __VERIFIER_nondet_uchar() [L183] input_133 = __VERIFIER_nondet_uchar() [L184] input_143 = __VERIFIER_nondet_uchar() [L185] input_147 = __VERIFIER_nondet_uchar() [L186] input_152 = __VERIFIER_nondet_uchar() [L187] input_154 = __VERIFIER_nondet_uchar() [L188] input_158 = __VERIFIER_nondet_uchar() [L189] input_162 = __VERIFIER_nondet_uchar() [L190] input_166 = __VERIFIER_nondet_uchar() [L191] input_175 = __VERIFIER_nondet_uchar() [L192] input_182 = __VERIFIER_nondet_uchar() [L193] input_184 = __VERIFIER_nondet_uchar() [L194] input_190 = __VERIFIER_nondet_uchar() [L197] SORT_3 var_59_arg_0 = state_12; [L198] SORT_3 var_59_arg_1 = var_58; [L199] SORT_4 var_59 = ((SORT_4)var_59_arg_0 << 16) | var_59_arg_1; [L200] SORT_4 var_61_arg_0 = var_59; [L201] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L201] var_61_arg_0 = (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L202] SORT_4 var_61_arg_1 = var_60; [L203] SORT_4 var_61 = (int)var_61_arg_0 >> var_61_arg_1; [L204] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L204] var_61 = (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L205] var_61 = var_61 & mask_SORT_4 [L206] SORT_4 var_62_arg_0 = var_57; [L207] SORT_4 var_62_arg_1 = var_61; [L208] SORT_1 var_62 = var_62_arg_0 == var_62_arg_1; [L209] SORT_1 var_65_arg_0 = state_35; [L210] SORT_4 var_65_arg_1 = var_63; [L211] SORT_4 var_65_arg_2 = var_64; [L212] EXPR var_65_arg_0 ? var_65_arg_1 : var_65_arg_2 [L212] SORT_4 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L213] var_65 = var_65 & mask_SORT_4 [L214] SORT_4 var_66_arg_0 = var_63; [L215] SORT_4 var_66_arg_1 = var_65; [L216] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L217] SORT_1 var_67_arg_0 = ~var_62; [L218] var_67_arg_0 = var_67_arg_0 & mask_SORT_1 [L219] SORT_1 var_67_arg_1 = var_66; [L220] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L221] SORT_1 var_68_arg_0 = ~state_55; [L222] var_68_arg_0 = var_68_arg_0 & mask_SORT_1 [L223] SORT_1 var_68_arg_1 = var_67; [L224] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L225] var_68 = var_68 & mask_SORT_1 [L226] SORT_1 bad_69_arg_0 = var_68; [L227] CALL __VERIFIER_assert(!(bad_69_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L227] RET __VERIFIER_assert(!(bad_69_arg_0)) [L229] SORT_1 var_76_arg_0 = input_75; [L230] SORT_3 var_76_arg_1 = var_71; [L231] SORT_3 var_76_arg_2 = state_6; [L232] EXPR var_76_arg_0 ? var_76_arg_1 : var_76_arg_2 [L232] SORT_3 var_76 = var_76_arg_0 ? var_76_arg_1 : var_76_arg_2; [L233] SORT_1 var_77_arg_0 = input_73; [L234] SORT_3 var_77_arg_1 = var_74; [L235] SORT_3 var_77_arg_2 = var_76; [L236] EXPR var_77_arg_0 ? var_77_arg_1 : var_77_arg_2 [L236] SORT_3 var_77 = var_77_arg_0 ? var_77_arg_1 : var_77_arg_2; [L237] SORT_1 var_78_arg_0 = input_72; [L238] SORT_3 var_78_arg_1 = var_71; [L239] SORT_3 var_78_arg_2 = var_77; [L240] EXPR var_78_arg_0 ? var_78_arg_1 : var_78_arg_2 [L240] SORT_3 var_78 = var_78_arg_0 ? var_78_arg_1 : var_78_arg_2; [L241] SORT_1 var_79_arg_0 = input_70; [L242] SORT_3 var_79_arg_1 = var_71; [L243] SORT_3 var_79_arg_2 = var_78; [L244] EXPR var_79_arg_0 ? var_79_arg_1 : var_79_arg_2 [L244] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L245] SORT_3 next_80_arg_1 = var_79; [L246] SORT_3 var_84_arg_0 = state_8; [L247] SORT_3 var_84_arg_1 = var_58; [L248] SORT_4 var_84 = ((SORT_4)var_84_arg_0 << 16) | var_84_arg_1; [L249] SORT_4 var_85_arg_0 = var_84; [L250] EXPR (var_85_arg_0 & msb_SORT_4) ? (var_85_arg_0 | ~mask_SORT_4) : (var_85_arg_0 & mask_SORT_4) [L250] var_85_arg_0 = (var_85_arg_0 & msb_SORT_4) ? (var_85_arg_0 | ~mask_SORT_4) : (var_85_arg_0 & mask_SORT_4) [L251] SORT_4 var_85_arg_1 = var_60; [L252] SORT_4 var_85 = (int)var_85_arg_0 >> var_85_arg_1; [L253] EXPR (var_85_arg_0 & msb_SORT_4) ? (var_85 | ~(mask_SORT_4 >> var_85_arg_1)) : var_85 [L253] var_85 = (var_85_arg_0 & msb_SORT_4) ? (var_85 | ~(mask_SORT_4 >> var_85_arg_1)) : var_85 [L254] var_85 = var_85 & mask_SORT_4 [L255] SORT_4 var_86_arg_0 = var_85; [L256] SORT_4 var_86_arg_1 = var_63; [L257] SORT_4 var_86 = var_86_arg_0 - var_86_arg_1; [L258] SORT_4 var_87_arg_0 = var_86; [L259] SORT_3 var_87 = var_87_arg_0 >> 0; [L260] SORT_4 var_89_arg_0 = var_63; [L261] SORT_4 var_89_arg_1 = var_85; [L262] SORT_4 var_89 = var_89_arg_0 + var_89_arg_1; [L263] SORT_4 var_90_arg_0 = var_89; [L264] SORT_3 var_90 = var_90_arg_0 >> 0; [L265] SORT_1 var_91_arg_0 = input_88; [L266] SORT_3 var_91_arg_1 = var_90; [L267] SORT_3 var_91_arg_2 = state_8; [L268] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 [L268] SORT_3 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L269] SORT_1 var_92_arg_0 = input_75; [L270] SORT_3 var_92_arg_1 = var_87; [L271] SORT_3 var_92_arg_2 = var_91; [L272] EXPR var_92_arg_0 ? var_92_arg_1 : var_92_arg_2 [L272] SORT_3 var_92 = var_92_arg_0 ? var_92_arg_1 : var_92_arg_2; [L273] SORT_1 var_93_arg_0 = input_73; [L274] SORT_3 var_93_arg_1 = var_87; [L275] SORT_3 var_93_arg_2 = var_92; [L276] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 [L276] SORT_3 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L277] SORT_1 var_94_arg_0 = input_83; [L278] SORT_3 var_94_arg_1 = var_74; [L279] SORT_3 var_94_arg_2 = var_93; [L280] EXPR var_94_arg_0 ? var_94_arg_1 : var_94_arg_2 [L280] SORT_3 var_94 = var_94_arg_0 ? var_94_arg_1 : var_94_arg_2; [L281] SORT_1 var_95_arg_0 = input_82; [L282] SORT_3 var_95_arg_1 = var_74; [L283] SORT_3 var_95_arg_2 = var_94; [L284] EXPR var_95_arg_0 ? var_95_arg_1 : var_95_arg_2 [L284] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L285] SORT_1 var_96_arg_0 = input_81; [L286] SORT_3 var_96_arg_1 = var_74; [L287] SORT_3 var_96_arg_2 = var_95; [L288] EXPR var_96_arg_0 ? var_96_arg_1 : var_96_arg_2 [L288] SORT_3 var_96 = var_96_arg_0 ? var_96_arg_1 : var_96_arg_2; [L289] SORT_3 next_97_arg_1 = var_96; [L290] SORT_3 next_98_arg_1 = state_10; [L291] SORT_4 var_102_arg_0 = var_63; [L292] SORT_4 var_102_arg_1 = var_61; [L293] SORT_4 var_102 = var_102_arg_0 + var_102_arg_1; [L294] SORT_4 var_103_arg_0 = var_102; [L295] SORT_3 var_103 = var_103_arg_0 >> 0; [L296] SORT_4 var_105_arg_0 = var_61; [L297] SORT_4 var_105_arg_1 = var_63; [L298] SORT_4 var_105 = var_105_arg_0 - var_105_arg_1; [L299] SORT_4 var_106_arg_0 = var_105; [L300] SORT_3 var_106 = var_106_arg_0 >> 0; [L301] SORT_1 var_107_arg_0 = input_104; [L302] SORT_3 var_107_arg_1 = var_106; [L303] SORT_3 var_107_arg_2 = state_12; [L304] EXPR var_107_arg_0 ? var_107_arg_1 : var_107_arg_2 [L304] SORT_3 var_107 = var_107_arg_0 ? var_107_arg_1 : var_107_arg_2; [L305] SORT_1 var_108_arg_0 = input_101; [L306] SORT_3 var_108_arg_1 = var_103; [L307] SORT_3 var_108_arg_2 = var_107; [L308] EXPR var_108_arg_0 ? var_108_arg_1 : var_108_arg_2 [L308] SORT_3 var_108 = var_108_arg_0 ? var_108_arg_1 : var_108_arg_2; [L309] SORT_1 var_109_arg_0 = input_99; [L310] SORT_3 var_109_arg_1 = var_100; [L311] SORT_3 var_109_arg_2 = var_108; [L312] EXPR var_109_arg_0 ? var_109_arg_1 : var_109_arg_2 [L312] SORT_3 var_109 = var_109_arg_0 ? var_109_arg_1 : var_109_arg_2; [L313] SORT_3 next_110_arg_1 = var_109; [L314] SORT_1 var_112_arg_0 = state_15; [L315] SORT_1 var_112_arg_1 = input_111; [L316] SORT_1 var_112 = var_112_arg_0 | var_112_arg_1; [L317] SORT_1 var_113_arg_0 = var_112; [L318] SORT_1 var_113_arg_1 = input_75; [L319] SORT_1 var_113 = var_113_arg_0 | var_113_arg_1; [L320] SORT_1 var_114_arg_0 = var_113; [L321] SORT_1 var_114_arg_1 = ~input_73; [L322] var_114_arg_1 = var_114_arg_1 & mask_SORT_1 [L323] SORT_1 var_114 = var_114_arg_0 & var_114_arg_1; [L324] SORT_1 var_115_arg_0 = var_114; [L325] SORT_1 var_115_arg_1 = input_72; [L326] SORT_1 var_115 = var_115_arg_0 | var_115_arg_1; [L327] SORT_1 var_117_arg_0 = var_115; [L328] SORT_1 var_117_arg_1 = ~input_116; [L329] var_117_arg_1 = var_117_arg_1 & mask_SORT_1 [L330] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L331] SORT_1 next_118_arg_1 = var_117; [L332] SORT_1 var_119_arg_0 = state_17; [L333] SORT_1 var_119_arg_1 = ~input_111; [L334] var_119_arg_1 = var_119_arg_1 & mask_SORT_1 [L335] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L336] SORT_1 var_121_arg_0 = var_119; [L337] SORT_1 var_121_arg_1 = ~input_120; [L338] var_121_arg_1 = var_121_arg_1 & mask_SORT_1 [L339] SORT_1 var_121 = var_121_arg_0 & var_121_arg_1; [L340] SORT_1 var_122_arg_0 = var_121; [L341] SORT_1 var_122_arg_1 = input_116; [L342] SORT_1 var_122 = var_122_arg_0 | var_122_arg_1; [L343] SORT_1 next_123_arg_1 = var_122; [L344] SORT_1 var_124_arg_0 = state_19; [L345] SORT_1 var_124_arg_1 = ~input_75; [L346] var_124_arg_1 = var_124_arg_1 & mask_SORT_1 [L347] SORT_1 var_124 = var_124_arg_0 & var_124_arg_1; [L348] SORT_1 var_125_arg_0 = var_124; [L349] SORT_1 var_125_arg_1 = input_73; [L350] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L351] SORT_1 var_126_arg_0 = var_125; [L352] SORT_1 var_126_arg_1 = input_120; [L353] SORT_1 var_126 = var_126_arg_0 | var_126_arg_1; [L354] SORT_1 next_127_arg_1 = var_126; [L355] SORT_1 var_128_arg_0 = ~state_21; [L356] var_128_arg_0 = var_128_arg_0 & mask_SORT_1 [L357] SORT_1 var_128_arg_1 = ~input_72; [L358] var_128_arg_1 = var_128_arg_1 & mask_SORT_1 [L359] SORT_1 var_128 = var_128_arg_0 & var_128_arg_1; [L360] SORT_1 next_129_arg_1 = ~var_128; [L361] next_129_arg_1 = next_129_arg_1 & mask_SORT_1 [L362] SORT_1 var_130_arg_0 = state_23; [L363] SORT_1 var_130_arg_1 = ~input_83; [L364] var_130_arg_1 = var_130_arg_1 & mask_SORT_1 [L365] SORT_1 var_130 = var_130_arg_0 & var_130_arg_1; [L366] SORT_1 var_131_arg_0 = var_130; [L367] SORT_1 var_131_arg_1 = ~input_82; [L368] var_131_arg_1 = var_131_arg_1 & mask_SORT_1 [L369] SORT_1 var_131 = var_131_arg_0 & var_131_arg_1; [L370] SORT_1 var_132_arg_0 = var_131; [L371] SORT_1 var_132_arg_1 = ~input_81; [L372] var_132_arg_1 = var_132_arg_1 & mask_SORT_1 [L373] SORT_1 var_132 = var_132_arg_0 & var_132_arg_1; [L374] SORT_1 var_134_arg_0 = var_132; [L375] SORT_1 var_134_arg_1 = input_133; [L376] SORT_1 var_134 = var_134_arg_0 | var_134_arg_1; [L377] SORT_1 next_135_arg_1 = var_134; [L378] SORT_1 var_136_arg_0 = state_25; [L379] SORT_1 var_136_arg_1 = input_104; [L380] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L381] SORT_1 var_137_arg_0 = var_136; [L382] SORT_1 var_137_arg_1 = input_101; [L383] SORT_1 var_137 = var_137_arg_0 | var_137_arg_1; [L384] SORT_1 var_138_arg_0 = var_137; [L385] SORT_1 var_138_arg_1 = input_99; [L386] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L387] SORT_1 var_139_arg_0 = var_138; [L388] SORT_1 var_139_arg_1 = ~input_116; [L389] var_139_arg_1 = var_139_arg_1 & mask_SORT_1 [L390] SORT_1 var_139 = var_139_arg_0 & var_139_arg_1; [L391] SORT_1 next_140_arg_1 = var_139; [L392] SORT_1 var_141_arg_0 = state_27; [L393] SORT_1 var_141_arg_1 = input_82; [L394] SORT_1 var_141 = var_141_arg_0 | var_141_arg_1; [L395] SORT_1 var_142_arg_0 = var_141; [L396] SORT_1 var_142_arg_1 = ~input_104; [L397] var_142_arg_1 = var_142_arg_1 & mask_SORT_1 [L398] SORT_1 var_142 = var_142_arg_0 & var_142_arg_1; [L399] SORT_1 var_144_arg_0 = var_142; [L400] SORT_1 var_144_arg_1 = ~input_143; [L401] var_144_arg_1 = var_144_arg_1 & mask_SORT_1 [L402] SORT_1 var_144 = var_144_arg_0 & var_144_arg_1; [L403] SORT_1 next_145_arg_1 = var_144; [L404] SORT_1 var_146_arg_0 = state_29; [L405] SORT_1 var_146_arg_1 = input_83; [L406] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L407] SORT_1 var_148_arg_0 = var_146; [L408] SORT_1 var_148_arg_1 = ~input_147; [L409] var_148_arg_1 = var_148_arg_1 & mask_SORT_1 [L410] SORT_1 var_148 = var_148_arg_0 & var_148_arg_1; [L411] SORT_1 next_149_arg_1 = var_148; [L412] SORT_1 var_150_arg_0 = state_31; [L413] SORT_1 var_150_arg_1 = input_81; [L414] SORT_1 var_150 = var_150_arg_0 | var_150_arg_1; [L415] SORT_1 var_151_arg_0 = var_150; [L416] SORT_1 var_151_arg_1 = ~input_101; [L417] var_151_arg_1 = var_151_arg_1 & mask_SORT_1 [L418] SORT_1 var_151 = var_151_arg_0 & var_151_arg_1; [L419] SORT_1 var_153_arg_0 = var_151; [L420] SORT_1 var_153_arg_1 = ~input_152; [L421] var_153_arg_1 = var_153_arg_1 & mask_SORT_1 [L422] SORT_1 var_153 = var_153_arg_0 & var_153_arg_1; [L423] SORT_1 var_155_arg_0 = var_153; [L424] SORT_1 var_155_arg_1 = input_154; [L425] SORT_1 var_155 = var_155_arg_0 | var_155_arg_1; [L426] SORT_1 next_156_arg_1 = var_155; [L427] SORT_1 var_157_arg_0 = state_33; [L428] SORT_1 var_157_arg_1 = input_143; [L429] SORT_1 var_157 = var_157_arg_0 | var_157_arg_1; [L430] SORT_1 var_159_arg_0 = var_157; [L431] SORT_1 var_159_arg_1 = ~input_158; [L432] var_159_arg_1 = var_159_arg_1 & mask_SORT_1 [L433] SORT_1 var_159 = var_159_arg_0 & var_159_arg_1; [L434] SORT_1 next_160_arg_1 = var_159; [L435] SORT_1 var_161_arg_0 = state_35; [L436] SORT_1 var_161_arg_1 = input_152; [L437] SORT_1 var_161 = var_161_arg_0 | var_161_arg_1; [L438] SORT_1 var_163_arg_0 = var_161; [L439] SORT_1 var_163_arg_1 = ~input_162; [L440] var_163_arg_1 = var_163_arg_1 & mask_SORT_1 [L441] SORT_1 var_163 = var_163_arg_0 & var_163_arg_1; [L442] var_163 = var_163 & mask_SORT_1 [L443] SORT_1 next_164_arg_1 = var_163; [L444] SORT_1 var_165_arg_0 = ~state_37; [L445] var_165_arg_0 = var_165_arg_0 & mask_SORT_1 [L446] SORT_1 var_165_arg_1 = ~input_99; [L447] var_165_arg_1 = var_165_arg_1 & mask_SORT_1 [L448] SORT_1 var_165 = var_165_arg_0 & var_165_arg_1; [L449] SORT_1 var_167_arg_0 = var_165; [L450] SORT_1 var_167_arg_1 = input_166; [L451] SORT_1 var_167 = var_167_arg_0 | var_167_arg_1; [L452] SORT_1 next_168_arg_1 = ~var_167; [L453] next_168_arg_1 = next_168_arg_1 & mask_SORT_1 [L454] SORT_1 var_169_arg_0 = state_39; [L455] SORT_1 var_169_arg_1 = input_158; [L456] SORT_1 var_169 = var_169_arg_0 | var_169_arg_1; [L457] SORT_1 var_170_arg_0 = var_169; [L458] SORT_1 var_170_arg_1 = input_162; [L459] SORT_1 var_170 = var_170_arg_0 | var_170_arg_1; [L460] SORT_1 var_171_arg_0 = var_170; [L461] SORT_1 var_171_arg_1 = input_147; [L462] SORT_1 var_171 = var_171_arg_0 | var_171_arg_1; [L463] SORT_1 var_172_arg_0 = var_171; [L464] SORT_1 var_172_arg_1 = ~input_166; [L465] var_172_arg_1 = var_172_arg_1 & mask_SORT_1 [L466] SORT_1 var_172 = var_172_arg_0 & var_172_arg_1; [L467] SORT_1 next_173_arg_1 = var_172; [L468] SORT_1 var_174_arg_0 = state_41; [L469] SORT_1 var_174_arg_1 = input_116; [L470] SORT_1 var_174 = var_174_arg_0 | var_174_arg_1; [L471] SORT_1 var_176_arg_0 = var_174; [L472] SORT_1 var_176_arg_1 = ~input_175; [L473] var_176_arg_1 = var_176_arg_1 & mask_SORT_1 [L474] SORT_1 var_176 = var_176_arg_0 & var_176_arg_1; [L475] SORT_1 next_177_arg_1 = var_176; [L476] SORT_1 var_178_arg_0 = state_43; [L477] SORT_1 var_178_arg_1 = input_175; [L478] SORT_1 var_178 = var_178_arg_0 | var_178_arg_1; [L479] SORT_1 var_179_arg_0 = var_178; [L480] SORT_1 var_179_arg_1 = ~input_133; [L481] var_179_arg_1 = var_179_arg_1 & mask_SORT_1 [L482] SORT_1 var_179 = var_179_arg_0 & var_179_arg_1; [L483] SORT_1 var_180_arg_0 = var_179; [L484] SORT_1 var_180_arg_1 = ~input_154; [L485] var_180_arg_1 = var_180_arg_1 & mask_SORT_1 [L486] SORT_1 var_180 = var_180_arg_0 & var_180_arg_1; [L487] SORT_1 next_181_arg_1 = var_180; [L488] SORT_1 var_183_arg_0 = state_45; [L489] SORT_1 var_183_arg_1 = ~input_182; [L490] var_183_arg_1 = var_183_arg_1 & mask_SORT_1 [L491] SORT_1 var_183 = var_183_arg_0 & var_183_arg_1; [L492] SORT_1 var_185_arg_0 = var_183; [L493] SORT_1 var_185_arg_1 = ~input_184; [L494] var_185_arg_1 = var_185_arg_1 & mask_SORT_1 [L495] SORT_1 var_185 = var_185_arg_0 & var_185_arg_1; [L496] SORT_1 var_186_arg_0 = var_185; [L497] SORT_1 var_186_arg_1 = input_175; [L498] SORT_1 var_186 = var_186_arg_0 | var_186_arg_1; [L499] SORT_1 next_187_arg_1 = var_186; [L500] SORT_1 var_188_arg_0 = state_47; [L501] SORT_1 var_188_arg_1 = input_182; [L502] SORT_1 var_188 = var_188_arg_0 | var_188_arg_1; [L503] SORT_1 var_189_arg_0 = var_188; [L504] SORT_1 var_189_arg_1 = ~input_70; [L505] var_189_arg_1 = var_189_arg_1 & mask_SORT_1 [L506] SORT_1 var_189 = var_189_arg_0 & var_189_arg_1; [L507] SORT_1 var_191_arg_0 = var_189; [L508] SORT_1 var_191_arg_1 = ~input_190; [L509] var_191_arg_1 = var_191_arg_1 & mask_SORT_1 [L510] SORT_1 var_191 = var_191_arg_0 & var_191_arg_1; [L511] SORT_1 next_192_arg_1 = var_191; [L512] SORT_1 var_193_arg_0 = state_49; [L513] SORT_1 var_193_arg_1 = input_184; [L514] SORT_1 var_193 = var_193_arg_0 | var_193_arg_1; [L515] SORT_1 var_194_arg_0 = var_193; [L516] SORT_1 var_194_arg_1 = input_190; [L517] SORT_1 var_194 = var_194_arg_0 | var_194_arg_1; [L518] SORT_1 var_195_arg_0 = var_194; [L519] SORT_1 var_195_arg_1 = ~input_154; [L520] var_195_arg_1 = var_195_arg_1 & mask_SORT_1 [L521] SORT_1 var_195 = var_195_arg_0 & var_195_arg_1; [L522] SORT_1 next_196_arg_1 = var_195; [L523] SORT_1 var_197_arg_0 = ~state_51; [L524] var_197_arg_0 = var_197_arg_0 & mask_SORT_1 [L525] SORT_1 var_197_arg_1 = ~input_175; [L526] var_197_arg_1 = var_197_arg_1 & mask_SORT_1 [L527] SORT_1 var_197 = var_197_arg_0 & var_197_arg_1; [L528] SORT_1 var_198_arg_0 = var_197; [L529] SORT_1 var_198_arg_1 = input_133; [L530] SORT_1 var_198 = var_198_arg_0 | var_198_arg_1; [L531] SORT_1 var_199_arg_0 = var_198; [L532] SORT_1 var_199_arg_1 = input_154; [L533] SORT_1 var_199 = var_199_arg_0 | var_199_arg_1; [L534] SORT_1 next_200_arg_1 = ~var_199; [L535] next_200_arg_1 = next_200_arg_1 & mask_SORT_1 [L536] SORT_1 var_201_arg_0 = state_53; [L537] SORT_1 var_201_arg_1 = input_70; [L538] SORT_1 var_201 = var_201_arg_0 | var_201_arg_1; [L539] SORT_1 var_202_arg_0 = var_201; [L540] SORT_1 var_202_arg_1 = ~input_133; [L541] var_202_arg_1 = var_202_arg_1 & mask_SORT_1 [L542] SORT_1 var_202 = var_202_arg_0 & var_202_arg_1; [L543] SORT_1 next_203_arg_1 = var_202; [L544] SORT_3 var_204_arg_0 = state_6; [L545] SORT_3 var_204_arg_1 = var_58; [L546] SORT_4 var_204 = ((SORT_4)var_204_arg_0 << 16) | var_204_arg_1; [L547] SORT_4 var_205_arg_0 = var_204; [L548] EXPR (var_205_arg_0 & msb_SORT_4) ? (var_205_arg_0 | ~mask_SORT_4) : (var_205_arg_0 & mask_SORT_4) [L548] var_205_arg_0 = (var_205_arg_0 & msb_SORT_4) ? (var_205_arg_0 | ~mask_SORT_4) : (var_205_arg_0 & mask_SORT_4) [L549] SORT_4 var_205_arg_1 = var_60; [L550] SORT_4 var_205 = (int)var_205_arg_0 >> var_205_arg_1; [L551] EXPR (var_205_arg_0 & msb_SORT_4) ? (var_205 | ~(mask_SORT_4 >> var_205_arg_1)) : var_205 [L551] var_205 = (var_205_arg_0 & msb_SORT_4) ? (var_205 | ~(mask_SORT_4 >> var_205_arg_1)) : var_205 [L552] var_205 = var_205 & mask_SORT_4 [L553] SORT_4 var_206_arg_0 = var_63; [L554] SORT_4 var_206_arg_1 = var_205; [L555] SORT_1 var_206 = var_206_arg_0 == var_206_arg_1; [L556] SORT_1 var_207_arg_0 = state_17; [L557] SORT_1 var_207_arg_1 = var_206; [L558] SORT_1 var_207 = var_207_arg_0 & var_207_arg_1; [L559] SORT_1 var_208_arg_0 = ~input_111; [L560] var_208_arg_0 = var_208_arg_0 & mask_SORT_1 [L561] SORT_1 var_208_arg_1 = var_207; [L562] SORT_1 var_208 = var_208_arg_0 | var_208_arg_1; [L563] SORT_4 var_210_arg_0 = var_209; [L564] SORT_4 var_210_arg_1 = var_85; [L565] SORT_1 var_210 = var_210_arg_0 <= var_210_arg_1; [L566] SORT_1 var_211_arg_0 = var_206; [L567] SORT_1 var_211_arg_1 = ~var_210; [L568] var_211_arg_1 = var_211_arg_1 & mask_SORT_1 [L569] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L570] SORT_1 var_212_arg_0 = state_15; [L571] SORT_1 var_212_arg_1 = var_211; [L572] SORT_1 var_212 = var_212_arg_0 & var_212_arg_1; [L573] SORT_1 var_213_arg_0 = ~input_88; [L574] var_213_arg_0 = var_213_arg_0 & mask_SORT_1 [L575] SORT_1 var_213_arg_1 = var_212; [L576] SORT_1 var_213 = var_213_arg_0 | var_213_arg_1; [L577] SORT_1 var_214_arg_0 = var_208; [L578] SORT_1 var_214_arg_1 = var_213; [L579] SORT_1 var_214 = var_214_arg_0 & var_214_arg_1; [L580] SORT_1 var_215_arg_0 = state_19; [L581] SORT_1 var_215_arg_1 = ~input_75; [L582] var_215_arg_1 = var_215_arg_1 & mask_SORT_1 [L583] SORT_1 var_215 = var_215_arg_0 | var_215_arg_1; [L584] SORT_1 var_216_arg_0 = var_214; [L585] SORT_1 var_216_arg_1 = var_215; [L586] SORT_1 var_216 = var_216_arg_0 & var_216_arg_1; [L587] SORT_1 var_217_arg_0 = state_15; [L588] SORT_1 var_217_arg_1 = ~input_73; [L589] var_217_arg_1 = var_217_arg_1 & mask_SORT_1 [L590] SORT_1 var_217 = var_217_arg_0 | var_217_arg_1; [L591] SORT_1 var_218_arg_0 = var_216; [L592] SORT_1 var_218_arg_1 = var_217; [L593] SORT_1 var_218 = var_218_arg_0 & var_218_arg_1; [L594] SORT_4 var_219_arg_0 = var_64; [L595] SORT_4 var_219_arg_1 = var_205; [L596] SORT_1 var_219 = var_219_arg_0 == var_219_arg_1; [L597] SORT_1 var_220_arg_0 = state_17; [L598] SORT_1 var_220_arg_1 = var_219; [L599] SORT_1 var_220 = var_220_arg_0 & var_220_arg_1; [L600] SORT_1 var_221_arg_0 = ~input_120; [L601] var_221_arg_0 = var_221_arg_0 & mask_SORT_1 [L602] SORT_1 var_221_arg_1 = var_220; [L603] SORT_1 var_221 = var_221_arg_0 | var_221_arg_1; [L604] SORT_1 var_222_arg_0 = var_218; [L605] SORT_1 var_222_arg_1 = var_221; [L606] SORT_1 var_222 = var_222_arg_0 & var_222_arg_1; [L607] SORT_1 var_223_arg_0 = ~state_21; [L608] var_223_arg_0 = var_223_arg_0 & mask_SORT_1 [L609] SORT_1 var_223_arg_1 = ~input_72; [L610] var_223_arg_1 = var_223_arg_1 & mask_SORT_1 [L611] SORT_1 var_223 = var_223_arg_0 | var_223_arg_1; [L612] SORT_1 var_224_arg_0 = var_222; [L613] SORT_1 var_224_arg_1 = var_223; [L614] SORT_1 var_224 = var_224_arg_0 & var_224_arg_1; [L615] SORT_4 var_226_arg_0 = var_85; [L616] SORT_4 var_226_arg_1 = var_225; [L617] SORT_1 var_226 = var_226_arg_0 <= var_226_arg_1; [L618] SORT_4 var_228_arg_0 = var_227; [L619] SORT_4 var_228_arg_1 = var_85; [L620] SORT_1 var_228 = var_228_arg_0 <= var_228_arg_1; [L621] SORT_1 var_229_arg_0 = ~var_226; [L622] var_229_arg_0 = var_229_arg_0 & mask_SORT_1 [L623] SORT_1 var_229_arg_1 = ~var_228; [L624] var_229_arg_1 = var_229_arg_1 & mask_SORT_1 [L625] SORT_1 var_229 = var_229_arg_0 & var_229_arg_1; [L626] SORT_1 var_230_arg_0 = state_23; [L627] SORT_1 var_230_arg_1 = var_229; [L628] SORT_1 var_230 = var_230_arg_0 & var_230_arg_1; [L629] SORT_1 var_231_arg_0 = ~input_83; [L630] var_231_arg_0 = var_231_arg_0 & mask_SORT_1 [L631] SORT_1 var_231_arg_1 = var_230; [L632] SORT_1 var_231 = var_231_arg_0 | var_231_arg_1; [L633] SORT_1 var_232_arg_0 = var_224; [L634] SORT_1 var_232_arg_1 = var_231; [L635] SORT_1 var_232 = var_232_arg_0 & var_232_arg_1; [L636] SORT_4 var_234_arg_0 = var_233; [L637] SORT_4 var_234_arg_1 = var_85; [L638] SORT_1 var_234 = var_234_arg_0 <= var_234_arg_1; [L639] SORT_1 var_235_arg_0 = state_23; [L640] SORT_1 var_235_arg_1 = ~var_234; [L641] var_235_arg_1 = var_235_arg_1 & mask_SORT_1 [L642] SORT_1 var_235 = var_235_arg_0 & var_235_arg_1; [L643] SORT_1 var_236_arg_0 = ~input_82; [L644] var_236_arg_0 = var_236_arg_0 & mask_SORT_1 [L645] SORT_1 var_236_arg_1 = var_235; [L646] SORT_1 var_236 = var_236_arg_0 | var_236_arg_1; [L647] SORT_1 var_237_arg_0 = var_232; [L648] SORT_1 var_237_arg_1 = var_236; [L649] SORT_1 var_237 = var_237_arg_0 & var_237_arg_1; [L650] SORT_4 var_239_arg_0 = var_85; [L651] SORT_4 var_239_arg_1 = var_238; [L652] SORT_1 var_239 = var_239_arg_0 <= var_239_arg_1; [L653] SORT_1 var_240_arg_0 = state_23; [L654] SORT_1 var_240_arg_1 = ~var_239; [L655] var_240_arg_1 = var_240_arg_1 & mask_SORT_1 [L656] SORT_1 var_240 = var_240_arg_0 & var_240_arg_1; [L657] SORT_1 var_241_arg_0 = ~input_81; [L658] var_241_arg_0 = var_241_arg_0 & mask_SORT_1 [L659] SORT_1 var_241_arg_1 = var_240; [L660] SORT_1 var_241 = var_241_arg_0 | var_241_arg_1; [L661] SORT_1 var_242_arg_0 = var_237; [L662] SORT_1 var_242_arg_1 = var_241; [L663] SORT_1 var_242 = var_242_arg_0 & var_242_arg_1; [L664] SORT_4 var_243_arg_0 = var_61; [L665] SORT_4 var_243_arg_1 = var_64; [L666] SORT_1 var_243 = var_243_arg_0 <= var_243_arg_1; [L667] SORT_1 var_244_arg_0 = state_27; [L668] SORT_1 var_244_arg_1 = ~var_243; [L669] var_244_arg_1 = var_244_arg_1 & mask_SORT_1 [L670] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L671] SORT_1 var_245_arg_0 = ~input_104; [L672] var_245_arg_0 = var_245_arg_0 & mask_SORT_1 [L673] SORT_1 var_245_arg_1 = var_244; [L674] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L675] SORT_1 var_246_arg_0 = var_242; [L676] SORT_1 var_246_arg_1 = var_245; [L677] SORT_1 var_246 = var_246_arg_0 & var_246_arg_1; [L678] SORT_4 var_247_arg_0 = var_57; [L679] SORT_4 var_247_arg_1 = var_61; [L680] SORT_1 var_247 = var_247_arg_0 <= var_247_arg_1; [L681] SORT_1 var_248_arg_0 = state_31; [L682] SORT_1 var_248_arg_1 = ~var_247; [L683] var_248_arg_1 = var_248_arg_1 & mask_SORT_1 [L684] SORT_1 var_248 = var_248_arg_0 & var_248_arg_1; [L685] SORT_1 var_249_arg_0 = ~input_101; [L686] var_249_arg_0 = var_249_arg_0 & mask_SORT_1 [L687] SORT_1 var_249_arg_1 = var_248; [L688] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L689] SORT_1 var_250_arg_0 = var_246; [L690] SORT_1 var_250_arg_1 = var_249; [L691] SORT_1 var_250 = var_250_arg_0 & var_250_arg_1; [L692] SORT_1 var_251_arg_0 = ~state_37; [L693] var_251_arg_0 = var_251_arg_0 & mask_SORT_1 [L694] SORT_1 var_251_arg_1 = ~input_99; [L695] var_251_arg_1 = var_251_arg_1 & mask_SORT_1 [L696] SORT_1 var_251 = var_251_arg_0 | var_251_arg_1; [L697] SORT_1 var_252_arg_0 = var_250; [L698] SORT_1 var_252_arg_1 = var_251; [L699] SORT_1 var_252 = var_252_arg_0 & var_252_arg_1; [L700] SORT_4 var_253_arg_0 = var_64; [L701] SORT_4 var_253_arg_1 = var_61; [L702] SORT_1 var_253 = var_253_arg_0 == var_253_arg_1; [L703] SORT_1 var_254_arg_0 = state_27; [L704] SORT_1 var_254_arg_1 = var_253; [L705] SORT_1 var_254 = var_254_arg_0 & var_254_arg_1; [L706] SORT_1 var_255_arg_0 = ~input_143; [L707] var_255_arg_0 = var_255_arg_0 & mask_SORT_1 [L708] SORT_1 var_255_arg_1 = var_254; [L709] SORT_1 var_255 = var_255_arg_0 | var_255_arg_1; [L710] SORT_1 var_256_arg_0 = var_252; [L711] SORT_1 var_256_arg_1 = var_255; [L712] SORT_1 var_256 = var_256_arg_0 & var_256_arg_1; [L713] SORT_1 var_257_arg_0 = state_31; [L714] SORT_1 var_257_arg_1 = var_62; [L715] SORT_1 var_257 = var_257_arg_0 & var_257_arg_1; [L716] SORT_1 var_258_arg_0 = ~input_152; [L717] var_258_arg_0 = var_258_arg_0 & mask_SORT_1 [L718] SORT_1 var_258_arg_1 = var_257; [L719] SORT_1 var_258 = var_258_arg_0 | var_258_arg_1; [L720] SORT_1 var_259_arg_0 = var_256; [L721] SORT_1 var_259_arg_1 = var_258; [L722] SORT_1 var_259 = var_259_arg_0 & var_259_arg_1; [L723] SORT_1 var_260_arg_0 = state_33; [L724] SORT_1 var_260_arg_1 = ~input_158; [L725] var_260_arg_1 = var_260_arg_1 & mask_SORT_1 [L726] SORT_1 var_260 = var_260_arg_0 | var_260_arg_1; [L727] SORT_1 var_261_arg_0 = var_259; [L728] SORT_1 var_261_arg_1 = var_260; [L729] SORT_1 var_261 = var_261_arg_0 & var_261_arg_1; [L730] SORT_1 var_262_arg_0 = state_35; [L731] SORT_1 var_262_arg_1 = ~input_162; [L732] var_262_arg_1 = var_262_arg_1 & mask_SORT_1 [L733] SORT_1 var_262 = var_262_arg_0 | var_262_arg_1; [L734] SORT_1 var_263_arg_0 = var_261; [L735] SORT_1 var_263_arg_1 = var_262; [L736] SORT_1 var_263 = var_263_arg_0 & var_263_arg_1; [L737] SORT_1 var_264_arg_0 = state_29; [L738] SORT_1 var_264_arg_1 = ~input_147; [L739] var_264_arg_1 = var_264_arg_1 & mask_SORT_1 [L740] SORT_1 var_264 = var_264_arg_0 | var_264_arg_1; [L741] SORT_1 var_265_arg_0 = var_263; [L742] SORT_1 var_265_arg_1 = var_264; [L743] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L744] SORT_1 var_266_arg_0 = state_39; [L745] SORT_1 var_266_arg_1 = ~input_166; [L746] var_266_arg_1 = var_266_arg_1 & mask_SORT_1 [L747] SORT_1 var_266 = var_266_arg_0 | var_266_arg_1; [L748] SORT_1 var_267_arg_0 = var_265; [L749] SORT_1 var_267_arg_1 = var_266; [L750] SORT_1 var_267 = var_267_arg_0 & var_267_arg_1; [L751] SORT_1 var_268_arg_0 = state_45; [L752] SORT_1 var_268_arg_1 = ~input_182; [L753] var_268_arg_1 = var_268_arg_1 & mask_SORT_1 [L754] SORT_1 var_268 = var_268_arg_0 | var_268_arg_1; [L755] SORT_1 var_269_arg_0 = var_267; [L756] SORT_1 var_269_arg_1 = var_268; [L757] SORT_1 var_269 = var_269_arg_0 & var_269_arg_1; [L758] SORT_1 var_270_arg_0 = state_45; [L759] SORT_1 var_270_arg_1 = ~input_184; [L760] var_270_arg_1 = var_270_arg_1 & mask_SORT_1 [L761] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L762] SORT_1 var_271_arg_0 = var_269; [L763] SORT_1 var_271_arg_1 = var_270; [L764] SORT_1 var_271 = var_271_arg_0 & var_271_arg_1; [L765] SORT_1 var_272_arg_0 = state_47; [L766] SORT_1 var_272_arg_1 = ~input_70; [L767] var_272_arg_1 = var_272_arg_1 & mask_SORT_1 [L768] SORT_1 var_272 = var_272_arg_0 | var_272_arg_1; [L769] SORT_1 var_273_arg_0 = var_271; [L770] SORT_1 var_273_arg_1 = var_272; [L771] SORT_1 var_273 = var_273_arg_0 & var_273_arg_1; [L772] SORT_1 var_274_arg_0 = state_47; [L773] SORT_1 var_274_arg_1 = ~input_190; [L774] var_274_arg_1 = var_274_arg_1 & mask_SORT_1 [L775] SORT_1 var_274 = var_274_arg_0 | var_274_arg_1; [L776] SORT_1 var_275_arg_0 = var_273; [L777] SORT_1 var_275_arg_1 = var_274; [L778] SORT_1 var_275 = var_275_arg_0 & var_275_arg_1; [L779] SORT_1 var_276_arg_0 = state_15; [L780] SORT_1 var_276_arg_1 = state_25; [L781] SORT_1 var_276 = var_276_arg_0 & var_276_arg_1; [L782] SORT_1 var_277_arg_0 = var_276; [L783] SORT_1 var_277_arg_1 = var_206; [L784] SORT_1 var_277 = var_277_arg_0 & var_277_arg_1; [L785] SORT_1 var_278_arg_0 = ~input_116; [L786] var_278_arg_0 = var_278_arg_0 & mask_SORT_1 [L787] SORT_1 var_278_arg_1 = var_277; [L788] SORT_1 var_278 = var_278_arg_0 | var_278_arg_1; [L789] SORT_1 var_279_arg_0 = var_275; [L790] SORT_1 var_279_arg_1 = var_278; [L791] SORT_1 var_279 = var_279_arg_0 & var_279_arg_1; [L792] SORT_1 var_280_arg_0 = state_41; [L793] SORT_1 var_280_arg_1 = ~state_51; [L794] var_280_arg_1 = var_280_arg_1 & mask_SORT_1 [L795] SORT_1 var_280 = var_280_arg_0 & var_280_arg_1; [L796] SORT_1 var_281_arg_0 = ~input_175; [L797] var_281_arg_0 = var_281_arg_0 & mask_SORT_1 [L798] SORT_1 var_281_arg_1 = var_280; [L799] SORT_1 var_281 = var_281_arg_0 | var_281_arg_1; [L800] SORT_1 var_282_arg_0 = var_279; [L801] SORT_1 var_282_arg_1 = var_281; [L802] SORT_1 var_282 = var_282_arg_0 & var_282_arg_1; [L803] SORT_1 var_283_arg_0 = state_43; [L804] SORT_1 var_283_arg_1 = state_53; [L805] SORT_1 var_283 = var_283_arg_0 & var_283_arg_1; [L806] SORT_1 var_284_arg_0 = ~input_133; [L807] var_284_arg_0 = var_284_arg_0 & mask_SORT_1 [L808] SORT_1 var_284_arg_1 = var_283; [L809] SORT_1 var_284 = var_284_arg_0 | var_284_arg_1; [L810] SORT_1 var_285_arg_0 = var_282; [L811] SORT_1 var_285_arg_1 = var_284; [L812] SORT_1 var_285 = var_285_arg_0 & var_285_arg_1; [L813] SORT_1 var_286_arg_0 = state_43; [L814] SORT_1 var_286_arg_1 = state_49; [L815] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L816] SORT_1 var_287_arg_0 = ~input_154; [L817] var_287_arg_0 = var_287_arg_0 & mask_SORT_1 [L818] SORT_1 var_287_arg_1 = var_286; [L819] SORT_1 var_287 = var_287_arg_0 | var_287_arg_1; [L820] SORT_1 var_288_arg_0 = var_285; [L821] SORT_1 var_288_arg_1 = var_287; [L822] SORT_1 var_288 = var_288_arg_0 & var_288_arg_1; [L823] SORT_1 var_289_arg_0 = input_111; [L824] SORT_1 var_289_arg_1 = input_88; [L825] SORT_1 var_289 = var_289_arg_0 | var_289_arg_1; [L826] SORT_1 var_290_arg_0 = input_75; [L827] SORT_1 var_290_arg_1 = var_289; [L828] SORT_1 var_290 = var_290_arg_0 | var_290_arg_1; [L829] SORT_1 var_291_arg_0 = input_73; [L830] SORT_1 var_291_arg_1 = var_290; [L831] SORT_1 var_291 = var_291_arg_0 | var_291_arg_1; [L832] SORT_1 var_292_arg_0 = input_120; [L833] SORT_1 var_292_arg_1 = var_291; [L834] SORT_1 var_292 = var_292_arg_0 | var_292_arg_1; [L835] SORT_1 var_293_arg_0 = input_72; [L836] SORT_1 var_293_arg_1 = var_292; [L837] SORT_1 var_293 = var_293_arg_0 | var_293_arg_1; [L838] SORT_1 var_294_arg_0 = input_83; [L839] SORT_1 var_294_arg_1 = var_293; [L840] SORT_1 var_294 = var_294_arg_0 | var_294_arg_1; [L841] SORT_1 var_295_arg_0 = input_82; [L842] SORT_1 var_295_arg_1 = var_294; [L843] SORT_1 var_295 = var_295_arg_0 | var_295_arg_1; [L844] SORT_1 var_296_arg_0 = input_81; [L845] SORT_1 var_296_arg_1 = var_295; [L846] SORT_1 var_296 = var_296_arg_0 | var_296_arg_1; [L847] SORT_1 var_297_arg_0 = input_104; [L848] SORT_1 var_297_arg_1 = var_296; [L849] SORT_1 var_297 = var_297_arg_0 | var_297_arg_1; [L850] SORT_1 var_298_arg_0 = input_101; [L851] SORT_1 var_298_arg_1 = var_297; [L852] SORT_1 var_298 = var_298_arg_0 | var_298_arg_1; [L853] SORT_1 var_299_arg_0 = input_99; [L854] SORT_1 var_299_arg_1 = var_298; [L855] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L856] SORT_1 var_300_arg_0 = input_143; [L857] SORT_1 var_300_arg_1 = var_299; [L858] SORT_1 var_300 = var_300_arg_0 | var_300_arg_1; [L859] SORT_1 var_301_arg_0 = input_152; [L860] SORT_1 var_301_arg_1 = var_300; [L861] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L862] SORT_1 var_302_arg_0 = input_158; [L863] SORT_1 var_302_arg_1 = var_301; [L864] SORT_1 var_302 = var_302_arg_0 | var_302_arg_1; [L865] SORT_1 var_303_arg_0 = input_162; [L866] SORT_1 var_303_arg_1 = var_302; [L867] SORT_1 var_303 = var_303_arg_0 | var_303_arg_1; [L868] SORT_1 var_304_arg_0 = input_147; [L869] SORT_1 var_304_arg_1 = var_303; [L870] SORT_1 var_304 = var_304_arg_0 | var_304_arg_1; [L871] SORT_1 var_305_arg_0 = input_166; [L872] SORT_1 var_305_arg_1 = var_304; [L873] SORT_1 var_305 = var_305_arg_0 | var_305_arg_1; [L874] SORT_1 var_306_arg_0 = input_182; [L875] SORT_1 var_306_arg_1 = var_305; [L876] SORT_1 var_306 = var_306_arg_0 | var_306_arg_1; [L877] SORT_1 var_307_arg_0 = input_184; [L878] SORT_1 var_307_arg_1 = var_306; [L879] SORT_1 var_307 = var_307_arg_0 | var_307_arg_1; [L880] SORT_1 var_308_arg_0 = input_70; [L881] SORT_1 var_308_arg_1 = var_307; [L882] SORT_1 var_308 = var_308_arg_0 | var_308_arg_1; [L883] SORT_1 var_309_arg_0 = input_190; [L884] SORT_1 var_309_arg_1 = var_308; [L885] SORT_1 var_309 = var_309_arg_0 | var_309_arg_1; [L886] SORT_1 var_310_arg_0 = input_116; [L887] SORT_1 var_310_arg_1 = var_309; [L888] SORT_1 var_310 = var_310_arg_0 | var_310_arg_1; [L889] SORT_1 var_311_arg_0 = input_175; [L890] SORT_1 var_311_arg_1 = var_310; [L891] SORT_1 var_311 = var_311_arg_0 | var_311_arg_1; [L892] SORT_1 var_312_arg_0 = input_133; [L893] SORT_1 var_312_arg_1 = var_311; [L894] SORT_1 var_312 = var_312_arg_0 | var_312_arg_1; [L895] SORT_1 var_313_arg_0 = input_154; [L896] SORT_1 var_313_arg_1 = var_312; [L897] SORT_1 var_313 = var_313_arg_0 | var_313_arg_1; [L898] SORT_1 var_314_arg_0 = var_288; [L899] SORT_1 var_314_arg_1 = var_313; [L900] SORT_1 var_314 = var_314_arg_0 & var_314_arg_1; [L901] SORT_1 var_315_arg_0 = input_111; [L902] SORT_1 var_315_arg_1 = input_88; [L903] SORT_1 var_315 = var_315_arg_0 & var_315_arg_1; [L904] SORT_1 var_316_arg_0 = input_75; [L905] SORT_1 var_316_arg_1 = var_289; [L906] SORT_1 var_316 = var_316_arg_0 & var_316_arg_1; [L907] SORT_1 var_317_arg_0 = var_315; [L908] SORT_1 var_317_arg_1 = var_316; [L909] SORT_1 var_317 = var_317_arg_0 | var_317_arg_1; [L910] SORT_1 var_318_arg_0 = input_73; [L911] SORT_1 var_318_arg_1 = var_290; [L912] SORT_1 var_318 = var_318_arg_0 & var_318_arg_1; [L913] SORT_1 var_319_arg_0 = var_317; [L914] SORT_1 var_319_arg_1 = var_318; [L915] SORT_1 var_319 = var_319_arg_0 | var_319_arg_1; [L916] SORT_1 var_320_arg_0 = input_120; [L917] SORT_1 var_320_arg_1 = var_291; [L918] SORT_1 var_320 = var_320_arg_0 & var_320_arg_1; [L919] SORT_1 var_321_arg_0 = var_319; [L920] SORT_1 var_321_arg_1 = var_320; [L921] SORT_1 var_321 = var_321_arg_0 | var_321_arg_1; [L922] SORT_1 var_322_arg_0 = input_72; [L923] SORT_1 var_322_arg_1 = var_292; [L924] SORT_1 var_322 = var_322_arg_0 & var_322_arg_1; [L925] SORT_1 var_323_arg_0 = var_321; [L926] SORT_1 var_323_arg_1 = var_322; [L927] SORT_1 var_323 = var_323_arg_0 | var_323_arg_1; [L928] SORT_1 var_324_arg_0 = input_83; [L929] SORT_1 var_324_arg_1 = var_293; [L930] SORT_1 var_324 = var_324_arg_0 & var_324_arg_1; [L931] SORT_1 var_325_arg_0 = var_323; [L932] SORT_1 var_325_arg_1 = var_324; [L933] SORT_1 var_325 = var_325_arg_0 | var_325_arg_1; [L934] SORT_1 var_326_arg_0 = input_82; [L935] SORT_1 var_326_arg_1 = var_294; [L936] SORT_1 var_326 = var_326_arg_0 & var_326_arg_1; [L937] SORT_1 var_327_arg_0 = var_325; [L938] SORT_1 var_327_arg_1 = var_326; [L939] SORT_1 var_327 = var_327_arg_0 | var_327_arg_1; [L940] SORT_1 var_328_arg_0 = input_81; [L941] SORT_1 var_328_arg_1 = var_295; [L942] SORT_1 var_328 = var_328_arg_0 & var_328_arg_1; [L943] SORT_1 var_329_arg_0 = var_327; [L944] SORT_1 var_329_arg_1 = var_328; [L945] SORT_1 var_329 = var_329_arg_0 | var_329_arg_1; [L946] SORT_1 var_330_arg_0 = input_104; [L947] SORT_1 var_330_arg_1 = var_296; [L948] SORT_1 var_330 = var_330_arg_0 & var_330_arg_1; [L949] SORT_1 var_331_arg_0 = var_329; [L950] SORT_1 var_331_arg_1 = var_330; [L951] SORT_1 var_331 = var_331_arg_0 | var_331_arg_1; [L952] SORT_1 var_332_arg_0 = input_101; [L953] SORT_1 var_332_arg_1 = var_297; [L954] SORT_1 var_332 = var_332_arg_0 & var_332_arg_1; [L955] SORT_1 var_333_arg_0 = var_331; [L956] SORT_1 var_333_arg_1 = var_332; [L957] SORT_1 var_333 = var_333_arg_0 | var_333_arg_1; [L958] SORT_1 var_334_arg_0 = input_99; [L959] SORT_1 var_334_arg_1 = var_298; [L960] SORT_1 var_334 = var_334_arg_0 & var_334_arg_1; [L961] SORT_1 var_335_arg_0 = var_333; [L962] SORT_1 var_335_arg_1 = var_334; [L963] SORT_1 var_335 = var_335_arg_0 | var_335_arg_1; [L964] SORT_1 var_336_arg_0 = input_143; [L965] SORT_1 var_336_arg_1 = var_299; [L966] SORT_1 var_336 = var_336_arg_0 & var_336_arg_1; [L967] SORT_1 var_337_arg_0 = var_335; [L968] SORT_1 var_337_arg_1 = var_336; [L969] SORT_1 var_337 = var_337_arg_0 | var_337_arg_1; [L970] SORT_1 var_338_arg_0 = input_152; [L971] SORT_1 var_338_arg_1 = var_300; [L972] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L973] SORT_1 var_339_arg_0 = var_337; [L974] SORT_1 var_339_arg_1 = var_338; [L975] SORT_1 var_339 = var_339_arg_0 | var_339_arg_1; [L976] SORT_1 var_340_arg_0 = input_158; [L977] SORT_1 var_340_arg_1 = var_301; [L978] SORT_1 var_340 = var_340_arg_0 & var_340_arg_1; [L979] SORT_1 var_341_arg_0 = var_339; [L980] SORT_1 var_341_arg_1 = var_340; [L981] SORT_1 var_341 = var_341_arg_0 | var_341_arg_1; [L982] SORT_1 var_342_arg_0 = input_162; [L983] SORT_1 var_342_arg_1 = var_302; [L984] SORT_1 var_342 = var_342_arg_0 & var_342_arg_1; [L985] SORT_1 var_343_arg_0 = var_341; [L986] SORT_1 var_343_arg_1 = var_342; [L987] SORT_1 var_343 = var_343_arg_0 | var_343_arg_1; [L988] SORT_1 var_344_arg_0 = input_147; [L989] SORT_1 var_344_arg_1 = var_303; [L990] SORT_1 var_344 = var_344_arg_0 & var_344_arg_1; [L991] SORT_1 var_345_arg_0 = var_343; [L992] SORT_1 var_345_arg_1 = var_344; [L993] SORT_1 var_345 = var_345_arg_0 | var_345_arg_1; [L994] SORT_1 var_346_arg_0 = input_166; [L995] SORT_1 var_346_arg_1 = var_304; [L996] SORT_1 var_346 = var_346_arg_0 & var_346_arg_1; [L997] SORT_1 var_347_arg_0 = var_345; [L998] SORT_1 var_347_arg_1 = var_346; [L999] SORT_1 var_347 = var_347_arg_0 | var_347_arg_1; [L1000] SORT_1 var_348_arg_0 = input_182; [L1001] SORT_1 var_348_arg_1 = var_305; [L1002] SORT_1 var_348 = var_348_arg_0 & var_348_arg_1; [L1003] SORT_1 var_349_arg_0 = var_347; [L1004] SORT_1 var_349_arg_1 = var_348; [L1005] SORT_1 var_349 = var_349_arg_0 | var_349_arg_1; [L1006] SORT_1 var_350_arg_0 = input_184; [L1007] SORT_1 var_350_arg_1 = var_306; [L1008] SORT_1 var_350 = var_350_arg_0 & var_350_arg_1; [L1009] SORT_1 var_351_arg_0 = var_349; [L1010] SORT_1 var_351_arg_1 = var_350; [L1011] SORT_1 var_351 = var_351_arg_0 | var_351_arg_1; [L1012] SORT_1 var_352_arg_0 = input_70; [L1013] SORT_1 var_352_arg_1 = var_307; [L1014] SORT_1 var_352 = var_352_arg_0 & var_352_arg_1; [L1015] SORT_1 var_353_arg_0 = var_351; [L1016] SORT_1 var_353_arg_1 = var_352; [L1017] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L1018] SORT_1 var_354_arg_0 = input_190; [L1019] SORT_1 var_354_arg_1 = var_308; [L1020] SORT_1 var_354 = var_354_arg_0 & var_354_arg_1; [L1021] SORT_1 var_355_arg_0 = var_353; [L1022] SORT_1 var_355_arg_1 = var_354; [L1023] SORT_1 var_355 = var_355_arg_0 | var_355_arg_1; [L1024] SORT_1 var_356_arg_0 = input_116; [L1025] SORT_1 var_356_arg_1 = var_309; [L1026] SORT_1 var_356 = var_356_arg_0 & var_356_arg_1; [L1027] SORT_1 var_357_arg_0 = var_355; [L1028] SORT_1 var_357_arg_1 = var_356; [L1029] SORT_1 var_357 = var_357_arg_0 | var_357_arg_1; [L1030] SORT_1 var_358_arg_0 = input_175; [L1031] SORT_1 var_358_arg_1 = var_310; [L1032] SORT_1 var_358 = var_358_arg_0 & var_358_arg_1; [L1033] SORT_1 var_359_arg_0 = var_357; [L1034] SORT_1 var_359_arg_1 = var_358; [L1035] SORT_1 var_359 = var_359_arg_0 | var_359_arg_1; [L1036] SORT_1 var_360_arg_0 = input_133; [L1037] SORT_1 var_360_arg_1 = var_311; [L1038] SORT_1 var_360 = var_360_arg_0 & var_360_arg_1; [L1039] SORT_1 var_361_arg_0 = var_359; [L1040] SORT_1 var_361_arg_1 = var_360; [L1041] SORT_1 var_361 = var_361_arg_0 | var_361_arg_1; [L1042] SORT_1 var_362_arg_0 = input_154; [L1043] SORT_1 var_362_arg_1 = var_312; [L1044] SORT_1 var_362 = var_362_arg_0 & var_362_arg_1; [L1045] SORT_1 var_363_arg_0 = var_361; [L1046] SORT_1 var_363_arg_1 = var_362; [L1047] SORT_1 var_363 = var_363_arg_0 | var_363_arg_1; [L1048] SORT_1 var_364_arg_0 = var_314; [L1049] SORT_1 var_364_arg_1 = ~var_363; [L1050] var_364_arg_1 = var_364_arg_1 & mask_SORT_1 [L1051] SORT_1 var_364 = var_364_arg_0 & var_364_arg_1; [L1052] SORT_1 var_365_arg_0 = state_15; [L1053] SORT_1 var_365_arg_1 = state_17; [L1054] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L1055] SORT_1 var_366_arg_0 = state_15; [L1056] SORT_1 var_366_arg_1 = state_17; [L1057] SORT_1 var_366 = var_366_arg_0 | var_366_arg_1; [L1058] SORT_1 var_367_arg_0 = state_19; [L1059] SORT_1 var_367_arg_1 = var_366; [L1060] SORT_1 var_367 = var_367_arg_0 & var_367_arg_1; [L1061] SORT_1 var_368_arg_0 = var_365; [L1062] SORT_1 var_368_arg_1 = var_367; [L1063] SORT_1 var_368 = var_368_arg_0 | var_368_arg_1; [L1064] SORT_1 var_369_arg_0 = state_19; [L1065] SORT_1 var_369_arg_1 = var_366; [L1066] SORT_1 var_369 = var_369_arg_0 | var_369_arg_1; [L1067] SORT_1 var_370_arg_0 = ~state_21; [L1068] var_370_arg_0 = var_370_arg_0 & mask_SORT_1 [L1069] SORT_1 var_370_arg_1 = var_369; [L1070] SORT_1 var_370 = var_370_arg_0 & var_370_arg_1; [L1071] SORT_1 var_371_arg_0 = var_368; [L1072] SORT_1 var_371_arg_1 = var_370; [L1073] SORT_1 var_371 = var_371_arg_0 | var_371_arg_1; [L1074] SORT_1 var_372_arg_0 = ~state_21; [L1075] var_372_arg_0 = var_372_arg_0 & mask_SORT_1 [L1076] SORT_1 var_372_arg_1 = var_369; [L1077] SORT_1 var_372 = var_372_arg_0 | var_372_arg_1; [L1078] SORT_1 var_373_arg_0 = ~var_371; [L1079] var_373_arg_0 = var_373_arg_0 & mask_SORT_1 [L1080] SORT_1 var_373_arg_1 = var_372; [L1081] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L1082] SORT_1 var_374_arg_0 = state_23; [L1083] SORT_1 var_374_arg_1 = state_25; [L1084] SORT_1 var_374 = var_374_arg_0 & var_374_arg_1; [L1085] SORT_1 var_375_arg_0 = state_23; [L1086] SORT_1 var_375_arg_1 = state_25; [L1087] SORT_1 var_375 = var_375_arg_0 | var_375_arg_1; [L1088] SORT_1 var_376_arg_0 = state_27; [L1089] SORT_1 var_376_arg_1 = var_375; [L1090] SORT_1 var_376 = var_376_arg_0 & var_376_arg_1; [L1091] SORT_1 var_377_arg_0 = var_374; [L1092] SORT_1 var_377_arg_1 = var_376; [L1093] SORT_1 var_377 = var_377_arg_0 | var_377_arg_1; [L1094] SORT_1 var_378_arg_0 = state_27; [L1095] SORT_1 var_378_arg_1 = var_375; [L1096] SORT_1 var_378 = var_378_arg_0 | var_378_arg_1; [L1097] SORT_1 var_379_arg_0 = state_29; [L1098] SORT_1 var_379_arg_1 = var_378; [L1099] SORT_1 var_379 = var_379_arg_0 & var_379_arg_1; [L1100] SORT_1 var_380_arg_0 = var_377; [L1101] SORT_1 var_380_arg_1 = var_379; [L1102] SORT_1 var_380 = var_380_arg_0 | var_380_arg_1; [L1103] SORT_1 var_381_arg_0 = state_29; [L1104] SORT_1 var_381_arg_1 = var_378; [L1105] SORT_1 var_381 = var_381_arg_0 | var_381_arg_1; [L1106] SORT_1 var_382_arg_0 = state_31; [L1107] SORT_1 var_382_arg_1 = var_381; [L1108] SORT_1 var_382 = var_382_arg_0 & var_382_arg_1; [L1109] SORT_1 var_383_arg_0 = var_380; [L1110] SORT_1 var_383_arg_1 = var_382; [L1111] SORT_1 var_383 = var_383_arg_0 | var_383_arg_1; [L1112] SORT_1 var_384_arg_0 = state_31; [L1113] SORT_1 var_384_arg_1 = var_381; [L1114] SORT_1 var_384 = var_384_arg_0 | var_384_arg_1; [L1115] SORT_1 var_385_arg_0 = state_33; [L1116] SORT_1 var_385_arg_1 = var_384; [L1117] SORT_1 var_385 = var_385_arg_0 & var_385_arg_1; [L1118] SORT_1 var_386_arg_0 = var_383; [L1119] SORT_1 var_386_arg_1 = var_385; [L1120] SORT_1 var_386 = var_386_arg_0 | var_386_arg_1; [L1121] SORT_1 var_387_arg_0 = state_33; [L1122] SORT_1 var_387_arg_1 = var_384; [L1123] SORT_1 var_387 = var_387_arg_0 | var_387_arg_1; [L1124] SORT_1 var_388_arg_0 = state_35; [L1125] SORT_1 var_388_arg_1 = var_387; [L1126] SORT_1 var_388 = var_388_arg_0 & var_388_arg_1; [L1127] SORT_1 var_389_arg_0 = var_386; [L1128] SORT_1 var_389_arg_1 = var_388; [L1129] SORT_1 var_389 = var_389_arg_0 | var_389_arg_1; [L1130] SORT_1 var_390_arg_0 = state_35; [L1131] SORT_1 var_390_arg_1 = var_387; [L1132] SORT_1 var_390 = var_390_arg_0 | var_390_arg_1; [L1133] SORT_1 var_391_arg_0 = ~state_37; [L1134] var_391_arg_0 = var_391_arg_0 & mask_SORT_1 [L1135] SORT_1 var_391_arg_1 = var_390; [L1136] SORT_1 var_391 = var_391_arg_0 & var_391_arg_1; [L1137] SORT_1 var_392_arg_0 = var_389; [L1138] SORT_1 var_392_arg_1 = var_391; [L1139] SORT_1 var_392 = var_392_arg_0 | var_392_arg_1; [L1140] SORT_1 var_393_arg_0 = ~state_37; [L1141] var_393_arg_0 = var_393_arg_0 & mask_SORT_1 [L1142] SORT_1 var_393_arg_1 = var_390; [L1143] SORT_1 var_393 = var_393_arg_0 | var_393_arg_1; [L1144] SORT_1 var_394_arg_0 = state_39; [L1145] SORT_1 var_394_arg_1 = var_393; [L1146] SORT_1 var_394 = var_394_arg_0 & var_394_arg_1; [L1147] SORT_1 var_395_arg_0 = var_392; [L1148] SORT_1 var_395_arg_1 = var_394; [L1149] SORT_1 var_395 = var_395_arg_0 | var_395_arg_1; [L1150] SORT_1 var_396_arg_0 = state_39; [L1151] SORT_1 var_396_arg_1 = var_393; [L1152] SORT_1 var_396 = var_396_arg_0 | var_396_arg_1; [L1153] SORT_1 var_397_arg_0 = state_41; [L1154] SORT_1 var_397_arg_1 = var_396; [L1155] SORT_1 var_397 = var_397_arg_0 & var_397_arg_1; [L1156] SORT_1 var_398_arg_0 = var_395; [L1157] SORT_1 var_398_arg_1 = var_397; [L1158] SORT_1 var_398 = var_398_arg_0 | var_398_arg_1; [L1159] SORT_1 var_399_arg_0 = state_41; [L1160] SORT_1 var_399_arg_1 = var_396; [L1161] SORT_1 var_399 = var_399_arg_0 | var_399_arg_1; [L1162] SORT_1 var_400_arg_0 = state_43; [L1163] SORT_1 var_400_arg_1 = var_399; [L1164] SORT_1 var_400 = var_400_arg_0 & var_400_arg_1; [L1165] SORT_1 var_401_arg_0 = var_398; [L1166] SORT_1 var_401_arg_1 = var_400; [L1167] SORT_1 var_401 = var_401_arg_0 | var_401_arg_1; [L1168] SORT_1 var_402_arg_0 = var_373; [L1169] SORT_1 var_402_arg_1 = ~var_401; [L1170] var_402_arg_1 = var_402_arg_1 & mask_SORT_1 [L1171] SORT_1 var_402 = var_402_arg_0 & var_402_arg_1; [L1172] SORT_1 var_403_arg_0 = state_43; [L1173] SORT_1 var_403_arg_1 = var_399; [L1174] SORT_1 var_403 = var_403_arg_0 | var_403_arg_1; [L1175] SORT_1 var_404_arg_0 = var_402; [L1176] SORT_1 var_404_arg_1 = var_403; [L1177] SORT_1 var_404 = var_404_arg_0 & var_404_arg_1; [L1178] SORT_1 var_405_arg_0 = state_45; [L1179] SORT_1 var_405_arg_1 = state_47; [L1180] SORT_1 var_405 = var_405_arg_0 & var_405_arg_1; [L1181] SORT_1 var_406_arg_0 = state_45; [L1182] SORT_1 var_406_arg_1 = state_47; [L1183] SORT_1 var_406 = var_406_arg_0 | var_406_arg_1; [L1184] SORT_1 var_407_arg_0 = state_49; [L1185] SORT_1 var_407_arg_1 = var_406; [L1186] SORT_1 var_407 = var_407_arg_0 & var_407_arg_1; [L1187] SORT_1 var_408_arg_0 = var_405; [L1188] SORT_1 var_408_arg_1 = var_407; [L1189] SORT_1 var_408 = var_408_arg_0 | var_408_arg_1; [L1190] SORT_1 var_409_arg_0 = state_49; [L1191] SORT_1 var_409_arg_1 = var_406; [L1192] SORT_1 var_409 = var_409_arg_0 | var_409_arg_1; [L1193] SORT_1 var_410_arg_0 = ~state_51; [L1194] var_410_arg_0 = var_410_arg_0 & mask_SORT_1 [L1195] SORT_1 var_410_arg_1 = var_409; [L1196] SORT_1 var_410 = var_410_arg_0 & var_410_arg_1; [L1197] SORT_1 var_411_arg_0 = var_408; [L1198] SORT_1 var_411_arg_1 = var_410; [L1199] SORT_1 var_411 = var_411_arg_0 | var_411_arg_1; [L1200] SORT_1 var_412_arg_0 = ~state_51; [L1201] var_412_arg_0 = var_412_arg_0 & mask_SORT_1 [L1202] SORT_1 var_412_arg_1 = var_409; [L1203] SORT_1 var_412 = var_412_arg_0 | var_412_arg_1; [L1204] SORT_1 var_413_arg_0 = state_53; [L1205] SORT_1 var_413_arg_1 = var_412; [L1206] SORT_1 var_413 = var_413_arg_0 & var_413_arg_1; [L1207] SORT_1 var_414_arg_0 = var_411; [L1208] SORT_1 var_414_arg_1 = var_413; [L1209] SORT_1 var_414 = var_414_arg_0 | var_414_arg_1; [L1210] SORT_1 var_415_arg_0 = var_404; [L1211] SORT_1 var_415_arg_1 = ~var_414; [L1212] var_415_arg_1 = var_415_arg_1 & mask_SORT_1 [L1213] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1214] SORT_1 var_416_arg_0 = state_53; [L1215] SORT_1 var_416_arg_1 = var_412; [L1216] SORT_1 var_416 = var_416_arg_0 | var_416_arg_1; [L1217] SORT_1 var_417_arg_0 = var_415; [L1218] SORT_1 var_417_arg_1 = var_416; [L1219] SORT_1 var_417 = var_417_arg_0 & var_417_arg_1; [L1220] SORT_1 var_418_arg_0 = var_364; [L1221] SORT_1 var_418_arg_1 = var_417; [L1222] SORT_1 var_418 = var_418_arg_0 & var_418_arg_1; [L1223] SORT_1 var_419_arg_0 = var_117; [L1224] SORT_1 var_419_arg_1 = var_122; [L1225] SORT_1 var_419 = var_419_arg_0 & var_419_arg_1; [L1226] SORT_1 var_420_arg_0 = var_117; [L1227] SORT_1 var_420_arg_1 = var_122; [L1228] SORT_1 var_420 = var_420_arg_0 | var_420_arg_1; [L1229] SORT_1 var_421_arg_0 = var_126; [L1230] SORT_1 var_421_arg_1 = var_420; [L1231] SORT_1 var_421 = var_421_arg_0 & var_421_arg_1; [L1232] SORT_1 var_422_arg_0 = var_419; [L1233] SORT_1 var_422_arg_1 = var_421; [L1234] SORT_1 var_422 = var_422_arg_0 | var_422_arg_1; [L1235] SORT_1 var_423_arg_0 = var_126; [L1236] SORT_1 var_423_arg_1 = var_420; [L1237] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1238] SORT_1 var_424_arg_0 = var_128; [L1239] SORT_1 var_424_arg_1 = var_423; [L1240] SORT_1 var_424 = var_424_arg_0 & var_424_arg_1; [L1241] SORT_1 var_425_arg_0 = var_422; [L1242] SORT_1 var_425_arg_1 = var_424; [L1243] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1244] SORT_1 var_426_arg_0 = var_128; [L1245] SORT_1 var_426_arg_1 = var_423; [L1246] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1247] SORT_1 var_427_arg_0 = ~var_425; [L1248] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L1249] SORT_1 var_427_arg_1 = var_426; [L1250] SORT_1 var_427 = var_427_arg_0 & var_427_arg_1; [L1251] SORT_1 var_428_arg_0 = var_139; [L1252] SORT_1 var_428_arg_1 = var_134; [L1253] SORT_1 var_428 = var_428_arg_0 & var_428_arg_1; [L1254] SORT_1 var_429_arg_0 = var_139; [L1255] SORT_1 var_429_arg_1 = var_134; [L1256] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1257] SORT_1 var_430_arg_0 = var_144; [L1258] SORT_1 var_430_arg_1 = var_429; [L1259] SORT_1 var_430 = var_430_arg_0 & var_430_arg_1; [L1260] SORT_1 var_431_arg_0 = var_428; [L1261] SORT_1 var_431_arg_1 = var_430; [L1262] SORT_1 var_431 = var_431_arg_0 | var_431_arg_1; [L1263] SORT_1 var_432_arg_0 = var_144; [L1264] SORT_1 var_432_arg_1 = var_429; [L1265] SORT_1 var_432 = var_432_arg_0 | var_432_arg_1; [L1266] SORT_1 var_433_arg_0 = var_148; [L1267] SORT_1 var_433_arg_1 = var_432; [L1268] SORT_1 var_433 = var_433_arg_0 & var_433_arg_1; [L1269] SORT_1 var_434_arg_0 = var_431; [L1270] SORT_1 var_434_arg_1 = var_433; [L1271] SORT_1 var_434 = var_434_arg_0 | var_434_arg_1; [L1272] SORT_1 var_435_arg_0 = var_148; [L1273] SORT_1 var_435_arg_1 = var_432; [L1274] SORT_1 var_435 = var_435_arg_0 | var_435_arg_1; [L1275] SORT_1 var_436_arg_0 = var_155; [L1276] SORT_1 var_436_arg_1 = var_435; [L1277] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1278] SORT_1 var_437_arg_0 = var_434; [L1279] SORT_1 var_437_arg_1 = var_436; [L1280] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1281] SORT_1 var_438_arg_0 = var_155; [L1282] SORT_1 var_438_arg_1 = var_435; [L1283] SORT_1 var_438 = var_438_arg_0 | var_438_arg_1; [L1284] SORT_1 var_439_arg_0 = var_159; [L1285] SORT_1 var_439_arg_1 = var_438; [L1286] SORT_1 var_439 = var_439_arg_0 & var_439_arg_1; [L1287] SORT_1 var_440_arg_0 = var_437; [L1288] SORT_1 var_440_arg_1 = var_439; [L1289] SORT_1 var_440 = var_440_arg_0 | var_440_arg_1; [L1290] SORT_1 var_441_arg_0 = var_159; [L1291] SORT_1 var_441_arg_1 = var_438; [L1292] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1293] SORT_1 var_442_arg_0 = var_163; [L1294] SORT_1 var_442_arg_1 = var_441; [L1295] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1296] SORT_1 var_443_arg_0 = var_440; [L1297] SORT_1 var_443_arg_1 = var_442; [L1298] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1299] SORT_1 var_444_arg_0 = var_163; [L1300] SORT_1 var_444_arg_1 = var_441; [L1301] SORT_1 var_444 = var_444_arg_0 | var_444_arg_1; [L1302] SORT_1 var_445_arg_0 = var_167; [L1303] SORT_1 var_445_arg_1 = var_444; [L1304] SORT_1 var_445 = var_445_arg_0 & var_445_arg_1; [L1305] SORT_1 var_446_arg_0 = var_443; [L1306] SORT_1 var_446_arg_1 = var_445; [L1307] SORT_1 var_446 = var_446_arg_0 | var_446_arg_1; [L1308] SORT_1 var_447_arg_0 = var_167; [L1309] SORT_1 var_447_arg_1 = var_444; [L1310] SORT_1 var_447 = var_447_arg_0 | var_447_arg_1; [L1311] SORT_1 var_448_arg_0 = var_172; [L1312] SORT_1 var_448_arg_1 = var_447; [L1313] SORT_1 var_448 = var_448_arg_0 & var_448_arg_1; [L1314] SORT_1 var_449_arg_0 = var_446; [L1315] SORT_1 var_449_arg_1 = var_448; [L1316] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1317] SORT_1 var_450_arg_0 = var_172; [L1318] SORT_1 var_450_arg_1 = var_447; [L1319] SORT_1 var_450 = var_450_arg_0 | var_450_arg_1; [L1320] SORT_1 var_451_arg_0 = var_176; [L1321] SORT_1 var_451_arg_1 = var_450; [L1322] SORT_1 var_451 = var_451_arg_0 & var_451_arg_1; [L1323] SORT_1 var_452_arg_0 = var_449; [L1324] SORT_1 var_452_arg_1 = var_451; [L1325] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1326] SORT_1 var_453_arg_0 = var_176; [L1327] SORT_1 var_453_arg_1 = var_450; [L1328] SORT_1 var_453 = var_453_arg_0 | var_453_arg_1; [L1329] SORT_1 var_454_arg_0 = var_180; [L1330] SORT_1 var_454_arg_1 = var_453; [L1331] SORT_1 var_454 = var_454_arg_0 & var_454_arg_1; [L1332] SORT_1 var_455_arg_0 = var_452; [L1333] SORT_1 var_455_arg_1 = var_454; [L1334] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1335] SORT_1 var_456_arg_0 = var_427; [L1336] SORT_1 var_456_arg_1 = ~var_455; [L1337] var_456_arg_1 = var_456_arg_1 & mask_SORT_1 [L1338] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1339] SORT_1 var_457_arg_0 = var_180; [L1340] SORT_1 var_457_arg_1 = var_453; [L1341] SORT_1 var_457 = var_457_arg_0 | var_457_arg_1; [L1342] SORT_1 var_458_arg_0 = var_456; [L1343] SORT_1 var_458_arg_1 = var_457; [L1344] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1345] SORT_1 var_459_arg_0 = var_191; [L1346] SORT_1 var_459_arg_1 = var_186; [L1347] SORT_1 var_459 = var_459_arg_0 & var_459_arg_1; [L1348] SORT_1 var_460_arg_0 = var_191; [L1349] SORT_1 var_460_arg_1 = var_186; [L1350] SORT_1 var_460 = var_460_arg_0 | var_460_arg_1; [L1351] SORT_1 var_461_arg_0 = var_195; [L1352] SORT_1 var_461_arg_1 = var_460; [L1353] SORT_1 var_461 = var_461_arg_0 & var_461_arg_1; [L1354] SORT_1 var_462_arg_0 = var_459; [L1355] SORT_1 var_462_arg_1 = var_461; [L1356] SORT_1 var_462 = var_462_arg_0 | var_462_arg_1; [L1357] SORT_1 var_463_arg_0 = var_195; [L1358] SORT_1 var_463_arg_1 = var_460; [L1359] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1360] SORT_1 var_464_arg_0 = var_199; [L1361] SORT_1 var_464_arg_1 = var_463; [L1362] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1363] SORT_1 var_465_arg_0 = var_462; [L1364] SORT_1 var_465_arg_1 = var_464; [L1365] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1366] SORT_1 var_466_arg_0 = var_199; [L1367] SORT_1 var_466_arg_1 = var_463; [L1368] SORT_1 var_466 = var_466_arg_0 | var_466_arg_1; [L1369] SORT_1 var_467_arg_0 = var_202; [L1370] SORT_1 var_467_arg_1 = var_466; [L1371] SORT_1 var_467 = var_467_arg_0 & var_467_arg_1; [L1372] SORT_1 var_468_arg_0 = var_465; [L1373] SORT_1 var_468_arg_1 = var_467; [L1374] SORT_1 var_468 = var_468_arg_0 | var_468_arg_1; [L1375] SORT_1 var_469_arg_0 = var_458; [L1376] SORT_1 var_469_arg_1 = ~var_468; [L1377] var_469_arg_1 = var_469_arg_1 & mask_SORT_1 [L1378] SORT_1 var_469 = var_469_arg_0 & var_469_arg_1; [L1379] SORT_1 var_470_arg_0 = var_202; [L1380] SORT_1 var_470_arg_1 = var_466; [L1381] SORT_1 var_470 = var_470_arg_0 | var_470_arg_1; [L1382] SORT_1 var_471_arg_0 = var_469; [L1383] SORT_1 var_471_arg_1 = var_470; [L1384] SORT_1 var_471 = var_471_arg_0 & var_471_arg_1; [L1385] SORT_1 var_472_arg_0 = var_418; [L1386] SORT_1 var_472_arg_1 = var_471; [L1387] SORT_1 var_472 = var_472_arg_0 & var_472_arg_1; [L1388] SORT_1 var_473_arg_0 = var_472; [L1389] SORT_1 var_473_arg_1 = ~state_55; [L1390] var_473_arg_1 = var_473_arg_1 & mask_SORT_1 [L1391] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1392] SORT_1 next_474_arg_1 = ~var_473; [L1393] next_474_arg_1 = next_474_arg_1 & mask_SORT_1 [L1395] state_6 = next_80_arg_1 [L1396] state_8 = next_97_arg_1 [L1397] state_10 = next_98_arg_1 [L1398] state_12 = next_110_arg_1 [L1399] state_15 = next_118_arg_1 [L1400] state_17 = next_123_arg_1 [L1401] state_19 = next_127_arg_1 [L1402] state_21 = next_129_arg_1 [L1403] state_23 = next_135_arg_1 [L1404] state_25 = next_140_arg_1 [L1405] state_27 = next_145_arg_1 [L1406] state_29 = next_149_arg_1 [L1407] state_31 = next_156_arg_1 [L1408] state_33 = next_160_arg_1 [L1409] state_35 = next_164_arg_1 [L1410] state_37 = next_168_arg_1 [L1411] state_39 = next_173_arg_1 [L1412] state_41 = next_177_arg_1 [L1413] state_43 = next_181_arg_1 [L1414] state_45 = next_187_arg_1 [L1415] state_47 = next_192_arg_1 [L1416] state_49 = next_196_arg_1 [L1417] state_51 = next_200_arg_1 [L1418] state_53 = next_203_arg_1 [L1419] state_55 = next_474_arg_1 VAL [bad_69_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_16_arg_1=0, init_18_arg_1=0, init_20_arg_1=0, init_22_arg_1=0, init_24_arg_1=0, init_26_arg_1=0, init_28_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_101=1, input_104=1, input_111=1, input_116=10, input_120=253, input_133=252, input_143=5, input_147=42, input_152=22, input_154=246, input_158=50, input_162=6, input_166=255, input_175=2, input_182=2, input_184=1, input_190=3, input_70=1, input_72=1, input_73=0, input_75=1, input_81=1, input_82=1, input_83=1, input_88=1, input_99=0, mask_SORT_1=1, mask_SORT_2=31, mask_SORT_3=65535, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=16, msb_SORT_3=32768, msb_SORT_4=2147483648, next_110_arg_1=1, next_118_arg_1=0, next_123_arg_1=0, next_127_arg_1=28, next_129_arg_1=0, next_135_arg_1=24, next_140_arg_1=1, next_145_arg_1=0, next_149_arg_1=0, next_156_arg_1=36, next_160_arg_1=1, next_164_arg_1=1, next_168_arg_1=1, next_173_arg_1=1, next_177_arg_1=0, next_181_arg_1=0, next_187_arg_1=1, next_192_arg_1=0, next_196_arg_1=0, next_200_arg_1=0, next_203_arg_1=1, next_474_arg_1=0, next_80_arg_1=1, next_97_arg_1=0, next_98_arg_1=0, state_10=0, state_12=1, state_15=0, state_17=0, state_19=28, state_21=0, state_23=24, state_25=1, state_27=0, state_29=0, state_31=36, state_33=1, state_35=1, state_37=1, state_39=1, state_41=0, state_43=0, state_45=1, state_47=0, state_49=0, state_51=0, state_53=1, state_55=0, state_6=1, state_8=0, var_100=3, var_102=1, var_102_arg_0=1, var_102_arg_1=0, var_103=1, var_103_arg_0=1, var_105=4294967295, var_105_arg_0=0, var_105_arg_1=1, var_106=65535, var_106_arg_0=4294967295, var_107=65535, var_107_arg_0=1, var_107_arg_1=65535, var_107_arg_2=0, var_108=1, var_108_arg_0=1, var_108_arg_1=1, var_108_arg_2=65535, var_109=1, var_109_arg_0=0, var_109_arg_1=3, var_109_arg_2=1, var_112=1, var_112_arg_0=0, var_112_arg_1=1, var_113=1, var_113_arg_0=1, var_113_arg_1=1, var_114=1, var_114_arg_0=1, var_114_arg_1=1, var_115=1, var_115_arg_0=1, var_115_arg_1=1, var_117=0, var_117_arg_0=1, var_117_arg_1=0, var_119=0, var_119_arg_0=0, var_119_arg_1=1, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_122=0, var_122_arg_0=0, var_122_arg_1=10, var_124=0, var_124_arg_0=0, var_124_arg_1=1, var_125=0, var_125_arg_0=0, var_125_arg_1=0, var_126=28, var_126_arg_0=0, var_126_arg_1=253, var_128=1, var_128_arg_0=1, var_128_arg_1=1, var_130=0, var_130_arg_0=0, var_130_arg_1=0, var_131=0, var_131_arg_0=0, var_131_arg_1=1, var_132=0, var_132_arg_0=0, var_132_arg_1=1, var_134=24, var_134_arg_0=0, var_134_arg_1=252, var_136=1, var_136_arg_0=0, var_136_arg_1=1, var_137=1, var_137_arg_0=1, var_137_arg_1=1, var_138=1, var_138_arg_0=1, var_138_arg_1=0, var_139=1, var_139_arg_0=1, var_139_arg_1=1, var_14=0, var_141=1, var_141_arg_0=0, var_141_arg_1=1, var_142=1, var_142_arg_0=1, var_142_arg_1=1, var_144=0, var_144_arg_0=1, var_144_arg_1=0, var_146=1, var_146_arg_0=0, var_146_arg_1=1, var_148=0, var_148_arg_0=1, var_148_arg_1=0, var_150=1, var_150_arg_0=0, var_150_arg_1=1, var_151=0, var_151_arg_0=1, var_151_arg_1=0, var_153=0, var_153_arg_0=0, var_153_arg_1=0, var_155=36, var_155_arg_0=0, var_155_arg_1=246, var_157=5, var_157_arg_0=0, var_157_arg_1=5, var_159=1, var_159_arg_0=5, var_159_arg_1=1, var_161=1, var_161_arg_0=0, var_161_arg_1=22, var_163=1, var_163_arg_0=1, var_163_arg_1=1, var_165=1, var_165_arg_0=1, var_165_arg_1=1, var_167=44, var_167_arg_0=1, var_167_arg_1=255, var_169=0, var_169_arg_0=0, var_169_arg_1=50, var_170=1, var_170_arg_0=0, var_170_arg_1=6, var_171=1, var_171_arg_0=1, var_171_arg_1=42, var_172=1, var_172_arg_0=1, var_172_arg_1=1, var_174=2, var_174_arg_0=0, var_174_arg_1=10, var_176=0, var_176_arg_0=2, var_176_arg_1=1, var_178=16, var_178_arg_0=0, var_178_arg_1=2, var_179=0, var_179_arg_0=16, var_179_arg_1=1, var_180=0, var_180_arg_0=0, var_180_arg_1=0, var_183=0, var_183_arg_0=0, var_183_arg_1=0, var_185=0, var_185_arg_0=0, var_185_arg_1=0, var_186=1, var_186_arg_0=0, var_186_arg_1=2, var_188=0, var_188_arg_0=0, var_188_arg_1=2, var_189=0, var_189_arg_0=0, var_189_arg_1=1, var_191=0, var_191_arg_0=0, var_191_arg_1=1, var_193=1, var_193_arg_0=0, var_193_arg_1=1, var_194=1, var_194_arg_0=1, var_194_arg_1=3, var_195=0, var_195_arg_0=1, var_195_arg_1=0, var_197=0, var_197_arg_0=0, var_197_arg_1=0, var_198=0, var_198_arg_0=0, var_198_arg_1=252, var_199=1, var_199_arg_0=0, var_199_arg_1=246, var_201=1, var_201_arg_0=0, var_201_arg_1=1, var_202=1, var_202_arg_0=1, var_202_arg_1=1, var_204=0, var_204_arg_0=0, var_204_arg_1=0, var_205=1, var_205_arg_0=0, var_205_arg_1=16, var_206=1, var_206_arg_0=1, var_206_arg_1=1, var_207=0, var_207_arg_0=0, var_207_arg_1=1, var_208=1, var_208_arg_0=1, var_208_arg_1=0, var_209=6200, var_210=0, var_210_arg_0=6200, var_210_arg_1=0, var_211=1, var_211_arg_0=1, var_211_arg_1=1, var_212=0, var_212_arg_0=0, var_212_arg_1=1, var_213=1, var_213_arg_0=1, var_213_arg_1=0, var_214=1, var_214_arg_0=1, var_214_arg_1=1, var_215=0, var_215_arg_0=0, var_215_arg_1=0, var_216=0, var_216_arg_0=1, var_216_arg_1=0, var_217=0, var_217_arg_0=0, var_217_arg_1=0, var_218=0, var_218_arg_0=0, var_218_arg_1=0, var_219=0, var_219_arg_0=0, var_219_arg_1=1, var_220=0, var_220_arg_0=0, var_220_arg_1=0, var_221=1, var_221_arg_0=1, var_221_arg_1=0, var_222=0, var_222_arg_0=0, var_222_arg_1=1, var_223=1, var_223_arg_0=1, var_223_arg_1=0, var_224=0, var_224_arg_0=0, var_224_arg_1=1, var_225=999, var_226=1, var_226_arg_0=0, var_226_arg_1=999, var_227=5999, var_228=0, var_228_arg_0=5999, var_228_arg_1=0, var_229=0, var_229_arg_0=0, var_229_arg_1=0, var_230=0, var_230_arg_0=0, var_230_arg_1=0, var_231=1, var_231_arg_0=1, var_231_arg_1=0, var_232=0, var_232_arg_0=0, var_232_arg_1=1, var_233=1000, var_234=0, var_234_arg_0=1000, var_234_arg_1=0, var_235=0, var_235_arg_0=0, var_235_arg_1=1, var_236=1, var_236_arg_0=1, var_236_arg_1=0, var_237=0, var_237_arg_0=0, var_237_arg_1=1, var_238=5800, var_239=1, var_239_arg_0=0, var_239_arg_1=5800, var_240=0, var_240_arg_0=0, var_240_arg_1=1, var_241=0, var_241_arg_0=0, var_241_arg_1=0, var_242=0, var_242_arg_0=0, var_242_arg_1=0, var_243=1, var_243_arg_0=0, var_243_arg_1=0, var_244=0, var_244_arg_0=0, var_244_arg_1=0, var_245=1, var_245_arg_0=1, var_245_arg_1=0, var_246=0, var_246_arg_0=0, var_246_arg_1=1, var_247=0, var_247_arg_0=5, var_247_arg_1=0, var_248=0, var_248_arg_0=0, var_248_arg_1=0, var_249=0, var_249_arg_0=0, var_249_arg_1=0, var_250=0, var_250_arg_0=0, var_250_arg_1=0, var_251=1, var_251_arg_0=1, var_251_arg_1=0, var_252=0, var_252_arg_0=0, var_252_arg_1=1, var_253=1, var_253_arg_0=0, var_253_arg_1=0, var_254=0, var_254_arg_0=0, var_254_arg_1=1, var_255=1, var_255_arg_0=1, var_255_arg_1=0, var_256=0, var_256_arg_0=0, var_256_arg_1=1, var_257=0, var_257_arg_0=0, var_257_arg_1=0, var_258=0, var_258_arg_0=0, var_258_arg_1=0, var_259=0, var_259_arg_0=0, var_259_arg_1=0, var_260=1, var_260_arg_0=0, var_260_arg_1=1, var_261=0, var_261_arg_0=0, var_261_arg_1=1, var_262=0, var_262_arg_0=0, var_262_arg_1=0, var_263=0, var_263_arg_0=0, var_263_arg_1=0, var_264=1, var_264_arg_0=0, var_264_arg_1=1, var_265=0, var_265_arg_0=0, var_265_arg_1=1, var_266=1, var_266_arg_0=0, var_266_arg_1=1, var_267=0, var_267_arg_0=0, var_267_arg_1=1, var_268=0, var_268_arg_0=0, var_268_arg_1=0, var_269=0, var_269_arg_0=0, var_269_arg_1=0, var_270=1, var_270_arg_0=0, var_270_arg_1=1, var_271=0, var_271_arg_0=0, var_271_arg_1=1, var_272=0, var_272_arg_0=0, var_272_arg_1=0, var_273=0, var_273_arg_0=0, var_273_arg_1=0, var_274=1, var_274_arg_0=0, var_274_arg_1=1, var_275=0, var_275_arg_0=0, var_275_arg_1=1, var_276=0, var_276_arg_0=0, var_276_arg_1=0, var_277=0, var_277_arg_0=0, var_277_arg_1=1, var_278=0, var_278_arg_0=0, var_278_arg_1=0, var_279=0, var_279_arg_0=0, var_279_arg_1=0, var_280=0, var_280_arg_0=0, var_280_arg_1=1, var_281=1, var_281_arg_0=1, var_281_arg_1=0, var_282=0, var_282_arg_0=0, var_282_arg_1=1, var_283=0, var_283_arg_0=0, var_283_arg_1=0, var_284=1, var_284_arg_0=1, var_284_arg_1=0, var_285=0, var_285_arg_0=0, var_285_arg_1=1, var_286=0, var_286_arg_0=0, var_286_arg_1=0, var_287=0, var_287_arg_0=0, var_287_arg_1=0, var_288=0, var_288_arg_0=0, var_288_arg_1=0, var_289=1, var_289_arg_0=1, var_289_arg_1=1, var_290=1, var_290_arg_0=1, var_290_arg_1=1, var_291=1, var_291_arg_0=0, var_291_arg_1=1, var_292=2, var_292_arg_0=253, var_292_arg_1=1, var_293=45, var_293_arg_0=1, var_293_arg_1=2, var_294=4, var_294_arg_0=1, var_294_arg_1=45, var_295=7, var_295_arg_0=1, var_295_arg_1=4, var_296=39, var_296_arg_0=1, var_296_arg_1=7, var_297=245, var_297_arg_0=1, var_297_arg_1=39, var_298=17, var_298_arg_0=1, var_298_arg_1=245, var_299=5, var_299_arg_0=0, var_299_arg_1=17, var_300=1, var_300_arg_0=5, var_300_arg_1=5, var_301=48, var_301_arg_0=22, var_301_arg_1=1, var_302=34, var_302_arg_0=50, var_302_arg_1=48, var_303=248, var_303_arg_0=6, var_303_arg_1=34, var_304=7, var_304_arg_0=42, var_304_arg_1=248, var_305=1, var_305_arg_0=255, var_305_arg_1=7, var_306=20, var_306_arg_0=2, var_306_arg_1=1, var_307=51, var_307_arg_0=1, var_307_arg_1=20, var_308=7, var_308_arg_0=1, var_308_arg_1=51, var_309=10, var_309_arg_0=3, var_309_arg_1=7, var_310=52, var_310_arg_0=10, var_310_arg_1=10, var_311=0, var_311_arg_0=2, var_311_arg_1=52, var_312=0, var_312_arg_0=252, var_312_arg_1=0, var_313=0, var_313_arg_0=246, var_313_arg_1=0, var_314=0, var_314_arg_0=0, var_314_arg_1=0, var_315=1, var_315_arg_0=1, var_315_arg_1=1, var_316=1, var_316_arg_0=1, var_316_arg_1=1, var_317=1, var_317_arg_0=1, var_317_arg_1=1, var_318=0, var_318_arg_0=0, var_318_arg_1=1, var_319=1, var_319_arg_0=1, var_319_arg_1=0, var_320=1, var_320_arg_0=253, var_320_arg_1=1, var_321=1, var_321_arg_0=1, var_321_arg_1=1, var_322=0, var_322_arg_0=1, var_322_arg_1=2, var_323=1, var_323_arg_0=1, var_323_arg_1=0, var_324=1, var_324_arg_0=1, var_324_arg_1=45, var_325=1, var_325_arg_0=1, var_325_arg_1=1, var_326=0, var_326_arg_0=1, var_326_arg_1=4, var_327=1, var_327_arg_0=1, var_327_arg_1=0, var_328=1, var_328_arg_0=1, var_328_arg_1=7, var_329=1, var_329_arg_0=1, var_329_arg_1=1, var_330=1, var_330_arg_0=1, var_330_arg_1=39, var_331=1, var_331_arg_0=1, var_331_arg_1=1, var_332=1, var_332_arg_0=1, var_332_arg_1=245, var_333=1, var_333_arg_0=1, var_333_arg_1=1, var_334=0, var_334_arg_0=0, var_334_arg_1=17, var_335=1, var_335_arg_0=1, var_335_arg_1=0, var_336=5, var_336_arg_0=5, var_336_arg_1=5, var_337=0, var_337_arg_0=1, var_337_arg_1=5, var_338=0, var_338_arg_0=22, var_338_arg_1=1, var_339=0, var_339_arg_0=0, var_339_arg_1=0, var_340=48, var_340_arg_0=50, var_340_arg_1=48, var_341=9, var_341_arg_0=0, var_341_arg_1=48, var_342=0, var_342_arg_0=6, var_342_arg_1=34, var_343=0, var_343_arg_0=9, var_343_arg_1=0, var_344=42, var_344_arg_0=42, var_344_arg_1=248, var_345=42, var_345_arg_0=0, var_345_arg_1=42, var_346=1, var_346_arg_0=255, var_346_arg_1=7, var_347=19, var_347_arg_0=42, var_347_arg_1=1, var_348=0, var_348_arg_0=2, var_348_arg_1=1, var_349=0, var_349_arg_0=19, var_349_arg_1=0, var_350=0, var_350_arg_0=1, var_350_arg_1=20, var_351=0, var_351_arg_0=0, var_351_arg_1=0, var_352=1, var_352_arg_0=1, var_352_arg_1=51, var_353=1, var_353_arg_0=0, var_353_arg_1=1, var_354=1, var_354_arg_0=3, var_354_arg_1=7, var_355=1, var_355_arg_0=1, var_355_arg_1=1, var_356=10, var_356_arg_0=10, var_356_arg_1=10, var_357=1, var_357_arg_0=1, var_357_arg_1=10, var_358=52, var_358_arg_0=2, var_358_arg_1=52, var_359=0, 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var_403_arg_0=0, var_403_arg_1=1, var_404=0, var_404_arg_0=0, var_404_arg_1=1, var_405=0, var_405_arg_0=0, var_405_arg_1=0, var_406=0, var_406_arg_0=0, var_406_arg_1=0, var_407=0, var_407_arg_0=0, var_407_arg_1=0, var_408=0, var_408_arg_0=0, var_408_arg_1=0, var_409=0, var_409_arg_0=0, var_409_arg_1=0, var_410=0, var_410_arg_0=1, var_410_arg_1=0, var_411=0, var_411_arg_0=0, var_411_arg_1=0, var_412=1, var_412_arg_0=1, var_412_arg_1=0, var_413=0, var_413_arg_0=0, var_413_arg_1=1, var_414=0, var_414_arg_0=0, var_414_arg_1=0, var_415=0, var_415_arg_0=0, var_415_arg_1=0, var_416=1, var_416_arg_0=0, var_416_arg_1=1, var_417=0, var_417_arg_0=0, var_417_arg_1=1, var_418=0, var_418_arg_0=0, var_418_arg_1=0, var_419=0, var_419_arg_0=0, var_419_arg_1=0, var_420=0, var_420_arg_0=0, var_420_arg_1=0, var_421=0, var_421_arg_0=28, var_421_arg_1=0, var_422=0, var_422_arg_0=0, var_422_arg_1=0, var_423=250, var_423_arg_0=28, var_423_arg_1=0, var_424=0, var_424_arg_0=1, var_424_arg_1=250, var_425=0, var_425_arg_0=0, var_425_arg_1=0, var_426=0, var_426_arg_0=1, var_426_arg_1=250, var_427=0, var_427_arg_0=0, var_427_arg_1=0, var_428=0, var_428_arg_0=1, var_428_arg_1=24, var_429=0, var_429_arg_0=1, var_429_arg_1=24, var_430=0, var_430_arg_0=0, var_430_arg_1=0, var_431=0, var_431_arg_0=0, var_431_arg_1=0, var_432=0, var_432_arg_0=0, var_432_arg_1=0, var_433=0, var_433_arg_0=0, var_433_arg_1=0, var_434=0, var_434_arg_0=0, var_434_arg_1=0, var_435=0, var_435_arg_0=0, var_435_arg_1=0, var_436=0, var_436_arg_0=36, var_436_arg_1=0, var_437=0, var_437_arg_0=0, var_437_arg_1=0, var_438=251, var_438_arg_0=36, var_438_arg_1=0, var_439=1, var_439_arg_0=1, var_439_arg_1=251, var_440=1, var_440_arg_0=0, var_440_arg_1=1, var_441=247, var_441_arg_0=1, var_441_arg_1=251, var_442=1, var_442_arg_0=1, var_442_arg_1=247, var_443=1, var_443_arg_0=1, var_443_arg_1=1, var_444=249, var_444_arg_0=1, var_444_arg_1=247, var_445=21, var_445_arg_0=44, var_445_arg_1=249, var_446=15, var_446_arg_0=1, var_446_arg_1=21, var_447=249, var_447_arg_0=44, var_447_arg_1=249, var_448=1, var_448_arg_0=1, var_448_arg_1=249, var_449=7, var_449_arg_0=15, var_449_arg_1=1, var_450=1, var_450_arg_0=1, var_450_arg_1=249, var_451=0, var_451_arg_0=0, var_451_arg_1=1, var_452=7, var_452_arg_0=7, var_452_arg_1=0, var_453=1, var_453_arg_0=0, var_453_arg_1=1, var_454=0, var_454_arg_0=0, var_454_arg_1=1, var_455=1, var_455_arg_0=7, var_455_arg_1=0, var_456=0, var_456_arg_0=0, var_456_arg_1=0, var_457=1, var_457_arg_0=0, var_457_arg_1=1, var_458=0, var_458_arg_0=0, var_458_arg_1=1, var_459=0, var_459_arg_0=0, var_459_arg_1=1, var_460=1, var_460_arg_0=0, var_460_arg_1=1, var_461=0, var_461_arg_0=0, var_461_arg_1=1, var_462=0, var_462_arg_0=0, var_462_arg_1=0, var_463=1, var_463_arg_0=0, var_463_arg_1=1, var_464=1, var_464_arg_0=1, var_464_arg_1=1, var_465=1, var_465_arg_0=0, var_465_arg_1=1, var_466=1, var_466_arg_0=1, var_466_arg_1=1, var_467=1, var_467_arg_0=1, var_467_arg_1=1, var_468=1, var_468_arg_0=1, var_468_arg_1=1, var_469=0, var_469_arg_0=0, var_469_arg_1=0, var_470=1, var_470_arg_0=1, var_470_arg_1=1, var_471=0, var_471_arg_0=0, var_471_arg_1=1, var_472=0, var_472_arg_0=0, var_472_arg_1=0, var_473=0, var_473_arg_0=0, var_473_arg_1=0, var_5=0, var_57=5, var_58=0, var_59=0, var_59_arg_0=0, var_59_arg_1=0, var_60=16, var_61=0, var_61_arg_0=0, var_61_arg_1=16, var_62=0, var_62_arg_0=5, var_62_arg_1=0, var_63=1, var_64=0, var_65=0, var_65_arg_0=0, var_65_arg_1=1, var_65_arg_2=0, var_66=0, var_66_arg_0=1, var_66_arg_1=0, var_67=0, var_67_arg_0=1, var_67_arg_1=0, var_68=0, var_68_arg_0=1, var_68_arg_1=0, var_71=1, var_74=0, var_76=1, var_76_arg_0=1, var_76_arg_1=1, var_76_arg_2=0, var_77=1, var_77_arg_0=0, var_77_arg_1=0, var_77_arg_2=1, var_78=1, var_78_arg_0=1, var_78_arg_1=1, var_78_arg_2=1, var_79=1, var_79_arg_0=1, var_79_arg_1=1, var_79_arg_2=1, var_84=0, var_84_arg_0=0, var_84_arg_1=0, var_85=0, var_85_arg_0=0, var_85_arg_1=16, var_86=4294967295, var_86_arg_0=0, var_86_arg_1=1, var_87=65535, var_87_arg_0=4294967295, var_89=1, var_89_arg_0=1, var_89_arg_1=0, var_90=1, var_90_arg_0=1, var_91=1, var_91_arg_0=1, var_91_arg_1=1, var_91_arg_2=0, var_92=65535, var_92_arg_0=1, var_92_arg_1=65535, var_92_arg_2=1, var_93=65535, var_93_arg_0=0, var_93_arg_1=65535, var_93_arg_2=65535, var_94=0, var_94_arg_0=1, var_94_arg_1=0, var_94_arg_2=65535, var_95=0, var_95_arg_0=1, var_95_arg_1=0, var_95_arg_2=0, var_96=0, var_96_arg_0=1, var_96_arg_1=0, var_96_arg_2=0] [L158] input_70 = __VERIFIER_nondet_uchar() [L159] input_70 = input_70 & mask_SORT_1 [L160] input_72 = __VERIFIER_nondet_uchar() [L161] input_72 = input_72 & mask_SORT_1 [L162] input_73 = __VERIFIER_nondet_uchar() [L163] input_73 = input_73 & mask_SORT_1 [L164] input_75 = __VERIFIER_nondet_uchar() [L165] input_75 = input_75 & mask_SORT_1 [L166] input_81 = __VERIFIER_nondet_uchar() [L167] input_81 = input_81 & mask_SORT_1 [L168] input_82 = __VERIFIER_nondet_uchar() [L169] input_82 = input_82 & mask_SORT_1 [L170] input_83 = __VERIFIER_nondet_uchar() [L171] input_83 = input_83 & mask_SORT_1 [L172] input_88 = __VERIFIER_nondet_uchar() [L173] input_88 = input_88 & mask_SORT_1 [L174] input_99 = __VERIFIER_nondet_uchar() [L175] input_99 = input_99 & mask_SORT_1 [L176] input_101 = __VERIFIER_nondet_uchar() [L177] input_101 = input_101 & mask_SORT_1 [L178] input_104 = __VERIFIER_nondet_uchar() [L179] input_104 = input_104 & mask_SORT_1 [L180] input_111 = __VERIFIER_nondet_uchar() [L181] input_116 = __VERIFIER_nondet_uchar() [L182] input_120 = __VERIFIER_nondet_uchar() [L183] input_133 = __VERIFIER_nondet_uchar() [L184] input_143 = __VERIFIER_nondet_uchar() [L185] input_147 = __VERIFIER_nondet_uchar() [L186] input_152 = __VERIFIER_nondet_uchar() [L187] input_154 = __VERIFIER_nondet_uchar() [L188] input_158 = __VERIFIER_nondet_uchar() [L189] input_162 = __VERIFIER_nondet_uchar() [L190] input_166 = __VERIFIER_nondet_uchar() [L191] input_175 = __VERIFIER_nondet_uchar() [L192] input_182 = __VERIFIER_nondet_uchar() [L193] input_184 = __VERIFIER_nondet_uchar() [L194] input_190 = __VERIFIER_nondet_uchar() [L197] SORT_3 var_59_arg_0 = state_12; [L198] SORT_3 var_59_arg_1 = var_58; [L199] SORT_4 var_59 = ((SORT_4)var_59_arg_0 << 16) | var_59_arg_1; [L200] SORT_4 var_61_arg_0 = var_59; [L201] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L201] var_61_arg_0 = (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L202] SORT_4 var_61_arg_1 = var_60; [L203] SORT_4 var_61 = (int)var_61_arg_0 >> var_61_arg_1; [L204] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L204] var_61 = (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L205] var_61 = var_61 & mask_SORT_4 [L206] SORT_4 var_62_arg_0 = var_57; [L207] SORT_4 var_62_arg_1 = var_61; [L208] SORT_1 var_62 = var_62_arg_0 == var_62_arg_1; [L209] SORT_1 var_65_arg_0 = state_35; [L210] SORT_4 var_65_arg_1 = var_63; [L211] SORT_4 var_65_arg_2 = var_64; [L212] EXPR var_65_arg_0 ? var_65_arg_1 : var_65_arg_2 [L212] SORT_4 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L213] var_65 = var_65 & mask_SORT_4 [L214] SORT_4 var_66_arg_0 = var_63; [L215] SORT_4 var_66_arg_1 = var_65; [L216] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L217] SORT_1 var_67_arg_0 = ~var_62; [L218] var_67_arg_0 = var_67_arg_0 & mask_SORT_1 [L219] SORT_1 var_67_arg_1 = var_66; [L220] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L221] SORT_1 var_68_arg_0 = ~state_55; [L222] var_68_arg_0 = var_68_arg_0 & mask_SORT_1 [L223] SORT_1 var_68_arg_1 = var_67; [L224] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L225] var_68 = var_68 & mask_SORT_1 [L226] SORT_1 bad_69_arg_0 = var_68; [L227] CALL __VERIFIER_assert(!(bad_69_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 260.2s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 2.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 1 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 2.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 2.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 7 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 7 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 122.4s SatisfiabilityAnalysisTime, 2.9s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 18 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 03:53:06,194 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 32680cd5468fc7b83afae376e65e08c96334765648dec339f78f485e369894d8 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 03:53:09,056 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 03:53:09,059 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 03:53:09,092 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 03:53:09,093 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 03:53:09,094 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 03:53:09,096 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 03:53:09,098 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 03:53:09,102 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 03:53:09,104 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 03:53:09,105 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 03:53:09,106 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 03:53:09,107 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 03:53:09,108 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 03:53:09,109 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 03:53:09,111 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 03:53:09,112 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 03:53:09,113 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 03:53:09,115 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 03:53:09,122 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 03:53:09,130 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 03:53:09,135 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 03:53:09,137 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 03:53:09,138 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 03:53:09,143 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 03:53:09,143 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 03:53:09,143 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 03:53:09,145 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 03:53:09,145 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 03:53:09,159 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 03:53:09,159 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 03:53:09,160 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 03:53:09,161 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 03:53:09,162 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 03:53:09,163 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 03:53:09,163 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 03:53:09,164 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 03:53:09,165 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 03:53:09,176 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 03:53:09,177 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 03:53:09,180 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 03:53:09,181 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 03:53:09,233 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 03:53:09,233 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 03:53:09,235 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 03:53:09,235 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 03:53:09,236 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 03:53:09,236 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 03:53:09,237 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 03:53:09,237 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 03:53:09,237 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 03:53:09,237 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 03:53:09,239 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 03:53:09,239 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 03:53:09,241 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 03:53:09,241 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 03:53:09,242 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 03:53:09,242 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 03:53:09,242 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 03:53:09,242 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 03:53:09,243 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 03:53:09,243 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 03:53:09,243 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 03:53:09,243 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 03:53:09,244 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 03:53:09,244 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 03:53:09,244 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 03:53:09,244 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 03:53:09,245 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:53:09,245 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 03:53:09,245 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 03:53:09,246 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 03:53:09,246 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 03:53:09,246 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 03:53:09,247 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 03:53:09,247 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 03:53:09,247 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 03:53:09,247 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 32680cd5468fc7b83afae376e65e08c96334765648dec339f78f485e369894d8 [2022-11-03 03:53:09,712 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 03:53:09,751 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 03:53:09,754 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 03:53:09,755 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 03:53:09,758 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 03:53:09,765 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:53:09,838 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/82d9c84bb/23f4fa5829724527ae6bc9d4f101ea3e/FLAG79564abfd [2022-11-03 03:53:10,658 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 03:53:10,659 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:53:10,685 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/82d9c84bb/23f4fa5829724527ae6bc9d4f101ea3e/FLAG79564abfd [2022-11-03 03:53:10,774 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/data/82d9c84bb/23f4fa5829724527ae6bc9d4f101ea3e [2022-11-03 03:53:10,777 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 03:53:10,779 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 03:53:10,780 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 03:53:10,781 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 03:53:10,788 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 03:53:10,790 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:53:10" (1/1) ... [2022-11-03 03:53:10,793 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@9041602 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:10, skipping insertion in model container [2022-11-03 03:53:10,794 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 03:53:10" (1/1) ... [2022-11-03 03:53:10,805 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 03:53:10,904 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 03:53:11,108 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c[1014,1027] [2022-11-03 03:53:11,507 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:53:11,535 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 03:53:11,545 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.resistance.1.prop3-func-interl.c[1014,1027] [2022-11-03 03:53:11,817 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 03:53:11,833 INFO L208 MainTranslator]: Completed translation [2022-11-03 03:53:11,834 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11 WrapperNode [2022-11-03 03:53:11,834 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 03:53:11,835 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 03:53:11,836 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 03:53:11,836 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 03:53:11,845 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:11,893 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,073 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 1526 [2022-11-03 03:53:12,074 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 03:53:12,075 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 03:53:12,075 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 03:53:12,075 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 03:53:12,092 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,092 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,103 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,104 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,144 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,153 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,160 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,168 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,183 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 03:53:12,184 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 03:53:12,184 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 03:53:12,184 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 03:53:12,185 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (1/1) ... [2022-11-03 03:53:12,193 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 03:53:12,209 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:53:12,223 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 03:53:12,279 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 03:53:12,357 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 03:53:12,357 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 03:53:12,927 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 03:53:12,930 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 03:53:14,845 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 03:53:14,854 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 03:53:14,855 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 03:53:14,857 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:53:14 BoogieIcfgContainer [2022-11-03 03:53:14,857 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 03:53:14,860 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 03:53:14,860 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 03:53:14,864 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 03:53:14,864 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 03:53:10" (1/3) ... [2022-11-03 03:53:14,865 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ce59510 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:53:14, skipping insertion in model container [2022-11-03 03:53:14,865 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 03:53:11" (2/3) ... [2022-11-03 03:53:14,865 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4ce59510 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 03:53:14, skipping insertion in model container [2022-11-03 03:53:14,866 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:53:14" (3/3) ... [2022-11-03 03:53:14,867 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.resistance.1.prop3-func-interl.c [2022-11-03 03:53:14,891 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 03:53:14,892 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 03:53:14,956 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 03:53:14,964 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@3fadfc9b, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 03:53:14,964 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 03:53:14,970 INFO L276 IsEmpty]: Start isEmpty. Operand has 51 states, 49 states have (on average 1.489795918367347) internal successors, (73), 50 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:14,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-11-03 03:53:14,977 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:14,978 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:14,979 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:14,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:14,985 INFO L85 PathProgramCache]: Analyzing trace with hash -1473645707, now seen corresponding path program 1 times [2022-11-03 03:53:15,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:15,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [303679725] [2022-11-03 03:53:15,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:15,003 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:15,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:15,010 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:15,020 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 03:53:15,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:15,563 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-03 03:53:15,587 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:15,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:15,749 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:15,750 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:15,751 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [303679725] [2022-11-03 03:53:15,751 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [303679725] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:15,752 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:15,752 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:53:15,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [336858998] [2022-11-03 03:53:15,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:15,761 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:53:15,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:15,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:53:15,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:53:15,802 INFO L87 Difference]: Start difference. First operand has 51 states, 49 states have (on average 1.489795918367347) internal successors, (73), 50 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:16,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:16,076 INFO L93 Difference]: Finished difference Result 98 states and 146 transitions. [2022-11-03 03:53:16,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-03 03:53:16,081 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-11-03 03:53:16,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:16,100 INFO L225 Difference]: With dead ends: 98 [2022-11-03 03:53:16,100 INFO L226 Difference]: Without dead ends: 49 [2022-11-03 03:53:16,107 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:53:16,113 INFO L413 NwaCegarLoop]: 65 mSDtfsCounter, 1 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 15 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 168 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 15 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 15 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:16,116 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 168 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 15 Invalid, 0 Unknown, 15 Unchecked, 0.2s Time] [2022-11-03 03:53:16,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-11-03 03:53:16,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2022-11-03 03:53:16,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 48 states have (on average 1.4375) internal successors, (69), 48 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:16,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 69 transitions. [2022-11-03 03:53:16,162 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 69 transitions. Word has length 11 [2022-11-03 03:53:16,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:16,162 INFO L495 AbstractCegarLoop]: Abstraction has 49 states and 69 transitions. [2022-11-03 03:53:16,163 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:16,163 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 69 transitions. [2022-11-03 03:53:16,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-11-03 03:53:16,164 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:16,164 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:16,175 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Ended with exit code 0 [2022-11-03 03:53:16,369 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:16,369 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:16,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:16,370 INFO L85 PathProgramCache]: Analyzing trace with hash 2011974963, now seen corresponding path program 1 times [2022-11-03 03:53:16,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:16,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [2108598208] [2022-11-03 03:53:16,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:16,372 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:16,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:16,374 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:16,394 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 03:53:16,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:16,802 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 03:53:16,809 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:16,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:16,961 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:16,962 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:16,962 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [2108598208] [2022-11-03 03:53:16,963 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [2108598208] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:16,963 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:16,963 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 03:53:16,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952940530] [2022-11-03 03:53:16,969 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:16,971 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:53:16,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:16,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:53:16,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:53:16,974 INFO L87 Difference]: Start difference. First operand 49 states and 69 transitions. Second operand has 5 states, 5 states have (on average 2.2) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:17,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:17,200 INFO L93 Difference]: Finished difference Result 96 states and 137 transitions. [2022-11-03 03:53:17,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 03:53:17,201 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-11-03 03:53:17,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:17,202 INFO L225 Difference]: With dead ends: 96 [2022-11-03 03:53:17,202 INFO L226 Difference]: Without dead ends: 51 [2022-11-03 03:53:17,203 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-11-03 03:53:17,204 INFO L413 NwaCegarLoop]: 63 mSDtfsCounter, 1 mSDsluCounter, 155 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1 SdHoareTripleChecker+Valid, 218 SdHoareTripleChecker+Invalid, 41 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 27 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:17,205 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1 Valid, 218 Invalid, 41 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 27 Unchecked, 0.2s Time] [2022-11-03 03:53:17,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2022-11-03 03:53:17,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2022-11-03 03:53:17,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 50 states have (on average 1.42) internal successors, (71), 50 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:17,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 71 transitions. [2022-11-03 03:53:17,218 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 71 transitions. Word has length 11 [2022-11-03 03:53:17,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:17,220 INFO L495 AbstractCegarLoop]: Abstraction has 51 states and 71 transitions. [2022-11-03 03:53:17,221 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.2) internal successors, (11), 5 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:17,226 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 71 transitions. [2022-11-03 03:53:17,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-11-03 03:53:17,226 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:17,227 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:17,250 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:17,442 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:17,443 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:17,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:17,443 INFO L85 PathProgramCache]: Analyzing trace with hash 2069233265, now seen corresponding path program 1 times [2022-11-03 03:53:17,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:17,444 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [139081099] [2022-11-03 03:53:17,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:17,445 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:17,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:17,446 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:17,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 03:53:17,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:17,903 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 03:53:17,908 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:17,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:17,939 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:17,939 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:17,940 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [139081099] [2022-11-03 03:53:17,940 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [139081099] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:17,940 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:17,940 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:53:17,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2078267695] [2022-11-03 03:53:17,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:17,941 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:53:17,942 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:17,942 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:53:17,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:53:17,943 INFO L87 Difference]: Start difference. First operand 51 states and 71 transitions. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:18,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:18,195 INFO L93 Difference]: Finished difference Result 181 states and 258 transitions. [2022-11-03 03:53:18,198 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:53:18,199 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-11-03 03:53:18,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:18,200 INFO L225 Difference]: With dead ends: 181 [2022-11-03 03:53:18,201 INFO L226 Difference]: Without dead ends: 136 [2022-11-03 03:53:18,201 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:53:18,203 INFO L413 NwaCegarLoop]: 68 mSDtfsCounter, 175 mSDsluCounter, 180 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 175 SdHoareTripleChecker+Valid, 248 SdHoareTripleChecker+Invalid, 13 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:18,203 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [175 Valid, 248 Invalid, 13 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 03:53:18,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2022-11-03 03:53:18,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 53. [2022-11-03 03:53:18,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 52 states have (on average 1.4038461538461537) internal successors, (73), 52 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:18,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 73 transitions. [2022-11-03 03:53:18,213 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 73 transitions. Word has length 11 [2022-11-03 03:53:18,214 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:18,214 INFO L495 AbstractCegarLoop]: Abstraction has 53 states and 73 transitions. [2022-11-03 03:53:18,214 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 4 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:18,214 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 73 transitions. [2022-11-03 03:53:18,215 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-11-03 03:53:18,215 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:18,215 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:18,244 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:18,444 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:18,445 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:18,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:18,445 INFO L85 PathProgramCache]: Analyzing trace with hash 2069292847, now seen corresponding path program 1 times [2022-11-03 03:53:18,446 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:18,446 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1297504107] [2022-11-03 03:53:18,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:18,446 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:18,447 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:18,450 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:18,454 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 03:53:18,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:18,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 03:53:18,864 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:19,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:19,130 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:19,130 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:19,130 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1297504107] [2022-11-03 03:53:19,133 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1297504107] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:19,134 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:19,134 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 03:53:19,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775290346] [2022-11-03 03:53:19,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:19,135 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 03:53:19,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:19,137 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 03:53:19,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-11-03 03:53:19,142 INFO L87 Difference]: Start difference. First operand 53 states and 73 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:19,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:19,672 INFO L93 Difference]: Finished difference Result 100 states and 140 transitions. [2022-11-03 03:53:19,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 03:53:19,673 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 11 [2022-11-03 03:53:19,673 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:19,674 INFO L225 Difference]: With dead ends: 100 [2022-11-03 03:53:19,674 INFO L226 Difference]: Without dead ends: 98 [2022-11-03 03:53:19,674 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=34, Invalid=56, Unknown=0, NotChecked=0, Total=90 [2022-11-03 03:53:19,675 INFO L413 NwaCegarLoop]: 61 mSDtfsCounter, 302 mSDsluCounter, 124 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 302 SdHoareTripleChecker+Valid, 185 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:19,676 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [302 Valid, 185 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-03 03:53:19,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2022-11-03 03:53:19,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 55. [2022-11-03 03:53:19,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 54 states have (on average 1.3888888888888888) internal successors, (75), 54 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:19,684 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 75 transitions. [2022-11-03 03:53:19,684 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 75 transitions. Word has length 11 [2022-11-03 03:53:19,685 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:19,685 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 75 transitions. [2022-11-03 03:53:19,685 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:19,685 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 75 transitions. [2022-11-03 03:53:19,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:53:19,687 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:19,688 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:19,710 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:19,904 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:19,904 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:19,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:19,905 INFO L85 PathProgramCache]: Analyzing trace with hash 1586803945, now seen corresponding path program 1 times [2022-11-03 03:53:19,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:19,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1225296428] [2022-11-03 03:53:19,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:19,909 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:19,909 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:19,911 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:19,915 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 03:53:20,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:20,888 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-03 03:53:20,900 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:21,124 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:21,124 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:21,124 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:21,125 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1225296428] [2022-11-03 03:53:21,125 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1225296428] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:21,125 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:21,125 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:53:21,125 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [147111334] [2022-11-03 03:53:21,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:21,126 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:53:21,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:21,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:53:21,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:53:21,127 INFO L87 Difference]: Start difference. First operand 55 states and 75 transitions. Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:21,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:21,299 INFO L93 Difference]: Finished difference Result 114 states and 159 transitions. [2022-11-03 03:53:21,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-03 03:53:21,300 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:53:21,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:21,301 INFO L225 Difference]: With dead ends: 114 [2022-11-03 03:53:21,301 INFO L226 Difference]: Without dead ends: 67 [2022-11-03 03:53:21,302 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:53:21,303 INFO L413 NwaCegarLoop]: 63 mSDtfsCounter, 5 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 17 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 5 SdHoareTripleChecker+Valid, 166 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 17 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 17 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:21,303 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [5 Valid, 166 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 17 Invalid, 0 Unknown, 17 Unchecked, 0.1s Time] [2022-11-03 03:53:21,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2022-11-03 03:53:21,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2022-11-03 03:53:21,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 66 states have (on average 1.378787878787879) internal successors, (91), 66 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:21,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 91 transitions. [2022-11-03 03:53:21,311 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 91 transitions. Word has length 54 [2022-11-03 03:53:21,312 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:21,312 INFO L495 AbstractCegarLoop]: Abstraction has 67 states and 91 transitions. [2022-11-03 03:53:21,312 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:21,312 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 91 transitions. [2022-11-03 03:53:21,313 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:53:21,314 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:21,314 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:21,346 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:21,539 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:21,540 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:21,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:21,540 INFO L85 PathProgramCache]: Analyzing trace with hash 742798443, now seen corresponding path program 1 times [2022-11-03 03:53:21,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:21,542 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [471695681] [2022-11-03 03:53:21,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:21,542 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:21,542 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:21,543 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:21,545 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 03:53:22,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:22,444 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 8 conjunts are in the unsatisfiable core [2022-11-03 03:53:22,456 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:22,803 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:22,804 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:22,804 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:22,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [471695681] [2022-11-03 03:53:22,804 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [471695681] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:22,805 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:22,805 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 03:53:22,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174480321] [2022-11-03 03:53:22,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:22,807 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 03:53:22,807 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:22,807 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 03:53:22,808 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 03:53:22,808 INFO L87 Difference]: Start difference. First operand 67 states and 91 transitions. Second operand has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:23,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:23,025 INFO L93 Difference]: Finished difference Result 136 states and 191 transitions. [2022-11-03 03:53:23,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-03 03:53:23,026 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:53:23,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:23,027 INFO L225 Difference]: With dead ends: 136 [2022-11-03 03:53:23,027 INFO L226 Difference]: Without dead ends: 89 [2022-11-03 03:53:23,028 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 03:53:23,029 INFO L413 NwaCegarLoop]: 59 mSDtfsCounter, 15 mSDsluCounter, 103 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 162 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 21 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:23,029 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 162 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 21 Invalid, 0 Unknown, 21 Unchecked, 0.2s Time] [2022-11-03 03:53:23,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2022-11-03 03:53:23,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2022-11-03 03:53:23,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 88 states have (on average 1.3977272727272727) internal successors, (123), 88 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:23,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 123 transitions. [2022-11-03 03:53:23,048 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 123 transitions. Word has length 54 [2022-11-03 03:53:23,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:23,049 INFO L495 AbstractCegarLoop]: Abstraction has 89 states and 123 transitions. [2022-11-03 03:53:23,049 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 13.5) internal successors, (54), 4 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:23,050 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 123 transitions. [2022-11-03 03:53:23,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:53:23,051 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:23,051 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:23,087 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:23,266 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:23,267 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:23,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:23,267 INFO L85 PathProgramCache]: Analyzing trace with hash 155992429, now seen corresponding path program 1 times [2022-11-03 03:53:23,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:23,269 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1834465367] [2022-11-03 03:53:23,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:23,269 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:23,270 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:23,275 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:23,320 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 03:53:24,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:24,220 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 10 conjunts are in the unsatisfiable core [2022-11-03 03:53:24,230 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:26,694 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:26,695 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:53:26,695 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:26,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1834465367] [2022-11-03 03:53:26,695 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1834465367] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:53:26,695 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:53:26,695 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-03 03:53:26,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796225626] [2022-11-03 03:53:26,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:53:26,696 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-03 03:53:26,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:53:26,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-03 03:53:26,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=19, Unknown=1, NotChecked=0, Total=30 [2022-11-03 03:53:26,697 INFO L87 Difference]: Start difference. First operand 89 states and 123 transitions. Second operand has 6 states, 6 states have (on average 9.0) internal successors, (54), 6 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:26,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:53:26,946 INFO L93 Difference]: Finished difference Result 138 states and 193 transitions. [2022-11-03 03:53:26,947 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-11-03 03:53:26,947 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.0) internal successors, (54), 6 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:53:26,948 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:53:26,948 INFO L225 Difference]: With dead ends: 138 [2022-11-03 03:53:26,948 INFO L226 Difference]: Without dead ends: 91 [2022-11-03 03:53:26,949 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 49 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=15, Invalid=26, Unknown=1, NotChecked=0, Total=42 [2022-11-03 03:53:26,950 INFO L413 NwaCegarLoop]: 57 mSDtfsCounter, 15 mSDsluCounter, 203 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 260 SdHoareTripleChecker+Invalid, 61 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 41 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:53:26,950 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 260 Invalid, 61 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 20 Invalid, 0 Unknown, 41 Unchecked, 0.2s Time] [2022-11-03 03:53:26,951 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2022-11-03 03:53:26,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 91. [2022-11-03 03:53:26,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 90 states have (on average 1.3888888888888888) internal successors, (125), 90 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:26,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 125 transitions. [2022-11-03 03:53:26,958 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 125 transitions. Word has length 54 [2022-11-03 03:53:26,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:53:26,959 INFO L495 AbstractCegarLoop]: Abstraction has 91 states and 125 transitions. [2022-11-03 03:53:26,959 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.0) internal successors, (54), 6 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:53:26,959 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 125 transitions. [2022-11-03 03:53:26,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:53:26,961 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:53:26,961 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:53:26,995 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 03:53:27,186 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:53:27,186 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:53:27,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:53:27,187 INFO L85 PathProgramCache]: Analyzing trace with hash 857057007, now seen corresponding path program 1 times [2022-11-03 03:53:27,189 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:53:27,189 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1085830253] [2022-11-03 03:53:27,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:27,189 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:53:27,189 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:53:27,191 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:53:27,197 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 03:53:28,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:28,073 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 03:53:28,084 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:29,266 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:29,267 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:53:36,140 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:36,141 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:53:36,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1085830253] [2022-11-03 03:53:36,141 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1085830253] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:53:36,141 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1285975906] [2022-11-03 03:53:36,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:36,142 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:53:36,142 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:53:36,145 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:53:36,150 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Waiting until timeout for monitored process [2022-11-03 03:53:37,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:37,577 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 32 conjunts are in the unsatisfiable core [2022-11-03 03:53:37,586 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:38,160 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:38,161 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:53:51,729 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:51,733 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1285975906] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:53:51,733 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1783640829] [2022-11-03 03:53:51,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:53:51,734 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:53:51,734 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:53:51,737 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:53:51,758 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-03 03:53:52,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:53:52,551 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 33 conjunts are in the unsatisfiable core [2022-11-03 03:53:52,558 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:53:53,738 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:53:53,739 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:04,528 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:04,529 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1783640829] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:04,529 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:54:04,529 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 15, 16, 16, 16] total 39 [2022-11-03 03:54:04,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853223536] [2022-11-03 03:54:04,530 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:54:04,531 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 39 states [2022-11-03 03:54:04,531 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:54:04,532 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-03 03:54:04,532 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=1357, Unknown=12, NotChecked=0, Total=1482 [2022-11-03 03:54:04,533 INFO L87 Difference]: Start difference. First operand 91 states and 125 transitions. Second operand has 39 states, 39 states have (on average 2.8974358974358974) internal successors, (113), 39 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:04,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:54:04,988 INFO L93 Difference]: Finished difference Result 170 states and 235 transitions. [2022-11-03 03:54:04,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-11-03 03:54:04,989 INFO L78 Accepts]: Start accepts. Automaton has has 39 states, 39 states have (on average 2.8974358974358974) internal successors, (113), 39 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:54:04,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:54:04,990 INFO L225 Difference]: With dead ends: 170 [2022-11-03 03:54:04,990 INFO L226 Difference]: Without dead ends: 123 [2022-11-03 03:54:04,992 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 321 GetRequests, 274 SyntacticMatches, 7 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 372 ImplicationChecksByTransitivity, 31.4s TimeCoverageRelationStatistics Valid=154, Invalid=1556, Unknown=12, NotChecked=0, Total=1722 [2022-11-03 03:54:04,992 INFO L413 NwaCegarLoop]: 53 mSDtfsCounter, 75 mSDsluCounter, 1093 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 75 SdHoareTripleChecker+Valid, 1146 SdHoareTripleChecker+Invalid, 259 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 231 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-03 03:54:04,993 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [75 Valid, 1146 Invalid, 259 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 26 Invalid, 0 Unknown, 231 Unchecked, 0.1s Time] [2022-11-03 03:54:04,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states. [2022-11-03 03:54:05,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 116. [2022-11-03 03:54:05,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 115 states have (on average 1.382608695652174) internal successors, (159), 115 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:05,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 159 transitions. [2022-11-03 03:54:05,003 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 159 transitions. Word has length 54 [2022-11-03 03:54:05,004 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:54:05,004 INFO L495 AbstractCegarLoop]: Abstraction has 116 states and 159 transitions. [2022-11-03 03:54:05,004 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 39 states, 39 states have (on average 2.8974358974358974) internal successors, (113), 39 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:05,005 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 159 transitions. [2022-11-03 03:54:05,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:54:05,006 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:54:05,007 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:54:05,026 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (10)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:05,238 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:05,449 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:05,618 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:54:05,619 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:54:05,619 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:54:05,619 INFO L85 PathProgramCache]: Analyzing trace with hash 47710381, now seen corresponding path program 1 times [2022-11-03 03:54:05,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:54:05,621 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1962943228] [2022-11-03 03:54:05,621 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:05,621 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:54:05,621 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:54:05,622 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:54:05,625 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 03:54:06,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:06,382 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-03 03:54:06,391 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:07,877 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:07,877 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:10,994 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:10,995 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:54:10,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1962943228] [2022-11-03 03:54:10,995 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1962943228] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:10,995 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [746592740] [2022-11-03 03:54:10,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:10,996 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:54:10,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:54:10,997 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:54:10,998 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Waiting until timeout for monitored process [2022-11-03 03:54:12,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:12,401 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 34 conjunts are in the unsatisfiable core [2022-11-03 03:54:12,410 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:12,985 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:12,985 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:13,828 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 4 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:13,829 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [746592740] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:13,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1360323914] [2022-11-03 03:54:13,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:13,833 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:54:13,834 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:54:13,838 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:54:13,847 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-03 03:54:14,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:14,490 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-03 03:54:14,496 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:15,069 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-03 03:54:15,069 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 03:54:15,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1360323914] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 03:54:15,070 INFO L184 FreeRefinementEngine]: Found 1 perfect and 4 imperfect interpolant sequences. [2022-11-03 03:54:15,070 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [17, 18, 17, 18] total 36 [2022-11-03 03:54:15,070 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [612865354] [2022-11-03 03:54:15,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 03:54:15,071 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 03:54:15,071 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:54:15,072 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 03:54:15,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=1137, Unknown=0, NotChecked=0, Total=1260 [2022-11-03 03:54:15,073 INFO L87 Difference]: Start difference. First operand 116 states and 159 transitions. Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:15,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:54:15,122 INFO L93 Difference]: Finished difference Result 165 states and 229 transitions. [2022-11-03 03:54:15,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 03:54:15,123 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:54:15,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:54:15,124 INFO L225 Difference]: With dead ends: 165 [2022-11-03 03:54:15,124 INFO L226 Difference]: Without dead ends: 118 [2022-11-03 03:54:15,125 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 265 GetRequests, 227 SyntacticMatches, 4 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=123, Invalid=1137, Unknown=0, NotChecked=0, Total=1260 [2022-11-03 03:54:15,126 INFO L413 NwaCegarLoop]: 54 mSDtfsCounter, 22 mSDsluCounter, 104 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 22 SdHoareTripleChecker+Valid, 158 SdHoareTripleChecker+Invalid, 37 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 26 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 03:54:15,126 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [22 Valid, 158 Invalid, 37 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 11 Invalid, 0 Unknown, 26 Unchecked, 0.0s Time] [2022-11-03 03:54:15,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2022-11-03 03:54:15,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2022-11-03 03:54:15,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 117 states have (on average 1.376068376068376) internal successors, (161), 117 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:15,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 161 transitions. [2022-11-03 03:54:15,135 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 161 transitions. Word has length 54 [2022-11-03 03:54:15,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:54:15,136 INFO L495 AbstractCegarLoop]: Abstraction has 118 states and 161 transitions. [2022-11-03 03:54:15,136 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:15,137 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 161 transitions. [2022-11-03 03:54:15,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:54:15,138 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:54:15,138 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:54:15,150 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (13)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:15,380 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2022-11-03 03:54:15,570 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:15,750 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:54:15,750 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:54:15,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:54:15,751 INFO L85 PathProgramCache]: Analyzing trace with hash 104968683, now seen corresponding path program 1 times [2022-11-03 03:54:15,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:54:15,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1371734195] [2022-11-03 03:54:15,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:15,752 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:54:15,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:54:15,754 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:54:15,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 03:54:16,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:16,583 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-03 03:54:16,591 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:17,630 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:17,630 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:23,223 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:23,224 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:54:23,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1371734195] [2022-11-03 03:54:23,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1371734195] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:23,224 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [836752337] [2022-11-03 03:54:23,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:23,224 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:54:23,225 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:54:23,226 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:54:23,230 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (16)] Waiting until timeout for monitored process [2022-11-03 03:54:24,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:24,615 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 40 conjunts are in the unsatisfiable core [2022-11-03 03:54:24,620 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:25,433 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:25,434 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:26,508 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:26,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [836752337] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:26,509 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [603769661] [2022-11-03 03:54:26,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:26,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:54:26,510 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:54:26,514 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:54:26,534 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2022-11-03 03:54:27,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:27,193 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-03 03:54:27,198 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:28,208 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:28,208 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:29,584 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:29,585 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [603769661] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:29,585 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:54:29,585 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 9, 9] total 16 [2022-11-03 03:54:29,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1111199127] [2022-11-03 03:54:29,586 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:54:29,587 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-11-03 03:54:29,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:54:29,588 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-11-03 03:54:29,588 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=181, Unknown=1, NotChecked=0, Total=240 [2022-11-03 03:54:29,589 INFO L87 Difference]: Start difference. First operand 118 states and 161 transitions. Second operand has 16 states, 16 states have (on average 6.875) internal successors, (110), 16 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:29,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:54:29,631 INFO L93 Difference]: Finished difference Result 215 states and 295 transitions. [2022-11-03 03:54:29,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-03 03:54:29,632 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 6.875) internal successors, (110), 16 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:54:29,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:54:29,635 INFO L225 Difference]: With dead ends: 215 [2022-11-03 03:54:29,635 INFO L226 Difference]: Without dead ends: 213 [2022-11-03 03:54:29,635 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 298 SyntacticMatches, 6 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 107 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=58, Invalid=181, Unknown=1, NotChecked=0, Total=240 [2022-11-03 03:54:29,637 INFO L413 NwaCegarLoop]: 108 mSDtfsCounter, 345 mSDsluCounter, 738 mSDsCounter, 0 mSdLazyCounter, 5 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 345 SdHoareTripleChecker+Valid, 846 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 5 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 29 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 03:54:29,638 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [345 Valid, 846 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 5 Invalid, 0 Unknown, 29 Unchecked, 0.0s Time] [2022-11-03 03:54:29,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2022-11-03 03:54:29,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 178. [2022-11-03 03:54:29,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 177 states have (on average 1.3728813559322033) internal successors, (243), 177 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:29,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 243 transitions. [2022-11-03 03:54:29,654 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 243 transitions. Word has length 54 [2022-11-03 03:54:29,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:54:29,656 INFO L495 AbstractCegarLoop]: Abstraction has 178 states and 243 transitions. [2022-11-03 03:54:29,656 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 6.875) internal successors, (110), 16 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:54:29,657 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 243 transitions. [2022-11-03 03:54:29,662 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:54:29,666 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:54:29,666 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:54:29,683 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (16)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:29,908 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:30,097 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 03:54:30,278 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:54:30,278 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:54:30,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:54:30,279 INFO L85 PathProgramCache]: Analyzing trace with hash 764500205, now seen corresponding path program 1 times [2022-11-03 03:54:30,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:54:30,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1161462597] [2022-11-03 03:54:30,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:30,280 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:54:30,281 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:54:30,282 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:54:30,300 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Waiting until timeout for monitored process [2022-11-03 03:54:31,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:31,042 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 03:54:31,047 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:32,662 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:32,662 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:54:44,933 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:44,933 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:54:44,933 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1161462597] [2022-11-03 03:54:44,934 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1161462597] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:54:44,934 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1607059490] [2022-11-03 03:54:44,934 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:54:44,934 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:54:44,934 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:54:44,935 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:54:44,945 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (19)] Waiting until timeout for monitored process [2022-11-03 03:54:46,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:54:46,378 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 03:54:46,383 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:54:47,406 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:54:47,406 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:55:40,647 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:55:40,648 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1607059490] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:55:40,648 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1941975489] [2022-11-03 03:55:40,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:55:40,648 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:55:40,649 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:55:40,650 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:55:40,654 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2022-11-03 03:55:41,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:55:41,231 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 52 conjunts are in the unsatisfiable core [2022-11-03 03:55:41,239 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:55:50,123 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:55:50,123 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:55:59,427 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:55:59,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1941975489] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:55:59,428 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:55:59,428 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 11, 11] total 37 [2022-11-03 03:55:59,433 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373117771] [2022-11-03 03:55:59,433 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:55:59,435 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-11-03 03:55:59,435 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:55:59,436 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-11-03 03:55:59,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=1130, Unknown=29, NotChecked=0, Total=1332 [2022-11-03 03:55:59,437 INFO L87 Difference]: Start difference. First operand 178 states and 243 transitions. Second operand has 37 states, 37 states have (on average 6.72972972972973) internal successors, (249), 37 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:15,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:56:15,457 INFO L93 Difference]: Finished difference Result 319 states and 434 transitions. [2022-11-03 03:56:15,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2022-11-03 03:56:15,458 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 37 states have (on average 6.72972972972973) internal successors, (249), 37 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:56:15,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:56:15,461 INFO L225 Difference]: With dead ends: 319 [2022-11-03 03:56:15,461 INFO L226 Difference]: Without dead ends: 317 [2022-11-03 03:56:15,463 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 339 GetRequests, 286 SyntacticMatches, 5 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 664 ImplicationChecksByTransitivity, 95.0s TimeCoverageRelationStatistics Valid=384, Invalid=2031, Unknown=35, NotChecked=0, Total=2450 [2022-11-03 03:56:15,463 INFO L413 NwaCegarLoop]: 96 mSDtfsCounter, 371 mSDsluCounter, 1483 mSDsCounter, 0 mSdLazyCounter, 9 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 371 SdHoareTripleChecker+Valid, 1579 SdHoareTripleChecker+Invalid, 92 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 9 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 82 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 03:56:15,464 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [371 Valid, 1579 Invalid, 92 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 9 Invalid, 0 Unknown, 82 Unchecked, 0.0s Time] [2022-11-03 03:56:15,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2022-11-03 03:56:15,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 258. [2022-11-03 03:56:15,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 258 states, 257 states have (on average 1.3813229571984436) internal successors, (355), 257 states have internal predecessors, (355), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:15,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 355 transitions. [2022-11-03 03:56:15,482 INFO L78 Accepts]: Start accepts. Automaton has 258 states and 355 transitions. Word has length 54 [2022-11-03 03:56:15,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:56:15,483 INFO L495 AbstractCegarLoop]: Abstraction has 258 states and 355 transitions. [2022-11-03 03:56:15,483 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 37 states have (on average 6.72972972972973) internal successors, (249), 37 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:15,483 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 355 transitions. [2022-11-03 03:56:15,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:56:15,485 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:56:15,485 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:56:15,497 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (19)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:15,728 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:15,918 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (18)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:16,098 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,20 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:56:16,098 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:56:16,099 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:56:16,099 INFO L85 PathProgramCache]: Analyzing trace with hash -1498515089, now seen corresponding path program 1 times [2022-11-03 03:56:16,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:56:16,101 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [425329641] [2022-11-03 03:56:16,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:56:16,101 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:56:16,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:56:16,103 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:56:16,107 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Waiting until timeout for monitored process [2022-11-03 03:56:16,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:56:16,807 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 03:56:16,813 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:56:17,189 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:17,189 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:56:17,683 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:17,684 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:56:17,684 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [425329641] [2022-11-03 03:56:17,684 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [425329641] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:56:17,684 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1656900094] [2022-11-03 03:56:17,684 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:56:17,684 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:56:17,684 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:56:17,686 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:56:17,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (22)] Waiting until timeout for monitored process [2022-11-03 03:56:19,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:56:19,085 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 03:56:19,089 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:56:19,356 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:19,357 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:56:19,635 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:19,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1656900094] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:56:19,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [813309463] [2022-11-03 03:56:19,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:56:19,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:56:19,636 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:56:19,637 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:56:19,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2022-11-03 03:56:20,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:56:20,258 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-03 03:56:20,264 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:56:20,606 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:20,606 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:56:20,886 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:20,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [813309463] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:56:20,887 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:56:20,887 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8, 8] total 14 [2022-11-03 03:56:20,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1163026698] [2022-11-03 03:56:20,890 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:56:20,891 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-03 03:56:20,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:56:20,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-03 03:56:20,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2022-11-03 03:56:20,892 INFO L87 Difference]: Start difference. First operand 258 states and 355 transitions. Second operand has 14 states, 14 states have (on average 7.142857142857143) internal successors, (100), 14 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:22,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:56:22,416 INFO L93 Difference]: Finished difference Result 849 states and 1191 transitions. [2022-11-03 03:56:22,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-11-03 03:56:22,417 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 7.142857142857143) internal successors, (100), 14 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:56:22,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:56:22,421 INFO L225 Difference]: With dead ends: 849 [2022-11-03 03:56:22,422 INFO L226 Difference]: Without dead ends: 796 [2022-11-03 03:56:22,423 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 338 GetRequests, 304 SyntacticMatches, 2 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 199 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=257, Invalid=865, Unknown=0, NotChecked=0, Total=1122 [2022-11-03 03:56:22,424 INFO L413 NwaCegarLoop]: 245 mSDtfsCounter, 767 mSDsluCounter, 1496 mSDsCounter, 0 mSdLazyCounter, 205 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 767 SdHoareTripleChecker+Valid, 1741 SdHoareTripleChecker+Invalid, 604 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 205 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 392 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-03 03:56:22,424 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [767 Valid, 1741 Invalid, 604 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 205 Invalid, 0 Unknown, 392 Unchecked, 0.8s Time] [2022-11-03 03:56:22,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 796 states. [2022-11-03 03:56:22,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 796 to 433. [2022-11-03 03:56:22,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 432 states have (on average 1.4097222222222223) internal successors, (609), 432 states have internal predecessors, (609), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:22,453 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 609 transitions. [2022-11-03 03:56:22,453 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 609 transitions. Word has length 54 [2022-11-03 03:56:22,453 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:56:22,454 INFO L495 AbstractCegarLoop]: Abstraction has 433 states and 609 transitions. [2022-11-03 03:56:22,454 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 7.142857142857143) internal successors, (100), 14 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:56:22,454 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 609 transitions. [2022-11-03 03:56:22,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:56:22,455 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:56:22,456 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:56:22,494 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (21)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:22,690 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (22)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:22,912 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Forceful destruction successful, exit code 0 [2022-11-03 03:56:23,082 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 21 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,22 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,23 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:56:23,082 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:56:23,083 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:56:23,083 INFO L85 PathProgramCache]: Analyzing trace with hash 2044363883, now seen corresponding path program 1 times [2022-11-03 03:56:23,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:56:23,084 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [366686648] [2022-11-03 03:56:23,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:56:23,085 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:56:23,085 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:56:23,086 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:56:23,087 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Waiting until timeout for monitored process [2022-11-03 03:56:23,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:56:23,815 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-03 03:56:23,820 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:56:25,197 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:25,198 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:56:36,019 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:36,019 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:56:36,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [366686648] [2022-11-03 03:56:36,020 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [366686648] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:56:36,020 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1804815731] [2022-11-03 03:56:36,020 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:56:36,020 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:56:36,021 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:56:36,022 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:56:36,046 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Waiting until timeout for monitored process [2022-11-03 03:56:37,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:56:37,380 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 58 conjunts are in the unsatisfiable core [2022-11-03 03:56:37,384 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:56:38,308 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:56:38,308 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:57:40,228 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:57:40,228 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [1804815731] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:57:40,228 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [634411858] [2022-11-03 03:57:40,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:57:40,229 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:57:40,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:57:40,230 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:57:40,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2022-11-03 03:57:40,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:57:40,863 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 68 conjunts are in the unsatisfiable core [2022-11-03 03:57:40,868 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:57:48,870 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:57:48,871 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:58:20,568 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:58:20,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [634411858] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 03:58:20,569 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 03:58:20,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 12, 12] total 40 [2022-11-03 03:58:20,570 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065689081] [2022-11-03 03:58:20,570 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 03:58:20,571 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 40 states [2022-11-03 03:58:20,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 03:58:20,571 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2022-11-03 03:58:20,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=214, Invalid=1307, Unknown=39, NotChecked=0, Total=1560 [2022-11-03 03:58:20,572 INFO L87 Difference]: Start difference. First operand 433 states and 609 transitions. Second operand has 40 states, 40 states have (on average 6.25) internal successors, (250), 40 states have internal predecessors, (250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:58:37,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 03:58:37,566 INFO L93 Difference]: Finished difference Result 513 states and 713 transitions. [2022-11-03 03:58:37,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-03 03:58:37,567 INFO L78 Accepts]: Start accepts. Automaton has has 40 states, 40 states have (on average 6.25) internal successors, (250), 40 states have internal predecessors, (250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 54 [2022-11-03 03:58:37,567 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 03:58:37,569 INFO L225 Difference]: With dead ends: 513 [2022-11-03 03:58:37,569 INFO L226 Difference]: Without dead ends: 511 [2022-11-03 03:58:37,571 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 336 GetRequests, 281 SyntacticMatches, 4 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 776 ImplicationChecksByTransitivity, 124.2s TimeCoverageRelationStatistics Valid=446, Invalid=2265, Unknown=45, NotChecked=0, Total=2756 [2022-11-03 03:58:37,571 INFO L413 NwaCegarLoop]: 65 mSDtfsCounter, 304 mSDsluCounter, 1567 mSDsCounter, 0 mSdLazyCounter, 9 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 304 SdHoareTripleChecker+Valid, 1632 SdHoareTripleChecker+Invalid, 206 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 9 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 197 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 03:58:37,572 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [304 Valid, 1632 Invalid, 206 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 9 Invalid, 0 Unknown, 197 Unchecked, 0.2s Time] [2022-11-03 03:58:37,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 511 states. [2022-11-03 03:58:37,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 511 to 484. [2022-11-03 03:58:37,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 484 states, 483 states have (on average 1.4078674948240166) internal successors, (680), 483 states have internal predecessors, (680), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:58:37,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 680 transitions. [2022-11-03 03:58:37,611 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 680 transitions. Word has length 54 [2022-11-03 03:58:37,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 03:58:37,611 INFO L495 AbstractCegarLoop]: Abstraction has 484 states and 680 transitions. [2022-11-03 03:58:37,612 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 40 states, 40 states have (on average 6.25) internal successors, (250), 40 states have internal predecessors, (250), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 03:58:37,612 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 680 transitions. [2022-11-03 03:58:37,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2022-11-03 03:58:37,613 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 03:58:37,613 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:58:37,630 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (25)] Forceful destruction successful, exit code 0 [2022-11-03 03:58:37,854 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Forceful destruction successful, exit code 0 [2022-11-03 03:58:38,043 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (24)] Forceful destruction successful, exit code 0 [2022-11-03 03:58:38,224 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 25 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,26 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true,24 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 03:58:38,225 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 03:58:38,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 03:58:38,225 INFO L85 PathProgramCache]: Analyzing trace with hash 456015981, now seen corresponding path program 1 times [2022-11-03 03:58:38,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 03:58:38,228 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1784326686] [2022-11-03 03:58:38,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:58:38,229 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 03:58:38,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 03:58:38,230 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 03:58:38,238 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Waiting until timeout for monitored process [2022-11-03 03:58:38,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:58:38,940 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 03:58:38,944 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:58:40,347 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 03:58:40,347 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 03:59:00,992 WARN L230 Executor]: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) stderr output: (error "out of memory") [2022-11-03 03:59:00,993 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 101 [2022-11-03 03:59:00,993 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 03:59:00,993 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1784326686] [2022-11-03 03:59:00,994 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_DEPENDING: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") [2022-11-03 03:59:00,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1241863811] [2022-11-03 03:59:00,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:59:00,994 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 03:59:00,995 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 03:59:00,996 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 03:59:01,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Waiting until timeout for monitored process [2022-11-03 03:59:02,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:59:02,688 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 62 conjunts are in the unsatisfiable core [2022-11-03 03:59:02,695 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:59:02,696 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_DEPENDING: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Connection to SMT solver broken [2022-11-03 03:59:02,697 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1698051588] [2022-11-03 03:59:02,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 03:59:02,697 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:59:02,697 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 03:59:02,698 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 03:59:02,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2022-11-03 03:59:03,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 03:59:03,381 INFO L263 TraceCheckSpWp]: Trace formula consists of 1332 conjuncts, 68 conjunts are in the unsatisfiable core [2022-11-03 03:59:03,387 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 03:59:03,390 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_DEPENDING: External (MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Connection to SMT solver broken [2022-11-03 03:59:03,390 INFO L184 FreeRefinementEngine]: Found 0 perfect and 0 imperfect interpolant sequences. [2022-11-03 03:59:03,390 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [] total 0 [2022-11-03 03:59:03,390 ERROR L170 FreeRefinementEngine]: Strategy WALRUS failed to provide any proof altough trace is infeasible [2022-11-03 03:59:03,390 INFO L359 BasicCegarLoop]: Counterexample might be feasible [2022-11-03 03:59:03,398 INFO L805 garLoopResultBuilder]: Registering result UNKNOWN for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 03:59:03,434 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (27)] Forceful destruction successful, exit code 0 [2022-11-03 03:59:03,631 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (28)] Forceful destruction successful, exit code 0 [2022-11-03 03:59:03,846 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Forceful destruction successful, exit code 0 [2022-11-03 03:59:04,014 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 27 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,28 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,29 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_07929458-98f7-46ec-83c8-1bf236a98467/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 03:59:04,018 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 03:59:04,022 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 03:59:04,066 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:59:04,067 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 03:59:04,125 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 03:59:04 BoogieIcfgContainer [2022-11-03 03:59:04,125 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 03:59:04,126 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 03:59:04,126 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 03:59:04,127 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 03:59:04,127 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 03:53:14" (3/4) ... [2022-11-03 03:59:04,131 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 03:59:04,131 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 03:59:04,132 INFO L158 Benchmark]: Toolchain (without parser) took 353353.62ms. Allocated memory was 69.2MB in the beginning and 706.7MB in the end (delta: 637.5MB). Free memory was 46.0MB in the beginning and 361.5MB in the end (delta: -315.5MB). Peak memory consumption was 320.0MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,133 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 69.2MB. Free memory is still 48.6MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 03:59:04,133 INFO L158 Benchmark]: CACSL2BoogieTranslator took 1054.24ms. Allocated memory was 69.2MB in the beginning and 102.8MB in the end (delta: 33.6MB). Free memory was 45.7MB in the beginning and 65.8MB in the end (delta: -20.1MB). Peak memory consumption was 16.3MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,136 INFO L158 Benchmark]: Boogie Procedure Inliner took 238.50ms. Allocated memory is still 102.8MB. Free memory was 65.8MB in the beginning and 55.4MB in the end (delta: 10.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,137 INFO L158 Benchmark]: Boogie Preprocessor took 108.23ms. Allocated memory is still 102.8MB. Free memory was 55.4MB in the beginning and 47.5MB in the end (delta: 7.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,137 INFO L158 Benchmark]: RCFGBuilder took 2674.05ms. Allocated memory was 102.8MB in the beginning and 151.0MB in the end (delta: 48.2MB). Free memory was 47.5MB in the beginning and 74.1MB in the end (delta: -26.6MB). Peak memory consumption was 44.8MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,138 INFO L158 Benchmark]: TraceAbstraction took 349265.84ms. Allocated memory was 151.0MB in the beginning and 706.7MB in the end (delta: 555.7MB). Free memory was 74.1MB in the beginning and 361.5MB in the end (delta: -287.4MB). Peak memory consumption was 267.3MB. Max. memory is 16.1GB. [2022-11-03 03:59:04,138 INFO L158 Benchmark]: Witness Printer took 5.47ms. Allocated memory is still 706.7MB. Free memory is still 361.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 03:59:04,140 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 69.2MB. Free memory is still 48.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 1054.24ms. Allocated memory was 69.2MB in the beginning and 102.8MB in the end (delta: 33.6MB). Free memory was 45.7MB in the beginning and 65.8MB in the end (delta: -20.1MB). Peak memory consumption was 16.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 238.50ms. Allocated memory is still 102.8MB. Free memory was 65.8MB in the beginning and 55.4MB in the end (delta: 10.4MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Preprocessor took 108.23ms. Allocated memory is still 102.8MB. Free memory was 55.4MB in the beginning and 47.5MB in the end (delta: 7.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * RCFGBuilder took 2674.05ms. Allocated memory was 102.8MB in the beginning and 151.0MB in the end (delta: 48.2MB). Free memory was 47.5MB in the beginning and 74.1MB in the end (delta: -26.6MB). Peak memory consumption was 44.8MB. Max. memory is 16.1GB. * TraceAbstraction took 349265.84ms. Allocated memory was 151.0MB in the beginning and 706.7MB in the end (delta: 555.7MB). Free memory was 74.1MB in the beginning and 361.5MB in the end (delta: -287.4MB). Peak memory consumption was 267.3MB. Max. memory is 16.1GB. * Witness Printer took 5.47ms. Allocated memory is still 706.7MB. Free memory is still 361.5MB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: unable to decide satisfiability of path constraint. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 5); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (5 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 16); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (16 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_3 var_5 = 0; [L38] const SORT_1 var_14 = 0; [L39] const SORT_4 var_57 = 5; [L40] const SORT_3 var_58 = 0; [L41] const SORT_4 var_60 = 16; [L42] const SORT_4 var_63 = 1; [L43] const SORT_4 var_64 = 0; [L44] const SORT_3 var_71 = 1; [L45] const SORT_3 var_74 = 0; [L46] const SORT_3 var_100 = 3; [L47] const SORT_4 var_209 = 6200; [L48] const SORT_4 var_225 = 999; [L49] const SORT_4 var_227 = 5999; [L50] const SORT_4 var_233 = 1000; [L51] const SORT_4 var_238 = 5800; [L53] SORT_1 input_70; [L54] SORT_1 input_72; [L55] SORT_1 input_73; [L56] SORT_1 input_75; [L57] SORT_1 input_81; [L58] SORT_1 input_82; [L59] SORT_1 input_83; [L60] SORT_1 input_88; [L61] SORT_1 input_99; [L62] SORT_1 input_101; [L63] SORT_1 input_104; [L64] SORT_1 input_111; [L65] SORT_1 input_116; [L66] SORT_1 input_120; [L67] SORT_1 input_133; [L68] SORT_1 input_143; [L69] SORT_1 input_147; [L70] SORT_1 input_152; [L71] SORT_1 input_154; [L72] SORT_1 input_158; [L73] SORT_1 input_162; [L74] SORT_1 input_166; [L75] SORT_1 input_175; [L76] SORT_1 input_182; [L77] SORT_1 input_184; [L78] SORT_1 input_190; [L80] SORT_3 state_6 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L81] SORT_3 state_8 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L82] SORT_3 state_10 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L83] SORT_3 state_12 = __VERIFIER_nondet_ushort() & mask_SORT_3; [L84] SORT_1 state_15 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L85] SORT_1 state_17 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L86] SORT_1 state_19 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L87] SORT_1 state_21 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L88] SORT_1 state_23 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] SORT_1 state_25 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] SORT_1 state_27 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] SORT_1 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L97] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L99] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L100] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L101] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L102] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L103] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L104] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L106] SORT_3 init_7_arg_1 = var_5; [L107] state_6 = init_7_arg_1 [L108] SORT_3 init_9_arg_1 = var_5; [L109] state_8 = init_9_arg_1 [L110] SORT_3 init_11_arg_1 = var_5; [L111] state_10 = init_11_arg_1 [L112] SORT_3 init_13_arg_1 = var_5; [L113] state_12 = init_13_arg_1 [L114] SORT_1 init_16_arg_1 = var_14; [L115] state_15 = init_16_arg_1 [L116] SORT_1 init_18_arg_1 = var_14; [L117] state_17 = init_18_arg_1 [L118] SORT_1 init_20_arg_1 = var_14; [L119] state_19 = init_20_arg_1 [L120] SORT_1 init_22_arg_1 = var_14; [L121] state_21 = init_22_arg_1 [L122] SORT_1 init_24_arg_1 = var_14; [L123] state_23 = init_24_arg_1 [L124] SORT_1 init_26_arg_1 = var_14; [L125] state_25 = init_26_arg_1 [L126] SORT_1 init_28_arg_1 = var_14; [L127] state_27 = init_28_arg_1 [L128] SORT_1 init_30_arg_1 = var_14; [L129] state_29 = init_30_arg_1 [L130] SORT_1 init_32_arg_1 = var_14; [L131] state_31 = init_32_arg_1 [L132] SORT_1 init_34_arg_1 = var_14; [L133] state_33 = init_34_arg_1 [L134] SORT_1 init_36_arg_1 = var_14; [L135] state_35 = init_36_arg_1 [L136] SORT_1 init_38_arg_1 = var_14; [L137] state_37 = init_38_arg_1 [L138] SORT_1 init_40_arg_1 = var_14; [L139] state_39 = init_40_arg_1 [L140] SORT_1 init_42_arg_1 = var_14; [L141] state_41 = init_42_arg_1 [L142] SORT_1 init_44_arg_1 = var_14; [L143] state_43 = init_44_arg_1 [L144] SORT_1 init_46_arg_1 = var_14; [L145] state_45 = init_46_arg_1 [L146] SORT_1 init_48_arg_1 = var_14; [L147] state_47 = init_48_arg_1 [L148] SORT_1 init_50_arg_1 = var_14; [L149] state_49 = init_50_arg_1 [L150] SORT_1 init_52_arg_1 = var_14; [L151] state_51 = init_52_arg_1 [L152] SORT_1 init_54_arg_1 = var_14; [L153] state_53 = init_54_arg_1 [L154] SORT_1 init_56_arg_1 = var_14; [L155] state_55 = init_56_arg_1 [L158] input_70 = __VERIFIER_nondet_uchar() [L159] input_70 = input_70 & mask_SORT_1 [L160] input_72 = __VERIFIER_nondet_uchar() [L161] input_72 = input_72 & mask_SORT_1 [L162] input_73 = __VERIFIER_nondet_uchar() [L163] input_73 = input_73 & mask_SORT_1 [L164] input_75 = __VERIFIER_nondet_uchar() [L165] input_75 = input_75 & mask_SORT_1 [L166] input_81 = __VERIFIER_nondet_uchar() [L167] input_81 = input_81 & mask_SORT_1 [L168] input_82 = __VERIFIER_nondet_uchar() [L169] input_82 = input_82 & mask_SORT_1 [L170] input_83 = __VERIFIER_nondet_uchar() [L171] input_83 = input_83 & mask_SORT_1 [L172] input_88 = __VERIFIER_nondet_uchar() [L173] input_88 = input_88 & mask_SORT_1 [L174] input_99 = __VERIFIER_nondet_uchar() [L175] input_99 = input_99 & mask_SORT_1 [L176] input_101 = __VERIFIER_nondet_uchar() [L177] input_101 = input_101 & mask_SORT_1 [L178] input_104 = __VERIFIER_nondet_uchar() [L179] input_104 = input_104 & mask_SORT_1 [L180] input_111 = __VERIFIER_nondet_uchar() [L181] input_116 = __VERIFIER_nondet_uchar() [L182] input_120 = __VERIFIER_nondet_uchar() [L183] input_133 = __VERIFIER_nondet_uchar() [L184] input_143 = __VERIFIER_nondet_uchar() [L185] input_147 = __VERIFIER_nondet_uchar() [L186] input_152 = __VERIFIER_nondet_uchar() [L187] input_154 = __VERIFIER_nondet_uchar() [L188] input_158 = __VERIFIER_nondet_uchar() [L189] input_162 = __VERIFIER_nondet_uchar() [L190] input_166 = __VERIFIER_nondet_uchar() [L191] input_175 = __VERIFIER_nondet_uchar() [L192] input_182 = __VERIFIER_nondet_uchar() [L193] input_184 = __VERIFIER_nondet_uchar() [L194] input_190 = __VERIFIER_nondet_uchar() [L197] SORT_3 var_59_arg_0 = state_12; [L198] SORT_3 var_59_arg_1 = var_58; [L199] SORT_4 var_59 = ((SORT_4)var_59_arg_0 << 16) | var_59_arg_1; [L200] SORT_4 var_61_arg_0 = var_59; [L201] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L201] var_61_arg_0 = (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L202] SORT_4 var_61_arg_1 = var_60; [L203] SORT_4 var_61 = (int)var_61_arg_0 >> var_61_arg_1; [L204] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L204] var_61 = (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L205] var_61 = var_61 & mask_SORT_4 [L206] SORT_4 var_62_arg_0 = var_57; [L207] SORT_4 var_62_arg_1 = var_61; [L208] SORT_1 var_62 = var_62_arg_0 == var_62_arg_1; [L209] SORT_1 var_65_arg_0 = state_35; [L210] SORT_4 var_65_arg_1 = var_63; [L211] SORT_4 var_65_arg_2 = var_64; [L212] EXPR var_65_arg_0 ? var_65_arg_1 : var_65_arg_2 [L212] SORT_4 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L213] var_65 = var_65 & mask_SORT_4 [L214] SORT_4 var_66_arg_0 = var_63; [L215] SORT_4 var_66_arg_1 = var_65; [L216] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L217] SORT_1 var_67_arg_0 = ~var_62; [L218] var_67_arg_0 = var_67_arg_0 & mask_SORT_1 [L219] SORT_1 var_67_arg_1 = var_66; [L220] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L221] SORT_1 var_68_arg_0 = ~state_55; [L222] var_68_arg_0 = var_68_arg_0 & mask_SORT_1 [L223] SORT_1 var_68_arg_1 = var_67; [L224] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L225] var_68 = var_68 & mask_SORT_1 [L226] SORT_1 bad_69_arg_0 = var_68; [L227] CALL __VERIFIER_assert(!(bad_69_arg_0)) [L20] COND FALSE !(!(cond)) [L227] RET __VERIFIER_assert(!(bad_69_arg_0)) [L229] SORT_1 var_76_arg_0 = input_75; [L230] SORT_3 var_76_arg_1 = var_71; [L231] SORT_3 var_76_arg_2 = state_6; [L232] EXPR var_76_arg_0 ? var_76_arg_1 : var_76_arg_2 [L232] SORT_3 var_76 = var_76_arg_0 ? var_76_arg_1 : var_76_arg_2; [L233] SORT_1 var_77_arg_0 = input_73; [L234] SORT_3 var_77_arg_1 = var_74; [L235] SORT_3 var_77_arg_2 = var_76; [L236] EXPR var_77_arg_0 ? var_77_arg_1 : var_77_arg_2 [L236] SORT_3 var_77 = var_77_arg_0 ? var_77_arg_1 : var_77_arg_2; [L237] SORT_1 var_78_arg_0 = input_72; [L238] SORT_3 var_78_arg_1 = var_71; [L239] SORT_3 var_78_arg_2 = var_77; [L240] EXPR var_78_arg_0 ? var_78_arg_1 : var_78_arg_2 [L240] SORT_3 var_78 = var_78_arg_0 ? var_78_arg_1 : var_78_arg_2; [L241] SORT_1 var_79_arg_0 = input_70; [L242] SORT_3 var_79_arg_1 = var_71; [L243] SORT_3 var_79_arg_2 = var_78; [L244] EXPR var_79_arg_0 ? var_79_arg_1 : var_79_arg_2 [L244] SORT_3 var_79 = var_79_arg_0 ? var_79_arg_1 : var_79_arg_2; [L245] SORT_3 next_80_arg_1 = var_79; [L246] SORT_3 var_84_arg_0 = state_8; [L247] SORT_3 var_84_arg_1 = var_58; [L248] SORT_4 var_84 = ((SORT_4)var_84_arg_0 << 16) | var_84_arg_1; [L249] SORT_4 var_85_arg_0 = var_84; [L250] EXPR (var_85_arg_0 & msb_SORT_4) ? (var_85_arg_0 | ~mask_SORT_4) : (var_85_arg_0 & mask_SORT_4) [L250] var_85_arg_0 = (var_85_arg_0 & msb_SORT_4) ? (var_85_arg_0 | ~mask_SORT_4) : (var_85_arg_0 & mask_SORT_4) [L251] SORT_4 var_85_arg_1 = var_60; [L252] SORT_4 var_85 = (int)var_85_arg_0 >> var_85_arg_1; [L253] EXPR (var_85_arg_0 & msb_SORT_4) ? (var_85 | ~(mask_SORT_4 >> var_85_arg_1)) : var_85 [L253] var_85 = (var_85_arg_0 & msb_SORT_4) ? (var_85 | ~(mask_SORT_4 >> var_85_arg_1)) : var_85 [L254] var_85 = var_85 & mask_SORT_4 [L255] SORT_4 var_86_arg_0 = var_85; [L256] SORT_4 var_86_arg_1 = var_63; [L257] SORT_4 var_86 = var_86_arg_0 - var_86_arg_1; [L258] SORT_4 var_87_arg_0 = var_86; [L259] SORT_3 var_87 = var_87_arg_0 >> 0; [L260] SORT_4 var_89_arg_0 = var_63; [L261] SORT_4 var_89_arg_1 = var_85; [L262] SORT_4 var_89 = var_89_arg_0 + var_89_arg_1; [L263] SORT_4 var_90_arg_0 = var_89; [L264] SORT_3 var_90 = var_90_arg_0 >> 0; [L265] SORT_1 var_91_arg_0 = input_88; [L266] SORT_3 var_91_arg_1 = var_90; [L267] SORT_3 var_91_arg_2 = state_8; [L268] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 [L268] SORT_3 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L269] SORT_1 var_92_arg_0 = input_75; [L270] SORT_3 var_92_arg_1 = var_87; [L271] SORT_3 var_92_arg_2 = var_91; [L272] EXPR var_92_arg_0 ? var_92_arg_1 : var_92_arg_2 [L272] SORT_3 var_92 = var_92_arg_0 ? var_92_arg_1 : var_92_arg_2; [L273] SORT_1 var_93_arg_0 = input_73; [L274] SORT_3 var_93_arg_1 = var_87; [L275] SORT_3 var_93_arg_2 = var_92; [L276] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 [L276] SORT_3 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L277] SORT_1 var_94_arg_0 = input_83; [L278] SORT_3 var_94_arg_1 = var_74; [L279] SORT_3 var_94_arg_2 = var_93; [L280] EXPR var_94_arg_0 ? var_94_arg_1 : var_94_arg_2 [L280] SORT_3 var_94 = var_94_arg_0 ? var_94_arg_1 : var_94_arg_2; [L281] SORT_1 var_95_arg_0 = input_82; [L282] SORT_3 var_95_arg_1 = var_74; [L283] SORT_3 var_95_arg_2 = var_94; [L284] EXPR var_95_arg_0 ? var_95_arg_1 : var_95_arg_2 [L284] SORT_3 var_95 = var_95_arg_0 ? var_95_arg_1 : var_95_arg_2; [L285] SORT_1 var_96_arg_0 = input_81; [L286] SORT_3 var_96_arg_1 = var_74; [L287] SORT_3 var_96_arg_2 = var_95; [L288] EXPR var_96_arg_0 ? var_96_arg_1 : var_96_arg_2 [L288] SORT_3 var_96 = var_96_arg_0 ? var_96_arg_1 : var_96_arg_2; [L289] SORT_3 next_97_arg_1 = var_96; [L290] SORT_3 next_98_arg_1 = state_10; [L291] SORT_4 var_102_arg_0 = var_63; [L292] SORT_4 var_102_arg_1 = var_61; [L293] SORT_4 var_102 = var_102_arg_0 + var_102_arg_1; [L294] SORT_4 var_103_arg_0 = var_102; [L295] SORT_3 var_103 = var_103_arg_0 >> 0; [L296] SORT_4 var_105_arg_0 = var_61; [L297] SORT_4 var_105_arg_1 = var_63; [L298] SORT_4 var_105 = var_105_arg_0 - var_105_arg_1; [L299] SORT_4 var_106_arg_0 = var_105; [L300] SORT_3 var_106 = var_106_arg_0 >> 0; [L301] SORT_1 var_107_arg_0 = input_104; [L302] SORT_3 var_107_arg_1 = var_106; [L303] SORT_3 var_107_arg_2 = state_12; [L304] EXPR var_107_arg_0 ? var_107_arg_1 : var_107_arg_2 [L304] SORT_3 var_107 = var_107_arg_0 ? var_107_arg_1 : var_107_arg_2; [L305] SORT_1 var_108_arg_0 = input_101; [L306] SORT_3 var_108_arg_1 = var_103; [L307] SORT_3 var_108_arg_2 = var_107; [L308] EXPR var_108_arg_0 ? var_108_arg_1 : var_108_arg_2 [L308] SORT_3 var_108 = var_108_arg_0 ? var_108_arg_1 : var_108_arg_2; [L309] SORT_1 var_109_arg_0 = input_99; [L310] SORT_3 var_109_arg_1 = var_100; [L311] SORT_3 var_109_arg_2 = var_108; [L312] EXPR var_109_arg_0 ? var_109_arg_1 : var_109_arg_2 [L312] SORT_3 var_109 = var_109_arg_0 ? var_109_arg_1 : var_109_arg_2; [L313] SORT_3 next_110_arg_1 = var_109; [L314] SORT_1 var_112_arg_0 = state_15; [L315] SORT_1 var_112_arg_1 = input_111; [L316] SORT_1 var_112 = var_112_arg_0 | var_112_arg_1; [L317] SORT_1 var_113_arg_0 = var_112; [L318] SORT_1 var_113_arg_1 = input_75; [L319] SORT_1 var_113 = var_113_arg_0 | var_113_arg_1; [L320] SORT_1 var_114_arg_0 = var_113; [L321] SORT_1 var_114_arg_1 = ~input_73; [L322] var_114_arg_1 = var_114_arg_1 & mask_SORT_1 [L323] SORT_1 var_114 = var_114_arg_0 & var_114_arg_1; [L324] SORT_1 var_115_arg_0 = var_114; [L325] SORT_1 var_115_arg_1 = input_72; [L326] SORT_1 var_115 = var_115_arg_0 | var_115_arg_1; [L327] SORT_1 var_117_arg_0 = var_115; [L328] SORT_1 var_117_arg_1 = ~input_116; [L329] var_117_arg_1 = var_117_arg_1 & mask_SORT_1 [L330] SORT_1 var_117 = var_117_arg_0 & var_117_arg_1; [L331] SORT_1 next_118_arg_1 = var_117; [L332] SORT_1 var_119_arg_0 = state_17; [L333] SORT_1 var_119_arg_1 = ~input_111; [L334] var_119_arg_1 = var_119_arg_1 & mask_SORT_1 [L335] SORT_1 var_119 = var_119_arg_0 & var_119_arg_1; [L336] SORT_1 var_121_arg_0 = var_119; [L337] SORT_1 var_121_arg_1 = ~input_120; [L338] var_121_arg_1 = var_121_arg_1 & mask_SORT_1 [L339] SORT_1 var_121 = var_121_arg_0 & var_121_arg_1; [L340] SORT_1 var_122_arg_0 = var_121; [L341] SORT_1 var_122_arg_1 = input_116; [L342] SORT_1 var_122 = var_122_arg_0 | var_122_arg_1; [L343] SORT_1 next_123_arg_1 = var_122; [L344] SORT_1 var_124_arg_0 = state_19; [L345] SORT_1 var_124_arg_1 = ~input_75; [L346] var_124_arg_1 = var_124_arg_1 & mask_SORT_1 [L347] SORT_1 var_124 = var_124_arg_0 & var_124_arg_1; [L348] SORT_1 var_125_arg_0 = var_124; [L349] SORT_1 var_125_arg_1 = input_73; [L350] SORT_1 var_125 = var_125_arg_0 | var_125_arg_1; [L351] SORT_1 var_126_arg_0 = var_125; [L352] SORT_1 var_126_arg_1 = input_120; [L353] SORT_1 var_126 = var_126_arg_0 | var_126_arg_1; [L354] SORT_1 next_127_arg_1 = var_126; [L355] SORT_1 var_128_arg_0 = ~state_21; [L356] var_128_arg_0 = var_128_arg_0 & mask_SORT_1 [L357] SORT_1 var_128_arg_1 = ~input_72; [L358] var_128_arg_1 = var_128_arg_1 & mask_SORT_1 [L359] SORT_1 var_128 = var_128_arg_0 & var_128_arg_1; [L360] SORT_1 next_129_arg_1 = ~var_128; [L361] next_129_arg_1 = next_129_arg_1 & mask_SORT_1 [L362] SORT_1 var_130_arg_0 = state_23; [L363] SORT_1 var_130_arg_1 = ~input_83; [L364] var_130_arg_1 = var_130_arg_1 & mask_SORT_1 [L365] SORT_1 var_130 = var_130_arg_0 & var_130_arg_1; [L366] SORT_1 var_131_arg_0 = var_130; [L367] SORT_1 var_131_arg_1 = ~input_82; [L368] var_131_arg_1 = var_131_arg_1 & mask_SORT_1 [L369] SORT_1 var_131 = var_131_arg_0 & var_131_arg_1; [L370] SORT_1 var_132_arg_0 = var_131; [L371] SORT_1 var_132_arg_1 = ~input_81; [L372] var_132_arg_1 = var_132_arg_1 & mask_SORT_1 [L373] SORT_1 var_132 = var_132_arg_0 & var_132_arg_1; [L374] SORT_1 var_134_arg_0 = var_132; [L375] SORT_1 var_134_arg_1 = input_133; [L376] SORT_1 var_134 = var_134_arg_0 | var_134_arg_1; [L377] SORT_1 next_135_arg_1 = var_134; [L378] SORT_1 var_136_arg_0 = state_25; [L379] SORT_1 var_136_arg_1 = input_104; [L380] SORT_1 var_136 = var_136_arg_0 | var_136_arg_1; [L381] SORT_1 var_137_arg_0 = var_136; [L382] SORT_1 var_137_arg_1 = input_101; [L383] SORT_1 var_137 = var_137_arg_0 | var_137_arg_1; [L384] SORT_1 var_138_arg_0 = var_137; [L385] SORT_1 var_138_arg_1 = input_99; [L386] SORT_1 var_138 = var_138_arg_0 | var_138_arg_1; [L387] SORT_1 var_139_arg_0 = var_138; [L388] SORT_1 var_139_arg_1 = ~input_116; [L389] var_139_arg_1 = var_139_arg_1 & mask_SORT_1 [L390] SORT_1 var_139 = var_139_arg_0 & var_139_arg_1; [L391] SORT_1 next_140_arg_1 = var_139; [L392] SORT_1 var_141_arg_0 = state_27; [L393] SORT_1 var_141_arg_1 = input_82; [L394] SORT_1 var_141 = var_141_arg_0 | var_141_arg_1; [L395] SORT_1 var_142_arg_0 = var_141; [L396] SORT_1 var_142_arg_1 = ~input_104; [L397] var_142_arg_1 = var_142_arg_1 & mask_SORT_1 [L398] SORT_1 var_142 = var_142_arg_0 & var_142_arg_1; [L399] SORT_1 var_144_arg_0 = var_142; [L400] SORT_1 var_144_arg_1 = ~input_143; [L401] var_144_arg_1 = var_144_arg_1 & mask_SORT_1 [L402] SORT_1 var_144 = var_144_arg_0 & var_144_arg_1; [L403] SORT_1 next_145_arg_1 = var_144; [L404] SORT_1 var_146_arg_0 = state_29; [L405] SORT_1 var_146_arg_1 = input_83; [L406] SORT_1 var_146 = var_146_arg_0 | var_146_arg_1; [L407] SORT_1 var_148_arg_0 = var_146; [L408] SORT_1 var_148_arg_1 = ~input_147; [L409] var_148_arg_1 = var_148_arg_1 & mask_SORT_1 [L410] SORT_1 var_148 = var_148_arg_0 & var_148_arg_1; [L411] SORT_1 next_149_arg_1 = var_148; [L412] SORT_1 var_150_arg_0 = state_31; [L413] SORT_1 var_150_arg_1 = input_81; [L414] SORT_1 var_150 = var_150_arg_0 | var_150_arg_1; [L415] SORT_1 var_151_arg_0 = var_150; [L416] SORT_1 var_151_arg_1 = ~input_101; [L417] var_151_arg_1 = var_151_arg_1 & mask_SORT_1 [L418] SORT_1 var_151 = var_151_arg_0 & var_151_arg_1; [L419] SORT_1 var_153_arg_0 = var_151; [L420] SORT_1 var_153_arg_1 = ~input_152; [L421] var_153_arg_1 = var_153_arg_1 & mask_SORT_1 [L422] SORT_1 var_153 = var_153_arg_0 & var_153_arg_1; [L423] SORT_1 var_155_arg_0 = var_153; [L424] SORT_1 var_155_arg_1 = input_154; [L425] SORT_1 var_155 = var_155_arg_0 | var_155_arg_1; [L426] SORT_1 next_156_arg_1 = var_155; [L427] SORT_1 var_157_arg_0 = state_33; [L428] SORT_1 var_157_arg_1 = input_143; [L429] SORT_1 var_157 = var_157_arg_0 | var_157_arg_1; [L430] SORT_1 var_159_arg_0 = var_157; [L431] SORT_1 var_159_arg_1 = ~input_158; [L432] var_159_arg_1 = var_159_arg_1 & mask_SORT_1 [L433] SORT_1 var_159 = var_159_arg_0 & var_159_arg_1; [L434] SORT_1 next_160_arg_1 = var_159; [L435] SORT_1 var_161_arg_0 = state_35; [L436] SORT_1 var_161_arg_1 = input_152; [L437] SORT_1 var_161 = var_161_arg_0 | var_161_arg_1; [L438] SORT_1 var_163_arg_0 = var_161; [L439] SORT_1 var_163_arg_1 = ~input_162; [L440] var_163_arg_1 = var_163_arg_1 & mask_SORT_1 [L441] SORT_1 var_163 = var_163_arg_0 & var_163_arg_1; [L442] var_163 = var_163 & mask_SORT_1 [L443] SORT_1 next_164_arg_1 = var_163; [L444] SORT_1 var_165_arg_0 = ~state_37; [L445] var_165_arg_0 = var_165_arg_0 & mask_SORT_1 [L446] SORT_1 var_165_arg_1 = ~input_99; [L447] var_165_arg_1 = var_165_arg_1 & mask_SORT_1 [L448] SORT_1 var_165 = var_165_arg_0 & var_165_arg_1; [L449] SORT_1 var_167_arg_0 = var_165; [L450] SORT_1 var_167_arg_1 = input_166; [L451] SORT_1 var_167 = var_167_arg_0 | var_167_arg_1; [L452] SORT_1 next_168_arg_1 = ~var_167; [L453] next_168_arg_1 = next_168_arg_1 & mask_SORT_1 [L454] SORT_1 var_169_arg_0 = state_39; [L455] SORT_1 var_169_arg_1 = input_158; [L456] SORT_1 var_169 = var_169_arg_0 | var_169_arg_1; [L457] SORT_1 var_170_arg_0 = var_169; [L458] SORT_1 var_170_arg_1 = input_162; [L459] SORT_1 var_170 = var_170_arg_0 | var_170_arg_1; [L460] SORT_1 var_171_arg_0 = var_170; [L461] SORT_1 var_171_arg_1 = input_147; [L462] SORT_1 var_171 = var_171_arg_0 | var_171_arg_1; [L463] SORT_1 var_172_arg_0 = var_171; [L464] SORT_1 var_172_arg_1 = ~input_166; [L465] var_172_arg_1 = var_172_arg_1 & mask_SORT_1 [L466] SORT_1 var_172 = var_172_arg_0 & var_172_arg_1; [L467] SORT_1 next_173_arg_1 = var_172; [L468] SORT_1 var_174_arg_0 = state_41; [L469] SORT_1 var_174_arg_1 = input_116; [L470] SORT_1 var_174 = var_174_arg_0 | var_174_arg_1; [L471] SORT_1 var_176_arg_0 = var_174; [L472] SORT_1 var_176_arg_1 = ~input_175; [L473] var_176_arg_1 = var_176_arg_1 & mask_SORT_1 [L474] SORT_1 var_176 = var_176_arg_0 & var_176_arg_1; [L475] SORT_1 next_177_arg_1 = var_176; [L476] SORT_1 var_178_arg_0 = state_43; [L477] SORT_1 var_178_arg_1 = input_175; [L478] SORT_1 var_178 = var_178_arg_0 | var_178_arg_1; [L479] SORT_1 var_179_arg_0 = var_178; [L480] SORT_1 var_179_arg_1 = ~input_133; [L481] var_179_arg_1 = var_179_arg_1 & mask_SORT_1 [L482] SORT_1 var_179 = var_179_arg_0 & var_179_arg_1; [L483] SORT_1 var_180_arg_0 = var_179; [L484] SORT_1 var_180_arg_1 = ~input_154; [L485] var_180_arg_1 = var_180_arg_1 & mask_SORT_1 [L486] SORT_1 var_180 = var_180_arg_0 & var_180_arg_1; [L487] SORT_1 next_181_arg_1 = var_180; [L488] SORT_1 var_183_arg_0 = state_45; [L489] SORT_1 var_183_arg_1 = ~input_182; [L490] var_183_arg_1 = var_183_arg_1 & mask_SORT_1 [L491] SORT_1 var_183 = var_183_arg_0 & var_183_arg_1; [L492] SORT_1 var_185_arg_0 = var_183; [L493] SORT_1 var_185_arg_1 = ~input_184; [L494] var_185_arg_1 = var_185_arg_1 & mask_SORT_1 [L495] SORT_1 var_185 = var_185_arg_0 & var_185_arg_1; [L496] SORT_1 var_186_arg_0 = var_185; [L497] SORT_1 var_186_arg_1 = input_175; [L498] SORT_1 var_186 = var_186_arg_0 | var_186_arg_1; [L499] SORT_1 next_187_arg_1 = var_186; [L500] SORT_1 var_188_arg_0 = state_47; [L501] SORT_1 var_188_arg_1 = input_182; [L502] SORT_1 var_188 = var_188_arg_0 | var_188_arg_1; [L503] SORT_1 var_189_arg_0 = var_188; [L504] SORT_1 var_189_arg_1 = ~input_70; [L505] var_189_arg_1 = var_189_arg_1 & mask_SORT_1 [L506] SORT_1 var_189 = var_189_arg_0 & var_189_arg_1; [L507] SORT_1 var_191_arg_0 = var_189; [L508] SORT_1 var_191_arg_1 = ~input_190; [L509] var_191_arg_1 = var_191_arg_1 & mask_SORT_1 [L510] SORT_1 var_191 = var_191_arg_0 & var_191_arg_1; [L511] SORT_1 next_192_arg_1 = var_191; [L512] SORT_1 var_193_arg_0 = state_49; [L513] SORT_1 var_193_arg_1 = input_184; [L514] SORT_1 var_193 = var_193_arg_0 | var_193_arg_1; [L515] SORT_1 var_194_arg_0 = var_193; [L516] SORT_1 var_194_arg_1 = input_190; [L517] SORT_1 var_194 = var_194_arg_0 | var_194_arg_1; [L518] SORT_1 var_195_arg_0 = var_194; [L519] SORT_1 var_195_arg_1 = ~input_154; [L520] var_195_arg_1 = var_195_arg_1 & mask_SORT_1 [L521] SORT_1 var_195 = var_195_arg_0 & var_195_arg_1; [L522] SORT_1 next_196_arg_1 = var_195; [L523] SORT_1 var_197_arg_0 = ~state_51; [L524] var_197_arg_0 = var_197_arg_0 & mask_SORT_1 [L525] SORT_1 var_197_arg_1 = ~input_175; [L526] var_197_arg_1 = var_197_arg_1 & mask_SORT_1 [L527] SORT_1 var_197 = var_197_arg_0 & var_197_arg_1; [L528] SORT_1 var_198_arg_0 = var_197; [L529] SORT_1 var_198_arg_1 = input_133; [L530] SORT_1 var_198 = var_198_arg_0 | var_198_arg_1; [L531] SORT_1 var_199_arg_0 = var_198; [L532] SORT_1 var_199_arg_1 = input_154; [L533] SORT_1 var_199 = var_199_arg_0 | var_199_arg_1; [L534] SORT_1 next_200_arg_1 = ~var_199; [L535] next_200_arg_1 = next_200_arg_1 & mask_SORT_1 [L536] SORT_1 var_201_arg_0 = state_53; [L537] SORT_1 var_201_arg_1 = input_70; [L538] SORT_1 var_201 = var_201_arg_0 | var_201_arg_1; [L539] SORT_1 var_202_arg_0 = var_201; [L540] SORT_1 var_202_arg_1 = ~input_133; [L541] var_202_arg_1 = var_202_arg_1 & mask_SORT_1 [L542] SORT_1 var_202 = var_202_arg_0 & var_202_arg_1; [L543] SORT_1 next_203_arg_1 = var_202; [L544] SORT_3 var_204_arg_0 = state_6; [L545] SORT_3 var_204_arg_1 = var_58; [L546] SORT_4 var_204 = ((SORT_4)var_204_arg_0 << 16) | var_204_arg_1; [L547] SORT_4 var_205_arg_0 = var_204; [L548] EXPR (var_205_arg_0 & msb_SORT_4) ? (var_205_arg_0 | ~mask_SORT_4) : (var_205_arg_0 & mask_SORT_4) [L548] var_205_arg_0 = (var_205_arg_0 & msb_SORT_4) ? (var_205_arg_0 | ~mask_SORT_4) : (var_205_arg_0 & mask_SORT_4) [L549] SORT_4 var_205_arg_1 = var_60; [L550] SORT_4 var_205 = (int)var_205_arg_0 >> var_205_arg_1; [L551] EXPR (var_205_arg_0 & msb_SORT_4) ? (var_205 | ~(mask_SORT_4 >> var_205_arg_1)) : var_205 [L551] var_205 = (var_205_arg_0 & msb_SORT_4) ? (var_205 | ~(mask_SORT_4 >> var_205_arg_1)) : var_205 [L552] var_205 = var_205 & mask_SORT_4 [L553] SORT_4 var_206_arg_0 = var_63; [L554] SORT_4 var_206_arg_1 = var_205; [L555] SORT_1 var_206 = var_206_arg_0 == var_206_arg_1; [L556] SORT_1 var_207_arg_0 = state_17; [L557] SORT_1 var_207_arg_1 = var_206; [L558] SORT_1 var_207 = var_207_arg_0 & var_207_arg_1; [L559] SORT_1 var_208_arg_0 = ~input_111; [L560] var_208_arg_0 = var_208_arg_0 & mask_SORT_1 [L561] SORT_1 var_208_arg_1 = var_207; [L562] SORT_1 var_208 = var_208_arg_0 | var_208_arg_1; [L563] SORT_4 var_210_arg_0 = var_209; [L564] SORT_4 var_210_arg_1 = var_85; [L565] SORT_1 var_210 = var_210_arg_0 <= var_210_arg_1; [L566] SORT_1 var_211_arg_0 = var_206; [L567] SORT_1 var_211_arg_1 = ~var_210; [L568] var_211_arg_1 = var_211_arg_1 & mask_SORT_1 [L569] SORT_1 var_211 = var_211_arg_0 & var_211_arg_1; [L570] SORT_1 var_212_arg_0 = state_15; [L571] SORT_1 var_212_arg_1 = var_211; [L572] SORT_1 var_212 = var_212_arg_0 & var_212_arg_1; [L573] SORT_1 var_213_arg_0 = ~input_88; [L574] var_213_arg_0 = var_213_arg_0 & mask_SORT_1 [L575] SORT_1 var_213_arg_1 = var_212; [L576] SORT_1 var_213 = var_213_arg_0 | var_213_arg_1; [L577] SORT_1 var_214_arg_0 = var_208; [L578] SORT_1 var_214_arg_1 = var_213; [L579] SORT_1 var_214 = var_214_arg_0 & var_214_arg_1; [L580] SORT_1 var_215_arg_0 = state_19; [L581] SORT_1 var_215_arg_1 = ~input_75; [L582] var_215_arg_1 = var_215_arg_1 & mask_SORT_1 [L583] SORT_1 var_215 = var_215_arg_0 | var_215_arg_1; [L584] SORT_1 var_216_arg_0 = var_214; [L585] SORT_1 var_216_arg_1 = var_215; [L586] SORT_1 var_216 = var_216_arg_0 & var_216_arg_1; [L587] SORT_1 var_217_arg_0 = state_15; [L588] SORT_1 var_217_arg_1 = ~input_73; [L589] var_217_arg_1 = var_217_arg_1 & mask_SORT_1 [L590] SORT_1 var_217 = var_217_arg_0 | var_217_arg_1; [L591] SORT_1 var_218_arg_0 = var_216; [L592] SORT_1 var_218_arg_1 = var_217; [L593] SORT_1 var_218 = var_218_arg_0 & var_218_arg_1; [L594] SORT_4 var_219_arg_0 = var_64; [L595] SORT_4 var_219_arg_1 = var_205; [L596] SORT_1 var_219 = var_219_arg_0 == var_219_arg_1; [L597] SORT_1 var_220_arg_0 = state_17; [L598] SORT_1 var_220_arg_1 = var_219; [L599] SORT_1 var_220 = var_220_arg_0 & var_220_arg_1; [L600] SORT_1 var_221_arg_0 = ~input_120; [L601] var_221_arg_0 = var_221_arg_0 & mask_SORT_1 [L602] SORT_1 var_221_arg_1 = var_220; [L603] SORT_1 var_221 = var_221_arg_0 | var_221_arg_1; [L604] SORT_1 var_222_arg_0 = var_218; [L605] SORT_1 var_222_arg_1 = var_221; [L606] SORT_1 var_222 = var_222_arg_0 & var_222_arg_1; [L607] SORT_1 var_223_arg_0 = ~state_21; [L608] var_223_arg_0 = var_223_arg_0 & mask_SORT_1 [L609] SORT_1 var_223_arg_1 = ~input_72; [L610] var_223_arg_1 = var_223_arg_1 & mask_SORT_1 [L611] SORT_1 var_223 = var_223_arg_0 | var_223_arg_1; [L612] SORT_1 var_224_arg_0 = var_222; [L613] SORT_1 var_224_arg_1 = var_223; [L614] SORT_1 var_224 = var_224_arg_0 & var_224_arg_1; [L615] SORT_4 var_226_arg_0 = var_85; [L616] SORT_4 var_226_arg_1 = var_225; [L617] SORT_1 var_226 = var_226_arg_0 <= var_226_arg_1; [L618] SORT_4 var_228_arg_0 = var_227; [L619] SORT_4 var_228_arg_1 = var_85; [L620] SORT_1 var_228 = var_228_arg_0 <= var_228_arg_1; [L621] SORT_1 var_229_arg_0 = ~var_226; [L622] var_229_arg_0 = var_229_arg_0 & mask_SORT_1 [L623] SORT_1 var_229_arg_1 = ~var_228; [L624] var_229_arg_1 = var_229_arg_1 & mask_SORT_1 [L625] SORT_1 var_229 = var_229_arg_0 & var_229_arg_1; [L626] SORT_1 var_230_arg_0 = state_23; [L627] SORT_1 var_230_arg_1 = var_229; [L628] SORT_1 var_230 = var_230_arg_0 & var_230_arg_1; [L629] SORT_1 var_231_arg_0 = ~input_83; [L630] var_231_arg_0 = var_231_arg_0 & mask_SORT_1 [L631] SORT_1 var_231_arg_1 = var_230; [L632] SORT_1 var_231 = var_231_arg_0 | var_231_arg_1; [L633] SORT_1 var_232_arg_0 = var_224; [L634] SORT_1 var_232_arg_1 = var_231; [L635] SORT_1 var_232 = var_232_arg_0 & var_232_arg_1; [L636] SORT_4 var_234_arg_0 = var_233; [L637] SORT_4 var_234_arg_1 = var_85; [L638] SORT_1 var_234 = var_234_arg_0 <= var_234_arg_1; [L639] SORT_1 var_235_arg_0 = state_23; [L640] SORT_1 var_235_arg_1 = ~var_234; [L641] var_235_arg_1 = var_235_arg_1 & mask_SORT_1 [L642] SORT_1 var_235 = var_235_arg_0 & var_235_arg_1; [L643] SORT_1 var_236_arg_0 = ~input_82; [L644] var_236_arg_0 = var_236_arg_0 & mask_SORT_1 [L645] SORT_1 var_236_arg_1 = var_235; [L646] SORT_1 var_236 = var_236_arg_0 | var_236_arg_1; [L647] SORT_1 var_237_arg_0 = var_232; [L648] SORT_1 var_237_arg_1 = var_236; [L649] SORT_1 var_237 = var_237_arg_0 & var_237_arg_1; [L650] SORT_4 var_239_arg_0 = var_85; [L651] SORT_4 var_239_arg_1 = var_238; [L652] SORT_1 var_239 = var_239_arg_0 <= var_239_arg_1; [L653] SORT_1 var_240_arg_0 = state_23; [L654] SORT_1 var_240_arg_1 = ~var_239; [L655] var_240_arg_1 = var_240_arg_1 & mask_SORT_1 [L656] SORT_1 var_240 = var_240_arg_0 & var_240_arg_1; [L657] SORT_1 var_241_arg_0 = ~input_81; [L658] var_241_arg_0 = var_241_arg_0 & mask_SORT_1 [L659] SORT_1 var_241_arg_1 = var_240; [L660] SORT_1 var_241 = var_241_arg_0 | var_241_arg_1; [L661] SORT_1 var_242_arg_0 = var_237; [L662] SORT_1 var_242_arg_1 = var_241; [L663] SORT_1 var_242 = var_242_arg_0 & var_242_arg_1; [L664] SORT_4 var_243_arg_0 = var_61; [L665] SORT_4 var_243_arg_1 = var_64; [L666] SORT_1 var_243 = var_243_arg_0 <= var_243_arg_1; [L667] SORT_1 var_244_arg_0 = state_27; [L668] SORT_1 var_244_arg_1 = ~var_243; [L669] var_244_arg_1 = var_244_arg_1 & mask_SORT_1 [L670] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L671] SORT_1 var_245_arg_0 = ~input_104; [L672] var_245_arg_0 = var_245_arg_0 & mask_SORT_1 [L673] SORT_1 var_245_arg_1 = var_244; [L674] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L675] SORT_1 var_246_arg_0 = var_242; [L676] SORT_1 var_246_arg_1 = var_245; [L677] SORT_1 var_246 = var_246_arg_0 & var_246_arg_1; [L678] SORT_4 var_247_arg_0 = var_57; [L679] SORT_4 var_247_arg_1 = var_61; [L680] SORT_1 var_247 = var_247_arg_0 <= var_247_arg_1; [L681] SORT_1 var_248_arg_0 = state_31; [L682] SORT_1 var_248_arg_1 = ~var_247; [L683] var_248_arg_1 = var_248_arg_1 & mask_SORT_1 [L684] SORT_1 var_248 = var_248_arg_0 & var_248_arg_1; [L685] SORT_1 var_249_arg_0 = ~input_101; [L686] var_249_arg_0 = var_249_arg_0 & mask_SORT_1 [L687] SORT_1 var_249_arg_1 = var_248; [L688] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L689] SORT_1 var_250_arg_0 = var_246; [L690] SORT_1 var_250_arg_1 = var_249; [L691] SORT_1 var_250 = var_250_arg_0 & var_250_arg_1; [L692] SORT_1 var_251_arg_0 = ~state_37; [L693] var_251_arg_0 = var_251_arg_0 & mask_SORT_1 [L694] SORT_1 var_251_arg_1 = ~input_99; [L695] var_251_arg_1 = var_251_arg_1 & mask_SORT_1 [L696] SORT_1 var_251 = var_251_arg_0 | var_251_arg_1; [L697] SORT_1 var_252_arg_0 = var_250; [L698] SORT_1 var_252_arg_1 = var_251; [L699] SORT_1 var_252 = var_252_arg_0 & var_252_arg_1; [L700] SORT_4 var_253_arg_0 = var_64; [L701] SORT_4 var_253_arg_1 = var_61; [L702] SORT_1 var_253 = var_253_arg_0 == var_253_arg_1; [L703] SORT_1 var_254_arg_0 = state_27; [L704] SORT_1 var_254_arg_1 = var_253; [L705] SORT_1 var_254 = var_254_arg_0 & var_254_arg_1; [L706] SORT_1 var_255_arg_0 = ~input_143; [L707] var_255_arg_0 = var_255_arg_0 & mask_SORT_1 [L708] SORT_1 var_255_arg_1 = var_254; [L709] SORT_1 var_255 = var_255_arg_0 | var_255_arg_1; [L710] SORT_1 var_256_arg_0 = var_252; [L711] SORT_1 var_256_arg_1 = var_255; [L712] SORT_1 var_256 = var_256_arg_0 & var_256_arg_1; [L713] SORT_1 var_257_arg_0 = state_31; [L714] SORT_1 var_257_arg_1 = var_62; [L715] SORT_1 var_257 = var_257_arg_0 & var_257_arg_1; [L716] SORT_1 var_258_arg_0 = ~input_152; [L717] var_258_arg_0 = var_258_arg_0 & mask_SORT_1 [L718] SORT_1 var_258_arg_1 = var_257; [L719] SORT_1 var_258 = var_258_arg_0 | var_258_arg_1; [L720] SORT_1 var_259_arg_0 = var_256; [L721] SORT_1 var_259_arg_1 = var_258; [L722] SORT_1 var_259 = var_259_arg_0 & var_259_arg_1; [L723] SORT_1 var_260_arg_0 = state_33; [L724] SORT_1 var_260_arg_1 = ~input_158; [L725] var_260_arg_1 = var_260_arg_1 & mask_SORT_1 [L726] SORT_1 var_260 = var_260_arg_0 | var_260_arg_1; [L727] SORT_1 var_261_arg_0 = var_259; [L728] SORT_1 var_261_arg_1 = var_260; [L729] SORT_1 var_261 = var_261_arg_0 & var_261_arg_1; [L730] SORT_1 var_262_arg_0 = state_35; [L731] SORT_1 var_262_arg_1 = ~input_162; [L732] var_262_arg_1 = var_262_arg_1 & mask_SORT_1 [L733] SORT_1 var_262 = var_262_arg_0 | var_262_arg_1; [L734] SORT_1 var_263_arg_0 = var_261; [L735] SORT_1 var_263_arg_1 = var_262; [L736] SORT_1 var_263 = var_263_arg_0 & var_263_arg_1; [L737] SORT_1 var_264_arg_0 = state_29; [L738] SORT_1 var_264_arg_1 = ~input_147; [L739] var_264_arg_1 = var_264_arg_1 & mask_SORT_1 [L740] SORT_1 var_264 = var_264_arg_0 | var_264_arg_1; [L741] SORT_1 var_265_arg_0 = var_263; [L742] SORT_1 var_265_arg_1 = var_264; [L743] SORT_1 var_265 = var_265_arg_0 & var_265_arg_1; [L744] SORT_1 var_266_arg_0 = state_39; [L745] SORT_1 var_266_arg_1 = ~input_166; [L746] var_266_arg_1 = var_266_arg_1 & mask_SORT_1 [L747] SORT_1 var_266 = var_266_arg_0 | var_266_arg_1; [L748] SORT_1 var_267_arg_0 = var_265; [L749] SORT_1 var_267_arg_1 = var_266; [L750] SORT_1 var_267 = var_267_arg_0 & var_267_arg_1; [L751] SORT_1 var_268_arg_0 = state_45; [L752] SORT_1 var_268_arg_1 = ~input_182; [L753] var_268_arg_1 = var_268_arg_1 & mask_SORT_1 [L754] SORT_1 var_268 = var_268_arg_0 | var_268_arg_1; [L755] SORT_1 var_269_arg_0 = var_267; [L756] SORT_1 var_269_arg_1 = var_268; [L757] SORT_1 var_269 = var_269_arg_0 & var_269_arg_1; [L758] SORT_1 var_270_arg_0 = state_45; [L759] SORT_1 var_270_arg_1 = ~input_184; [L760] var_270_arg_1 = var_270_arg_1 & mask_SORT_1 [L761] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L762] SORT_1 var_271_arg_0 = var_269; [L763] SORT_1 var_271_arg_1 = var_270; [L764] SORT_1 var_271 = var_271_arg_0 & var_271_arg_1; [L765] SORT_1 var_272_arg_0 = state_47; [L766] SORT_1 var_272_arg_1 = ~input_70; [L767] var_272_arg_1 = var_272_arg_1 & mask_SORT_1 [L768] SORT_1 var_272 = var_272_arg_0 | var_272_arg_1; [L769] SORT_1 var_273_arg_0 = var_271; [L770] SORT_1 var_273_arg_1 = var_272; [L771] SORT_1 var_273 = var_273_arg_0 & var_273_arg_1; [L772] SORT_1 var_274_arg_0 = state_47; [L773] SORT_1 var_274_arg_1 = ~input_190; [L774] var_274_arg_1 = var_274_arg_1 & mask_SORT_1 [L775] SORT_1 var_274 = var_274_arg_0 | var_274_arg_1; [L776] SORT_1 var_275_arg_0 = var_273; [L777] SORT_1 var_275_arg_1 = var_274; [L778] SORT_1 var_275 = var_275_arg_0 & var_275_arg_1; [L779] SORT_1 var_276_arg_0 = state_15; [L780] SORT_1 var_276_arg_1 = state_25; [L781] SORT_1 var_276 = var_276_arg_0 & var_276_arg_1; [L782] SORT_1 var_277_arg_0 = var_276; [L783] SORT_1 var_277_arg_1 = var_206; [L784] SORT_1 var_277 = var_277_arg_0 & var_277_arg_1; [L785] SORT_1 var_278_arg_0 = ~input_116; [L786] var_278_arg_0 = var_278_arg_0 & mask_SORT_1 [L787] SORT_1 var_278_arg_1 = var_277; [L788] SORT_1 var_278 = var_278_arg_0 | var_278_arg_1; [L789] SORT_1 var_279_arg_0 = var_275; [L790] SORT_1 var_279_arg_1 = var_278; [L791] SORT_1 var_279 = var_279_arg_0 & var_279_arg_1; [L792] SORT_1 var_280_arg_0 = state_41; [L793] SORT_1 var_280_arg_1 = ~state_51; [L794] var_280_arg_1 = var_280_arg_1 & mask_SORT_1 [L795] SORT_1 var_280 = var_280_arg_0 & var_280_arg_1; [L796] SORT_1 var_281_arg_0 = ~input_175; [L797] var_281_arg_0 = var_281_arg_0 & mask_SORT_1 [L798] SORT_1 var_281_arg_1 = var_280; [L799] SORT_1 var_281 = var_281_arg_0 | var_281_arg_1; [L800] SORT_1 var_282_arg_0 = var_279; [L801] SORT_1 var_282_arg_1 = var_281; [L802] SORT_1 var_282 = var_282_arg_0 & var_282_arg_1; [L803] SORT_1 var_283_arg_0 = state_43; [L804] SORT_1 var_283_arg_1 = state_53; [L805] SORT_1 var_283 = var_283_arg_0 & var_283_arg_1; [L806] SORT_1 var_284_arg_0 = ~input_133; [L807] var_284_arg_0 = var_284_arg_0 & mask_SORT_1 [L808] SORT_1 var_284_arg_1 = var_283; [L809] SORT_1 var_284 = var_284_arg_0 | var_284_arg_1; [L810] SORT_1 var_285_arg_0 = var_282; [L811] SORT_1 var_285_arg_1 = var_284; [L812] SORT_1 var_285 = var_285_arg_0 & var_285_arg_1; [L813] SORT_1 var_286_arg_0 = state_43; [L814] SORT_1 var_286_arg_1 = state_49; [L815] SORT_1 var_286 = var_286_arg_0 & var_286_arg_1; [L816] SORT_1 var_287_arg_0 = ~input_154; [L817] var_287_arg_0 = var_287_arg_0 & mask_SORT_1 [L818] SORT_1 var_287_arg_1 = var_286; [L819] SORT_1 var_287 = var_287_arg_0 | var_287_arg_1; [L820] SORT_1 var_288_arg_0 = var_285; [L821] SORT_1 var_288_arg_1 = var_287; [L822] SORT_1 var_288 = var_288_arg_0 & var_288_arg_1; [L823] SORT_1 var_289_arg_0 = input_111; [L824] SORT_1 var_289_arg_1 = input_88; [L825] SORT_1 var_289 = var_289_arg_0 | var_289_arg_1; [L826] SORT_1 var_290_arg_0 = input_75; [L827] SORT_1 var_290_arg_1 = var_289; [L828] SORT_1 var_290 = var_290_arg_0 | var_290_arg_1; [L829] SORT_1 var_291_arg_0 = input_73; [L830] SORT_1 var_291_arg_1 = var_290; [L831] SORT_1 var_291 = var_291_arg_0 | var_291_arg_1; [L832] SORT_1 var_292_arg_0 = input_120; [L833] SORT_1 var_292_arg_1 = var_291; [L834] SORT_1 var_292 = var_292_arg_0 | var_292_arg_1; [L835] SORT_1 var_293_arg_0 = input_72; [L836] SORT_1 var_293_arg_1 = var_292; [L837] SORT_1 var_293 = var_293_arg_0 | var_293_arg_1; [L838] SORT_1 var_294_arg_0 = input_83; [L839] SORT_1 var_294_arg_1 = var_293; [L840] SORT_1 var_294 = var_294_arg_0 | var_294_arg_1; [L841] SORT_1 var_295_arg_0 = input_82; [L842] SORT_1 var_295_arg_1 = var_294; [L843] SORT_1 var_295 = var_295_arg_0 | var_295_arg_1; [L844] SORT_1 var_296_arg_0 = input_81; [L845] SORT_1 var_296_arg_1 = var_295; [L846] SORT_1 var_296 = var_296_arg_0 | var_296_arg_1; [L847] SORT_1 var_297_arg_0 = input_104; [L848] SORT_1 var_297_arg_1 = var_296; [L849] SORT_1 var_297 = var_297_arg_0 | var_297_arg_1; [L850] SORT_1 var_298_arg_0 = input_101; [L851] SORT_1 var_298_arg_1 = var_297; [L852] SORT_1 var_298 = var_298_arg_0 | var_298_arg_1; [L853] SORT_1 var_299_arg_0 = input_99; [L854] SORT_1 var_299_arg_1 = var_298; [L855] SORT_1 var_299 = var_299_arg_0 | var_299_arg_1; [L856] SORT_1 var_300_arg_0 = input_143; [L857] SORT_1 var_300_arg_1 = var_299; [L858] SORT_1 var_300 = var_300_arg_0 | var_300_arg_1; [L859] SORT_1 var_301_arg_0 = input_152; [L860] SORT_1 var_301_arg_1 = var_300; [L861] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L862] SORT_1 var_302_arg_0 = input_158; [L863] SORT_1 var_302_arg_1 = var_301; [L864] SORT_1 var_302 = var_302_arg_0 | var_302_arg_1; [L865] SORT_1 var_303_arg_0 = input_162; [L866] SORT_1 var_303_arg_1 = var_302; [L867] SORT_1 var_303 = var_303_arg_0 | var_303_arg_1; [L868] SORT_1 var_304_arg_0 = input_147; [L869] SORT_1 var_304_arg_1 = var_303; [L870] SORT_1 var_304 = var_304_arg_0 | var_304_arg_1; [L871] SORT_1 var_305_arg_0 = input_166; [L872] SORT_1 var_305_arg_1 = var_304; [L873] SORT_1 var_305 = var_305_arg_0 | var_305_arg_1; [L874] SORT_1 var_306_arg_0 = input_182; [L875] SORT_1 var_306_arg_1 = var_305; [L876] SORT_1 var_306 = var_306_arg_0 | var_306_arg_1; [L877] SORT_1 var_307_arg_0 = input_184; [L878] SORT_1 var_307_arg_1 = var_306; [L879] SORT_1 var_307 = var_307_arg_0 | var_307_arg_1; [L880] SORT_1 var_308_arg_0 = input_70; [L881] SORT_1 var_308_arg_1 = var_307; [L882] SORT_1 var_308 = var_308_arg_0 | var_308_arg_1; [L883] SORT_1 var_309_arg_0 = input_190; [L884] SORT_1 var_309_arg_1 = var_308; [L885] SORT_1 var_309 = var_309_arg_0 | var_309_arg_1; [L886] SORT_1 var_310_arg_0 = input_116; [L887] SORT_1 var_310_arg_1 = var_309; [L888] SORT_1 var_310 = var_310_arg_0 | var_310_arg_1; [L889] SORT_1 var_311_arg_0 = input_175; [L890] SORT_1 var_311_arg_1 = var_310; [L891] SORT_1 var_311 = var_311_arg_0 | var_311_arg_1; [L892] SORT_1 var_312_arg_0 = input_133; [L893] SORT_1 var_312_arg_1 = var_311; [L894] SORT_1 var_312 = var_312_arg_0 | var_312_arg_1; [L895] SORT_1 var_313_arg_0 = input_154; [L896] SORT_1 var_313_arg_1 = var_312; [L897] SORT_1 var_313 = var_313_arg_0 | var_313_arg_1; [L898] SORT_1 var_314_arg_0 = var_288; [L899] SORT_1 var_314_arg_1 = var_313; [L900] SORT_1 var_314 = var_314_arg_0 & var_314_arg_1; [L901] SORT_1 var_315_arg_0 = input_111; [L902] SORT_1 var_315_arg_1 = input_88; [L903] SORT_1 var_315 = var_315_arg_0 & var_315_arg_1; [L904] SORT_1 var_316_arg_0 = input_75; [L905] SORT_1 var_316_arg_1 = var_289; [L906] SORT_1 var_316 = var_316_arg_0 & var_316_arg_1; [L907] SORT_1 var_317_arg_0 = var_315; [L908] SORT_1 var_317_arg_1 = var_316; [L909] SORT_1 var_317 = var_317_arg_0 | var_317_arg_1; [L910] SORT_1 var_318_arg_0 = input_73; [L911] SORT_1 var_318_arg_1 = var_290; [L912] SORT_1 var_318 = var_318_arg_0 & var_318_arg_1; [L913] SORT_1 var_319_arg_0 = var_317; [L914] SORT_1 var_319_arg_1 = var_318; [L915] SORT_1 var_319 = var_319_arg_0 | var_319_arg_1; [L916] SORT_1 var_320_arg_0 = input_120; [L917] SORT_1 var_320_arg_1 = var_291; [L918] SORT_1 var_320 = var_320_arg_0 & var_320_arg_1; [L919] SORT_1 var_321_arg_0 = var_319; [L920] SORT_1 var_321_arg_1 = var_320; [L921] SORT_1 var_321 = var_321_arg_0 | var_321_arg_1; [L922] SORT_1 var_322_arg_0 = input_72; [L923] SORT_1 var_322_arg_1 = var_292; [L924] SORT_1 var_322 = var_322_arg_0 & var_322_arg_1; [L925] SORT_1 var_323_arg_0 = var_321; [L926] SORT_1 var_323_arg_1 = var_322; [L927] SORT_1 var_323 = var_323_arg_0 | var_323_arg_1; [L928] SORT_1 var_324_arg_0 = input_83; [L929] SORT_1 var_324_arg_1 = var_293; [L930] SORT_1 var_324 = var_324_arg_0 & var_324_arg_1; [L931] SORT_1 var_325_arg_0 = var_323; [L932] SORT_1 var_325_arg_1 = var_324; [L933] SORT_1 var_325 = var_325_arg_0 | var_325_arg_1; [L934] SORT_1 var_326_arg_0 = input_82; [L935] SORT_1 var_326_arg_1 = var_294; [L936] SORT_1 var_326 = var_326_arg_0 & var_326_arg_1; [L937] SORT_1 var_327_arg_0 = var_325; [L938] SORT_1 var_327_arg_1 = var_326; [L939] SORT_1 var_327 = var_327_arg_0 | var_327_arg_1; [L940] SORT_1 var_328_arg_0 = input_81; [L941] SORT_1 var_328_arg_1 = var_295; [L942] SORT_1 var_328 = var_328_arg_0 & var_328_arg_1; [L943] SORT_1 var_329_arg_0 = var_327; [L944] SORT_1 var_329_arg_1 = var_328; [L945] SORT_1 var_329 = var_329_arg_0 | var_329_arg_1; [L946] SORT_1 var_330_arg_0 = input_104; [L947] SORT_1 var_330_arg_1 = var_296; [L948] SORT_1 var_330 = var_330_arg_0 & var_330_arg_1; [L949] SORT_1 var_331_arg_0 = var_329; [L950] SORT_1 var_331_arg_1 = var_330; [L951] SORT_1 var_331 = var_331_arg_0 | var_331_arg_1; [L952] SORT_1 var_332_arg_0 = input_101; [L953] SORT_1 var_332_arg_1 = var_297; [L954] SORT_1 var_332 = var_332_arg_0 & var_332_arg_1; [L955] SORT_1 var_333_arg_0 = var_331; [L956] SORT_1 var_333_arg_1 = var_332; [L957] SORT_1 var_333 = var_333_arg_0 | var_333_arg_1; [L958] SORT_1 var_334_arg_0 = input_99; [L959] SORT_1 var_334_arg_1 = var_298; [L960] SORT_1 var_334 = var_334_arg_0 & var_334_arg_1; [L961] SORT_1 var_335_arg_0 = var_333; [L962] SORT_1 var_335_arg_1 = var_334; [L963] SORT_1 var_335 = var_335_arg_0 | var_335_arg_1; [L964] SORT_1 var_336_arg_0 = input_143; [L965] SORT_1 var_336_arg_1 = var_299; [L966] SORT_1 var_336 = var_336_arg_0 & var_336_arg_1; [L967] SORT_1 var_337_arg_0 = var_335; [L968] SORT_1 var_337_arg_1 = var_336; [L969] SORT_1 var_337 = var_337_arg_0 | var_337_arg_1; [L970] SORT_1 var_338_arg_0 = input_152; [L971] SORT_1 var_338_arg_1 = var_300; [L972] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L973] SORT_1 var_339_arg_0 = var_337; [L974] SORT_1 var_339_arg_1 = var_338; [L975] SORT_1 var_339 = var_339_arg_0 | var_339_arg_1; [L976] SORT_1 var_340_arg_0 = input_158; [L977] SORT_1 var_340_arg_1 = var_301; [L978] SORT_1 var_340 = var_340_arg_0 & var_340_arg_1; [L979] SORT_1 var_341_arg_0 = var_339; [L980] SORT_1 var_341_arg_1 = var_340; [L981] SORT_1 var_341 = var_341_arg_0 | var_341_arg_1; [L982] SORT_1 var_342_arg_0 = input_162; [L983] SORT_1 var_342_arg_1 = var_302; [L984] SORT_1 var_342 = var_342_arg_0 & var_342_arg_1; [L985] SORT_1 var_343_arg_0 = var_341; [L986] SORT_1 var_343_arg_1 = var_342; [L987] SORT_1 var_343 = var_343_arg_0 | var_343_arg_1; [L988] SORT_1 var_344_arg_0 = input_147; [L989] SORT_1 var_344_arg_1 = var_303; [L990] SORT_1 var_344 = var_344_arg_0 & var_344_arg_1; [L991] SORT_1 var_345_arg_0 = var_343; [L992] SORT_1 var_345_arg_1 = var_344; [L993] SORT_1 var_345 = var_345_arg_0 | var_345_arg_1; [L994] SORT_1 var_346_arg_0 = input_166; [L995] SORT_1 var_346_arg_1 = var_304; [L996] SORT_1 var_346 = var_346_arg_0 & var_346_arg_1; [L997] SORT_1 var_347_arg_0 = var_345; [L998] SORT_1 var_347_arg_1 = var_346; [L999] SORT_1 var_347 = var_347_arg_0 | var_347_arg_1; [L1000] SORT_1 var_348_arg_0 = input_182; [L1001] SORT_1 var_348_arg_1 = var_305; [L1002] SORT_1 var_348 = var_348_arg_0 & var_348_arg_1; [L1003] SORT_1 var_349_arg_0 = var_347; [L1004] SORT_1 var_349_arg_1 = var_348; [L1005] SORT_1 var_349 = var_349_arg_0 | var_349_arg_1; [L1006] SORT_1 var_350_arg_0 = input_184; [L1007] SORT_1 var_350_arg_1 = var_306; [L1008] SORT_1 var_350 = var_350_arg_0 & var_350_arg_1; [L1009] SORT_1 var_351_arg_0 = var_349; [L1010] SORT_1 var_351_arg_1 = var_350; [L1011] SORT_1 var_351 = var_351_arg_0 | var_351_arg_1; [L1012] SORT_1 var_352_arg_0 = input_70; [L1013] SORT_1 var_352_arg_1 = var_307; [L1014] SORT_1 var_352 = var_352_arg_0 & var_352_arg_1; [L1015] SORT_1 var_353_arg_0 = var_351; [L1016] SORT_1 var_353_arg_1 = var_352; [L1017] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L1018] SORT_1 var_354_arg_0 = input_190; [L1019] SORT_1 var_354_arg_1 = var_308; [L1020] SORT_1 var_354 = var_354_arg_0 & var_354_arg_1; [L1021] SORT_1 var_355_arg_0 = var_353; [L1022] SORT_1 var_355_arg_1 = var_354; [L1023] SORT_1 var_355 = var_355_arg_0 | var_355_arg_1; [L1024] SORT_1 var_356_arg_0 = input_116; [L1025] SORT_1 var_356_arg_1 = var_309; [L1026] SORT_1 var_356 = var_356_arg_0 & var_356_arg_1; [L1027] SORT_1 var_357_arg_0 = var_355; [L1028] SORT_1 var_357_arg_1 = var_356; [L1029] SORT_1 var_357 = var_357_arg_0 | var_357_arg_1; [L1030] SORT_1 var_358_arg_0 = input_175; [L1031] SORT_1 var_358_arg_1 = var_310; [L1032] SORT_1 var_358 = var_358_arg_0 & var_358_arg_1; [L1033] SORT_1 var_359_arg_0 = var_357; [L1034] SORT_1 var_359_arg_1 = var_358; [L1035] SORT_1 var_359 = var_359_arg_0 | var_359_arg_1; [L1036] SORT_1 var_360_arg_0 = input_133; [L1037] SORT_1 var_360_arg_1 = var_311; [L1038] SORT_1 var_360 = var_360_arg_0 & var_360_arg_1; [L1039] SORT_1 var_361_arg_0 = var_359; [L1040] SORT_1 var_361_arg_1 = var_360; [L1041] SORT_1 var_361 = var_361_arg_0 | var_361_arg_1; [L1042] SORT_1 var_362_arg_0 = input_154; [L1043] SORT_1 var_362_arg_1 = var_312; [L1044] SORT_1 var_362 = var_362_arg_0 & var_362_arg_1; [L1045] SORT_1 var_363_arg_0 = var_361; [L1046] SORT_1 var_363_arg_1 = var_362; [L1047] SORT_1 var_363 = var_363_arg_0 | var_363_arg_1; [L1048] SORT_1 var_364_arg_0 = var_314; [L1049] SORT_1 var_364_arg_1 = ~var_363; [L1050] var_364_arg_1 = var_364_arg_1 & mask_SORT_1 [L1051] SORT_1 var_364 = var_364_arg_0 & var_364_arg_1; [L1052] SORT_1 var_365_arg_0 = state_15; [L1053] SORT_1 var_365_arg_1 = state_17; [L1054] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L1055] SORT_1 var_366_arg_0 = state_15; [L1056] SORT_1 var_366_arg_1 = state_17; [L1057] SORT_1 var_366 = var_366_arg_0 | var_366_arg_1; [L1058] SORT_1 var_367_arg_0 = state_19; [L1059] SORT_1 var_367_arg_1 = var_366; [L1060] SORT_1 var_367 = var_367_arg_0 & var_367_arg_1; [L1061] SORT_1 var_368_arg_0 = var_365; [L1062] SORT_1 var_368_arg_1 = var_367; [L1063] SORT_1 var_368 = var_368_arg_0 | var_368_arg_1; [L1064] SORT_1 var_369_arg_0 = state_19; [L1065] SORT_1 var_369_arg_1 = var_366; [L1066] SORT_1 var_369 = var_369_arg_0 | var_369_arg_1; [L1067] SORT_1 var_370_arg_0 = ~state_21; [L1068] var_370_arg_0 = var_370_arg_0 & mask_SORT_1 [L1069] SORT_1 var_370_arg_1 = var_369; [L1070] SORT_1 var_370 = var_370_arg_0 & var_370_arg_1; [L1071] SORT_1 var_371_arg_0 = var_368; [L1072] SORT_1 var_371_arg_1 = var_370; [L1073] SORT_1 var_371 = var_371_arg_0 | var_371_arg_1; [L1074] SORT_1 var_372_arg_0 = ~state_21; [L1075] var_372_arg_0 = var_372_arg_0 & mask_SORT_1 [L1076] SORT_1 var_372_arg_1 = var_369; [L1077] SORT_1 var_372 = var_372_arg_0 | var_372_arg_1; [L1078] SORT_1 var_373_arg_0 = ~var_371; [L1079] var_373_arg_0 = var_373_arg_0 & mask_SORT_1 [L1080] SORT_1 var_373_arg_1 = var_372; [L1081] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L1082] SORT_1 var_374_arg_0 = state_23; [L1083] SORT_1 var_374_arg_1 = state_25; [L1084] SORT_1 var_374 = var_374_arg_0 & var_374_arg_1; [L1085] SORT_1 var_375_arg_0 = state_23; [L1086] SORT_1 var_375_arg_1 = state_25; [L1087] SORT_1 var_375 = var_375_arg_0 | var_375_arg_1; [L1088] SORT_1 var_376_arg_0 = state_27; [L1089] SORT_1 var_376_arg_1 = var_375; [L1090] SORT_1 var_376 = var_376_arg_0 & var_376_arg_1; [L1091] SORT_1 var_377_arg_0 = var_374; [L1092] SORT_1 var_377_arg_1 = var_376; [L1093] SORT_1 var_377 = var_377_arg_0 | var_377_arg_1; [L1094] SORT_1 var_378_arg_0 = state_27; [L1095] SORT_1 var_378_arg_1 = var_375; [L1096] SORT_1 var_378 = var_378_arg_0 | var_378_arg_1; [L1097] SORT_1 var_379_arg_0 = state_29; [L1098] SORT_1 var_379_arg_1 = var_378; [L1099] SORT_1 var_379 = var_379_arg_0 & var_379_arg_1; [L1100] SORT_1 var_380_arg_0 = var_377; [L1101] SORT_1 var_380_arg_1 = var_379; [L1102] SORT_1 var_380 = var_380_arg_0 | var_380_arg_1; [L1103] SORT_1 var_381_arg_0 = state_29; [L1104] SORT_1 var_381_arg_1 = var_378; [L1105] SORT_1 var_381 = var_381_arg_0 | var_381_arg_1; [L1106] SORT_1 var_382_arg_0 = state_31; [L1107] SORT_1 var_382_arg_1 = var_381; [L1108] SORT_1 var_382 = var_382_arg_0 & var_382_arg_1; [L1109] SORT_1 var_383_arg_0 = var_380; [L1110] SORT_1 var_383_arg_1 = var_382; [L1111] SORT_1 var_383 = var_383_arg_0 | var_383_arg_1; [L1112] SORT_1 var_384_arg_0 = state_31; [L1113] SORT_1 var_384_arg_1 = var_381; [L1114] SORT_1 var_384 = var_384_arg_0 | var_384_arg_1; [L1115] SORT_1 var_385_arg_0 = state_33; [L1116] SORT_1 var_385_arg_1 = var_384; [L1117] SORT_1 var_385 = var_385_arg_0 & var_385_arg_1; [L1118] SORT_1 var_386_arg_0 = var_383; [L1119] SORT_1 var_386_arg_1 = var_385; [L1120] SORT_1 var_386 = var_386_arg_0 | var_386_arg_1; [L1121] SORT_1 var_387_arg_0 = state_33; [L1122] SORT_1 var_387_arg_1 = var_384; [L1123] SORT_1 var_387 = var_387_arg_0 | var_387_arg_1; [L1124] SORT_1 var_388_arg_0 = state_35; [L1125] SORT_1 var_388_arg_1 = var_387; [L1126] SORT_1 var_388 = var_388_arg_0 & var_388_arg_1; [L1127] SORT_1 var_389_arg_0 = var_386; [L1128] SORT_1 var_389_arg_1 = var_388; [L1129] SORT_1 var_389 = var_389_arg_0 | var_389_arg_1; [L1130] SORT_1 var_390_arg_0 = state_35; [L1131] SORT_1 var_390_arg_1 = var_387; [L1132] SORT_1 var_390 = var_390_arg_0 | var_390_arg_1; [L1133] SORT_1 var_391_arg_0 = ~state_37; [L1134] var_391_arg_0 = var_391_arg_0 & mask_SORT_1 [L1135] SORT_1 var_391_arg_1 = var_390; [L1136] SORT_1 var_391 = var_391_arg_0 & var_391_arg_1; [L1137] SORT_1 var_392_arg_0 = var_389; [L1138] SORT_1 var_392_arg_1 = var_391; [L1139] SORT_1 var_392 = var_392_arg_0 | var_392_arg_1; [L1140] SORT_1 var_393_arg_0 = ~state_37; [L1141] var_393_arg_0 = var_393_arg_0 & mask_SORT_1 [L1142] SORT_1 var_393_arg_1 = var_390; [L1143] SORT_1 var_393 = var_393_arg_0 | var_393_arg_1; [L1144] SORT_1 var_394_arg_0 = state_39; [L1145] SORT_1 var_394_arg_1 = var_393; [L1146] SORT_1 var_394 = var_394_arg_0 & var_394_arg_1; [L1147] SORT_1 var_395_arg_0 = var_392; [L1148] SORT_1 var_395_arg_1 = var_394; [L1149] SORT_1 var_395 = var_395_arg_0 | var_395_arg_1; [L1150] SORT_1 var_396_arg_0 = state_39; [L1151] SORT_1 var_396_arg_1 = var_393; [L1152] SORT_1 var_396 = var_396_arg_0 | var_396_arg_1; [L1153] SORT_1 var_397_arg_0 = state_41; [L1154] SORT_1 var_397_arg_1 = var_396; [L1155] SORT_1 var_397 = var_397_arg_0 & var_397_arg_1; [L1156] SORT_1 var_398_arg_0 = var_395; [L1157] SORT_1 var_398_arg_1 = var_397; [L1158] SORT_1 var_398 = var_398_arg_0 | var_398_arg_1; [L1159] SORT_1 var_399_arg_0 = state_41; [L1160] SORT_1 var_399_arg_1 = var_396; [L1161] SORT_1 var_399 = var_399_arg_0 | var_399_arg_1; [L1162] SORT_1 var_400_arg_0 = state_43; [L1163] SORT_1 var_400_arg_1 = var_399; [L1164] SORT_1 var_400 = var_400_arg_0 & var_400_arg_1; [L1165] SORT_1 var_401_arg_0 = var_398; [L1166] SORT_1 var_401_arg_1 = var_400; [L1167] SORT_1 var_401 = var_401_arg_0 | var_401_arg_1; [L1168] SORT_1 var_402_arg_0 = var_373; [L1169] SORT_1 var_402_arg_1 = ~var_401; [L1170] var_402_arg_1 = var_402_arg_1 & mask_SORT_1 [L1171] SORT_1 var_402 = var_402_arg_0 & var_402_arg_1; [L1172] SORT_1 var_403_arg_0 = state_43; [L1173] SORT_1 var_403_arg_1 = var_399; [L1174] SORT_1 var_403 = var_403_arg_0 | var_403_arg_1; [L1175] SORT_1 var_404_arg_0 = var_402; [L1176] SORT_1 var_404_arg_1 = var_403; [L1177] SORT_1 var_404 = var_404_arg_0 & var_404_arg_1; [L1178] SORT_1 var_405_arg_0 = state_45; [L1179] SORT_1 var_405_arg_1 = state_47; [L1180] SORT_1 var_405 = var_405_arg_0 & var_405_arg_1; [L1181] SORT_1 var_406_arg_0 = state_45; [L1182] SORT_1 var_406_arg_1 = state_47; [L1183] SORT_1 var_406 = var_406_arg_0 | var_406_arg_1; [L1184] SORT_1 var_407_arg_0 = state_49; [L1185] SORT_1 var_407_arg_1 = var_406; [L1186] SORT_1 var_407 = var_407_arg_0 & var_407_arg_1; [L1187] SORT_1 var_408_arg_0 = var_405; [L1188] SORT_1 var_408_arg_1 = var_407; [L1189] SORT_1 var_408 = var_408_arg_0 | var_408_arg_1; [L1190] SORT_1 var_409_arg_0 = state_49; [L1191] SORT_1 var_409_arg_1 = var_406; [L1192] SORT_1 var_409 = var_409_arg_0 | var_409_arg_1; [L1193] SORT_1 var_410_arg_0 = ~state_51; [L1194] var_410_arg_0 = var_410_arg_0 & mask_SORT_1 [L1195] SORT_1 var_410_arg_1 = var_409; [L1196] SORT_1 var_410 = var_410_arg_0 & var_410_arg_1; [L1197] SORT_1 var_411_arg_0 = var_408; [L1198] SORT_1 var_411_arg_1 = var_410; [L1199] SORT_1 var_411 = var_411_arg_0 | var_411_arg_1; [L1200] SORT_1 var_412_arg_0 = ~state_51; [L1201] var_412_arg_0 = var_412_arg_0 & mask_SORT_1 [L1202] SORT_1 var_412_arg_1 = var_409; [L1203] SORT_1 var_412 = var_412_arg_0 | var_412_arg_1; [L1204] SORT_1 var_413_arg_0 = state_53; [L1205] SORT_1 var_413_arg_1 = var_412; [L1206] SORT_1 var_413 = var_413_arg_0 & var_413_arg_1; [L1207] SORT_1 var_414_arg_0 = var_411; [L1208] SORT_1 var_414_arg_1 = var_413; [L1209] SORT_1 var_414 = var_414_arg_0 | var_414_arg_1; [L1210] SORT_1 var_415_arg_0 = var_404; [L1211] SORT_1 var_415_arg_1 = ~var_414; [L1212] var_415_arg_1 = var_415_arg_1 & mask_SORT_1 [L1213] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1214] SORT_1 var_416_arg_0 = state_53; [L1215] SORT_1 var_416_arg_1 = var_412; [L1216] SORT_1 var_416 = var_416_arg_0 | var_416_arg_1; [L1217] SORT_1 var_417_arg_0 = var_415; [L1218] SORT_1 var_417_arg_1 = var_416; [L1219] SORT_1 var_417 = var_417_arg_0 & var_417_arg_1; [L1220] SORT_1 var_418_arg_0 = var_364; [L1221] SORT_1 var_418_arg_1 = var_417; [L1222] SORT_1 var_418 = var_418_arg_0 & var_418_arg_1; [L1223] SORT_1 var_419_arg_0 = var_117; [L1224] SORT_1 var_419_arg_1 = var_122; [L1225] SORT_1 var_419 = var_419_arg_0 & var_419_arg_1; [L1226] SORT_1 var_420_arg_0 = var_117; [L1227] SORT_1 var_420_arg_1 = var_122; [L1228] SORT_1 var_420 = var_420_arg_0 | var_420_arg_1; [L1229] SORT_1 var_421_arg_0 = var_126; [L1230] SORT_1 var_421_arg_1 = var_420; [L1231] SORT_1 var_421 = var_421_arg_0 & var_421_arg_1; [L1232] SORT_1 var_422_arg_0 = var_419; [L1233] SORT_1 var_422_arg_1 = var_421; [L1234] SORT_1 var_422 = var_422_arg_0 | var_422_arg_1; [L1235] SORT_1 var_423_arg_0 = var_126; [L1236] SORT_1 var_423_arg_1 = var_420; [L1237] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1238] SORT_1 var_424_arg_0 = var_128; [L1239] SORT_1 var_424_arg_1 = var_423; [L1240] SORT_1 var_424 = var_424_arg_0 & var_424_arg_1; [L1241] SORT_1 var_425_arg_0 = var_422; [L1242] SORT_1 var_425_arg_1 = var_424; [L1243] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1244] SORT_1 var_426_arg_0 = var_128; [L1245] SORT_1 var_426_arg_1 = var_423; [L1246] SORT_1 var_426 = var_426_arg_0 | var_426_arg_1; [L1247] SORT_1 var_427_arg_0 = ~var_425; [L1248] var_427_arg_0 = var_427_arg_0 & mask_SORT_1 [L1249] SORT_1 var_427_arg_1 = var_426; [L1250] SORT_1 var_427 = var_427_arg_0 & var_427_arg_1; [L1251] SORT_1 var_428_arg_0 = var_139; [L1252] SORT_1 var_428_arg_1 = var_134; [L1253] SORT_1 var_428 = var_428_arg_0 & var_428_arg_1; [L1254] SORT_1 var_429_arg_0 = var_139; [L1255] SORT_1 var_429_arg_1 = var_134; [L1256] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1257] SORT_1 var_430_arg_0 = var_144; [L1258] SORT_1 var_430_arg_1 = var_429; [L1259] SORT_1 var_430 = var_430_arg_0 & var_430_arg_1; [L1260] SORT_1 var_431_arg_0 = var_428; [L1261] SORT_1 var_431_arg_1 = var_430; [L1262] SORT_1 var_431 = var_431_arg_0 | var_431_arg_1; [L1263] SORT_1 var_432_arg_0 = var_144; [L1264] SORT_1 var_432_arg_1 = var_429; [L1265] SORT_1 var_432 = var_432_arg_0 | var_432_arg_1; [L1266] SORT_1 var_433_arg_0 = var_148; [L1267] SORT_1 var_433_arg_1 = var_432; [L1268] SORT_1 var_433 = var_433_arg_0 & var_433_arg_1; [L1269] SORT_1 var_434_arg_0 = var_431; [L1270] SORT_1 var_434_arg_1 = var_433; [L1271] SORT_1 var_434 = var_434_arg_0 | var_434_arg_1; [L1272] SORT_1 var_435_arg_0 = var_148; [L1273] SORT_1 var_435_arg_1 = var_432; [L1274] SORT_1 var_435 = var_435_arg_0 | var_435_arg_1; [L1275] SORT_1 var_436_arg_0 = var_155; [L1276] SORT_1 var_436_arg_1 = var_435; [L1277] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1278] SORT_1 var_437_arg_0 = var_434; [L1279] SORT_1 var_437_arg_1 = var_436; [L1280] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1281] SORT_1 var_438_arg_0 = var_155; [L1282] SORT_1 var_438_arg_1 = var_435; [L1283] SORT_1 var_438 = var_438_arg_0 | var_438_arg_1; [L1284] SORT_1 var_439_arg_0 = var_159; [L1285] SORT_1 var_439_arg_1 = var_438; [L1286] SORT_1 var_439 = var_439_arg_0 & var_439_arg_1; [L1287] SORT_1 var_440_arg_0 = var_437; [L1288] SORT_1 var_440_arg_1 = var_439; [L1289] SORT_1 var_440 = var_440_arg_0 | var_440_arg_1; [L1290] SORT_1 var_441_arg_0 = var_159; [L1291] SORT_1 var_441_arg_1 = var_438; [L1292] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1293] SORT_1 var_442_arg_0 = var_163; [L1294] SORT_1 var_442_arg_1 = var_441; [L1295] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1296] SORT_1 var_443_arg_0 = var_440; [L1297] SORT_1 var_443_arg_1 = var_442; [L1298] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1299] SORT_1 var_444_arg_0 = var_163; [L1300] SORT_1 var_444_arg_1 = var_441; [L1301] SORT_1 var_444 = var_444_arg_0 | var_444_arg_1; [L1302] SORT_1 var_445_arg_0 = var_167; [L1303] SORT_1 var_445_arg_1 = var_444; [L1304] SORT_1 var_445 = var_445_arg_0 & var_445_arg_1; [L1305] SORT_1 var_446_arg_0 = var_443; [L1306] SORT_1 var_446_arg_1 = var_445; [L1307] SORT_1 var_446 = var_446_arg_0 | var_446_arg_1; [L1308] SORT_1 var_447_arg_0 = var_167; [L1309] SORT_1 var_447_arg_1 = var_444; [L1310] SORT_1 var_447 = var_447_arg_0 | var_447_arg_1; [L1311] SORT_1 var_448_arg_0 = var_172; [L1312] SORT_1 var_448_arg_1 = var_447; [L1313] SORT_1 var_448 = var_448_arg_0 & var_448_arg_1; [L1314] SORT_1 var_449_arg_0 = var_446; [L1315] SORT_1 var_449_arg_1 = var_448; [L1316] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1317] SORT_1 var_450_arg_0 = var_172; [L1318] SORT_1 var_450_arg_1 = var_447; [L1319] SORT_1 var_450 = var_450_arg_0 | var_450_arg_1; [L1320] SORT_1 var_451_arg_0 = var_176; [L1321] SORT_1 var_451_arg_1 = var_450; [L1322] SORT_1 var_451 = var_451_arg_0 & var_451_arg_1; [L1323] SORT_1 var_452_arg_0 = var_449; [L1324] SORT_1 var_452_arg_1 = var_451; [L1325] SORT_1 var_452 = var_452_arg_0 | var_452_arg_1; [L1326] SORT_1 var_453_arg_0 = var_176; [L1327] SORT_1 var_453_arg_1 = var_450; [L1328] SORT_1 var_453 = var_453_arg_0 | var_453_arg_1; [L1329] SORT_1 var_454_arg_0 = var_180; [L1330] SORT_1 var_454_arg_1 = var_453; [L1331] SORT_1 var_454 = var_454_arg_0 & var_454_arg_1; [L1332] SORT_1 var_455_arg_0 = var_452; [L1333] SORT_1 var_455_arg_1 = var_454; [L1334] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1335] SORT_1 var_456_arg_0 = var_427; [L1336] SORT_1 var_456_arg_1 = ~var_455; [L1337] var_456_arg_1 = var_456_arg_1 & mask_SORT_1 [L1338] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1339] SORT_1 var_457_arg_0 = var_180; [L1340] SORT_1 var_457_arg_1 = var_453; [L1341] SORT_1 var_457 = var_457_arg_0 | var_457_arg_1; [L1342] SORT_1 var_458_arg_0 = var_456; [L1343] SORT_1 var_458_arg_1 = var_457; [L1344] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1345] SORT_1 var_459_arg_0 = var_191; [L1346] SORT_1 var_459_arg_1 = var_186; [L1347] SORT_1 var_459 = var_459_arg_0 & var_459_arg_1; [L1348] SORT_1 var_460_arg_0 = var_191; [L1349] SORT_1 var_460_arg_1 = var_186; [L1350] SORT_1 var_460 = var_460_arg_0 | var_460_arg_1; [L1351] SORT_1 var_461_arg_0 = var_195; [L1352] SORT_1 var_461_arg_1 = var_460; [L1353] SORT_1 var_461 = var_461_arg_0 & var_461_arg_1; [L1354] SORT_1 var_462_arg_0 = var_459; [L1355] SORT_1 var_462_arg_1 = var_461; [L1356] SORT_1 var_462 = var_462_arg_0 | var_462_arg_1; [L1357] SORT_1 var_463_arg_0 = var_195; [L1358] SORT_1 var_463_arg_1 = var_460; [L1359] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1360] SORT_1 var_464_arg_0 = var_199; [L1361] SORT_1 var_464_arg_1 = var_463; [L1362] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1363] SORT_1 var_465_arg_0 = var_462; [L1364] SORT_1 var_465_arg_1 = var_464; [L1365] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1366] SORT_1 var_466_arg_0 = var_199; [L1367] SORT_1 var_466_arg_1 = var_463; [L1368] SORT_1 var_466 = var_466_arg_0 | var_466_arg_1; [L1369] SORT_1 var_467_arg_0 = var_202; [L1370] SORT_1 var_467_arg_1 = var_466; [L1371] SORT_1 var_467 = var_467_arg_0 & var_467_arg_1; [L1372] SORT_1 var_468_arg_0 = var_465; [L1373] SORT_1 var_468_arg_1 = var_467; [L1374] SORT_1 var_468 = var_468_arg_0 | var_468_arg_1; [L1375] SORT_1 var_469_arg_0 = var_458; [L1376] SORT_1 var_469_arg_1 = ~var_468; [L1377] var_469_arg_1 = var_469_arg_1 & mask_SORT_1 [L1378] SORT_1 var_469 = var_469_arg_0 & var_469_arg_1; [L1379] SORT_1 var_470_arg_0 = var_202; [L1380] SORT_1 var_470_arg_1 = var_466; [L1381] SORT_1 var_470 = var_470_arg_0 | var_470_arg_1; [L1382] SORT_1 var_471_arg_0 = var_469; [L1383] SORT_1 var_471_arg_1 = var_470; [L1384] SORT_1 var_471 = var_471_arg_0 & var_471_arg_1; [L1385] SORT_1 var_472_arg_0 = var_418; [L1386] SORT_1 var_472_arg_1 = var_471; [L1387] SORT_1 var_472 = var_472_arg_0 & var_472_arg_1; [L1388] SORT_1 var_473_arg_0 = var_472; [L1389] SORT_1 var_473_arg_1 = ~state_55; [L1390] var_473_arg_1 = var_473_arg_1 & mask_SORT_1 [L1391] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1392] SORT_1 next_474_arg_1 = ~var_473; [L1393] next_474_arg_1 = next_474_arg_1 & mask_SORT_1 [L1395] state_6 = next_80_arg_1 [L1396] state_8 = next_97_arg_1 [L1397] state_10 = next_98_arg_1 [L1398] state_12 = next_110_arg_1 [L1399] state_15 = next_118_arg_1 [L1400] state_17 = next_123_arg_1 [L1401] state_19 = next_127_arg_1 [L1402] state_21 = next_129_arg_1 [L1403] state_23 = next_135_arg_1 [L1404] state_25 = next_140_arg_1 [L1405] state_27 = next_145_arg_1 [L1406] state_29 = next_149_arg_1 [L1407] state_31 = next_156_arg_1 [L1408] state_33 = next_160_arg_1 [L1409] state_35 = next_164_arg_1 [L1410] state_37 = next_168_arg_1 [L1411] state_39 = next_173_arg_1 [L1412] state_41 = next_177_arg_1 [L1413] state_43 = next_181_arg_1 [L1414] state_45 = next_187_arg_1 [L1415] state_47 = next_192_arg_1 [L1416] state_49 = next_196_arg_1 [L1417] state_51 = next_200_arg_1 [L1418] state_53 = next_203_arg_1 [L1419] state_55 = next_474_arg_1 [L158] input_70 = __VERIFIER_nondet_uchar() [L159] input_70 = input_70 & mask_SORT_1 [L160] input_72 = __VERIFIER_nondet_uchar() [L161] input_72 = input_72 & mask_SORT_1 [L162] input_73 = __VERIFIER_nondet_uchar() [L163] input_73 = input_73 & mask_SORT_1 [L164] input_75 = __VERIFIER_nondet_uchar() [L165] input_75 = input_75 & mask_SORT_1 [L166] input_81 = __VERIFIER_nondet_uchar() [L167] input_81 = input_81 & mask_SORT_1 [L168] input_82 = __VERIFIER_nondet_uchar() [L169] input_82 = input_82 & mask_SORT_1 [L170] input_83 = __VERIFIER_nondet_uchar() [L171] input_83 = input_83 & mask_SORT_1 [L172] input_88 = __VERIFIER_nondet_uchar() [L173] input_88 = input_88 & mask_SORT_1 [L174] input_99 = __VERIFIER_nondet_uchar() [L175] input_99 = input_99 & mask_SORT_1 [L176] input_101 = __VERIFIER_nondet_uchar() [L177] input_101 = input_101 & mask_SORT_1 [L178] input_104 = __VERIFIER_nondet_uchar() [L179] input_104 = input_104 & mask_SORT_1 [L180] input_111 = __VERIFIER_nondet_uchar() [L181] input_116 = __VERIFIER_nondet_uchar() [L182] input_120 = __VERIFIER_nondet_uchar() [L183] input_133 = __VERIFIER_nondet_uchar() [L184] input_143 = __VERIFIER_nondet_uchar() [L185] input_147 = __VERIFIER_nondet_uchar() [L186] input_152 = __VERIFIER_nondet_uchar() [L187] input_154 = __VERIFIER_nondet_uchar() [L188] input_158 = __VERIFIER_nondet_uchar() [L189] input_162 = __VERIFIER_nondet_uchar() [L190] input_166 = __VERIFIER_nondet_uchar() [L191] input_175 = __VERIFIER_nondet_uchar() [L192] input_182 = __VERIFIER_nondet_uchar() [L193] input_184 = __VERIFIER_nondet_uchar() [L194] input_190 = __VERIFIER_nondet_uchar() [L197] SORT_3 var_59_arg_0 = state_12; [L198] SORT_3 var_59_arg_1 = var_58; [L199] SORT_4 var_59 = ((SORT_4)var_59_arg_0 << 16) | var_59_arg_1; [L200] SORT_4 var_61_arg_0 = var_59; [L201] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L201] var_61_arg_0 = (var_61_arg_0 & msb_SORT_4) ? (var_61_arg_0 | ~mask_SORT_4) : (var_61_arg_0 & mask_SORT_4) [L202] SORT_4 var_61_arg_1 = var_60; [L203] SORT_4 var_61 = (int)var_61_arg_0 >> var_61_arg_1; [L204] EXPR (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L204] var_61 = (var_61_arg_0 & msb_SORT_4) ? (var_61 | ~(mask_SORT_4 >> var_61_arg_1)) : var_61 [L205] var_61 = var_61 & mask_SORT_4 [L206] SORT_4 var_62_arg_0 = var_57; [L207] SORT_4 var_62_arg_1 = var_61; [L208] SORT_1 var_62 = var_62_arg_0 == var_62_arg_1; [L209] SORT_1 var_65_arg_0 = state_35; [L210] SORT_4 var_65_arg_1 = var_63; [L211] SORT_4 var_65_arg_2 = var_64; [L212] EXPR var_65_arg_0 ? var_65_arg_1 : var_65_arg_2 [L212] SORT_4 var_65 = var_65_arg_0 ? var_65_arg_1 : var_65_arg_2; [L213] var_65 = var_65 & mask_SORT_4 [L214] SORT_4 var_66_arg_0 = var_63; [L215] SORT_4 var_66_arg_1 = var_65; [L216] SORT_1 var_66 = var_66_arg_0 == var_66_arg_1; [L217] SORT_1 var_67_arg_0 = ~var_62; [L218] var_67_arg_0 = var_67_arg_0 & mask_SORT_1 [L219] SORT_1 var_67_arg_1 = var_66; [L220] SORT_1 var_67 = var_67_arg_0 & var_67_arg_1; [L221] SORT_1 var_68_arg_0 = ~state_55; [L222] var_68_arg_0 = var_68_arg_0 & mask_SORT_1 [L223] SORT_1 var_68_arg_1 = var_67; [L224] SORT_1 var_68 = var_68_arg_0 & var_68_arg_1; [L225] var_68 = var_68 & mask_SORT_1 [L226] SORT_1 bad_69_arg_0 = var_68; [L227] CALL __VERIFIER_assert(!(bad_69_arg_0)) [L20] COND TRUE !(cond) [L20] reach_error() - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 51 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 349.1s, OverallIterations: 14, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 37.2s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2398 SdHoareTripleChecker+Valid, 2.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2398 mSDsluCounter, 8509 SdHoareTripleChecker+Invalid, 2.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 1078 IncrementalHoareTripleChecker+Unchecked, 7452 mSDsCounter, 18 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 405 IncrementalHoareTripleChecker+Invalid, 1501 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 18 mSolverCounterUnsat, 1057 mSDtfsCounter, 405 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 2126 GetRequests, 1849 SyntacticMatches, 29 SemanticMatches, 248 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2356 ImplicationChecksByTransitivity, 264.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=484occurred in iteration=13, InterpolantAutomatonStates: 139, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 13 MinimizatonAttempts, 617 StatesRemovedByMinimization, 7 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 5.5s SsaConstructionTime, 9.6s SatisfiabilityAnalysisTime, 281.5s InterpolantComputationTime, 1232 NumberOfCodeBlocks, 1232 NumberOfCodeBlocksAsserted, 26 NumberOfCheckSat, 2107 ConstructedInterpolants, 1484 QuantifiedInterpolants, 83767 SizeOfPredicates, 958 NumberOfNonLiveVariables, 29852 ConjunctsInSsa, 814 ConjunctsInUnsatCore, 43 InterpolantComputations, 8 PerfectInterpolantSequences, 125/312 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN