./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 5e519f3a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cf45e19d1839caf080de34cfa9fd4f236bd55e600d76c016a3ed5d411a793a9e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:38:15,424 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:38:15,427 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:38:15,455 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:38:15,456 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:38:15,457 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:38:15,458 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:38:15,461 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:38:15,463 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:38:15,464 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:38:15,465 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:38:15,466 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:38:15,467 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:38:15,468 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:38:15,470 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:38:15,471 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:38:15,472 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:38:15,473 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:38:15,475 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:38:15,477 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:38:15,479 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:38:15,481 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:38:15,482 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:38:15,483 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:38:15,488 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:38:15,495 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:38:15,496 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:38:15,497 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:38:15,497 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:38:15,499 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:38:15,499 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:38:15,500 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:38:15,501 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:38:15,507 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:38:15,508 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:38:15,509 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:38:15,510 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:38:15,510 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:38:15,510 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:38:15,512 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:38:15,514 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:38:15,515 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Default.epf [2022-11-03 02:38:15,554 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:38:15,560 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:38:15,561 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:38:15,561 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:38:15,562 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:38:15,562 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:38:15,562 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:38:15,563 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:38:15,563 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:38:15,563 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-03 02:38:15,564 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:38:15,564 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:38:15,565 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-03 02:38:15,565 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-03 02:38:15,565 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:38:15,565 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-03 02:38:15,566 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-03 02:38:15,566 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-03 02:38:15,567 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:38:15,567 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-03 02:38:15,567 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:38:15,567 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:38:15,568 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:38:15,568 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:38:15,568 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:38:15,568 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:38:15,568 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:38:15,570 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:38:15,570 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:38:15,571 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:38:15,571 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:38:15,571 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-03 02:38:15,572 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:38:15,572 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:38:15,573 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-03 02:38:15,573 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-03 02:38:15,573 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:38:15,573 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:38:15,574 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cf45e19d1839caf080de34cfa9fd4f236bd55e600d76c016a3ed5d411a793a9e [2022-11-03 02:38:15,907 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:38:15,950 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:38:15,953 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:38:15,954 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:38:15,955 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:38:15,956 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:38:16,036 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/42ba6792c/43c7a224329d4bfa8d943266cfb6a255/FLAGdb87950c9 [2022-11-03 02:38:16,681 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:38:16,682 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:38:16,704 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/42ba6792c/43c7a224329d4bfa8d943266cfb6a255/FLAGdb87950c9 [2022-11-03 02:38:16,896 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/42ba6792c/43c7a224329d4bfa8d943266cfb6a255 [2022-11-03 02:38:16,899 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:38:16,901 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:38:16,905 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:38:16,905 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:38:16,909 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:38:16,910 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:38:16" (1/1) ... [2022-11-03 02:38:16,912 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3098978c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:16, skipping insertion in model container [2022-11-03 02:38:16,912 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:38:16" (1/1) ... [2022-11-03 02:38:16,922 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:38:17,007 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:38:17,256 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c[1014,1027] [2022-11-03 02:38:17,662 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:38:17,666 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:38:17,677 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c[1014,1027] [2022-11-03 02:38:17,827 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:38:17,840 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:38:17,840 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17 WrapperNode [2022-11-03 02:38:17,840 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:38:17,842 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:38:17,842 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:38:17,842 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:38:17,850 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:17,916 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,211 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2014 [2022-11-03 02:38:18,212 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:38:18,213 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:38:18,213 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:38:18,214 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:38:18,225 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,225 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,255 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,255 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,403 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,424 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,490 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,505 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,593 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:38:18,595 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:38:18,595 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:38:18,595 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:38:18,596 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (1/1) ... [2022-11-03 02:38:18,603 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:38:18,617 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:38:18,633 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:38:18,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:38:18,678 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:38:18,679 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:38:19,106 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:38:19,108 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:42:09,187 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:42:32,786 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:42:32,786 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:42:32,789 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:42:32 BoogieIcfgContainer [2022-11-03 02:42:32,789 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:42:32,791 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:42:32,791 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:42:32,796 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:42:32,797 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:38:16" (1/3) ... [2022-11-03 02:42:32,797 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@60426088 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:42:32, skipping insertion in model container [2022-11-03 02:42:32,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:38:17" (2/3) ... [2022-11-03 02:42:32,798 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@60426088 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:42:32, skipping insertion in model container [2022-11-03 02:42:32,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:42:32" (3/3) ... [2022-11-03 02:42:32,800 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:42:32,817 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:42:32,817 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:42:32,861 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:42:32,868 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@742b3dc2, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:42:32,868 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:42:32,873 INFO L276 IsEmpty]: Start isEmpty. Operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:42:32,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2022-11-03 02:42:32,879 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:42:32,880 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1] [2022-11-03 02:42:32,881 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:42:32,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:42:32,886 INFO L85 PathProgramCache]: Analyzing trace with hash 13505351, now seen corresponding path program 1 times [2022-11-03 02:42:32,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:42:32,897 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305118785] [2022-11-03 02:42:32,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:42:32,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:42:33,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:42:34,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:42:34,937 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-03 02:42:34,937 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305118785] [2022-11-03 02:42:34,938 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305118785] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:42:34,938 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:42:34,938 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-03 02:42:34,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33243147] [2022-11-03 02:42:34,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:42:34,945 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:42:34,945 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-03 02:42:34,971 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:42:34,972 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:42:34,974 INFO L87 Difference]: Start difference. First operand has 7 states, 5 states have (on average 1.6) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:42:37,284 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.24s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2022-11-03 02:42:37,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:42:37,426 INFO L93 Difference]: Finished difference Result 15 states and 20 transitions. [2022-11-03 02:42:37,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:42:37,429 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 4 [2022-11-03 02:42:37,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:42:37,437 INFO L225 Difference]: With dead ends: 15 [2022-11-03 02:42:37,437 INFO L226 Difference]: Without dead ends: 9 [2022-11-03 02:42:37,439 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:42:37,445 INFO L413 NwaCegarLoop]: 2 mSDtfsCounter, 3 mSDsluCounter, 5 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 1 mSolverCounterUnsat, 1 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 3 SdHoareTripleChecker+Valid, 6 SdHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 1 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:42:37,447 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [3 Valid, 6 Invalid, 9 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 7 Invalid, 1 Unknown, 0 Unchecked, 2.4s Time] [2022-11-03 02:42:37,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states. [2022-11-03 02:42:37,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 8. [2022-11-03 02:42:37,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:42:37,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 8 transitions. [2022-11-03 02:42:37,483 INFO L78 Accepts]: Start accepts. Automaton has 8 states and 8 transitions. Word has length 4 [2022-11-03 02:42:37,483 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:42:37,484 INFO L495 AbstractCegarLoop]: Abstraction has 8 states and 8 transitions. [2022-11-03 02:42:37,484 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:42:37,484 INFO L276 IsEmpty]: Start isEmpty. Operand 8 states and 8 transitions. [2022-11-03 02:42:37,490 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 8 [2022-11-03 02:42:37,491 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:42:37,492 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1] [2022-11-03 02:42:37,492 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-03 02:42:37,492 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:42:37,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:42:37,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1367167352, now seen corresponding path program 1 times [2022-11-03 02:42:37,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-03 02:42:37,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077571038] [2022-11-03 02:42:37,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:42:37,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-03 02:46:24,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:46:24,721 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-03 02:49:29,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-03 02:49:30,194 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-03 02:49:30,194 INFO L359 BasicCegarLoop]: Counterexample is feasible [2022-11-03 02:49:30,197 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-03 02:49:30,199 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-03 02:49:30,210 INFO L444 BasicCegarLoop]: Path program histogram: [1, 1] [2022-11-03 02:49:30,214 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-03 02:49:30,351 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:49:30,352 WARN L320 BoogieBacktranslator]: Removing null node from list of ATEs: ATE program state null [2022-11-03 02:49:30,450 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 03.11 02:49:30 BoogieIcfgContainer [2022-11-03 02:49:30,451 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-03 02:49:30,453 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-03 02:49:30,453 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-03 02:49:30,453 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-03 02:49:30,454 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:42:32" (3/4) ... [2022-11-03 02:49:30,458 INFO L140 WitnessPrinter]: No result that supports witness generation found [2022-11-03 02:49:30,458 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-03 02:49:30,460 INFO L158 Benchmark]: Toolchain (without parser) took 673558.47ms. Allocated memory was 130.0MB in the beginning and 3.6GB in the end (delta: 3.4GB). Free memory was 86.4MB in the beginning and 2.6GB in the end (delta: -2.5GB). Peak memory consumption was 944.3MB. Max. memory is 16.1GB. [2022-11-03 02:49:30,461 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 130.0MB. Free memory is still 105.5MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:49:30,470 INFO L158 Benchmark]: CACSL2BoogieTranslator took 935.69ms. Allocated memory is still 130.0MB. Free memory was 86.2MB in the beginning and 55.0MB in the end (delta: 31.2MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. [2022-11-03 02:49:30,471 INFO L158 Benchmark]: Boogie Procedure Inliner took 370.09ms. Allocated memory is still 130.0MB. Free memory was 55.0MB in the beginning and 58.7MB in the end (delta: -3.8MB). Peak memory consumption was 14.8MB. Max. memory is 16.1GB. [2022-11-03 02:49:30,472 INFO L158 Benchmark]: Boogie Preprocessor took 381.23ms. Allocated memory was 130.0MB in the beginning and 197.1MB in the end (delta: 67.1MB). Free memory was 58.7MB in the beginning and 131.9MB in the end (delta: -73.2MB). Peak memory consumption was 56.3MB. Max. memory is 16.1GB. [2022-11-03 02:49:30,473 INFO L158 Benchmark]: RCFGBuilder took 254194.41ms. Allocated memory was 197.1MB in the beginning and 3.1GB in the end (delta: 2.9GB). Free memory was 131.9MB in the beginning and 2.8GB in the end (delta: -2.7GB). Peak memory consumption was 1.6GB. Max. memory is 16.1GB. [2022-11-03 02:49:30,473 INFO L158 Benchmark]: TraceAbstraction took 417660.51ms. Allocated memory was 3.1GB in the beginning and 3.6GB in the end (delta: 522.2MB). Free memory was 2.8GB in the beginning and 2.6GB in the end (delta: 230.4MB). Peak memory consumption was 2.2GB. Max. memory is 16.1GB. [2022-11-03 02:49:30,474 INFO L158 Benchmark]: Witness Printer took 5.82ms. Allocated memory is still 3.6GB. Free memory is still 2.6GB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-03 02:49:30,476 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 130.0MB. Free memory is still 105.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 935.69ms. Allocated memory is still 130.0MB. Free memory was 86.2MB in the beginning and 55.0MB in the end (delta: 31.2MB). Peak memory consumption was 29.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 370.09ms. Allocated memory is still 130.0MB. Free memory was 55.0MB in the beginning and 58.7MB in the end (delta: -3.8MB). Peak memory consumption was 14.8MB. Max. memory is 16.1GB. * Boogie Preprocessor took 381.23ms. Allocated memory was 130.0MB in the beginning and 197.1MB in the end (delta: 67.1MB). Free memory was 58.7MB in the beginning and 131.9MB in the end (delta: -73.2MB). Peak memory consumption was 56.3MB. Max. memory is 16.1GB. * RCFGBuilder took 254194.41ms. Allocated memory was 197.1MB in the beginning and 3.1GB in the end (delta: 2.9GB). Free memory was 131.9MB in the beginning and 2.8GB in the end (delta: -2.7GB). Peak memory consumption was 1.6GB. Max. memory is 16.1GB. * TraceAbstraction took 417660.51ms. Allocated memory was 3.1GB in the beginning and 3.6GB in the end (delta: 522.2MB). Free memory was 2.8GB in the beginning and 2.6GB in the end (delta: 230.4MB). Peak memory consumption was 2.2GB. Max. memory is 16.1GB. * Witness Printer took 5.82ms. Allocated memory is still 3.6GB. Free memory is still 2.6GB. There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - UnprovableResult [Line: 20]: Unable to prove that call to reach_error is unreachable Unable to prove that call to reach_error is unreachable Reason: overapproximation of bitwiseComplement at line 231, overapproximation of bitwiseOr at line 273, overapproximation of bitwiseAnd at line 183. Possible FailurePath: [L25] const SORT_1 mask_SORT_1 = (SORT_1)-1 >> (sizeof(SORT_1) * 8 - 1); [L26] const SORT_1 msb_SORT_1 = (SORT_1)1 << (1 - 1); [L28] const SORT_2 mask_SORT_2 = (SORT_2)-1 >> (sizeof(SORT_2) * 8 - 8); [L29] const SORT_2 msb_SORT_2 = (SORT_2)1 << (8 - 1); [L31] const SORT_3 mask_SORT_3 = (SORT_3)-1 >> (sizeof(SORT_3) * 8 - 24); [L32] const SORT_3 msb_SORT_3 = (SORT_3)1 << (24 - 1); [L34] const SORT_4 mask_SORT_4 = (SORT_4)-1 >> (sizeof(SORT_4) * 8 - 32); [L35] const SORT_4 msb_SORT_4 = (SORT_4)1 << (32 - 1); [L37] const SORT_2 var_5 = 0; [L38] const SORT_1 var_28 = 0; [L39] const SORT_2 var_80 = 2; [L40] const SORT_2 var_82 = 1; [L41] const SORT_2 var_97 = 0; [L42] const SORT_4 var_107 = 1; [L43] const SORT_3 var_108 = 0; [L44] const SORT_2 var_128 = 25; [L45] const SORT_2 var_129 = 15; [L46] const SORT_2 var_130 = 20; [L47] const SORT_2 var_131 = 5; [L48] const SORT_4 var_158 = 0; [L49] const SORT_4 var_310 = 10; [L50] const SORT_4 var_315 = 5; [L51] const SORT_4 var_360 = 3; [L53] SORT_1 input_78; [L54] SORT_1 input_79; [L55] SORT_1 input_81; [L56] SORT_1 input_83; [L57] SORT_1 input_84; [L58] SORT_1 input_85; [L59] SORT_1 input_86; [L60] SORT_1 input_98; [L61] SORT_1 input_99; [L62] SORT_1 input_100; [L63] SORT_1 input_101; [L64] SORT_1 input_102; [L65] SORT_1 input_103; [L66] SORT_1 input_104; [L67] SORT_1 input_105; [L68] SORT_1 input_106; [L69] SORT_1 input_149; [L70] SORT_1 input_151; [L71] SORT_1 input_154; [L72] SORT_1 input_156; [L73] SORT_1 input_192; [L74] SORT_1 input_222; [L75] SORT_1 input_225; [L77] SORT_2 state_6 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L78] SORT_2 state_8 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L79] SORT_2 state_10 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L80] SORT_2 state_12 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L81] SORT_2 state_14 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L82] SORT_2 state_16 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L83] SORT_2 state_18 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L84] SORT_2 state_20 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L85] SORT_2 state_22 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L86] SORT_2 state_24 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L87] SORT_2 state_26 = __VERIFIER_nondet_uchar() & mask_SORT_2; [L88] SORT_1 state_29 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L89] SORT_1 state_31 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L90] SORT_1 state_33 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L91] SORT_1 state_35 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L92] SORT_1 state_37 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L93] SORT_1 state_39 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L94] SORT_1 state_41 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L95] SORT_1 state_43 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L96] SORT_1 state_45 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L97] SORT_1 state_47 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L98] SORT_1 state_49 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L99] SORT_1 state_51 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L100] SORT_1 state_53 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L101] SORT_1 state_55 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L102] SORT_1 state_57 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L103] SORT_1 state_59 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L104] SORT_1 state_61 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L105] SORT_1 state_63 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L106] SORT_1 state_65 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L107] SORT_1 state_67 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L108] SORT_1 state_69 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L109] SORT_1 state_71 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L110] SORT_1 state_73 = __VERIFIER_nondet_uchar() & mask_SORT_1; [L112] SORT_2 init_7_arg_1 = var_5; [L113] state_6 = init_7_arg_1 [L114] SORT_2 init_9_arg_1 = var_5; [L115] state_8 = init_9_arg_1 [L116] SORT_2 init_11_arg_1 = var_5; [L117] state_10 = init_11_arg_1 [L118] SORT_2 init_13_arg_1 = var_5; [L119] state_12 = init_13_arg_1 [L120] SORT_2 init_15_arg_1 = var_5; [L121] state_14 = init_15_arg_1 [L122] SORT_2 init_17_arg_1 = var_5; [L123] state_16 = init_17_arg_1 [L124] SORT_2 init_19_arg_1 = var_5; [L125] state_18 = init_19_arg_1 [L126] SORT_2 init_21_arg_1 = var_5; [L127] state_20 = init_21_arg_1 [L128] SORT_2 init_23_arg_1 = var_5; [L129] state_22 = init_23_arg_1 [L130] SORT_2 init_25_arg_1 = var_5; [L131] state_24 = init_25_arg_1 [L132] SORT_2 init_27_arg_1 = var_5; [L133] state_26 = init_27_arg_1 [L134] SORT_1 init_30_arg_1 = var_28; [L135] state_29 = init_30_arg_1 [L136] SORT_1 init_32_arg_1 = var_28; [L137] state_31 = init_32_arg_1 [L138] SORT_1 init_34_arg_1 = var_28; [L139] state_33 = init_34_arg_1 [L140] SORT_1 init_36_arg_1 = var_28; [L141] state_35 = init_36_arg_1 [L142] SORT_1 init_38_arg_1 = var_28; [L143] state_37 = init_38_arg_1 [L144] SORT_1 init_40_arg_1 = var_28; [L145] state_39 = init_40_arg_1 [L146] SORT_1 init_42_arg_1 = var_28; [L147] state_41 = init_42_arg_1 [L148] SORT_1 init_44_arg_1 = var_28; [L149] state_43 = init_44_arg_1 [L150] SORT_1 init_46_arg_1 = var_28; [L151] state_45 = init_46_arg_1 [L152] SORT_1 init_48_arg_1 = var_28; [L153] state_47 = init_48_arg_1 [L154] SORT_1 init_50_arg_1 = var_28; [L155] state_49 = init_50_arg_1 [L156] SORT_1 init_52_arg_1 = var_28; [L157] state_51 = init_52_arg_1 [L158] SORT_1 init_54_arg_1 = var_28; [L159] state_53 = init_54_arg_1 [L160] SORT_1 init_56_arg_1 = var_28; [L161] state_55 = init_56_arg_1 [L162] SORT_1 init_58_arg_1 = var_28; [L163] state_57 = init_58_arg_1 [L164] SORT_1 init_60_arg_1 = var_28; [L165] state_59 = init_60_arg_1 [L166] SORT_1 init_62_arg_1 = var_28; [L167] state_61 = init_62_arg_1 [L168] SORT_1 init_64_arg_1 = var_28; [L169] state_63 = init_64_arg_1 [L170] SORT_1 init_66_arg_1 = var_28; [L171] state_65 = init_66_arg_1 [L172] SORT_1 init_68_arg_1 = var_28; [L173] state_67 = init_68_arg_1 [L174] SORT_1 init_70_arg_1 = var_28; [L175] state_69 = init_70_arg_1 [L176] SORT_1 init_72_arg_1 = var_28; [L177] state_71 = init_72_arg_1 [L178] SORT_1 init_74_arg_1 = var_28; [L179] state_73 = init_74_arg_1 VAL [init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_29=0, state_31=0, state_33=0, state_35=0, state_37=0, state_39=0, state_41=0, state_43=0, state_45=0, state_47=0, state_49=0, state_51=0, state_53=0, state_55=0, state_57=0, state_59=0, state_6=0, state_61=0, state_63=0, state_65=0, state_67=0, state_69=0, state_71=0, state_73=0, state_8=0, var_107=1, var_108=0, var_128=25, var_129=15, var_130=20, var_131=5, var_158=0, var_28=0, var_310=10, var_315=5, var_360=3, var_5=0, var_80=2, var_82=1, var_97=0] [L182] input_78 = __VERIFIER_nondet_uchar() [L183] input_78 = input_78 & mask_SORT_1 [L184] input_79 = __VERIFIER_nondet_uchar() [L185] input_79 = input_79 & mask_SORT_1 [L186] input_81 = __VERIFIER_nondet_uchar() [L187] input_81 = input_81 & mask_SORT_1 [L188] input_83 = __VERIFIER_nondet_uchar() [L189] input_83 = input_83 & mask_SORT_1 [L190] input_84 = __VERIFIER_nondet_uchar() [L191] input_84 = input_84 & mask_SORT_1 [L192] input_85 = __VERIFIER_nondet_uchar() [L193] input_85 = input_85 & mask_SORT_1 [L194] input_86 = __VERIFIER_nondet_uchar() [L195] input_86 = input_86 & mask_SORT_1 [L196] input_98 = __VERIFIER_nondet_uchar() [L197] input_98 = input_98 & mask_SORT_1 [L198] input_99 = __VERIFIER_nondet_uchar() [L199] input_99 = input_99 & mask_SORT_1 [L200] input_100 = __VERIFIER_nondet_uchar() [L201] input_100 = input_100 & mask_SORT_1 [L202] input_101 = __VERIFIER_nondet_uchar() [L203] input_101 = input_101 & mask_SORT_1 [L204] input_102 = __VERIFIER_nondet_uchar() [L205] input_102 = input_102 & mask_SORT_1 [L206] input_103 = __VERIFIER_nondet_uchar() [L207] input_103 = input_103 & mask_SORT_1 [L208] input_104 = __VERIFIER_nondet_uchar() [L209] input_104 = input_104 & mask_SORT_1 [L210] input_105 = __VERIFIER_nondet_uchar() [L211] input_105 = input_105 & mask_SORT_1 [L212] input_106 = __VERIFIER_nondet_uchar() [L213] input_106 = input_106 & mask_SORT_1 [L214] input_149 = __VERIFIER_nondet_uchar() [L215] input_149 = input_149 & mask_SORT_1 [L216] input_151 = __VERIFIER_nondet_uchar() [L217] input_151 = input_151 & mask_SORT_1 [L218] input_154 = __VERIFIER_nondet_uchar() [L219] input_154 = input_154 & mask_SORT_1 [L220] input_156 = __VERIFIER_nondet_uchar() [L221] input_156 = input_156 & mask_SORT_1 [L222] input_192 = __VERIFIER_nondet_uchar() [L223] input_192 = input_192 & mask_SORT_1 [L224] input_222 = __VERIFIER_nondet_uchar() [L225] input_225 = __VERIFIER_nondet_uchar() [L228] SORT_1 var_75_arg_0 = state_57; [L229] SORT_1 var_75_arg_1 = state_67; [L230] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L231] SORT_1 var_76_arg_0 = ~state_73; [L232] var_76_arg_0 = var_76_arg_0 & mask_SORT_1 [L233] SORT_1 var_76_arg_1 = var_75; [L234] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L235] var_76 = var_76 & mask_SORT_1 [L236] SORT_1 bad_77_arg_0 = var_76; [L237] CALL __VERIFIER_assert(!(bad_77_arg_0)) [L20] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1] [L237] RET __VERIFIER_assert(!(bad_77_arg_0)) [L239] SORT_1 var_87_arg_0 = input_86; [L240] SORT_2 var_87_arg_1 = var_82; [L241] SORT_2 var_87_arg_2 = state_6; [L242] EXPR var_87_arg_0 ? var_87_arg_1 : var_87_arg_2 [L242] SORT_2 var_87 = var_87_arg_0 ? var_87_arg_1 : var_87_arg_2; [L243] SORT_1 var_88_arg_0 = input_85; [L244] SORT_2 var_88_arg_1 = var_82; [L245] SORT_2 var_88_arg_2 = var_87; [L246] EXPR var_88_arg_0 ? var_88_arg_1 : var_88_arg_2 [L246] SORT_2 var_88 = var_88_arg_0 ? var_88_arg_1 : var_88_arg_2; [L247] SORT_1 var_89_arg_0 = input_84; [L248] SORT_2 var_89_arg_1 = var_80; [L249] SORT_2 var_89_arg_2 = var_88; [L250] EXPR var_89_arg_0 ? var_89_arg_1 : var_89_arg_2 [L250] SORT_2 var_89 = var_89_arg_0 ? var_89_arg_1 : var_89_arg_2; [L251] SORT_1 var_90_arg_0 = input_83; [L252] SORT_2 var_90_arg_1 = var_80; [L253] SORT_2 var_90_arg_2 = var_89; [L254] EXPR var_90_arg_0 ? var_90_arg_1 : var_90_arg_2 [L254] SORT_2 var_90 = var_90_arg_0 ? var_90_arg_1 : var_90_arg_2; [L255] SORT_1 var_91_arg_0 = input_81; [L256] SORT_2 var_91_arg_1 = var_82; [L257] SORT_2 var_91_arg_2 = var_90; [L258] EXPR var_91_arg_0 ? var_91_arg_1 : var_91_arg_2 [L258] SORT_2 var_91 = var_91_arg_0 ? var_91_arg_1 : var_91_arg_2; [L259] SORT_1 var_92_arg_0 = input_79; [L260] SORT_2 var_92_arg_1 = var_80; [L261] SORT_2 var_92_arg_2 = var_91; [L262] EXPR var_92_arg_0 ? var_92_arg_1 : var_92_arg_2 [L262] SORT_2 var_92 = var_92_arg_0 ? var_92_arg_1 : var_92_arg_2; [L263] SORT_1 var_93_arg_0 = input_78; [L264] SORT_2 var_93_arg_1 = state_18; [L265] SORT_2 var_93_arg_2 = var_92; [L266] EXPR var_93_arg_0 ? var_93_arg_1 : var_93_arg_2 [L266] SORT_2 var_93 = var_93_arg_0 ? var_93_arg_1 : var_93_arg_2; [L267] var_93 = var_93 & mask_SORT_2 [L268] SORT_2 next_94_arg_1 = var_93; [L269] SORT_2 next_95_arg_1 = state_8; [L270] SORT_2 next_96_arg_1 = state_10; [L271] SORT_3 var_109_arg_0 = var_108; [L272] SORT_2 var_109_arg_1 = state_12; [L273] SORT_4 var_109 = ((SORT_4)var_109_arg_0 << 8) | var_109_arg_1; [L274] var_109 = var_109 & mask_SORT_4 [L275] SORT_4 var_110_arg_0 = var_107; [L276] SORT_4 var_110_arg_1 = var_109; [L277] SORT_4 var_110 = var_110_arg_0 + var_110_arg_1; [L278] SORT_4 var_111_arg_0 = var_110; [L279] SORT_2 var_111 = var_111_arg_0 >> 0; [L280] SORT_1 var_112_arg_0 = input_106; [L281] SORT_2 var_112_arg_1 = var_111; [L282] SORT_2 var_112_arg_2 = state_12; [L283] EXPR var_112_arg_0 ? var_112_arg_1 : var_112_arg_2 [L283] SORT_2 var_112 = var_112_arg_0 ? var_112_arg_1 : var_112_arg_2; [L284] SORT_1 var_113_arg_0 = input_105; [L285] SORT_2 var_113_arg_1 = var_97; [L286] SORT_2 var_113_arg_2 = var_112; [L287] EXPR var_113_arg_0 ? var_113_arg_1 : var_113_arg_2 [L287] SORT_2 var_113 = var_113_arg_0 ? var_113_arg_1 : var_113_arg_2; [L288] SORT_1 var_114_arg_0 = input_104; [L289] SORT_2 var_114_arg_1 = var_97; [L290] SORT_2 var_114_arg_2 = var_113; [L291] EXPR var_114_arg_0 ? var_114_arg_1 : var_114_arg_2 [L291] SORT_2 var_114 = var_114_arg_0 ? var_114_arg_1 : var_114_arg_2; [L292] SORT_1 var_115_arg_0 = input_103; [L293] SORT_2 var_115_arg_1 = var_97; [L294] SORT_2 var_115_arg_2 = var_114; [L295] EXPR var_115_arg_0 ? var_115_arg_1 : var_115_arg_2 [L295] SORT_2 var_115 = var_115_arg_0 ? var_115_arg_1 : var_115_arg_2; [L296] SORT_1 var_116_arg_0 = input_102; [L297] SORT_2 var_116_arg_1 = var_97; [L298] SORT_2 var_116_arg_2 = var_115; [L299] EXPR var_116_arg_0 ? var_116_arg_1 : var_116_arg_2 [L299] SORT_2 var_116 = var_116_arg_0 ? var_116_arg_1 : var_116_arg_2; [L300] SORT_1 var_117_arg_0 = input_86; [L301] SORT_2 var_117_arg_1 = var_97; [L302] SORT_2 var_117_arg_2 = var_116; [L303] EXPR var_117_arg_0 ? var_117_arg_1 : var_117_arg_2 [L303] SORT_2 var_117 = var_117_arg_0 ? var_117_arg_1 : var_117_arg_2; [L304] SORT_1 var_118_arg_0 = input_85; [L305] SORT_2 var_118_arg_1 = var_97; [L306] SORT_2 var_118_arg_2 = var_117; [L307] EXPR var_118_arg_0 ? var_118_arg_1 : var_118_arg_2 [L307] SORT_2 var_118 = var_118_arg_0 ? var_118_arg_1 : var_118_arg_2; [L308] SORT_1 var_119_arg_0 = input_84; [L309] SORT_2 var_119_arg_1 = var_97; [L310] SORT_2 var_119_arg_2 = var_118; [L311] EXPR var_119_arg_0 ? var_119_arg_1 : var_119_arg_2 [L311] SORT_2 var_119 = var_119_arg_0 ? var_119_arg_1 : var_119_arg_2; [L312] SORT_1 var_120_arg_0 = input_83; [L313] SORT_2 var_120_arg_1 = var_97; [L314] SORT_2 var_120_arg_2 = var_119; [L315] EXPR var_120_arg_0 ? var_120_arg_1 : var_120_arg_2 [L315] SORT_2 var_120 = var_120_arg_0 ? var_120_arg_1 : var_120_arg_2; [L316] SORT_1 var_121_arg_0 = input_101; [L317] SORT_2 var_121_arg_1 = var_97; [L318] SORT_2 var_121_arg_2 = var_120; [L319] EXPR var_121_arg_0 ? var_121_arg_1 : var_121_arg_2 [L319] SORT_2 var_121 = var_121_arg_0 ? var_121_arg_1 : var_121_arg_2; [L320] SORT_1 var_122_arg_0 = input_100; [L321] SORT_2 var_122_arg_1 = var_97; [L322] SORT_2 var_122_arg_2 = var_121; [L323] EXPR var_122_arg_0 ? var_122_arg_1 : var_122_arg_2 [L323] SORT_2 var_122 = var_122_arg_0 ? var_122_arg_1 : var_122_arg_2; [L324] SORT_1 var_123_arg_0 = input_99; [L325] SORT_2 var_123_arg_1 = var_97; [L326] SORT_2 var_123_arg_2 = var_122; [L327] EXPR var_123_arg_0 ? var_123_arg_1 : var_123_arg_2 [L327] SORT_2 var_123 = var_123_arg_0 ? var_123_arg_1 : var_123_arg_2; [L328] SORT_1 var_124_arg_0 = input_98; [L329] SORT_2 var_124_arg_1 = var_97; [L330] SORT_2 var_124_arg_2 = var_123; [L331] EXPR var_124_arg_0 ? var_124_arg_1 : var_124_arg_2 [L331] SORT_2 var_124 = var_124_arg_0 ? var_124_arg_1 : var_124_arg_2; [L332] SORT_1 var_125_arg_0 = input_81; [L333] SORT_2 var_125_arg_1 = var_97; [L334] SORT_2 var_125_arg_2 = var_124; [L335] EXPR var_125_arg_0 ? var_125_arg_1 : var_125_arg_2 [L335] SORT_2 var_125 = var_125_arg_0 ? var_125_arg_1 : var_125_arg_2; [L336] SORT_1 var_126_arg_0 = input_79; [L337] SORT_2 var_126_arg_1 = var_97; [L338] SORT_2 var_126_arg_2 = var_125; [L339] EXPR var_126_arg_0 ? var_126_arg_1 : var_126_arg_2 [L339] SORT_2 var_126 = var_126_arg_0 ? var_126_arg_1 : var_126_arg_2; [L340] var_126 = var_126 & mask_SORT_2 [L341] SORT_2 next_127_arg_1 = var_126; [L342] SORT_1 var_132_arg_0 = input_105; [L343] SORT_2 var_132_arg_1 = var_131; [L344] SORT_2 var_132_arg_2 = state_14; [L345] EXPR var_132_arg_0 ? var_132_arg_1 : var_132_arg_2 [L345] SORT_2 var_132 = var_132_arg_0 ? var_132_arg_1 : var_132_arg_2; [L346] SORT_1 var_133_arg_0 = input_104; [L347] SORT_2 var_133_arg_1 = var_131; [L348] SORT_2 var_133_arg_2 = var_132; [L349] EXPR var_133_arg_0 ? var_133_arg_1 : var_133_arg_2 [L349] SORT_2 var_133 = var_133_arg_0 ? var_133_arg_1 : var_133_arg_2; [L350] SORT_1 var_134_arg_0 = input_86; [L351] SORT_2 var_134_arg_1 = var_130; [L352] SORT_2 var_134_arg_2 = var_133; [L353] EXPR var_134_arg_0 ? var_134_arg_1 : var_134_arg_2 [L353] SORT_2 var_134 = var_134_arg_0 ? var_134_arg_1 : var_134_arg_2; [L354] SORT_1 var_135_arg_0 = input_85; [L355] SORT_2 var_135_arg_1 = var_130; [L356] SORT_2 var_135_arg_2 = var_134; [L357] EXPR var_135_arg_0 ? var_135_arg_1 : var_135_arg_2 [L357] SORT_2 var_135 = var_135_arg_0 ? var_135_arg_1 : var_135_arg_2; [L358] SORT_1 var_136_arg_0 = input_101; [L359] SORT_2 var_136_arg_1 = var_128; [L360] SORT_2 var_136_arg_2 = var_135; [L361] EXPR var_136_arg_0 ? var_136_arg_1 : var_136_arg_2 [L361] SORT_2 var_136 = var_136_arg_0 ? var_136_arg_1 : var_136_arg_2; [L362] SORT_1 var_137_arg_0 = input_99; [L363] SORT_2 var_137_arg_1 = var_129; [L364] SORT_2 var_137_arg_2 = var_136; [L365] EXPR var_137_arg_0 ? var_137_arg_1 : var_137_arg_2 [L365] SORT_2 var_137 = var_137_arg_0 ? var_137_arg_1 : var_137_arg_2; [L366] SORT_1 var_138_arg_0 = input_81; [L367] SORT_2 var_138_arg_1 = var_128; [L368] SORT_2 var_138_arg_2 = var_137; [L369] EXPR var_138_arg_0 ? var_138_arg_1 : var_138_arg_2 [L369] SORT_2 var_138 = var_138_arg_0 ? var_138_arg_1 : var_138_arg_2; [L370] var_138 = var_138 & mask_SORT_2 [L371] SORT_2 next_139_arg_1 = var_138; [L372] SORT_1 var_140_arg_0 = input_103; [L373] SORT_2 var_140_arg_1 = var_131; [L374] SORT_2 var_140_arg_2 = state_16; [L375] EXPR var_140_arg_0 ? var_140_arg_1 : var_140_arg_2 [L375] SORT_2 var_140 = var_140_arg_0 ? var_140_arg_1 : var_140_arg_2; [L376] SORT_1 var_141_arg_0 = input_102; [L377] SORT_2 var_141_arg_1 = var_131; [L378] SORT_2 var_141_arg_2 = var_140; [L379] EXPR var_141_arg_0 ? var_141_arg_1 : var_141_arg_2 [L379] SORT_2 var_141 = var_141_arg_0 ? var_141_arg_1 : var_141_arg_2; [L380] SORT_1 var_142_arg_0 = input_84; [L381] SORT_2 var_142_arg_1 = var_130; [L382] SORT_2 var_142_arg_2 = var_141; [L383] EXPR var_142_arg_0 ? var_142_arg_1 : var_142_arg_2 [L383] SORT_2 var_142 = var_142_arg_0 ? var_142_arg_1 : var_142_arg_2; [L384] SORT_1 var_143_arg_0 = input_83; [L385] SORT_2 var_143_arg_1 = var_130; [L386] SORT_2 var_143_arg_2 = var_142; [L387] EXPR var_143_arg_0 ? var_143_arg_1 : var_143_arg_2 [L387] SORT_2 var_143 = var_143_arg_0 ? var_143_arg_1 : var_143_arg_2; [L388] SORT_1 var_144_arg_0 = input_100; [L389] SORT_2 var_144_arg_1 = var_128; [L390] SORT_2 var_144_arg_2 = var_143; [L391] EXPR var_144_arg_0 ? var_144_arg_1 : var_144_arg_2 [L391] SORT_2 var_144 = var_144_arg_0 ? var_144_arg_1 : var_144_arg_2; [L392] SORT_1 var_145_arg_0 = input_98; [L393] SORT_2 var_145_arg_1 = var_129; [L394] SORT_2 var_145_arg_2 = var_144; [L395] EXPR var_145_arg_0 ? var_145_arg_1 : var_145_arg_2 [L395] SORT_2 var_145 = var_145_arg_0 ? var_145_arg_1 : var_145_arg_2; [L396] SORT_1 var_146_arg_0 = input_79; [L397] SORT_2 var_146_arg_1 = var_128; [L398] SORT_2 var_146_arg_2 = var_145; [L399] EXPR var_146_arg_0 ? var_146_arg_1 : var_146_arg_2 [L399] SORT_2 var_146 = var_146_arg_0 ? var_146_arg_1 : var_146_arg_2; [L400] var_146 = var_146 & mask_SORT_2 [L401] SORT_2 next_147_arg_1 = var_146; [L402] SORT_2 var_148_arg_0 = var_97; [L403] SORT_2 var_148_arg_1 = state_24; [L404] SORT_1 var_148 = var_148_arg_0 == var_148_arg_1; [L405] SORT_1 var_150_arg_0 = var_148; [L406] SORT_1 var_150_arg_1 = input_149; [L407] SORT_1 var_150 = var_150_arg_0 & var_150_arg_1; [L408] var_150 = var_150 & mask_SORT_1 [L409] SORT_1 var_152_arg_0 = var_148; [L410] SORT_1 var_152_arg_1 = input_151; [L411] SORT_1 var_152 = var_152_arg_0 & var_152_arg_1; [L412] var_152 = var_152 & mask_SORT_1 [L413] SORT_2 var_153_arg_0 = var_97; [L414] SORT_2 var_153_arg_1 = state_26; [L415] SORT_1 var_153 = var_153_arg_0 == var_153_arg_1; [L416] SORT_1 var_155_arg_0 = var_153; [L417] SORT_1 var_155_arg_1 = input_154; [L418] SORT_1 var_155 = var_155_arg_0 & var_155_arg_1; [L419] var_155 = var_155 & mask_SORT_1 [L420] SORT_1 var_157_arg_0 = input_156; [L421] SORT_1 var_157_arg_1 = var_153; [L422] SORT_1 var_157 = var_157_arg_0 & var_157_arg_1; [L423] var_157 = var_157 & mask_SORT_1 [L424] SORT_3 var_159_arg_0 = var_108; [L425] SORT_2 var_159_arg_1 = state_26; [L426] SORT_4 var_159 = ((SORT_4)var_159_arg_0 << 8) | var_159_arg_1; [L427] var_159 = var_159 & mask_SORT_4 [L428] SORT_4 var_160_arg_0 = var_107; [L429] SORT_4 var_160_arg_1 = var_159; [L430] SORT_4 var_160 = var_160_arg_0 + var_160_arg_1; [L431] var_160 = var_160 & mask_SORT_4 [L432] SORT_4 var_161_arg_0 = var_158; [L433] SORT_4 var_161_arg_1 = var_160; [L434] SORT_1 var_161 = var_161_arg_0 == var_161_arg_1; [L435] SORT_4 var_162_arg_0 = var_107; [L436] SORT_4 var_162_arg_1 = var_160; [L437] SORT_1 var_162 = var_162_arg_0 == var_162_arg_1; [L438] SORT_1 var_163_arg_0 = var_162; [L439] SORT_2 var_163_arg_1 = state_20; [L440] SORT_2 var_163_arg_2 = state_22; [L441] EXPR var_163_arg_0 ? var_163_arg_1 : var_163_arg_2 [L441] SORT_2 var_163 = var_163_arg_0 ? var_163_arg_1 : var_163_arg_2; [L442] SORT_1 var_164_arg_0 = var_161; [L443] SORT_2 var_164_arg_1 = state_18; [L444] SORT_2 var_164_arg_2 = var_163; [L445] EXPR var_164_arg_0 ? var_164_arg_1 : var_164_arg_2 [L445] SORT_2 var_164 = var_164_arg_0 ? var_164_arg_1 : var_164_arg_2; [L446] SORT_1 var_165_arg_0 = var_157; [L447] SORT_2 var_165_arg_1 = var_164; [L448] SORT_2 var_165_arg_2 = state_18; [L449] EXPR var_165_arg_0 ? var_165_arg_1 : var_165_arg_2 [L449] SORT_2 var_165 = var_165_arg_0 ? var_165_arg_1 : var_165_arg_2; [L450] SORT_1 var_166_arg_0 = var_155; [L451] SORT_2 var_166_arg_1 = var_97; [L452] SORT_2 var_166_arg_2 = var_165; [L453] EXPR var_166_arg_0 ? var_166_arg_1 : var_166_arg_2 [L453] SORT_2 var_166 = var_166_arg_0 ? var_166_arg_1 : var_166_arg_2; [L454] SORT_1 var_167_arg_0 = var_152; [L455] SORT_2 var_167_arg_1 = state_6; [L456] SORT_2 var_167_arg_2 = var_166; [L457] EXPR var_167_arg_0 ? var_167_arg_1 : var_167_arg_2 [L457] SORT_2 var_167 = var_167_arg_0 ? var_167_arg_1 : var_167_arg_2; [L458] SORT_1 var_168_arg_0 = var_150; [L459] SORT_2 var_168_arg_1 = state_6; [L460] SORT_2 var_168_arg_2 = var_167; [L461] EXPR var_168_arg_0 ? var_168_arg_1 : var_168_arg_2 [L461] SORT_2 var_168 = var_168_arg_0 ? var_168_arg_1 : var_168_arg_2; [L462] SORT_2 next_169_arg_1 = var_168; [L463] SORT_2 var_170_arg_0 = var_82; [L464] SORT_2 var_170_arg_1 = state_24; [L465] SORT_1 var_170 = var_170_arg_0 == var_170_arg_1; [L466] SORT_1 var_171_arg_0 = var_170; [L467] SORT_1 var_171_arg_1 = input_149; [L468] SORT_1 var_171 = var_171_arg_0 & var_171_arg_1; [L469] var_171 = var_171 & mask_SORT_1 [L470] SORT_1 var_172_arg_0 = input_151; [L471] SORT_1 var_172_arg_1 = var_170; [L472] SORT_1 var_172 = var_172_arg_0 & var_172_arg_1; [L473] var_172 = var_172 & mask_SORT_1 [L474] SORT_2 var_173_arg_0 = var_82; [L475] SORT_2 var_173_arg_1 = state_26; [L476] SORT_1 var_173 = var_173_arg_0 == var_173_arg_1; [L477] SORT_1 var_174_arg_0 = var_173; [L478] SORT_1 var_174_arg_1 = input_154; [L479] SORT_1 var_174 = var_174_arg_0 & var_174_arg_1; [L480] var_174 = var_174 & mask_SORT_1 [L481] SORT_1 var_175_arg_0 = input_156; [L482] SORT_1 var_175_arg_1 = var_173; [L483] SORT_1 var_175 = var_175_arg_0 & var_175_arg_1; [L484] var_175 = var_175 & mask_SORT_1 [L485] SORT_1 var_176_arg_0 = var_175; [L486] SORT_2 var_176_arg_1 = var_164; [L487] SORT_2 var_176_arg_2 = state_20; [L488] EXPR var_176_arg_0 ? var_176_arg_1 : var_176_arg_2 [L488] SORT_2 var_176 = var_176_arg_0 ? var_176_arg_1 : var_176_arg_2; [L489] SORT_1 var_177_arg_0 = var_174; [L490] SORT_2 var_177_arg_1 = var_97; [L491] SORT_2 var_177_arg_2 = var_176; [L492] EXPR var_177_arg_0 ? var_177_arg_1 : var_177_arg_2 [L492] SORT_2 var_177 = var_177_arg_0 ? var_177_arg_1 : var_177_arg_2; [L493] SORT_1 var_178_arg_0 = var_172; [L494] SORT_2 var_178_arg_1 = state_6; [L495] SORT_2 var_178_arg_2 = var_177; [L496] EXPR var_178_arg_0 ? var_178_arg_1 : var_178_arg_2 [L496] SORT_2 var_178 = var_178_arg_0 ? var_178_arg_1 : var_178_arg_2; [L497] SORT_1 var_179_arg_0 = var_171; [L498] SORT_2 var_179_arg_1 = state_6; [L499] SORT_2 var_179_arg_2 = var_178; [L500] EXPR var_179_arg_0 ? var_179_arg_1 : var_179_arg_2 [L500] SORT_2 var_179 = var_179_arg_0 ? var_179_arg_1 : var_179_arg_2; [L501] SORT_2 next_180_arg_1 = var_179; [L502] SORT_2 var_181_arg_0 = var_80; [L503] SORT_2 var_181_arg_1 = state_24; [L504] SORT_1 var_181 = var_181_arg_0 == var_181_arg_1; [L505] SORT_1 var_182_arg_0 = var_181; [L506] SORT_1 var_182_arg_1 = input_149; [L507] SORT_1 var_182 = var_182_arg_0 & var_182_arg_1; [L508] var_182 = var_182 & mask_SORT_1 [L509] SORT_1 var_183_arg_0 = input_151; [L510] SORT_1 var_183_arg_1 = var_181; [L511] SORT_1 var_183 = var_183_arg_0 & var_183_arg_1; [L512] var_183 = var_183 & mask_SORT_1 [L513] SORT_2 var_184_arg_0 = var_80; [L514] SORT_2 var_184_arg_1 = state_26; [L515] SORT_1 var_184 = var_184_arg_0 == var_184_arg_1; [L516] SORT_1 var_185_arg_0 = var_184; [L517] SORT_1 var_185_arg_1 = input_154; [L518] SORT_1 var_185 = var_185_arg_0 & var_185_arg_1; [L519] var_185 = var_185 & mask_SORT_1 [L520] SORT_1 var_186_arg_0 = input_156; [L521] SORT_1 var_186_arg_1 = var_184; [L522] SORT_1 var_186 = var_186_arg_0 & var_186_arg_1; [L523] var_186 = var_186 & mask_SORT_1 [L524] SORT_1 var_187_arg_0 = var_186; [L525] SORT_2 var_187_arg_1 = var_164; [L526] SORT_2 var_187_arg_2 = state_22; [L527] EXPR var_187_arg_0 ? var_187_arg_1 : var_187_arg_2 [L527] SORT_2 var_187 = var_187_arg_0 ? var_187_arg_1 : var_187_arg_2; [L528] SORT_1 var_188_arg_0 = var_185; [L529] SORT_2 var_188_arg_1 = var_97; [L530] SORT_2 var_188_arg_2 = var_187; [L531] EXPR var_188_arg_0 ? var_188_arg_1 : var_188_arg_2 [L531] SORT_2 var_188 = var_188_arg_0 ? var_188_arg_1 : var_188_arg_2; [L532] SORT_1 var_189_arg_0 = var_183; [L533] SORT_2 var_189_arg_1 = state_6; [L534] SORT_2 var_189_arg_2 = var_188; [L535] EXPR var_189_arg_0 ? var_189_arg_1 : var_189_arg_2 [L535] SORT_2 var_189 = var_189_arg_0 ? var_189_arg_1 : var_189_arg_2; [L536] SORT_1 var_190_arg_0 = var_182; [L537] SORT_2 var_190_arg_1 = state_6; [L538] SORT_2 var_190_arg_2 = var_189; [L539] EXPR var_190_arg_0 ? var_190_arg_1 : var_190_arg_2 [L539] SORT_2 var_190 = var_190_arg_0 ? var_190_arg_1 : var_190_arg_2; [L540] SORT_2 next_191_arg_1 = var_190; [L541] SORT_3 var_193_arg_0 = var_108; [L542] SORT_2 var_193_arg_1 = state_24; [L543] SORT_4 var_193 = ((SORT_4)var_193_arg_0 << 8) | var_193_arg_1; [L544] var_193 = var_193 & mask_SORT_4 [L545] SORT_4 var_194_arg_0 = var_193; [L546] SORT_4 var_194_arg_1 = var_107; [L547] SORT_4 var_194 = var_194_arg_0 - var_194_arg_1; [L548] SORT_4 var_195_arg_0 = var_194; [L549] SORT_2 var_195 = var_195_arg_0 >> 0; [L550] SORT_4 var_196_arg_0 = var_107; [L551] SORT_4 var_196_arg_1 = var_193; [L552] SORT_4 var_196 = var_196_arg_0 + var_196_arg_1; [L553] SORT_4 var_197_arg_0 = var_196; [L554] SORT_2 var_197 = var_197_arg_0 >> 0; [L555] SORT_1 var_198_arg_0 = input_151; [L556] SORT_2 var_198_arg_1 = var_197; [L557] SORT_2 var_198_arg_2 = state_24; [L558] EXPR var_198_arg_0 ? var_198_arg_1 : var_198_arg_2 [L558] SORT_2 var_198 = var_198_arg_0 ? var_198_arg_1 : var_198_arg_2; [L559] SORT_1 var_199_arg_0 = input_149; [L560] SORT_2 var_199_arg_1 = var_197; [L561] SORT_2 var_199_arg_2 = var_198; [L562] EXPR var_199_arg_0 ? var_199_arg_1 : var_199_arg_2 [L562] SORT_2 var_199 = var_199_arg_0 ? var_199_arg_1 : var_199_arg_2; [L563] SORT_1 var_200_arg_0 = input_192; [L564] SORT_2 var_200_arg_1 = var_195; [L565] SORT_2 var_200_arg_2 = var_199; [L566] EXPR var_200_arg_0 ? var_200_arg_1 : var_200_arg_2 [L566] SORT_2 var_200 = var_200_arg_0 ? var_200_arg_1 : var_200_arg_2; [L567] var_200 = var_200 & mask_SORT_2 [L568] SORT_2 next_201_arg_1 = var_200; [L569] SORT_4 var_202_arg_0 = var_160; [L570] SORT_2 var_202 = var_202_arg_0 >> 0; [L571] SORT_1 var_203_arg_0 = input_156; [L572] SORT_2 var_203_arg_1 = var_202; [L573] SORT_2 var_203_arg_2 = state_26; [L574] EXPR var_203_arg_0 ? var_203_arg_1 : var_203_arg_2 [L574] SORT_2 var_203 = var_203_arg_0 ? var_203_arg_1 : var_203_arg_2; [L575] SORT_1 var_204_arg_0 = input_154; [L576] SORT_2 var_204_arg_1 = var_97; [L577] SORT_2 var_204_arg_2 = var_203; [L578] EXPR var_204_arg_0 ? var_204_arg_1 : var_204_arg_2 [L578] SORT_2 var_204 = var_204_arg_0 ? var_204_arg_1 : var_204_arg_2; [L579] SORT_1 var_205_arg_0 = input_192; [L580] SORT_2 var_205_arg_1 = var_97; [L581] SORT_2 var_205_arg_2 = var_204; [L582] EXPR var_205_arg_0 ? var_205_arg_1 : var_205_arg_2 [L582] SORT_2 var_205 = var_205_arg_0 ? var_205_arg_1 : var_205_arg_2; [L583] var_205 = var_205 & mask_SORT_2 [L584] SORT_2 next_206_arg_1 = var_205; [L585] SORT_1 next_207_arg_1 = state_29; [L586] SORT_1 var_208_arg_0 = state_31; [L587] SORT_1 var_208_arg_1 = input_81; [L588] SORT_1 var_208 = var_208_arg_0 | var_208_arg_1; [L589] SORT_1 var_209_arg_0 = var_208; [L590] SORT_1 var_209_arg_1 = input_79; [L591] SORT_1 var_209 = var_209_arg_0 | var_209_arg_1; [L592] SORT_1 var_210_arg_0 = var_209; [L593] SORT_1 var_210_arg_1 = ~input_192; [L594] var_210_arg_1 = var_210_arg_1 & mask_SORT_1 [L595] SORT_1 var_210 = var_210_arg_0 & var_210_arg_1; [L596] SORT_1 next_211_arg_1 = var_210; [L597] SORT_1 var_212_arg_0 = state_33; [L598] SORT_1 var_212_arg_1 = input_101; [L599] SORT_1 var_212 = var_212_arg_0 | var_212_arg_1; [L600] SORT_1 var_213_arg_0 = var_212; [L601] SORT_1 var_213_arg_1 = input_100; [L602] SORT_1 var_213 = var_213_arg_0 | var_213_arg_1; [L603] SORT_1 var_214_arg_0 = var_213; [L604] SORT_1 var_214_arg_1 = ~input_149; [L605] var_214_arg_1 = var_214_arg_1 & mask_SORT_1 [L606] SORT_1 var_214 = var_214_arg_0 & var_214_arg_1; [L607] SORT_1 next_215_arg_1 = var_214; [L608] SORT_1 var_216_arg_0 = state_35; [L609] SORT_1 var_216_arg_1 = input_85; [L610] SORT_1 var_216 = var_216_arg_0 | var_216_arg_1; [L611] SORT_1 var_217_arg_0 = var_216; [L612] SORT_1 var_217_arg_1 = input_83; [L613] SORT_1 var_217 = var_217_arg_0 | var_217_arg_1; [L614] SORT_1 var_218_arg_0 = var_217; [L615] SORT_1 var_218_arg_1 = ~input_151; [L616] var_218_arg_1 = var_218_arg_1 & mask_SORT_1 [L617] SORT_1 var_218 = var_218_arg_0 & var_218_arg_1; [L618] SORT_1 next_219_arg_1 = var_218; [L619] SORT_1 var_220_arg_0 = state_37; [L620] SORT_1 var_220_arg_1 = ~input_85; [L621] var_220_arg_1 = var_220_arg_1 & mask_SORT_1 [L622] SORT_1 var_220 = var_220_arg_0 & var_220_arg_1; [L623] SORT_1 var_221_arg_0 = var_220; [L624] SORT_1 var_221_arg_1 = ~input_83; [L625] var_221_arg_1 = var_221_arg_1 & mask_SORT_1 [L626] SORT_1 var_221 = var_221_arg_0 & var_221_arg_1; [L627] SORT_1 var_223_arg_0 = var_221; [L628] SORT_1 var_223_arg_1 = input_222; [L629] SORT_1 var_223 = var_223_arg_0 | var_223_arg_1; [L630] SORT_1 next_224_arg_1 = var_223; [L631] SORT_1 var_226_arg_0 = state_39; [L632] SORT_1 var_226_arg_1 = input_225; [L633] SORT_1 var_226 = var_226_arg_0 | var_226_arg_1; [L634] SORT_1 var_227_arg_0 = var_226; [L635] SORT_1 var_227_arg_1 = ~input_78; [L636] var_227_arg_1 = var_227_arg_1 & mask_SORT_1 [L637] SORT_1 var_227 = var_227_arg_0 & var_227_arg_1; [L638] SORT_1 next_228_arg_1 = var_227; [L639] SORT_1 var_229_arg_0 = state_41; [L640] SORT_1 var_229_arg_1 = input_86; [L641] SORT_1 var_229 = var_229_arg_0 | var_229_arg_1; [L642] SORT_1 var_230_arg_0 = var_229; [L643] SORT_1 var_230_arg_1 = input_84; [L644] SORT_1 var_230 = var_230_arg_0 | var_230_arg_1; [L645] SORT_1 var_231_arg_0 = var_230; [L646] SORT_1 var_231_arg_1 = ~input_101; [L647] var_231_arg_1 = var_231_arg_1 & mask_SORT_1 [L648] SORT_1 var_231 = var_231_arg_0 & var_231_arg_1; [L649] SORT_1 var_232_arg_0 = var_231; [L650] SORT_1 var_232_arg_1 = ~input_100; [L651] var_232_arg_1 = var_232_arg_1 & mask_SORT_1 [L652] SORT_1 var_232 = var_232_arg_0 & var_232_arg_1; [L653] SORT_1 next_233_arg_1 = var_232; [L654] SORT_1 var_234_arg_0 = state_43; [L655] SORT_1 var_234_arg_1 = ~input_86; [L656] var_234_arg_1 = var_234_arg_1 & mask_SORT_1 [L657] SORT_1 var_234 = var_234_arg_0 & var_234_arg_1; [L658] SORT_1 var_235_arg_0 = var_234; [L659] SORT_1 var_235_arg_1 = ~input_84; [L660] var_235_arg_1 = var_235_arg_1 & mask_SORT_1 [L661] SORT_1 var_235 = var_235_arg_0 & var_235_arg_1; [L662] SORT_1 var_236_arg_0 = var_235; [L663] SORT_1 var_236_arg_1 = input_99; [L664] SORT_1 var_236 = var_236_arg_0 | var_236_arg_1; [L665] SORT_1 var_237_arg_0 = var_236; [L666] SORT_1 var_237_arg_1 = input_98; [L667] SORT_1 var_237 = var_237_arg_0 | var_237_arg_1; [L668] SORT_1 var_238_arg_0 = var_237; [L669] SORT_1 var_238_arg_1 = ~input_81; [L670] var_238_arg_1 = var_238_arg_1 & mask_SORT_1 [L671] SORT_1 var_238 = var_238_arg_0 & var_238_arg_1; [L672] SORT_1 var_239_arg_0 = var_238; [L673] SORT_1 var_239_arg_1 = ~input_79; [L674] var_239_arg_1 = var_239_arg_1 & mask_SORT_1 [L675] SORT_1 var_239 = var_239_arg_0 & var_239_arg_1; [L676] SORT_1 var_240_arg_0 = var_239; [L677] SORT_1 var_240_arg_1 = input_151; [L678] SORT_1 var_240 = var_240_arg_0 | var_240_arg_1; [L679] SORT_1 var_241_arg_0 = var_240; [L680] SORT_1 var_241_arg_1 = input_149; [L681] SORT_1 var_241 = var_241_arg_0 | var_241_arg_1; [L682] SORT_1 next_242_arg_1 = var_241; [L683] SORT_1 var_243_arg_0 = ~state_45; [L684] var_243_arg_0 = var_243_arg_0 & mask_SORT_1 [L685] SORT_1 var_243_arg_1 = ~input_222; [L686] var_243_arg_1 = var_243_arg_1 & mask_SORT_1 [L687] SORT_1 var_243 = var_243_arg_0 & var_243_arg_1; [L688] SORT_1 var_244_arg_0 = var_243; [L689] SORT_1 var_244_arg_1 = ~input_225; [L690] var_244_arg_1 = var_244_arg_1 & mask_SORT_1 [L691] SORT_1 var_244 = var_244_arg_0 & var_244_arg_1; [L692] SORT_1 var_245_arg_0 = var_244; [L693] SORT_1 var_245_arg_1 = input_192; [L694] SORT_1 var_245 = var_245_arg_0 | var_245_arg_1; [L695] SORT_1 next_246_arg_1 = ~var_245; [L696] next_246_arg_1 = next_246_arg_1 & mask_SORT_1 [L697] SORT_1 var_247_arg_0 = state_47; [L698] SORT_1 var_247_arg_1 = ~input_99; [L699] var_247_arg_1 = var_247_arg_1 & mask_SORT_1 [L700] SORT_1 var_247 = var_247_arg_0 & var_247_arg_1; [L701] SORT_1 var_248_arg_0 = var_247; [L702] SORT_1 var_248_arg_1 = ~input_98; [L703] var_248_arg_1 = var_248_arg_1 & mask_SORT_1 [L704] SORT_1 var_248 = var_248_arg_0 & var_248_arg_1; [L705] SORT_1 var_249_arg_0 = var_248; [L706] SORT_1 var_249_arg_1 = input_78; [L707] SORT_1 var_249 = var_249_arg_0 | var_249_arg_1; [L708] SORT_1 next_250_arg_1 = var_249; [L709] SORT_1 var_251_arg_0 = ~state_49; [L710] var_251_arg_0 = var_251_arg_0 & mask_SORT_1 [L711] SORT_1 var_251_arg_1 = input_154; [L712] SORT_1 var_251 = var_251_arg_0 | var_251_arg_1; [L713] SORT_1 var_252_arg_0 = var_251; [L714] SORT_1 var_252_arg_1 = ~input_192; [L715] var_252_arg_1 = var_252_arg_1 & mask_SORT_1 [L716] SORT_1 var_252 = var_252_arg_0 & var_252_arg_1; [L717] SORT_1 next_253_arg_1 = ~var_252; [L718] next_253_arg_1 = next_253_arg_1 & mask_SORT_1 [L719] SORT_1 var_254_arg_0 = state_51; [L720] SORT_1 var_254_arg_1 = ~input_154; [L721] var_254_arg_1 = var_254_arg_1 & mask_SORT_1 [L722] SORT_1 var_254 = var_254_arg_0 & var_254_arg_1; [L723] SORT_1 var_255_arg_0 = var_254; [L724] SORT_1 var_255_arg_1 = input_192; [L725] SORT_1 var_255 = var_255_arg_0 | var_255_arg_1; [L726] SORT_1 next_256_arg_1 = var_255; [L727] SORT_1 var_257_arg_0 = ~state_53; [L728] var_257_arg_0 = var_257_arg_0 & mask_SORT_1 [L729] SORT_1 var_257_arg_1 = ~input_86; [L730] var_257_arg_1 = var_257_arg_1 & mask_SORT_1 [L731] SORT_1 var_257 = var_257_arg_0 & var_257_arg_1; [L732] SORT_1 var_258_arg_0 = var_257; [L733] SORT_1 var_258_arg_1 = ~input_85; [L734] var_258_arg_1 = var_258_arg_1 & mask_SORT_1 [L735] SORT_1 var_258 = var_258_arg_0 & var_258_arg_1; [L736] SORT_1 var_259_arg_0 = var_258; [L737] SORT_1 var_259_arg_1 = input_81; [L738] SORT_1 var_259 = var_259_arg_0 | var_259_arg_1; [L739] SORT_1 next_260_arg_1 = ~var_259; [L740] next_260_arg_1 = next_260_arg_1 & mask_SORT_1 [L741] SORT_1 var_261_arg_0 = state_55; [L742] SORT_1 var_261_arg_1 = input_101; [L743] SORT_1 var_261 = var_261_arg_0 | var_261_arg_1; [L744] SORT_1 var_262_arg_0 = var_261; [L745] SORT_1 var_262_arg_1 = ~input_99; [L746] var_262_arg_1 = var_262_arg_1 & mask_SORT_1 [L747] SORT_1 var_262 = var_262_arg_0 & var_262_arg_1; [L748] SORT_1 next_263_arg_1 = var_262; [L749] SORT_1 var_264_arg_0 = state_57; [L750] SORT_1 var_264_arg_1 = input_105; [L751] SORT_1 var_264 = var_264_arg_0 | var_264_arg_1; [L752] SORT_1 var_265_arg_0 = var_264; [L753] SORT_1 var_265_arg_1 = input_104; [L754] SORT_1 var_265 = var_265_arg_0 | var_265_arg_1; [L755] SORT_1 var_266_arg_0 = var_265; [L756] SORT_1 var_266_arg_1 = ~input_81; [L757] var_266_arg_1 = var_266_arg_1 & mask_SORT_1 [L758] SORT_1 var_266 = var_266_arg_0 & var_266_arg_1; [L759] SORT_1 next_267_arg_1 = var_266; [L760] SORT_1 var_268_arg_0 = state_59; [L761] SORT_1 var_268_arg_1 = ~input_105; [L762] var_268_arg_1 = var_268_arg_1 & mask_SORT_1 [L763] SORT_1 var_268 = var_268_arg_0 & var_268_arg_1; [L764] SORT_1 var_269_arg_0 = var_268; [L765] SORT_1 var_269_arg_1 = input_86; [L766] SORT_1 var_269 = var_269_arg_0 | var_269_arg_1; [L767] SORT_1 var_270_arg_0 = var_269; [L768] SORT_1 var_270_arg_1 = input_85; [L769] SORT_1 var_270 = var_270_arg_0 | var_270_arg_1; [L770] SORT_1 var_271_arg_0 = var_270; [L771] SORT_1 var_271_arg_1 = ~input_101; [L772] var_271_arg_1 = var_271_arg_1 & mask_SORT_1 [L773] SORT_1 var_271 = var_271_arg_0 & var_271_arg_1; [L774] SORT_1 next_272_arg_1 = var_271; [L775] SORT_1 var_273_arg_0 = state_61; [L776] SORT_1 var_273_arg_1 = ~input_104; [L777] var_273_arg_1 = var_273_arg_1 & mask_SORT_1 [L778] SORT_1 var_273 = var_273_arg_0 & var_273_arg_1; [L779] SORT_1 var_274_arg_0 = var_273; [L780] SORT_1 var_274_arg_1 = input_99; [L781] SORT_1 var_274 = var_274_arg_0 | var_274_arg_1; [L782] SORT_1 next_275_arg_1 = var_274; [L783] SORT_1 var_276_arg_0 = ~state_63; [L784] var_276_arg_0 = var_276_arg_0 & mask_SORT_1 [L785] SORT_1 var_276_arg_1 = ~input_84; [L786] var_276_arg_1 = var_276_arg_1 & mask_SORT_1 [L787] SORT_1 var_276 = var_276_arg_0 & var_276_arg_1; [L788] SORT_1 var_277_arg_0 = var_276; [L789] SORT_1 var_277_arg_1 = ~input_83; [L790] var_277_arg_1 = var_277_arg_1 & mask_SORT_1 [L791] SORT_1 var_277 = var_277_arg_0 & var_277_arg_1; [L792] SORT_1 var_278_arg_0 = var_277; [L793] SORT_1 var_278_arg_1 = input_79; [L794] SORT_1 var_278 = var_278_arg_0 | var_278_arg_1; [L795] SORT_1 next_279_arg_1 = ~var_278; [L796] next_279_arg_1 = next_279_arg_1 & mask_SORT_1 [L797] SORT_1 var_280_arg_0 = state_65; [L798] SORT_1 var_280_arg_1 = input_100; [L799] SORT_1 var_280 = var_280_arg_0 | var_280_arg_1; [L800] SORT_1 var_281_arg_0 = var_280; [L801] SORT_1 var_281_arg_1 = ~input_98; [L802] var_281_arg_1 = var_281_arg_1 & mask_SORT_1 [L803] SORT_1 var_281 = var_281_arg_0 & var_281_arg_1; [L804] SORT_1 next_282_arg_1 = var_281; [L805] SORT_1 var_283_arg_0 = state_67; [L806] SORT_1 var_283_arg_1 = input_103; [L807] SORT_1 var_283 = var_283_arg_0 | var_283_arg_1; [L808] SORT_1 var_284_arg_0 = var_283; [L809] SORT_1 var_284_arg_1 = input_102; [L810] SORT_1 var_284 = var_284_arg_0 | var_284_arg_1; [L811] SORT_1 var_285_arg_0 = var_284; [L812] SORT_1 var_285_arg_1 = ~input_79; [L813] var_285_arg_1 = var_285_arg_1 & mask_SORT_1 [L814] SORT_1 var_285 = var_285_arg_0 & var_285_arg_1; [L815] SORT_1 next_286_arg_1 = var_285; [L816] SORT_1 var_287_arg_0 = state_69; [L817] SORT_1 var_287_arg_1 = ~input_103; [L818] var_287_arg_1 = var_287_arg_1 & mask_SORT_1 [L819] SORT_1 var_287 = var_287_arg_0 & var_287_arg_1; [L820] SORT_1 var_288_arg_0 = var_287; [L821] SORT_1 var_288_arg_1 = input_84; [L822] SORT_1 var_288 = var_288_arg_0 | var_288_arg_1; [L823] SORT_1 var_289_arg_0 = var_288; [L824] SORT_1 var_289_arg_1 = input_83; [L825] SORT_1 var_289 = var_289_arg_0 | var_289_arg_1; [L826] SORT_1 var_290_arg_0 = var_289; [L827] SORT_1 var_290_arg_1 = ~input_100; [L828] var_290_arg_1 = var_290_arg_1 & mask_SORT_1 [L829] SORT_1 var_290 = var_290_arg_0 & var_290_arg_1; [L830] SORT_1 next_291_arg_1 = var_290; [L831] SORT_1 var_292_arg_0 = state_71; [L832] SORT_1 var_292_arg_1 = ~input_102; [L833] var_292_arg_1 = var_292_arg_1 & mask_SORT_1 [L834] SORT_1 var_292 = var_292_arg_0 & var_292_arg_1; [L835] SORT_1 var_293_arg_0 = var_292; [L836] SORT_1 var_293_arg_1 = input_98; [L837] SORT_1 var_293 = var_293_arg_0 | var_293_arg_1; [L838] SORT_1 next_294_arg_1 = var_293; [L839] SORT_3 var_295_arg_0 = var_108; [L840] SORT_2 var_295_arg_1 = state_16; [L841] SORT_4 var_295 = ((SORT_4)var_295_arg_0 << 8) | var_295_arg_1; [L842] var_295 = var_295 & mask_SORT_4 [L843] SORT_4 var_296_arg_0 = var_109; [L844] SORT_4 var_296_arg_1 = var_295; [L845] SORT_1 var_296 = var_296_arg_0 <= var_296_arg_1; [L846] SORT_3 var_297_arg_0 = var_108; [L847] SORT_2 var_297_arg_1 = state_14; [L848] SORT_4 var_297 = ((SORT_4)var_297_arg_0 << 8) | var_297_arg_1; [L849] var_297 = var_297 & mask_SORT_4 [L850] SORT_4 var_298_arg_0 = var_109; [L851] SORT_4 var_298_arg_1 = var_297; [L852] SORT_1 var_298 = var_298_arg_0 <= var_298_arg_1; [L853] SORT_1 var_299_arg_0 = var_296; [L854] SORT_1 var_299_arg_1 = var_298; [L855] SORT_1 var_299 = var_299_arg_0 & var_299_arg_1; [L856] SORT_1 var_300_arg_0 = ~state_29; [L857] var_300_arg_0 = var_300_arg_0 & mask_SORT_1 [L858] SORT_1 var_300_arg_1 = var_299; [L859] SORT_1 var_300 = var_300_arg_0 & var_300_arg_1; [L860] SORT_1 var_301_arg_0 = ~input_106; [L861] var_301_arg_0 = var_301_arg_0 & mask_SORT_1 [L862] SORT_1 var_301_arg_1 = var_300; [L863] SORT_1 var_301 = var_301_arg_0 | var_301_arg_1; [L864] SORT_4 var_302_arg_0 = var_193; [L865] SORT_4 var_302_arg_1 = var_159; [L866] SORT_1 var_302 = var_302_arg_0 <= var_302_arg_1; [L867] SORT_1 var_303_arg_0 = state_51; [L868] SORT_1 var_303_arg_1 = ~var_302; [L869] var_303_arg_1 = var_303_arg_1 & mask_SORT_1 [L870] SORT_1 var_303 = var_303_arg_0 & var_303_arg_1; [L871] SORT_1 var_304_arg_0 = ~input_156; [L872] var_304_arg_0 = var_304_arg_0 & mask_SORT_1 [L873] SORT_1 var_304_arg_1 = var_303; [L874] SORT_1 var_304 = var_304_arg_0 | var_304_arg_1; [L875] SORT_1 var_305_arg_0 = var_301; [L876] SORT_1 var_305_arg_1 = var_304; [L877] SORT_1 var_305 = var_305_arg_0 & var_305_arg_1; [L878] SORT_2 var_306_arg_0 = state_24; [L879] SORT_2 var_306_arg_1 = state_26; [L880] SORT_1 var_306 = var_306_arg_0 == var_306_arg_1; [L881] SORT_1 var_307_arg_0 = state_51; [L882] SORT_1 var_307_arg_1 = var_306; [L883] SORT_1 var_307 = var_307_arg_0 & var_307_arg_1; [L884] SORT_1 var_308_arg_0 = ~input_154; [L885] var_308_arg_0 = var_308_arg_0 & mask_SORT_1 [L886] SORT_1 var_308_arg_1 = var_307; [L887] SORT_1 var_308 = var_308_arg_0 | var_308_arg_1; [L888] SORT_1 var_309_arg_0 = var_305; [L889] SORT_1 var_309_arg_1 = var_308; [L890] SORT_1 var_309 = var_309_arg_0 & var_309_arg_1; [L891] SORT_4 var_311_arg_0 = var_310; [L892] SORT_4 var_311_arg_1 = var_109; [L893] SORT_1 var_311 = var_311_arg_0 <= var_311_arg_1; [L894] SORT_1 var_312_arg_0 = state_59; [L895] SORT_1 var_312_arg_1 = var_311; [L896] SORT_1 var_312 = var_312_arg_0 & var_312_arg_1; [L897] SORT_1 var_313_arg_0 = ~input_105; [L898] var_313_arg_0 = var_313_arg_0 & mask_SORT_1 [L899] SORT_1 var_313_arg_1 = var_312; [L900] SORT_1 var_313 = var_313_arg_0 | var_313_arg_1; [L901] SORT_1 var_314_arg_0 = var_309; [L902] SORT_1 var_314_arg_1 = var_313; [L903] SORT_1 var_314 = var_314_arg_0 & var_314_arg_1; [L904] SORT_4 var_316_arg_0 = var_315; [L905] SORT_4 var_316_arg_1 = var_109; [L906] SORT_1 var_316 = var_316_arg_0 <= var_316_arg_1; [L907] SORT_1 var_317_arg_0 = state_61; [L908] SORT_1 var_317_arg_1 = var_316; [L909] SORT_1 var_317 = var_317_arg_0 & var_317_arg_1; [L910] SORT_1 var_318_arg_0 = ~input_104; [L911] var_318_arg_0 = var_318_arg_0 & mask_SORT_1 [L912] SORT_1 var_318_arg_1 = var_317; [L913] SORT_1 var_318 = var_318_arg_0 | var_318_arg_1; [L914] SORT_1 var_319_arg_0 = var_314; [L915] SORT_1 var_319_arg_1 = var_318; [L916] SORT_1 var_319 = var_319_arg_0 & var_319_arg_1; [L917] SORT_1 var_320_arg_0 = state_69; [L918] SORT_1 var_320_arg_1 = var_311; [L919] SORT_1 var_320 = var_320_arg_0 & var_320_arg_1; [L920] SORT_1 var_321_arg_0 = ~input_103; [L921] var_321_arg_0 = var_321_arg_0 & mask_SORT_1 [L922] SORT_1 var_321_arg_1 = var_320; [L923] SORT_1 var_321 = var_321_arg_0 | var_321_arg_1; [L924] SORT_1 var_322_arg_0 = var_319; [L925] SORT_1 var_322_arg_1 = var_321; [L926] SORT_1 var_322 = var_322_arg_0 & var_322_arg_1; [L927] SORT_1 var_323_arg_0 = state_71; [L928] SORT_1 var_323_arg_1 = var_316; [L929] SORT_1 var_323 = var_323_arg_0 & var_323_arg_1; [L930] SORT_1 var_324_arg_0 = ~input_102; [L931] var_324_arg_0 = var_324_arg_0 & mask_SORT_1 [L932] SORT_1 var_324_arg_1 = var_323; [L933] SORT_1 var_324 = var_324_arg_0 | var_324_arg_1; [L934] SORT_1 var_325_arg_0 = var_322; [L935] SORT_1 var_325_arg_1 = var_324; [L936] SORT_1 var_325 = var_325_arg_0 & var_325_arg_1; [L937] SORT_1 var_326_arg_0 = state_43; [L938] SORT_1 var_326_arg_1 = ~state_53; [L939] var_326_arg_1 = var_326_arg_1 & mask_SORT_1 [L940] SORT_1 var_326 = var_326_arg_0 & var_326_arg_1; [L941] SORT_1 var_327_arg_0 = ~input_86; [L942] var_327_arg_0 = var_327_arg_0 & mask_SORT_1 [L943] SORT_1 var_327_arg_1 = var_326; [L944] SORT_1 var_327 = var_327_arg_0 | var_327_arg_1; [L945] SORT_1 var_328_arg_0 = var_325; [L946] SORT_1 var_328_arg_1 = var_327; [L947] SORT_1 var_328 = var_328_arg_0 & var_328_arg_1; [L948] SORT_1 var_329_arg_0 = state_37; [L949] SORT_1 var_329_arg_1 = ~state_53; [L950] var_329_arg_1 = var_329_arg_1 & mask_SORT_1 [L951] SORT_1 var_329 = var_329_arg_0 & var_329_arg_1; [L952] SORT_1 var_330_arg_0 = ~input_85; [L953] var_330_arg_0 = var_330_arg_0 & mask_SORT_1 [L954] SORT_1 var_330_arg_1 = var_329; [L955] SORT_1 var_330 = var_330_arg_0 | var_330_arg_1; [L956] SORT_1 var_331_arg_0 = var_328; [L957] SORT_1 var_331_arg_1 = var_330; [L958] SORT_1 var_331 = var_331_arg_0 & var_331_arg_1; [L959] SORT_1 var_332_arg_0 = state_43; [L960] SORT_1 var_332_arg_1 = ~state_63; [L961] var_332_arg_1 = var_332_arg_1 & mask_SORT_1 [L962] SORT_1 var_332 = var_332_arg_0 & var_332_arg_1; [L963] SORT_1 var_333_arg_0 = ~input_84; [L964] var_333_arg_0 = var_333_arg_0 & mask_SORT_1 [L965] SORT_1 var_333_arg_1 = var_332; [L966] SORT_1 var_333 = var_333_arg_0 | var_333_arg_1; [L967] SORT_1 var_334_arg_0 = var_331; [L968] SORT_1 var_334_arg_1 = var_333; [L969] SORT_1 var_334 = var_334_arg_0 & var_334_arg_1; [L970] SORT_1 var_335_arg_0 = state_37; [L971] SORT_1 var_335_arg_1 = ~state_63; [L972] var_335_arg_1 = var_335_arg_1 & mask_SORT_1 [L973] SORT_1 var_335 = var_335_arg_0 & var_335_arg_1; [L974] SORT_1 var_336_arg_0 = ~input_83; [L975] var_336_arg_0 = var_336_arg_0 & mask_SORT_1 [L976] SORT_1 var_336_arg_1 = var_335; [L977] SORT_1 var_336 = var_336_arg_0 | var_336_arg_1; [L978] SORT_1 var_337_arg_0 = var_334; [L979] SORT_1 var_337_arg_1 = var_336; [L980] SORT_1 var_337 = var_337_arg_0 & var_337_arg_1; [L981] SORT_1 var_338_arg_0 = state_41; [L982] SORT_1 var_338_arg_1 = state_59; [L983] SORT_1 var_338 = var_338_arg_0 & var_338_arg_1; [L984] SORT_4 var_339_arg_0 = var_109; [L985] SORT_4 var_339_arg_1 = var_310; [L986] SORT_1 var_339 = var_339_arg_0 <= var_339_arg_1; [L987] SORT_2 var_340_arg_0 = var_82; [L988] SORT_2 var_340_arg_1 = state_6; [L989] SORT_1 var_340 = var_340_arg_0 == var_340_arg_1; [L990] SORT_1 var_341_arg_0 = var_339; [L991] SORT_1 var_341_arg_1 = var_340; [L992] SORT_1 var_341 = var_341_arg_0 & var_341_arg_1; [L993] SORT_1 var_342_arg_0 = var_338; [L994] SORT_1 var_342_arg_1 = var_341; [L995] SORT_1 var_342 = var_342_arg_0 & var_342_arg_1; [L996] SORT_1 var_343_arg_0 = ~input_101; [L997] var_343_arg_0 = var_343_arg_0 & mask_SORT_1 [L998] SORT_1 var_343_arg_1 = var_342; [L999] SORT_1 var_343 = var_343_arg_0 | var_343_arg_1; [L1000] SORT_1 var_344_arg_0 = var_337; [L1001] SORT_1 var_344_arg_1 = var_343; [L1002] SORT_1 var_344 = var_344_arg_0 & var_344_arg_1; [L1003] SORT_1 var_345_arg_0 = state_41; [L1004] SORT_1 var_345_arg_1 = state_69; [L1005] SORT_1 var_345 = var_345_arg_0 & var_345_arg_1; [L1006] SORT_2 var_346_arg_0 = var_80; [L1007] SORT_2 var_346_arg_1 = state_6; [L1008] SORT_1 var_346 = var_346_arg_0 == var_346_arg_1; [L1009] SORT_1 var_347_arg_0 = var_339; [L1010] SORT_1 var_347_arg_1 = var_346; [L1011] SORT_1 var_347 = var_347_arg_0 & var_347_arg_1; [L1012] SORT_1 var_348_arg_0 = var_345; [L1013] SORT_1 var_348_arg_1 = var_347; [L1014] SORT_1 var_348 = var_348_arg_0 & var_348_arg_1; [L1015] SORT_1 var_349_arg_0 = ~input_100; [L1016] var_349_arg_0 = var_349_arg_0 & mask_SORT_1 [L1017] SORT_1 var_349_arg_1 = var_348; [L1018] SORT_1 var_349 = var_349_arg_0 | var_349_arg_1; [L1019] SORT_1 var_350_arg_0 = var_344; [L1020] SORT_1 var_350_arg_1 = var_349; [L1021] SORT_1 var_350 = var_350_arg_0 & var_350_arg_1; [L1022] SORT_1 var_351_arg_0 = state_47; [L1023] SORT_1 var_351_arg_1 = state_55; [L1024] SORT_1 var_351 = var_351_arg_0 & var_351_arg_1; [L1025] SORT_1 var_352_arg_0 = var_351; [L1026] SORT_1 var_352_arg_1 = var_340; [L1027] SORT_1 var_352 = var_352_arg_0 & var_352_arg_1; [L1028] SORT_1 var_353_arg_0 = ~input_99; [L1029] var_353_arg_0 = var_353_arg_0 & mask_SORT_1 [L1030] SORT_1 var_353_arg_1 = var_352; [L1031] SORT_1 var_353 = var_353_arg_0 | var_353_arg_1; [L1032] SORT_1 var_354_arg_0 = var_350; [L1033] SORT_1 var_354_arg_1 = var_353; [L1034] SORT_1 var_354 = var_354_arg_0 & var_354_arg_1; [L1035] SORT_1 var_355_arg_0 = state_47; [L1036] SORT_1 var_355_arg_1 = state_65; [L1037] SORT_1 var_355 = var_355_arg_0 & var_355_arg_1; [L1038] SORT_1 var_356_arg_0 = var_355; [L1039] SORT_1 var_356_arg_1 = var_346; [L1040] SORT_1 var_356 = var_356_arg_0 & var_356_arg_1; [L1041] SORT_1 var_357_arg_0 = ~input_98; [L1042] var_357_arg_0 = var_357_arg_0 & mask_SORT_1 [L1043] SORT_1 var_357_arg_1 = var_356; [L1044] SORT_1 var_357 = var_357_arg_0 | var_357_arg_1; [L1045] SORT_1 var_358_arg_0 = var_354; [L1046] SORT_1 var_358_arg_1 = var_357; [L1047] SORT_1 var_358 = var_358_arg_0 & var_358_arg_1; [L1048] SORT_1 var_359_arg_0 = state_43; [L1049] SORT_1 var_359_arg_1 = state_57; [L1050] SORT_1 var_359 = var_359_arg_0 & var_359_arg_1; [L1051] SORT_4 var_361_arg_0 = var_360; [L1052] SORT_4 var_361_arg_1 = var_109; [L1053] SORT_1 var_361 = var_361_arg_0 <= var_361_arg_1; [L1054] SORT_1 var_362_arg_0 = var_359; [L1055] SORT_1 var_362_arg_1 = var_361; [L1056] SORT_1 var_362 = var_362_arg_0 & var_362_arg_1; [L1057] SORT_1 var_363_arg_0 = ~input_81; [L1058] var_363_arg_0 = var_363_arg_0 & mask_SORT_1 [L1059] SORT_1 var_363_arg_1 = var_362; [L1060] SORT_1 var_363 = var_363_arg_0 | var_363_arg_1; [L1061] SORT_1 var_364_arg_0 = var_358; [L1062] SORT_1 var_364_arg_1 = var_363; [L1063] SORT_1 var_364 = var_364_arg_0 & var_364_arg_1; [L1064] SORT_1 var_365_arg_0 = state_43; [L1065] SORT_1 var_365_arg_1 = state_67; [L1066] SORT_1 var_365 = var_365_arg_0 & var_365_arg_1; [L1067] SORT_1 var_366_arg_0 = var_365; [L1068] SORT_1 var_366_arg_1 = var_361; [L1069] SORT_1 var_366 = var_366_arg_0 & var_366_arg_1; [L1070] SORT_1 var_367_arg_0 = ~input_79; [L1071] var_367_arg_0 = var_367_arg_0 & mask_SORT_1 [L1072] SORT_1 var_367_arg_1 = var_366; [L1073] SORT_1 var_367 = var_367_arg_0 | var_367_arg_1; [L1074] SORT_1 var_368_arg_0 = var_364; [L1075] SORT_1 var_368_arg_1 = var_367; [L1076] SORT_1 var_368 = var_368_arg_0 & var_368_arg_1; [L1077] SORT_1 var_369_arg_0 = ~state_45; [L1078] var_369_arg_0 = var_369_arg_0 & mask_SORT_1 [L1079] SORT_1 var_369_arg_1 = ~state_49; [L1080] var_369_arg_1 = var_369_arg_1 & mask_SORT_1 [L1081] SORT_1 var_369 = var_369_arg_0 & var_369_arg_1; [L1082] SORT_1 var_370_arg_0 = var_369; [L1083] SORT_1 var_370_arg_1 = var_148; [L1084] SORT_1 var_370 = var_370_arg_0 & var_370_arg_1; [L1085] SORT_1 var_371_arg_0 = ~input_222; [L1086] var_371_arg_0 = var_371_arg_0 & mask_SORT_1 [L1087] SORT_1 var_371_arg_1 = var_370; [L1088] SORT_1 var_371 = var_371_arg_0 | var_371_arg_1; [L1089] SORT_1 var_372_arg_0 = var_368; [L1090] SORT_1 var_372_arg_1 = var_371; [L1091] SORT_1 var_372 = var_372_arg_0 & var_372_arg_1; [L1092] SORT_1 var_373_arg_0 = ~state_45; [L1093] var_373_arg_0 = var_373_arg_0 & mask_SORT_1 [L1094] SORT_1 var_373_arg_1 = ~state_49; [L1095] var_373_arg_1 = var_373_arg_1 & mask_SORT_1 [L1096] SORT_1 var_373 = var_373_arg_0 & var_373_arg_1; [L1097] SORT_4 var_374_arg_0 = var_193; [L1098] SORT_4 var_374_arg_1 = var_158; [L1099] SORT_1 var_374 = var_374_arg_0 <= var_374_arg_1; [L1100] SORT_1 var_375_arg_0 = var_373; [L1101] SORT_1 var_375_arg_1 = ~var_374; [L1102] var_375_arg_1 = var_375_arg_1 & mask_SORT_1 [L1103] SORT_1 var_375 = var_375_arg_0 & var_375_arg_1; [L1104] SORT_1 var_376_arg_0 = ~input_225; [L1105] var_376_arg_0 = var_376_arg_0 & mask_SORT_1 [L1106] SORT_1 var_376_arg_1 = var_375; [L1107] SORT_1 var_376 = var_376_arg_0 | var_376_arg_1; [L1108] SORT_1 var_377_arg_0 = var_372; [L1109] SORT_1 var_377_arg_1 = var_376; [L1110] SORT_1 var_377 = var_377_arg_0 & var_377_arg_1; [L1111] SORT_1 var_378_arg_0 = state_39; [L1112] SORT_1 var_378_arg_1 = ~state_49; [L1113] var_378_arg_1 = var_378_arg_1 & mask_SORT_1 [L1114] SORT_1 var_378 = var_378_arg_0 & var_378_arg_1; [L1115] SORT_1 var_379_arg_0 = ~input_78; [L1116] var_379_arg_0 = var_379_arg_0 & mask_SORT_1 [L1117] SORT_1 var_379_arg_1 = var_378; [L1118] SORT_1 var_379 = var_379_arg_0 | var_379_arg_1; [L1119] SORT_1 var_380_arg_0 = var_377; [L1120] SORT_1 var_380_arg_1 = var_379; [L1121] SORT_1 var_380 = var_380_arg_0 & var_380_arg_1; [L1122] SORT_1 var_381_arg_0 = state_35; [L1123] SORT_1 var_381_arg_1 = ~state_49; [L1124] var_381_arg_1 = var_381_arg_1 & mask_SORT_1 [L1125] SORT_1 var_381 = var_381_arg_0 & var_381_arg_1; [L1126] SORT_1 var_382_arg_0 = ~input_151; [L1127] var_382_arg_0 = var_382_arg_0 & mask_SORT_1 [L1128] SORT_1 var_382_arg_1 = var_381; [L1129] SORT_1 var_382 = var_382_arg_0 | var_382_arg_1; [L1130] SORT_1 var_383_arg_0 = var_380; [L1131] SORT_1 var_383_arg_1 = var_382; [L1132] SORT_1 var_383 = var_383_arg_0 & var_383_arg_1; [L1133] SORT_1 var_384_arg_0 = state_33; [L1134] SORT_1 var_384_arg_1 = ~state_49; [L1135] var_384_arg_1 = var_384_arg_1 & mask_SORT_1 [L1136] SORT_1 var_384 = var_384_arg_0 & var_384_arg_1; [L1137] SORT_1 var_385_arg_0 = ~input_149; [L1138] var_385_arg_0 = var_385_arg_0 & mask_SORT_1 [L1139] SORT_1 var_385_arg_1 = var_384; [L1140] SORT_1 var_385 = var_385_arg_0 | var_385_arg_1; [L1141] SORT_1 var_386_arg_0 = var_383; [L1142] SORT_1 var_386_arg_1 = var_385; [L1143] SORT_1 var_386 = var_386_arg_0 & var_386_arg_1; [L1144] SORT_1 var_387_arg_0 = state_31; [L1145] SORT_1 var_387_arg_1 = ~state_49; [L1146] var_387_arg_1 = var_387_arg_1 & mask_SORT_1 [L1147] SORT_1 var_387 = var_387_arg_0 & var_387_arg_1; [L1148] SORT_4 var_388_arg_0 = var_107; [L1149] SORT_4 var_388_arg_1 = var_193; [L1150] SORT_1 var_388 = var_388_arg_0 <= var_388_arg_1; [L1151] SORT_1 var_389_arg_0 = var_387; [L1152] SORT_1 var_389_arg_1 = var_388; [L1153] SORT_1 var_389 = var_389_arg_0 & var_389_arg_1; [L1154] SORT_1 var_390_arg_0 = ~input_192; [L1155] var_390_arg_0 = var_390_arg_0 & mask_SORT_1 [L1156] SORT_1 var_390_arg_1 = var_389; [L1157] SORT_1 var_390 = var_390_arg_0 | var_390_arg_1; [L1158] SORT_1 var_391_arg_0 = var_386; [L1159] SORT_1 var_391_arg_1 = var_390; [L1160] SORT_1 var_391 = var_391_arg_0 & var_391_arg_1; [L1161] SORT_1 var_392_arg_0 = input_106; [L1162] SORT_1 var_392_arg_1 = input_156; [L1163] SORT_1 var_392 = var_392_arg_0 | var_392_arg_1; [L1164] SORT_1 var_393_arg_0 = input_154; [L1165] SORT_1 var_393_arg_1 = var_392; [L1166] SORT_1 var_393 = var_393_arg_0 | var_393_arg_1; [L1167] SORT_1 var_394_arg_0 = input_105; [L1168] SORT_1 var_394_arg_1 = var_393; [L1169] SORT_1 var_394 = var_394_arg_0 | var_394_arg_1; [L1170] SORT_1 var_395_arg_0 = input_104; [L1171] SORT_1 var_395_arg_1 = var_394; [L1172] SORT_1 var_395 = var_395_arg_0 | var_395_arg_1; [L1173] SORT_1 var_396_arg_0 = input_103; [L1174] SORT_1 var_396_arg_1 = var_395; [L1175] SORT_1 var_396 = var_396_arg_0 | var_396_arg_1; [L1176] SORT_1 var_397_arg_0 = input_102; [L1177] SORT_1 var_397_arg_1 = var_396; [L1178] SORT_1 var_397 = var_397_arg_0 | var_397_arg_1; [L1179] SORT_1 var_398_arg_0 = input_86; [L1180] SORT_1 var_398_arg_1 = var_397; [L1181] SORT_1 var_398 = var_398_arg_0 | var_398_arg_1; [L1182] SORT_1 var_399_arg_0 = input_85; [L1183] SORT_1 var_399_arg_1 = var_398; [L1184] SORT_1 var_399 = var_399_arg_0 | var_399_arg_1; [L1185] SORT_1 var_400_arg_0 = input_84; [L1186] SORT_1 var_400_arg_1 = var_399; [L1187] SORT_1 var_400 = var_400_arg_0 | var_400_arg_1; [L1188] SORT_1 var_401_arg_0 = input_83; [L1189] SORT_1 var_401_arg_1 = var_400; [L1190] SORT_1 var_401 = var_401_arg_0 | var_401_arg_1; [L1191] SORT_1 var_402_arg_0 = input_101; [L1192] SORT_1 var_402_arg_1 = var_401; [L1193] SORT_1 var_402 = var_402_arg_0 | var_402_arg_1; [L1194] SORT_1 var_403_arg_0 = input_100; [L1195] SORT_1 var_403_arg_1 = var_402; [L1196] SORT_1 var_403 = var_403_arg_0 | var_403_arg_1; [L1197] SORT_1 var_404_arg_0 = input_99; [L1198] SORT_1 var_404_arg_1 = var_403; [L1199] SORT_1 var_404 = var_404_arg_0 | var_404_arg_1; [L1200] SORT_1 var_405_arg_0 = input_98; [L1201] SORT_1 var_405_arg_1 = var_404; [L1202] SORT_1 var_405 = var_405_arg_0 | var_405_arg_1; [L1203] SORT_1 var_406_arg_0 = input_81; [L1204] SORT_1 var_406_arg_1 = var_405; [L1205] SORT_1 var_406 = var_406_arg_0 | var_406_arg_1; [L1206] SORT_1 var_407_arg_0 = input_79; [L1207] SORT_1 var_407_arg_1 = var_406; [L1208] SORT_1 var_407 = var_407_arg_0 | var_407_arg_1; [L1209] SORT_1 var_408_arg_0 = input_222; [L1210] SORT_1 var_408_arg_1 = var_407; [L1211] SORT_1 var_408 = var_408_arg_0 | var_408_arg_1; [L1212] SORT_1 var_409_arg_0 = input_225; [L1213] SORT_1 var_409_arg_1 = var_408; [L1214] SORT_1 var_409 = var_409_arg_0 | var_409_arg_1; [L1215] SORT_1 var_410_arg_0 = input_78; [L1216] SORT_1 var_410_arg_1 = var_409; [L1217] SORT_1 var_410 = var_410_arg_0 | var_410_arg_1; [L1218] SORT_1 var_411_arg_0 = input_151; [L1219] SORT_1 var_411_arg_1 = var_410; [L1220] SORT_1 var_411 = var_411_arg_0 | var_411_arg_1; [L1221] SORT_1 var_412_arg_0 = input_149; [L1222] SORT_1 var_412_arg_1 = var_411; [L1223] SORT_1 var_412 = var_412_arg_0 | var_412_arg_1; [L1224] SORT_1 var_413_arg_0 = input_192; [L1225] SORT_1 var_413_arg_1 = var_412; [L1226] SORT_1 var_413 = var_413_arg_0 | var_413_arg_1; [L1227] SORT_1 var_414_arg_0 = var_391; [L1228] SORT_1 var_414_arg_1 = var_413; [L1229] SORT_1 var_414 = var_414_arg_0 & var_414_arg_1; [L1230] SORT_1 var_415_arg_0 = input_106; [L1231] SORT_1 var_415_arg_1 = input_156; [L1232] SORT_1 var_415 = var_415_arg_0 & var_415_arg_1; [L1233] SORT_1 var_416_arg_0 = input_154; [L1234] SORT_1 var_416_arg_1 = var_392; [L1235] SORT_1 var_416 = var_416_arg_0 & var_416_arg_1; [L1236] SORT_1 var_417_arg_0 = var_415; [L1237] SORT_1 var_417_arg_1 = var_416; [L1238] SORT_1 var_417 = var_417_arg_0 | var_417_arg_1; [L1239] SORT_1 var_418_arg_0 = input_105; [L1240] SORT_1 var_418_arg_1 = var_393; [L1241] SORT_1 var_418 = var_418_arg_0 & var_418_arg_1; [L1242] SORT_1 var_419_arg_0 = var_417; [L1243] SORT_1 var_419_arg_1 = var_418; [L1244] SORT_1 var_419 = var_419_arg_0 | var_419_arg_1; [L1245] SORT_1 var_420_arg_0 = input_104; [L1246] SORT_1 var_420_arg_1 = var_394; [L1247] SORT_1 var_420 = var_420_arg_0 & var_420_arg_1; [L1248] SORT_1 var_421_arg_0 = var_419; [L1249] SORT_1 var_421_arg_1 = var_420; [L1250] SORT_1 var_421 = var_421_arg_0 | var_421_arg_1; [L1251] SORT_1 var_422_arg_0 = input_103; [L1252] SORT_1 var_422_arg_1 = var_395; [L1253] SORT_1 var_422 = var_422_arg_0 & var_422_arg_1; [L1254] SORT_1 var_423_arg_0 = var_421; [L1255] SORT_1 var_423_arg_1 = var_422; [L1256] SORT_1 var_423 = var_423_arg_0 | var_423_arg_1; [L1257] SORT_1 var_424_arg_0 = input_102; [L1258] SORT_1 var_424_arg_1 = var_396; [L1259] SORT_1 var_424 = var_424_arg_0 & var_424_arg_1; [L1260] SORT_1 var_425_arg_0 = var_423; [L1261] SORT_1 var_425_arg_1 = var_424; [L1262] SORT_1 var_425 = var_425_arg_0 | var_425_arg_1; [L1263] SORT_1 var_426_arg_0 = input_86; [L1264] SORT_1 var_426_arg_1 = var_397; [L1265] SORT_1 var_426 = var_426_arg_0 & var_426_arg_1; [L1266] SORT_1 var_427_arg_0 = var_425; [L1267] SORT_1 var_427_arg_1 = var_426; [L1268] SORT_1 var_427 = var_427_arg_0 | var_427_arg_1; [L1269] SORT_1 var_428_arg_0 = input_85; [L1270] SORT_1 var_428_arg_1 = var_398; [L1271] SORT_1 var_428 = var_428_arg_0 & var_428_arg_1; [L1272] SORT_1 var_429_arg_0 = var_427; [L1273] SORT_1 var_429_arg_1 = var_428; [L1274] SORT_1 var_429 = var_429_arg_0 | var_429_arg_1; [L1275] SORT_1 var_430_arg_0 = input_84; [L1276] SORT_1 var_430_arg_1 = var_399; [L1277] SORT_1 var_430 = var_430_arg_0 & var_430_arg_1; [L1278] SORT_1 var_431_arg_0 = var_429; [L1279] SORT_1 var_431_arg_1 = var_430; [L1280] SORT_1 var_431 = var_431_arg_0 | var_431_arg_1; [L1281] SORT_1 var_432_arg_0 = input_83; [L1282] SORT_1 var_432_arg_1 = var_400; [L1283] SORT_1 var_432 = var_432_arg_0 & var_432_arg_1; [L1284] SORT_1 var_433_arg_0 = var_431; [L1285] SORT_1 var_433_arg_1 = var_432; [L1286] SORT_1 var_433 = var_433_arg_0 | var_433_arg_1; [L1287] SORT_1 var_434_arg_0 = input_101; [L1288] SORT_1 var_434_arg_1 = var_401; [L1289] SORT_1 var_434 = var_434_arg_0 & var_434_arg_1; [L1290] SORT_1 var_435_arg_0 = var_433; [L1291] SORT_1 var_435_arg_1 = var_434; [L1292] SORT_1 var_435 = var_435_arg_0 | var_435_arg_1; [L1293] SORT_1 var_436_arg_0 = input_100; [L1294] SORT_1 var_436_arg_1 = var_402; [L1295] SORT_1 var_436 = var_436_arg_0 & var_436_arg_1; [L1296] SORT_1 var_437_arg_0 = var_435; [L1297] SORT_1 var_437_arg_1 = var_436; [L1298] SORT_1 var_437 = var_437_arg_0 | var_437_arg_1; [L1299] SORT_1 var_438_arg_0 = input_99; [L1300] SORT_1 var_438_arg_1 = var_403; [L1301] SORT_1 var_438 = var_438_arg_0 & var_438_arg_1; [L1302] SORT_1 var_439_arg_0 = var_437; [L1303] SORT_1 var_439_arg_1 = var_438; [L1304] SORT_1 var_439 = var_439_arg_0 | var_439_arg_1; [L1305] SORT_1 var_440_arg_0 = input_98; [L1306] SORT_1 var_440_arg_1 = var_404; [L1307] SORT_1 var_440 = var_440_arg_0 & var_440_arg_1; [L1308] SORT_1 var_441_arg_0 = var_439; [L1309] SORT_1 var_441_arg_1 = var_440; [L1310] SORT_1 var_441 = var_441_arg_0 | var_441_arg_1; [L1311] SORT_1 var_442_arg_0 = input_81; [L1312] SORT_1 var_442_arg_1 = var_405; [L1313] SORT_1 var_442 = var_442_arg_0 & var_442_arg_1; [L1314] SORT_1 var_443_arg_0 = var_441; [L1315] SORT_1 var_443_arg_1 = var_442; [L1316] SORT_1 var_443 = var_443_arg_0 | var_443_arg_1; [L1317] SORT_1 var_444_arg_0 = input_79; [L1318] SORT_1 var_444_arg_1 = var_406; [L1319] SORT_1 var_444 = var_444_arg_0 & var_444_arg_1; [L1320] SORT_1 var_445_arg_0 = var_443; [L1321] SORT_1 var_445_arg_1 = var_444; [L1322] SORT_1 var_445 = var_445_arg_0 | var_445_arg_1; [L1323] SORT_1 var_446_arg_0 = input_222; [L1324] SORT_1 var_446_arg_1 = var_407; [L1325] SORT_1 var_446 = var_446_arg_0 & var_446_arg_1; [L1326] SORT_1 var_447_arg_0 = var_445; [L1327] SORT_1 var_447_arg_1 = var_446; [L1328] SORT_1 var_447 = var_447_arg_0 | var_447_arg_1; [L1329] SORT_1 var_448_arg_0 = input_225; [L1330] SORT_1 var_448_arg_1 = var_408; [L1331] SORT_1 var_448 = var_448_arg_0 & var_448_arg_1; [L1332] SORT_1 var_449_arg_0 = var_447; [L1333] SORT_1 var_449_arg_1 = var_448; [L1334] SORT_1 var_449 = var_449_arg_0 | var_449_arg_1; [L1335] SORT_1 var_450_arg_0 = input_78; [L1336] SORT_1 var_450_arg_1 = var_409; [L1337] SORT_1 var_450 = var_450_arg_0 & var_450_arg_1; [L1338] SORT_1 var_451_arg_0 = var_449; [L1339] SORT_1 var_451_arg_1 = var_450; [L1340] SORT_1 var_451 = var_451_arg_0 | var_451_arg_1; [L1341] SORT_1 var_452_arg_0 = input_151; [L1342] SORT_1 var_452_arg_1 = var_410; [L1343] SORT_1 var_452 = var_452_arg_0 & var_452_arg_1; [L1344] SORT_1 var_453_arg_0 = var_451; [L1345] SORT_1 var_453_arg_1 = var_452; [L1346] SORT_1 var_453 = var_453_arg_0 | var_453_arg_1; [L1347] SORT_1 var_454_arg_0 = input_149; [L1348] SORT_1 var_454_arg_1 = var_411; [L1349] SORT_1 var_454 = var_454_arg_0 & var_454_arg_1; [L1350] SORT_1 var_455_arg_0 = var_453; [L1351] SORT_1 var_455_arg_1 = var_454; [L1352] SORT_1 var_455 = var_455_arg_0 | var_455_arg_1; [L1353] SORT_1 var_456_arg_0 = input_192; [L1354] SORT_1 var_456_arg_1 = var_412; [L1355] SORT_1 var_456 = var_456_arg_0 & var_456_arg_1; [L1356] SORT_1 var_457_arg_0 = var_455; [L1357] SORT_1 var_457_arg_1 = var_456; [L1358] SORT_1 var_457 = var_457_arg_0 | var_457_arg_1; [L1359] SORT_1 var_458_arg_0 = var_414; [L1360] SORT_1 var_458_arg_1 = ~var_457; [L1361] var_458_arg_1 = var_458_arg_1 & mask_SORT_1 [L1362] SORT_1 var_458 = var_458_arg_0 & var_458_arg_1; [L1363] SORT_1 var_459_arg_0 = state_31; [L1364] SORT_1 var_459_arg_1 = state_33; [L1365] SORT_1 var_459 = var_459_arg_0 & var_459_arg_1; [L1366] SORT_1 var_460_arg_0 = state_31; [L1367] SORT_1 var_460_arg_1 = state_33; [L1368] SORT_1 var_460 = var_460_arg_0 | var_460_arg_1; [L1369] SORT_1 var_461_arg_0 = state_35; [L1370] SORT_1 var_461_arg_1 = var_460; [L1371] SORT_1 var_461 = var_461_arg_0 & var_461_arg_1; [L1372] SORT_1 var_462_arg_0 = var_459; [L1373] SORT_1 var_462_arg_1 = var_461; [L1374] SORT_1 var_462 = var_462_arg_0 | var_462_arg_1; [L1375] SORT_1 var_463_arg_0 = state_35; [L1376] SORT_1 var_463_arg_1 = var_460; [L1377] SORT_1 var_463 = var_463_arg_0 | var_463_arg_1; [L1378] SORT_1 var_464_arg_0 = state_37; [L1379] SORT_1 var_464_arg_1 = var_463; [L1380] SORT_1 var_464 = var_464_arg_0 & var_464_arg_1; [L1381] SORT_1 var_465_arg_0 = var_462; [L1382] SORT_1 var_465_arg_1 = var_464; [L1383] SORT_1 var_465 = var_465_arg_0 | var_465_arg_1; [L1384] SORT_1 var_466_arg_0 = state_37; [L1385] SORT_1 var_466_arg_1 = var_463; [L1386] SORT_1 var_466 = var_466_arg_0 | var_466_arg_1; [L1387] SORT_1 var_467_arg_0 = state_39; [L1388] SORT_1 var_467_arg_1 = var_466; [L1389] SORT_1 var_467 = var_467_arg_0 & var_467_arg_1; [L1390] SORT_1 var_468_arg_0 = var_465; [L1391] SORT_1 var_468_arg_1 = var_467; [L1392] SORT_1 var_468 = var_468_arg_0 | var_468_arg_1; [L1393] SORT_1 var_469_arg_0 = state_39; [L1394] SORT_1 var_469_arg_1 = var_466; [L1395] SORT_1 var_469 = var_469_arg_0 | var_469_arg_1; [L1396] SORT_1 var_470_arg_0 = state_41; [L1397] SORT_1 var_470_arg_1 = var_469; [L1398] SORT_1 var_470 = var_470_arg_0 & var_470_arg_1; [L1399] SORT_1 var_471_arg_0 = var_468; [L1400] SORT_1 var_471_arg_1 = var_470; [L1401] SORT_1 var_471 = var_471_arg_0 | var_471_arg_1; [L1402] SORT_1 var_472_arg_0 = state_41; [L1403] SORT_1 var_472_arg_1 = var_469; [L1404] SORT_1 var_472 = var_472_arg_0 | var_472_arg_1; [L1405] SORT_1 var_473_arg_0 = state_43; [L1406] SORT_1 var_473_arg_1 = var_472; [L1407] SORT_1 var_473 = var_473_arg_0 & var_473_arg_1; [L1408] SORT_1 var_474_arg_0 = var_471; [L1409] SORT_1 var_474_arg_1 = var_473; [L1410] SORT_1 var_474 = var_474_arg_0 | var_474_arg_1; [L1411] SORT_1 var_475_arg_0 = state_43; [L1412] SORT_1 var_475_arg_1 = var_472; [L1413] SORT_1 var_475 = var_475_arg_0 | var_475_arg_1; [L1414] SORT_1 var_476_arg_0 = ~state_45; [L1415] var_476_arg_0 = var_476_arg_0 & mask_SORT_1 [L1416] SORT_1 var_476_arg_1 = var_475; [L1417] SORT_1 var_476 = var_476_arg_0 & var_476_arg_1; [L1418] SORT_1 var_477_arg_0 = var_474; [L1419] SORT_1 var_477_arg_1 = var_476; [L1420] SORT_1 var_477 = var_477_arg_0 | var_477_arg_1; [L1421] SORT_1 var_478_arg_0 = ~state_45; [L1422] var_478_arg_0 = var_478_arg_0 & mask_SORT_1 [L1423] SORT_1 var_478_arg_1 = var_475; [L1424] SORT_1 var_478 = var_478_arg_0 | var_478_arg_1; [L1425] SORT_1 var_479_arg_0 = state_47; [L1426] SORT_1 var_479_arg_1 = var_478; [L1427] SORT_1 var_479 = var_479_arg_0 & var_479_arg_1; [L1428] SORT_1 var_480_arg_0 = var_477; [L1429] SORT_1 var_480_arg_1 = var_479; [L1430] SORT_1 var_480 = var_480_arg_0 | var_480_arg_1; [L1431] SORT_1 var_481_arg_0 = ~state_29; [L1432] var_481_arg_0 = var_481_arg_0 & mask_SORT_1 [L1433] SORT_1 var_481_arg_1 = ~var_480; [L1434] var_481_arg_1 = var_481_arg_1 & mask_SORT_1 [L1435] SORT_1 var_481 = var_481_arg_0 & var_481_arg_1; [L1436] SORT_1 var_482_arg_0 = state_47; [L1437] SORT_1 var_482_arg_1 = var_478; [L1438] SORT_1 var_482 = var_482_arg_0 | var_482_arg_1; [L1439] SORT_1 var_483_arg_0 = var_481; [L1440] SORT_1 var_483_arg_1 = var_482; [L1441] SORT_1 var_483 = var_483_arg_0 & var_483_arg_1; [L1442] SORT_1 var_484_arg_0 = ~state_49; [L1443] var_484_arg_0 = var_484_arg_0 & mask_SORT_1 [L1444] SORT_1 var_484_arg_1 = state_51; [L1445] SORT_1 var_484 = var_484_arg_0 & var_484_arg_1; [L1446] SORT_1 var_485_arg_0 = var_483; [L1447] SORT_1 var_485_arg_1 = ~var_484; [L1448] var_485_arg_1 = var_485_arg_1 & mask_SORT_1 [L1449] SORT_1 var_485 = var_485_arg_0 & var_485_arg_1; [L1450] SORT_1 var_486_arg_0 = ~state_49; [L1451] var_486_arg_0 = var_486_arg_0 & mask_SORT_1 [L1452] SORT_1 var_486_arg_1 = state_51; [L1453] SORT_1 var_486 = var_486_arg_0 | var_486_arg_1; [L1454] SORT_1 var_487_arg_0 = var_485; [L1455] SORT_1 var_487_arg_1 = var_486; [L1456] SORT_1 var_487 = var_487_arg_0 & var_487_arg_1; [L1457] SORT_1 var_488_arg_0 = ~state_53; [L1458] var_488_arg_0 = var_488_arg_0 & mask_SORT_1 [L1459] SORT_1 var_488_arg_1 = state_55; [L1460] SORT_1 var_488 = var_488_arg_0 & var_488_arg_1; [L1461] SORT_1 var_489_arg_0 = ~state_53; [L1462] var_489_arg_0 = var_489_arg_0 & mask_SORT_1 [L1463] SORT_1 var_489_arg_1 = state_55; [L1464] SORT_1 var_489 = var_489_arg_0 | var_489_arg_1; [L1465] SORT_1 var_490_arg_0 = state_57; [L1466] SORT_1 var_490_arg_1 = var_489; [L1467] SORT_1 var_490 = var_490_arg_0 & var_490_arg_1; [L1468] SORT_1 var_491_arg_0 = var_488; [L1469] SORT_1 var_491_arg_1 = var_490; [L1470] SORT_1 var_491 = var_491_arg_0 | var_491_arg_1; [L1471] SORT_1 var_492_arg_0 = state_57; [L1472] SORT_1 var_492_arg_1 = var_489; [L1473] SORT_1 var_492 = var_492_arg_0 | var_492_arg_1; [L1474] SORT_1 var_493_arg_0 = state_59; [L1475] SORT_1 var_493_arg_1 = var_492; [L1476] SORT_1 var_493 = var_493_arg_0 & var_493_arg_1; [L1477] SORT_1 var_494_arg_0 = var_491; [L1478] SORT_1 var_494_arg_1 = var_493; [L1479] SORT_1 var_494 = var_494_arg_0 | var_494_arg_1; [L1480] SORT_1 var_495_arg_0 = state_59; [L1481] SORT_1 var_495_arg_1 = var_492; [L1482] SORT_1 var_495 = var_495_arg_0 | var_495_arg_1; [L1483] SORT_1 var_496_arg_0 = state_61; [L1484] SORT_1 var_496_arg_1 = var_495; [L1485] SORT_1 var_496 = var_496_arg_0 & var_496_arg_1; [L1486] SORT_1 var_497_arg_0 = var_494; [L1487] SORT_1 var_497_arg_1 = var_496; [L1488] SORT_1 var_497 = var_497_arg_0 | var_497_arg_1; [L1489] SORT_1 var_498_arg_0 = var_487; [L1490] SORT_1 var_498_arg_1 = ~var_497; [L1491] var_498_arg_1 = var_498_arg_1 & mask_SORT_1 [L1492] SORT_1 var_498 = var_498_arg_0 & var_498_arg_1; [L1493] SORT_1 var_499_arg_0 = state_61; [L1494] SORT_1 var_499_arg_1 = var_495; [L1495] SORT_1 var_499 = var_499_arg_0 | var_499_arg_1; [L1496] SORT_1 var_500_arg_0 = var_498; [L1497] SORT_1 var_500_arg_1 = var_499; [L1498] SORT_1 var_500 = var_500_arg_0 & var_500_arg_1; [L1499] SORT_1 var_501_arg_0 = ~state_63; [L1500] var_501_arg_0 = var_501_arg_0 & mask_SORT_1 [L1501] SORT_1 var_501_arg_1 = state_65; [L1502] SORT_1 var_501 = var_501_arg_0 & var_501_arg_1; [L1503] SORT_1 var_502_arg_0 = ~state_63; [L1504] var_502_arg_0 = var_502_arg_0 & mask_SORT_1 [L1505] SORT_1 var_502_arg_1 = state_65; [L1506] SORT_1 var_502 = var_502_arg_0 | var_502_arg_1; [L1507] SORT_1 var_503_arg_0 = state_67; [L1508] SORT_1 var_503_arg_1 = var_502; [L1509] SORT_1 var_503 = var_503_arg_0 & var_503_arg_1; [L1510] SORT_1 var_504_arg_0 = var_501; [L1511] SORT_1 var_504_arg_1 = var_503; [L1512] SORT_1 var_504 = var_504_arg_0 | var_504_arg_1; [L1513] SORT_1 var_505_arg_0 = state_67; [L1514] SORT_1 var_505_arg_1 = var_502; [L1515] SORT_1 var_505 = var_505_arg_0 | var_505_arg_1; [L1516] SORT_1 var_506_arg_0 = state_69; [L1517] SORT_1 var_506_arg_1 = var_505; [L1518] SORT_1 var_506 = var_506_arg_0 & var_506_arg_1; [L1519] SORT_1 var_507_arg_0 = var_504; [L1520] SORT_1 var_507_arg_1 = var_506; [L1521] SORT_1 var_507 = var_507_arg_0 | var_507_arg_1; [L1522] SORT_1 var_508_arg_0 = state_69; [L1523] SORT_1 var_508_arg_1 = var_505; [L1524] SORT_1 var_508 = var_508_arg_0 | var_508_arg_1; [L1525] SORT_1 var_509_arg_0 = state_71; [L1526] SORT_1 var_509_arg_1 = var_508; [L1527] SORT_1 var_509 = var_509_arg_0 & var_509_arg_1; [L1528] SORT_1 var_510_arg_0 = var_507; [L1529] SORT_1 var_510_arg_1 = var_509; [L1530] SORT_1 var_510 = var_510_arg_0 | var_510_arg_1; [L1531] SORT_1 var_511_arg_0 = var_500; [L1532] SORT_1 var_511_arg_1 = ~var_510; [L1533] var_511_arg_1 = var_511_arg_1 & mask_SORT_1 [L1534] SORT_1 var_511 = var_511_arg_0 & var_511_arg_1; [L1535] SORT_1 var_512_arg_0 = state_71; [L1536] SORT_1 var_512_arg_1 = var_508; [L1537] SORT_1 var_512 = var_512_arg_0 | var_512_arg_1; [L1538] SORT_1 var_513_arg_0 = var_511; [L1539] SORT_1 var_513_arg_1 = var_512; [L1540] SORT_1 var_513 = var_513_arg_0 & var_513_arg_1; [L1541] SORT_1 var_514_arg_0 = var_458; [L1542] SORT_1 var_514_arg_1 = var_513; [L1543] SORT_1 var_514 = var_514_arg_0 & var_514_arg_1; [L1544] SORT_1 var_515_arg_0 = var_214; [L1545] SORT_1 var_515_arg_1 = var_210; [L1546] SORT_1 var_515 = var_515_arg_0 & var_515_arg_1; [L1547] SORT_1 var_516_arg_0 = var_214; [L1548] SORT_1 var_516_arg_1 = var_210; [L1549] SORT_1 var_516 = var_516_arg_0 | var_516_arg_1; [L1550] SORT_1 var_517_arg_0 = var_218; [L1551] SORT_1 var_517_arg_1 = var_516; [L1552] SORT_1 var_517 = var_517_arg_0 & var_517_arg_1; [L1553] SORT_1 var_518_arg_0 = var_515; [L1554] SORT_1 var_518_arg_1 = var_517; [L1555] SORT_1 var_518 = var_518_arg_0 | var_518_arg_1; [L1556] SORT_1 var_519_arg_0 = var_218; [L1557] SORT_1 var_519_arg_1 = var_516; [L1558] SORT_1 var_519 = var_519_arg_0 | var_519_arg_1; [L1559] SORT_1 var_520_arg_0 = var_223; [L1560] SORT_1 var_520_arg_1 = var_519; [L1561] SORT_1 var_520 = var_520_arg_0 & var_520_arg_1; [L1562] SORT_1 var_521_arg_0 = var_518; [L1563] SORT_1 var_521_arg_1 = var_520; [L1564] SORT_1 var_521 = var_521_arg_0 | var_521_arg_1; [L1565] SORT_1 var_522_arg_0 = var_223; [L1566] SORT_1 var_522_arg_1 = var_519; [L1567] SORT_1 var_522 = var_522_arg_0 | var_522_arg_1; [L1568] SORT_1 var_523_arg_0 = var_227; [L1569] SORT_1 var_523_arg_1 = var_522; [L1570] SORT_1 var_523 = var_523_arg_0 & var_523_arg_1; [L1571] SORT_1 var_524_arg_0 = var_521; [L1572] SORT_1 var_524_arg_1 = var_523; [L1573] SORT_1 var_524 = var_524_arg_0 | var_524_arg_1; [L1574] SORT_1 var_525_arg_0 = var_227; [L1575] SORT_1 var_525_arg_1 = var_522; [L1576] SORT_1 var_525 = var_525_arg_0 | var_525_arg_1; [L1577] SORT_1 var_526_arg_0 = var_232; [L1578] SORT_1 var_526_arg_1 = var_525; [L1579] SORT_1 var_526 = var_526_arg_0 & var_526_arg_1; [L1580] SORT_1 var_527_arg_0 = var_524; [L1581] SORT_1 var_527_arg_1 = var_526; [L1582] SORT_1 var_527 = var_527_arg_0 | var_527_arg_1; [L1583] SORT_1 var_528_arg_0 = var_232; [L1584] SORT_1 var_528_arg_1 = var_525; [L1585] SORT_1 var_528 = var_528_arg_0 | var_528_arg_1; [L1586] SORT_1 var_529_arg_0 = var_241; [L1587] SORT_1 var_529_arg_1 = var_528; [L1588] SORT_1 var_529 = var_529_arg_0 & var_529_arg_1; [L1589] SORT_1 var_530_arg_0 = var_527; [L1590] SORT_1 var_530_arg_1 = var_529; [L1591] SORT_1 var_530 = var_530_arg_0 | var_530_arg_1; [L1592] SORT_1 var_531_arg_0 = var_241; [L1593] SORT_1 var_531_arg_1 = var_528; [L1594] SORT_1 var_531 = var_531_arg_0 | var_531_arg_1; [L1595] SORT_1 var_532_arg_0 = var_245; [L1596] SORT_1 var_532_arg_1 = var_531; [L1597] SORT_1 var_532 = var_532_arg_0 & var_532_arg_1; [L1598] SORT_1 var_533_arg_0 = var_530; [L1599] SORT_1 var_533_arg_1 = var_532; [L1600] SORT_1 var_533 = var_533_arg_0 | var_533_arg_1; [L1601] SORT_1 var_534_arg_0 = var_245; [L1602] SORT_1 var_534_arg_1 = var_531; [L1603] SORT_1 var_534 = var_534_arg_0 | var_534_arg_1; [L1604] SORT_1 var_535_arg_0 = var_249; [L1605] SORT_1 var_535_arg_1 = var_534; [L1606] SORT_1 var_535 = var_535_arg_0 & var_535_arg_1; [L1607] SORT_1 var_536_arg_0 = var_533; [L1608] SORT_1 var_536_arg_1 = var_535; [L1609] SORT_1 var_536 = var_536_arg_0 | var_536_arg_1; [L1610] SORT_1 var_537_arg_0 = ~state_29; [L1611] var_537_arg_0 = var_537_arg_0 & mask_SORT_1 [L1612] SORT_1 var_537_arg_1 = ~var_536; [L1613] var_537_arg_1 = var_537_arg_1 & mask_SORT_1 [L1614] SORT_1 var_537 = var_537_arg_0 & var_537_arg_1; [L1615] SORT_1 var_538_arg_0 = var_249; [L1616] SORT_1 var_538_arg_1 = var_534; [L1617] SORT_1 var_538 = var_538_arg_0 | var_538_arg_1; [L1618] SORT_1 var_539_arg_0 = var_537; [L1619] SORT_1 var_539_arg_1 = var_538; [L1620] SORT_1 var_539 = var_539_arg_0 & var_539_arg_1; [L1621] SORT_1 var_540_arg_0 = var_252; [L1622] SORT_1 var_540_arg_1 = var_255; [L1623] SORT_1 var_540 = var_540_arg_0 & var_540_arg_1; [L1624] SORT_1 var_541_arg_0 = var_539; [L1625] SORT_1 var_541_arg_1 = ~var_540; [L1626] var_541_arg_1 = var_541_arg_1 & mask_SORT_1 [L1627] SORT_1 var_541 = var_541_arg_0 & var_541_arg_1; [L1628] SORT_1 var_542_arg_0 = var_252; [L1629] SORT_1 var_542_arg_1 = var_255; [L1630] SORT_1 var_542 = var_542_arg_0 | var_542_arg_1; [L1631] SORT_1 var_543_arg_0 = var_541; [L1632] SORT_1 var_543_arg_1 = var_542; [L1633] SORT_1 var_543 = var_543_arg_0 & var_543_arg_1; [L1634] SORT_1 var_544_arg_0 = var_262; [L1635] SORT_1 var_544_arg_1 = var_259; [L1636] SORT_1 var_544 = var_544_arg_0 & var_544_arg_1; [L1637] SORT_1 var_545_arg_0 = var_262; [L1638] SORT_1 var_545_arg_1 = var_259; [L1639] SORT_1 var_545 = var_545_arg_0 | var_545_arg_1; [L1640] SORT_1 var_546_arg_0 = var_266; [L1641] SORT_1 var_546_arg_1 = var_545; [L1642] SORT_1 var_546 = var_546_arg_0 & var_546_arg_1; [L1643] SORT_1 var_547_arg_0 = var_544; [L1644] SORT_1 var_547_arg_1 = var_546; [L1645] SORT_1 var_547 = var_547_arg_0 | var_547_arg_1; [L1646] SORT_1 var_548_arg_0 = var_266; [L1647] SORT_1 var_548_arg_1 = var_545; [L1648] SORT_1 var_548 = var_548_arg_0 | var_548_arg_1; [L1649] SORT_1 var_549_arg_0 = var_271; [L1650] SORT_1 var_549_arg_1 = var_548; [L1651] SORT_1 var_549 = var_549_arg_0 & var_549_arg_1; [L1652] SORT_1 var_550_arg_0 = var_547; [L1653] SORT_1 var_550_arg_1 = var_549; [L1654] SORT_1 var_550 = var_550_arg_0 | var_550_arg_1; [L1655] SORT_1 var_551_arg_0 = var_271; [L1656] SORT_1 var_551_arg_1 = var_548; [L1657] SORT_1 var_551 = var_551_arg_0 | var_551_arg_1; [L1658] SORT_1 var_552_arg_0 = var_274; [L1659] SORT_1 var_552_arg_1 = var_551; [L1660] SORT_1 var_552 = var_552_arg_0 & var_552_arg_1; [L1661] SORT_1 var_553_arg_0 = var_550; [L1662] SORT_1 var_553_arg_1 = var_552; [L1663] SORT_1 var_553 = var_553_arg_0 | var_553_arg_1; [L1664] SORT_1 var_554_arg_0 = var_543; [L1665] SORT_1 var_554_arg_1 = ~var_553; [L1666] var_554_arg_1 = var_554_arg_1 & mask_SORT_1 [L1667] SORT_1 var_554 = var_554_arg_0 & var_554_arg_1; [L1668] SORT_1 var_555_arg_0 = var_274; [L1669] SORT_1 var_555_arg_1 = var_551; [L1670] SORT_1 var_555 = var_555_arg_0 | var_555_arg_1; [L1671] SORT_1 var_556_arg_0 = var_554; [L1672] SORT_1 var_556_arg_1 = var_555; [L1673] SORT_1 var_556 = var_556_arg_0 & var_556_arg_1; [L1674] SORT_1 var_557_arg_0 = var_281; [L1675] SORT_1 var_557_arg_1 = var_278; [L1676] SORT_1 var_557 = var_557_arg_0 & var_557_arg_1; [L1677] SORT_1 var_558_arg_0 = var_281; [L1678] SORT_1 var_558_arg_1 = var_278; [L1679] SORT_1 var_558 = var_558_arg_0 | var_558_arg_1; [L1680] SORT_1 var_559_arg_0 = var_285; [L1681] SORT_1 var_559_arg_1 = var_558; [L1682] SORT_1 var_559 = var_559_arg_0 & var_559_arg_1; [L1683] SORT_1 var_560_arg_0 = var_557; [L1684] SORT_1 var_560_arg_1 = var_559; [L1685] SORT_1 var_560 = var_560_arg_0 | var_560_arg_1; [L1686] SORT_1 var_561_arg_0 = var_285; [L1687] SORT_1 var_561_arg_1 = var_558; [L1688] SORT_1 var_561 = var_561_arg_0 | var_561_arg_1; [L1689] SORT_1 var_562_arg_0 = var_290; [L1690] SORT_1 var_562_arg_1 = var_561; [L1691] SORT_1 var_562 = var_562_arg_0 & var_562_arg_1; [L1692] SORT_1 var_563_arg_0 = var_560; [L1693] SORT_1 var_563_arg_1 = var_562; [L1694] SORT_1 var_563 = var_563_arg_0 | var_563_arg_1; [L1695] SORT_1 var_564_arg_0 = var_290; [L1696] SORT_1 var_564_arg_1 = var_561; [L1697] SORT_1 var_564 = var_564_arg_0 | var_564_arg_1; [L1698] SORT_1 var_565_arg_0 = var_293; [L1699] SORT_1 var_565_arg_1 = var_564; [L1700] SORT_1 var_565 = var_565_arg_0 & var_565_arg_1; [L1701] SORT_1 var_566_arg_0 = var_563; [L1702] SORT_1 var_566_arg_1 = var_565; [L1703] SORT_1 var_566 = var_566_arg_0 | var_566_arg_1; [L1704] SORT_1 var_567_arg_0 = var_556; [L1705] SORT_1 var_567_arg_1 = ~var_566; [L1706] var_567_arg_1 = var_567_arg_1 & mask_SORT_1 [L1707] SORT_1 var_567 = var_567_arg_0 & var_567_arg_1; [L1708] SORT_1 var_568_arg_0 = var_293; [L1709] SORT_1 var_568_arg_1 = var_564; [L1710] SORT_1 var_568 = var_568_arg_0 | var_568_arg_1; [L1711] SORT_1 var_569_arg_0 = var_567; [L1712] SORT_1 var_569_arg_1 = var_568; [L1713] SORT_1 var_569 = var_569_arg_0 & var_569_arg_1; [L1714] SORT_1 var_570_arg_0 = var_514; [L1715] SORT_1 var_570_arg_1 = var_569; [L1716] SORT_1 var_570 = var_570_arg_0 & var_570_arg_1; [L1717] SORT_1 var_571_arg_0 = var_570; [L1718] SORT_1 var_571_arg_1 = ~state_73; [L1719] var_571_arg_1 = var_571_arg_1 & mask_SORT_1 [L1720] SORT_1 var_571 = var_571_arg_0 & var_571_arg_1; [L1721] SORT_1 next_572_arg_1 = ~var_571; [L1722] next_572_arg_1 = next_572_arg_1 & mask_SORT_1 [L1724] state_6 = next_94_arg_1 [L1725] state_8 = next_95_arg_1 [L1726] state_10 = next_96_arg_1 [L1727] state_12 = next_127_arg_1 [L1728] state_14 = next_139_arg_1 [L1729] state_16 = next_147_arg_1 [L1730] state_18 = next_169_arg_1 [L1731] state_20 = next_180_arg_1 [L1732] state_22 = next_191_arg_1 [L1733] state_24 = next_201_arg_1 [L1734] state_26 = next_206_arg_1 [L1735] state_29 = next_207_arg_1 [L1736] state_31 = next_211_arg_1 [L1737] state_33 = next_215_arg_1 [L1738] state_35 = next_219_arg_1 [L1739] state_37 = next_224_arg_1 [L1740] state_39 = next_228_arg_1 [L1741] state_41 = next_233_arg_1 [L1742] state_43 = next_242_arg_1 [L1743] state_45 = next_246_arg_1 [L1744] state_47 = next_250_arg_1 [L1745] state_49 = next_253_arg_1 [L1746] state_51 = next_256_arg_1 [L1747] state_53 = next_260_arg_1 [L1748] state_55 = next_263_arg_1 [L1749] state_57 = next_267_arg_1 [L1750] state_59 = next_272_arg_1 [L1751] state_61 = next_275_arg_1 [L1752] state_63 = next_279_arg_1 [L1753] state_65 = next_282_arg_1 [L1754] state_67 = next_286_arg_1 [L1755] state_69 = next_291_arg_1 [L1756] state_71 = next_294_arg_1 [L1757] state_73 = next_572_arg_1 VAL [bad_77_arg_0=0, init_11_arg_1=0, init_13_arg_1=0, init_15_arg_1=0, init_17_arg_1=0, init_19_arg_1=0, init_21_arg_1=0, init_23_arg_1=0, init_25_arg_1=0, init_27_arg_1=0, init_30_arg_1=0, init_32_arg_1=0, init_34_arg_1=0, init_36_arg_1=0, init_38_arg_1=0, init_40_arg_1=0, init_42_arg_1=0, init_44_arg_1=0, init_46_arg_1=0, init_48_arg_1=0, init_50_arg_1=0, init_52_arg_1=0, init_54_arg_1=0, init_56_arg_1=0, init_58_arg_1=0, init_60_arg_1=0, init_62_arg_1=0, init_64_arg_1=0, init_66_arg_1=0, init_68_arg_1=0, init_70_arg_1=0, init_72_arg_1=0, init_74_arg_1=0, init_7_arg_1=0, init_9_arg_1=0, input_100=1, input_101=0, input_102=1, input_103=1, input_104=1, input_105=1, input_106=0, input_149=0, input_151=0, input_154=0, input_156=1, input_192=1, input_222=45, input_225=255, input_78=1, input_79=0, input_81=1, input_83=1, input_84=1, input_85=0, input_86=0, input_98=1, input_99=1, mask_SORT_1=1, mask_SORT_2=255, mask_SORT_3=4294967295, mask_SORT_4=4294967295, msb_SORT_1=1, msb_SORT_2=128, msb_SORT_3=8388608, msb_SORT_4=2147483648, next_127_arg_1=0, next_139_arg_1=0, next_147_arg_1=0, next_169_arg_1=0, next_180_arg_1=0, next_191_arg_1=0, next_201_arg_1=0, next_206_arg_1=0, next_207_arg_1=0, next_211_arg_1=0, next_215_arg_1=1, next_219_arg_1=1, next_224_arg_1=30, next_228_arg_1=1, next_233_arg_1=0, next_242_arg_1=0, next_246_arg_1=0, next_250_arg_1=1, next_253_arg_1=1, next_256_arg_1=1, next_260_arg_1=1, next_263_arg_1=0, next_267_arg_1=1, next_272_arg_1=0, next_275_arg_1=1, next_279_arg_1=0, next_282_arg_1=0, next_286_arg_1=1, next_291_arg_1=1, next_294_arg_1=1, next_572_arg_1=0, next_94_arg_1=0, next_95_arg_1=0, next_96_arg_1=0, state_10=0, state_12=0, state_14=0, state_16=0, state_18=0, state_20=0, state_22=0, state_24=0, state_26=0, state_29=0, state_31=0, state_33=1, state_35=1, state_37=30, state_39=1, state_41=0, state_43=0, state_45=0, state_47=1, state_49=1, state_51=1, state_53=1, state_55=0, state_57=1, state_59=0, state_6=0, state_61=1, state_63=0, state_65=0, state_67=1, state_69=1, state_71=1, state_73=0, state_8=0, var_107=1, var_108=0, var_109=0, var_109_arg_0=0, var_109_arg_1=0, var_110=1, var_110_arg_0=1, var_110_arg_1=0, var_111=1, var_111_arg_0=1, var_112=0, var_112_arg_0=0, var_112_arg_1=1, var_112_arg_2=0, var_113=0, var_113_arg_0=1, var_113_arg_1=0, var_113_arg_2=0, var_114=0, var_114_arg_0=1, var_114_arg_1=0, var_114_arg_2=0, var_115=0, var_115_arg_0=1, var_115_arg_1=0, var_115_arg_2=0, var_116=0, var_116_arg_0=1, var_116_arg_1=0, var_116_arg_2=0, var_117=0, var_117_arg_0=0, var_117_arg_1=0, var_117_arg_2=0, var_118=0, var_118_arg_0=0, var_118_arg_1=0, var_118_arg_2=0, var_119=0, var_119_arg_0=1, var_119_arg_1=0, var_119_arg_2=0, var_120=0, var_120_arg_0=1, var_120_arg_1=0, var_120_arg_2=0, var_121=0, var_121_arg_0=0, var_121_arg_1=0, var_121_arg_2=0, var_122=0, var_122_arg_0=1, var_122_arg_1=0, var_122_arg_2=0, var_123=0, var_123_arg_0=1, var_123_arg_1=0, var_123_arg_2=0, var_124=0, var_124_arg_0=1, var_124_arg_1=0, var_124_arg_2=0, var_125=0, var_125_arg_0=1, var_125_arg_1=0, var_125_arg_2=0, var_126=0, var_126_arg_0=0, var_126_arg_1=0, var_126_arg_2=0, var_128=25, var_129=15, var_130=20, var_131=5, var_132=5, var_132_arg_0=1, var_132_arg_1=5, var_132_arg_2=0, var_133=5, var_133_arg_0=1, var_133_arg_1=5, var_133_arg_2=5, var_134=5, var_134_arg_0=0, var_134_arg_1=20, var_134_arg_2=5, var_135=5, var_135_arg_0=0, var_135_arg_1=20, var_135_arg_2=5, var_136=5, var_136_arg_0=0, var_136_arg_1=25, var_136_arg_2=5, var_137=15, var_137_arg_0=1, var_137_arg_1=15, var_137_arg_2=5, var_138=0, var_138_arg_0=1, var_138_arg_1=25, var_138_arg_2=15, var_140=5, var_140_arg_0=1, var_140_arg_1=5, var_140_arg_2=0, var_141=5, var_141_arg_0=1, var_141_arg_1=5, var_141_arg_2=5, var_142=20, var_142_arg_0=1, var_142_arg_1=20, var_142_arg_2=5, var_143=20, var_143_arg_0=1, var_143_arg_1=20, var_143_arg_2=20, var_144=25, var_144_arg_0=1, var_144_arg_1=25, var_144_arg_2=20, var_145=15, var_145_arg_0=1, var_145_arg_1=15, var_145_arg_2=25, var_146=0, var_146_arg_0=0, var_146_arg_1=25, var_146_arg_2=15, var_148=1, var_148_arg_0=0, var_148_arg_1=0, var_150=0, var_150_arg_0=1, var_150_arg_1=0, var_152=0, var_152_arg_0=1, var_152_arg_1=0, var_153=1, var_153_arg_0=0, var_153_arg_1=0, var_155=0, var_155_arg_0=1, var_155_arg_1=0, var_157=1, var_157_arg_0=1, var_157_arg_1=1, var_158=0, var_159=0, var_159_arg_0=0, var_159_arg_1=0, var_160=1, var_160_arg_0=1, var_160_arg_1=0, var_161=0, var_161_arg_0=0, var_161_arg_1=1, var_162=1, var_162_arg_0=1, var_162_arg_1=1, var_163=0, var_163_arg_0=1, var_163_arg_1=0, var_163_arg_2=0, var_164=0, var_164_arg_0=0, var_164_arg_1=0, var_164_arg_2=0, var_165=0, var_165_arg_0=1, var_165_arg_1=0, var_165_arg_2=0, var_166=0, var_166_arg_0=0, var_166_arg_1=0, var_166_arg_2=0, var_167=0, var_167_arg_0=0, var_167_arg_1=0, var_167_arg_2=0, var_168=0, var_168_arg_0=0, var_168_arg_1=0, var_168_arg_2=0, var_170=0, var_170_arg_0=1, var_170_arg_1=0, var_171=0, var_171_arg_0=0, var_171_arg_1=0, var_172=0, var_172_arg_0=0, var_172_arg_1=0, var_173=0, var_173_arg_0=1, var_173_arg_1=0, var_174=0, var_174_arg_0=0, var_174_arg_1=0, var_175=0, var_175_arg_0=1, var_175_arg_1=0, var_176=0, var_176_arg_0=0, var_176_arg_1=0, var_176_arg_2=0, var_177=0, var_177_arg_0=0, var_177_arg_1=0, var_177_arg_2=0, var_178=0, var_178_arg_0=0, var_178_arg_1=0, var_178_arg_2=0, var_179=0, var_179_arg_0=0, var_179_arg_1=0, var_179_arg_2=0, var_181=0, var_181_arg_0=2, var_181_arg_1=0, var_182=0, var_182_arg_0=0, var_182_arg_1=0, var_183=0, var_183_arg_0=0, var_183_arg_1=0, var_184=0, var_184_arg_0=2, var_184_arg_1=0, var_185=0, var_185_arg_0=0, var_185_arg_1=0, var_186=0, var_186_arg_0=1, var_186_arg_1=0, var_187=0, var_187_arg_0=0, var_187_arg_1=0, var_187_arg_2=0, var_188=0, var_188_arg_0=0, var_188_arg_1=0, var_188_arg_2=0, var_189=0, var_189_arg_0=0, var_189_arg_1=0, var_189_arg_2=0, var_190=0, var_190_arg_0=0, var_190_arg_1=0, var_190_arg_2=0, var_193=0, var_193_arg_0=0, var_193_arg_1=0, var_194=4294967295, var_194_arg_0=0, var_194_arg_1=1, var_195=255, var_195_arg_0=4294967295, var_196=1, var_196_arg_0=1, var_196_arg_1=0, var_197=1, var_197_arg_0=1, var_198=0, var_198_arg_0=0, var_198_arg_1=1, var_198_arg_2=0, var_199=0, var_199_arg_0=0, var_199_arg_1=1, var_199_arg_2=0, var_200=0, var_200_arg_0=1, var_200_arg_1=255, var_200_arg_2=0, var_202=1, var_202_arg_0=1, var_203=1, var_203_arg_0=1, var_203_arg_1=1, var_203_arg_2=0, var_204=1, var_204_arg_0=0, var_204_arg_1=0, var_204_arg_2=1, var_205=0, var_205_arg_0=1, var_205_arg_1=0, var_205_arg_2=1, var_208=1, var_208_arg_0=0, var_208_arg_1=1, var_209=1, var_209_arg_0=1, var_209_arg_1=0, var_210=0, var_210_arg_0=1, var_210_arg_1=0, var_212=0, var_212_arg_0=0, var_212_arg_1=0, var_213=1, var_213_arg_0=0, var_213_arg_1=1, var_214=1, var_214_arg_0=1, var_214_arg_1=1, var_216=0, var_216_arg_0=0, var_216_arg_1=0, var_217=1, var_217_arg_0=0, var_217_arg_1=1, var_218=1, var_218_arg_0=1, var_218_arg_1=1, var_220=0, var_220_arg_0=0, var_220_arg_1=0, var_221=0, var_221_arg_0=0, var_221_arg_1=1, var_223=30, var_223_arg_0=0, var_223_arg_1=45, var_226=1, var_226_arg_0=0, var_226_arg_1=255, var_227=1, var_227_arg_0=1, var_227_arg_1=1, var_229=0, var_229_arg_0=0, var_229_arg_1=0, var_230=1, var_230_arg_0=0, var_230_arg_1=1, var_231=0, var_231_arg_0=1, var_231_arg_1=0, var_232=0, var_232_arg_0=0, var_232_arg_1=1, var_234=0, var_234_arg_0=0, var_234_arg_1=0, var_235=0, var_235_arg_0=0, var_235_arg_1=0, var_236=1, var_236_arg_0=0, var_236_arg_1=1, var_237=1, var_237_arg_0=1, var_237_arg_1=1, var_238=0, var_238_arg_0=1, var_238_arg_1=0, var_239=0, var_239_arg_0=0, var_239_arg_1=1, var_240=0, var_240_arg_0=0, var_240_arg_1=0, var_241=0, var_241_arg_0=0, var_241_arg_1=0, var_243=1, var_243_arg_0=1, var_243_arg_1=1, var_244=1, var_244_arg_0=1, var_244_arg_1=1, var_245=1, var_245_arg_0=1, var_245_arg_1=1, var_247=0, var_247_arg_0=0, var_247_arg_1=1, var_248=0, var_248_arg_0=0, var_248_arg_1=0, var_249=1, var_249_arg_0=0, var_249_arg_1=1, var_251=1, var_251_arg_0=1, var_251_arg_1=0, var_252=1, var_252_arg_0=1, var_252_arg_1=1, var_254=0, var_254_arg_0=0, var_254_arg_1=1, var_255=1, var_255_arg_0=0, var_255_arg_1=1, var_257=1, var_257_arg_0=1, var_257_arg_1=1, var_258=1, var_258_arg_0=1, var_258_arg_1=1, var_259=1, var_259_arg_0=1, var_259_arg_1=1, var_261=0, var_261_arg_0=0, var_261_arg_1=0, var_262=0, var_262_arg_0=0, var_262_arg_1=0, var_264=1, var_264_arg_0=0, var_264_arg_1=1, var_265=1, var_265_arg_0=1, var_265_arg_1=1, var_266=1, var_266_arg_0=1, var_266_arg_1=1, var_268=0, var_268_arg_0=0, var_268_arg_1=1, var_269=0, var_269_arg_0=0, var_269_arg_1=0, var_270=0, var_270_arg_0=0, var_270_arg_1=0, var_271=0, var_271_arg_0=0, var_271_arg_1=1, var_273=0, var_273_arg_0=0, var_273_arg_1=1, var_274=1, var_274_arg_0=0, var_274_arg_1=1, var_276=1, var_276_arg_0=1, var_276_arg_1=1, var_277=0, var_277_arg_0=1, var_277_arg_1=0, var_278=0, var_278_arg_0=0, var_278_arg_1=0, var_28=0, var_280=1, var_280_arg_0=0, var_280_arg_1=1, var_281=0, var_281_arg_0=1, var_281_arg_1=0, var_283=1, var_283_arg_0=0, var_283_arg_1=1, var_284=1, var_284_arg_0=1, var_284_arg_1=1, var_285=1, var_285_arg_0=1, var_285_arg_1=1, var_287=0, var_287_arg_0=0, var_287_arg_1=0, var_288=1, var_288_arg_0=0, var_288_arg_1=1, var_289=1, var_289_arg_0=1, var_289_arg_1=1, var_290=1, var_290_arg_0=1, var_290_arg_1=1, var_292=0, var_292_arg_0=0, var_292_arg_1=0, var_293=1, var_293_arg_0=0, var_293_arg_1=1, var_295=0, var_295_arg_0=0, var_295_arg_1=0, var_296=1, var_296_arg_0=0, var_296_arg_1=0, var_297=0, var_297_arg_0=0, var_297_arg_1=0, var_298=1, var_298_arg_0=0, var_298_arg_1=0, var_299=1, var_299_arg_0=1, var_299_arg_1=1, var_300=1, var_300_arg_0=1, var_300_arg_1=1, var_301=1, var_301_arg_0=1, var_301_arg_1=1, var_302=1, var_302_arg_0=0, var_302_arg_1=0, var_303=0, var_303_arg_0=0, var_303_arg_1=1, var_304=1, var_304_arg_0=1, var_304_arg_1=0, var_305=1, var_305_arg_0=1, var_305_arg_1=1, var_306=1, var_306_arg_0=0, var_306_arg_1=0, var_307=0, var_307_arg_0=0, var_307_arg_1=1, var_308=1, var_308_arg_0=1, var_308_arg_1=0, var_309=1, var_309_arg_0=1, var_309_arg_1=1, var_310=10, var_311=0, var_311_arg_0=10, var_311_arg_1=0, var_312=0, var_312_arg_0=0, var_312_arg_1=0, var_313=1, var_313_arg_0=1, var_313_arg_1=0, var_314=1, var_314_arg_0=1, var_314_arg_1=1, var_315=5, var_316=0, var_316_arg_0=5, var_316_arg_1=0, var_317=0, var_317_arg_0=0, var_317_arg_1=0, var_318=1, var_318_arg_0=1, var_318_arg_1=0, var_319=1, var_319_arg_0=1, var_319_arg_1=1, var_320=0, var_320_arg_0=0, var_320_arg_1=0, var_321=1, var_321_arg_0=1, var_321_arg_1=0, var_322=1, var_322_arg_0=1, var_322_arg_1=1, var_323=0, var_323_arg_0=0, var_323_arg_1=0, var_324=1, var_324_arg_0=1, var_324_arg_1=0, var_325=1, var_325_arg_0=1, var_325_arg_1=1, var_326=0, var_326_arg_0=0, var_326_arg_1=1, var_327=1, var_327_arg_0=1, var_327_arg_1=0, var_328=1, var_328_arg_0=1, var_328_arg_1=1, var_329=0, var_329_arg_0=0, var_329_arg_1=0, var_330=0, var_330_arg_0=0, var_330_arg_1=0, var_331=0, var_331_arg_0=1, var_331_arg_1=0, var_332=0, var_332_arg_0=0, var_332_arg_1=0, var_333=0, var_333_arg_0=0, var_333_arg_1=0, var_334=0, var_334_arg_0=0, var_334_arg_1=0, var_335=0, var_335_arg_0=0, var_335_arg_1=1, var_336=1, var_336_arg_0=1, var_336_arg_1=0, var_337=0, var_337_arg_0=0, var_337_arg_1=1, var_338=0, var_338_arg_0=0, var_338_arg_1=0, var_339=1, var_339_arg_0=0, var_339_arg_1=10, var_340=0, var_340_arg_0=1, var_340_arg_1=0, var_341=0, var_341_arg_0=1, var_341_arg_1=0, var_342=0, var_342_arg_0=0, var_342_arg_1=0, var_343=1, var_343_arg_0=1, var_343_arg_1=0, var_344=0, var_344_arg_0=0, var_344_arg_1=1, var_345=0, var_345_arg_0=0, var_345_arg_1=0, var_346=0, var_346_arg_0=2, var_346_arg_1=0, var_347=0, var_347_arg_0=1, var_347_arg_1=0, var_348=0, var_348_arg_0=0, var_348_arg_1=0, var_349=1, var_349_arg_0=1, var_349_arg_1=0, var_350=0, var_350_arg_0=0, var_350_arg_1=1, var_351=0, var_351_arg_0=0, var_351_arg_1=0, var_352=0, var_352_arg_0=0, var_352_arg_1=0, var_353=1, var_353_arg_0=1, var_353_arg_1=0, var_354=0, var_354_arg_0=0, var_354_arg_1=1, var_355=0, var_355_arg_0=0, var_355_arg_1=0, var_356=0, var_356_arg_0=0, var_356_arg_1=0, var_357=1, var_357_arg_0=1, var_357_arg_1=0, var_358=0, var_358_arg_0=0, var_358_arg_1=1, var_359=0, var_359_arg_0=0, var_359_arg_1=0, var_360=3, var_361=0, var_361_arg_0=3, var_361_arg_1=0, var_362=0, var_362_arg_0=0, var_362_arg_1=0, var_363=1, var_363_arg_0=1, var_363_arg_1=0, var_364=0, var_364_arg_0=0, var_364_arg_1=1, var_365=0, var_365_arg_0=0, var_365_arg_1=0, var_366=0, var_366_arg_0=0, var_366_arg_1=0, var_367=1, var_367_arg_0=1, var_367_arg_1=0, var_368=0, var_368_arg_0=0, var_368_arg_1=1, var_369=0, var_369_arg_0=0, var_369_arg_1=0, var_370=0, var_370_arg_0=0, var_370_arg_1=1, var_371=1, var_371_arg_0=1, var_371_arg_1=0, var_372=0, var_372_arg_0=0, var_372_arg_1=1, var_373=0, var_373_arg_0=1, var_373_arg_1=0, var_374=1, var_374_arg_0=0, var_374_arg_1=0, var_375=0, var_375_arg_0=0, var_375_arg_1=1, var_376=1, var_376_arg_0=1, var_376_arg_1=0, var_377=0, var_377_arg_0=0, var_377_arg_1=1, var_378=0, var_378_arg_0=0, var_378_arg_1=0, var_379=1, var_379_arg_0=1, var_379_arg_1=0, var_380=0, var_380_arg_0=0, var_380_arg_1=1, var_381=0, var_381_arg_0=0, var_381_arg_1=0, var_382=1, var_382_arg_0=1, var_382_arg_1=0, var_383=0, var_383_arg_0=0, var_383_arg_1=1, var_384=0, var_384_arg_0=0, var_384_arg_1=1, var_385=0, var_385_arg_0=0, var_385_arg_1=0, var_386=0, var_386_arg_0=0, var_386_arg_1=0, var_387=0, var_387_arg_0=0, var_387_arg_1=1, var_388=0, var_388_arg_0=1, var_388_arg_1=0, var_389=0, var_389_arg_0=0, var_389_arg_1=0, var_390=0, var_390_arg_0=0, var_390_arg_1=0, var_391=0, var_391_arg_0=0, var_391_arg_1=0, var_392=1, var_392_arg_0=0, var_392_arg_1=1, var_393=1, var_393_arg_0=0, var_393_arg_1=1, var_394=1, var_394_arg_0=1, var_394_arg_1=1, var_395=1, var_395_arg_0=1, var_395_arg_1=1, var_396=1, var_396_arg_0=1, var_396_arg_1=1, var_397=1, var_397_arg_0=1, var_397_arg_1=1, var_398=1, var_398_arg_0=0, var_398_arg_1=1, var_399=1, var_399_arg_0=0, var_399_arg_1=1, var_400=1, var_400_arg_0=1, var_400_arg_1=1, var_401=1, var_401_arg_0=1, var_401_arg_1=1, var_402=1, var_402_arg_0=0, var_402_arg_1=1, var_403=1, var_403_arg_0=1, var_403_arg_1=1, var_404=1, var_404_arg_0=1, var_404_arg_1=1, var_405=1, var_405_arg_0=1, var_405_arg_1=1, var_406=1, var_406_arg_0=1, var_406_arg_1=1, var_407=1, var_407_arg_0=0, var_407_arg_1=1, var_408=1, var_408_arg_0=45, var_408_arg_1=1, var_409=1, var_409_arg_0=255, var_409_arg_1=1, var_410=1, var_410_arg_0=1, var_410_arg_1=1, var_411=1, var_411_arg_0=0, var_411_arg_1=1, var_412=1, var_412_arg_0=0, var_412_arg_1=1, var_413=1, var_413_arg_0=1, var_413_arg_1=1, var_414=0, var_414_arg_0=0, var_414_arg_1=1, var_415=0, var_415_arg_0=0, var_415_arg_1=1, var_416=0, var_416_arg_0=0, var_416_arg_1=1, var_417=0, var_417_arg_0=0, var_417_arg_1=0, var_418=1, var_418_arg_0=1, var_418_arg_1=1, var_419=1, var_419_arg_0=0, var_419_arg_1=1, var_420=1, var_420_arg_0=1, var_420_arg_1=1, var_421=1, var_421_arg_0=1, var_421_arg_1=1, var_422=1, var_422_arg_0=1, var_422_arg_1=1, var_423=1, var_423_arg_0=1, var_423_arg_1=1, var_424=1, var_424_arg_0=1, var_424_arg_1=1, var_425=1, var_425_arg_0=1, var_425_arg_1=1, var_426=0, var_426_arg_0=0, var_426_arg_1=1, var_427=1, var_427_arg_0=1, var_427_arg_1=0, var_428=0, var_428_arg_0=0, var_428_arg_1=1, var_429=1, var_429_arg_0=1, var_429_arg_1=0, var_430=1, var_430_arg_0=1, var_430_arg_1=1, var_431=1, var_431_arg_0=1, var_431_arg_1=1, var_432=1, var_432_arg_0=1, var_432_arg_1=1, var_433=1, var_433_arg_0=1, var_433_arg_1=1, var_434=0, var_434_arg_0=0, var_434_arg_1=1, var_435=1, var_435_arg_0=1, var_435_arg_1=0, var_436=1, var_436_arg_0=1, var_436_arg_1=1, var_437=1, var_437_arg_0=1, var_437_arg_1=1, var_438=1, var_438_arg_0=1, var_438_arg_1=1, var_439=1, var_439_arg_0=1, var_439_arg_1=1, var_440=1, var_440_arg_0=1, var_440_arg_1=1, var_441=1, var_441_arg_0=1, var_441_arg_1=1, var_442=1, var_442_arg_0=1, var_442_arg_1=1, var_443=1, var_443_arg_0=1, var_443_arg_1=1, var_444=0, var_444_arg_0=0, var_444_arg_1=1, var_445=1, var_445_arg_0=1, var_445_arg_1=0, var_446=1, var_446_arg_0=45, var_446_arg_1=1, var_447=1, var_447_arg_0=1, var_447_arg_1=1, var_448=1, var_448_arg_0=255, var_448_arg_1=1, var_449=1, var_449_arg_0=1, var_449_arg_1=1, var_450=1, var_450_arg_0=1, var_450_arg_1=1, var_451=1, var_451_arg_0=1, var_451_arg_1=1, var_452=0, var_452_arg_0=0, var_452_arg_1=1, var_453=1, var_453_arg_0=1, var_453_arg_1=0, var_454=0, var_454_arg_0=0, var_454_arg_1=1, var_455=1, var_455_arg_0=1, var_455_arg_1=0, var_456=1, var_456_arg_0=1, var_456_arg_1=1, var_457=1, var_457_arg_0=1, var_457_arg_1=1, var_458=0, var_458_arg_0=0, var_458_arg_1=1, var_459=0, var_459_arg_0=0, var_459_arg_1=0, var_460=0, var_460_arg_0=0, var_460_arg_1=0, var_461=0, var_461_arg_0=0, var_461_arg_1=0, var_462=0, var_462_arg_0=0, var_462_arg_1=0, var_463=0, var_463_arg_0=0, var_463_arg_1=0, var_464=0, var_464_arg_0=0, var_464_arg_1=0, var_465=0, var_465_arg_0=0, var_465_arg_1=0, var_466=0, var_466_arg_0=0, var_466_arg_1=0, var_467=0, var_467_arg_0=0, var_467_arg_1=0, var_468=0, var_468_arg_0=0, var_468_arg_1=0, var_469=0, var_469_arg_0=0, var_469_arg_1=0, var_470=0, var_470_arg_0=0, var_470_arg_1=0, var_471=0, var_471_arg_0=0, var_471_arg_1=0, var_472=0, var_472_arg_0=0, var_472_arg_1=0, var_473=0, var_473_arg_0=0, var_473_arg_1=0, var_474=0, var_474_arg_0=0, var_474_arg_1=0, var_475=0, var_475_arg_0=0, var_475_arg_1=0, var_476=0, var_476_arg_0=1, var_476_arg_1=0, var_477=0, var_477_arg_0=0, var_477_arg_1=0, var_478=1, var_478_arg_0=1, var_478_arg_1=0, var_479=0, var_479_arg_0=0, var_479_arg_1=1, var_480=0, var_480_arg_0=0, var_480_arg_1=0, var_481=1, var_481_arg_0=1, var_481_arg_1=1, var_482=1, var_482_arg_0=0, var_482_arg_1=1, var_483=1, var_483_arg_0=1, var_483_arg_1=1, var_484=0, var_484_arg_0=1, var_484_arg_1=0, var_485=1, var_485_arg_0=1, var_485_arg_1=1, var_486=1, var_486_arg_0=1, var_486_arg_1=0, var_487=1, var_487_arg_0=1, var_487_arg_1=1, var_488=0, var_488_arg_0=1, var_488_arg_1=0, var_489=0, var_489_arg_0=0, var_489_arg_1=0, var_490=0, var_490_arg_0=0, var_490_arg_1=0, var_491=0, var_491_arg_0=0, var_491_arg_1=0, var_492=0, var_492_arg_0=0, var_492_arg_1=0, var_493=0, var_493_arg_0=0, var_493_arg_1=0, var_494=0, var_494_arg_0=0, var_494_arg_1=0, var_495=0, var_495_arg_0=0, var_495_arg_1=0, var_496=0, var_496_arg_0=0, var_496_arg_1=0, var_497=0, var_497_arg_0=0, var_497_arg_1=0, var_498=1, var_498_arg_0=1, var_498_arg_1=1, var_499=0, var_499_arg_0=0, var_499_arg_1=0, var_5=0, var_500=0, var_500_arg_0=1, var_500_arg_1=0, var_501=0, var_501_arg_0=1, var_501_arg_1=0, var_502=0, var_502_arg_0=0, var_502_arg_1=0, var_503=0, var_503_arg_0=0, var_503_arg_1=0, var_504=0, var_504_arg_0=0, var_504_arg_1=0, var_505=0, var_505_arg_0=0, var_505_arg_1=0, var_506=0, var_506_arg_0=0, var_506_arg_1=0, var_507=0, var_507_arg_0=0, var_507_arg_1=0, var_508=0, var_508_arg_0=0, var_508_arg_1=0, var_509=0, var_509_arg_0=0, var_509_arg_1=0, var_510=0, var_510_arg_0=0, var_510_arg_1=0, var_511=0, var_511_arg_0=0, var_511_arg_1=1, var_512=0, var_512_arg_0=0, var_512_arg_1=0, var_513=0, var_513_arg_0=0, var_513_arg_1=0, var_514=0, var_514_arg_0=0, var_514_arg_1=0, var_515=0, var_515_arg_0=1, var_515_arg_1=0, var_516=1, var_516_arg_0=1, var_516_arg_1=0, var_517=1, var_517_arg_0=1, var_517_arg_1=1, var_518=1, var_518_arg_0=0, var_518_arg_1=1, var_519=1, var_519_arg_0=1, var_519_arg_1=1, var_520=0, var_520_arg_0=30, var_520_arg_1=1, var_521=1, var_521_arg_0=1, var_521_arg_1=0, var_522=1, var_522_arg_0=30, var_522_arg_1=1, var_523=1, var_523_arg_0=1, var_523_arg_1=1, var_524=1, var_524_arg_0=1, var_524_arg_1=1, var_525=1, var_525_arg_0=1, var_525_arg_1=1, var_526=0, var_526_arg_0=0, var_526_arg_1=1, var_527=1, var_527_arg_0=1, var_527_arg_1=0, var_528=1, var_528_arg_0=0, var_528_arg_1=1, var_529=0, var_529_arg_0=0, var_529_arg_1=1, var_530=1, var_530_arg_0=1, var_530_arg_1=0, var_531=1, var_531_arg_0=0, var_531_arg_1=1, var_532=1, var_532_arg_0=1, var_532_arg_1=1, var_533=1, var_533_arg_0=1, var_533_arg_1=1, var_534=1, var_534_arg_0=1, var_534_arg_1=1, var_535=1, var_535_arg_0=1, var_535_arg_1=1, var_536=1, var_536_arg_0=1, var_536_arg_1=1, var_537=1, var_537_arg_0=1, var_537_arg_1=1, var_538=1, var_538_arg_0=1, var_538_arg_1=1, var_539=1, var_539_arg_0=1, var_539_arg_1=1, var_540=1, var_540_arg_0=1, var_540_arg_1=1, var_541=0, var_541_arg_0=1, var_541_arg_1=0, var_542=1, var_542_arg_0=1, var_542_arg_1=1, var_543=0, var_543_arg_0=0, var_543_arg_1=1, var_544=0, var_544_arg_0=0, var_544_arg_1=1, var_545=1, var_545_arg_0=0, var_545_arg_1=1, var_546=1, var_546_arg_0=1, var_546_arg_1=1, var_547=1, var_547_arg_0=0, var_547_arg_1=1, var_548=1, var_548_arg_0=1, var_548_arg_1=1, var_549=0, var_549_arg_0=0, var_549_arg_1=1, var_550=1, var_550_arg_0=1, var_550_arg_1=0, var_551=1, var_551_arg_0=0, var_551_arg_1=1, var_552=1, var_552_arg_0=1, var_552_arg_1=1, var_553=1, var_553_arg_0=1, var_553_arg_1=1, var_554=0, var_554_arg_0=0, var_554_arg_1=0, var_555=1, var_555_arg_0=1, var_555_arg_1=1, var_556=0, var_556_arg_0=0, var_556_arg_1=1, var_557=0, var_557_arg_0=0, var_557_arg_1=0, var_558=0, var_558_arg_0=0, var_558_arg_1=0, var_559=0, var_559_arg_0=1, var_559_arg_1=0, var_560=0, var_560_arg_0=0, var_560_arg_1=0, var_561=1, var_561_arg_0=1, var_561_arg_1=0, var_562=1, var_562_arg_0=1, var_562_arg_1=1, var_563=1, var_563_arg_0=0, var_563_arg_1=1, var_564=1, var_564_arg_0=1, var_564_arg_1=1, var_565=1, var_565_arg_0=1, var_565_arg_1=1, var_566=1, var_566_arg_0=1, var_566_arg_1=1, var_567=0, var_567_arg_0=0, var_567_arg_1=1, var_568=1, var_568_arg_0=1, var_568_arg_1=1, var_569=0, var_569_arg_0=0, var_569_arg_1=1, var_570=0, var_570_arg_0=0, var_570_arg_1=0, var_571=0, var_571_arg_0=0, var_571_arg_1=1, var_75=0, var_75_arg_0=0, var_75_arg_1=0, var_76=0, var_76_arg_0=1, var_76_arg_1=0, var_80=2, var_82=1, var_87=0, var_87_arg_0=0, var_87_arg_1=1, var_87_arg_2=0, var_88=0, var_88_arg_0=0, var_88_arg_1=1, var_88_arg_2=0, var_89=2, var_89_arg_0=1, var_89_arg_1=2, var_89_arg_2=0, var_90=2, var_90_arg_0=1, var_90_arg_1=2, var_90_arg_2=2, var_91=1, var_91_arg_0=1, var_91_arg_1=1, var_91_arg_2=2, var_92=1, var_92_arg_0=0, var_92_arg_1=2, var_92_arg_2=1, var_93=0, var_93_arg_0=1, var_93_arg_1=0, var_93_arg_2=1, var_97=0] [L182] input_78 = __VERIFIER_nondet_uchar() [L183] input_78 = input_78 & mask_SORT_1 [L184] input_79 = __VERIFIER_nondet_uchar() [L185] input_79 = input_79 & mask_SORT_1 [L186] input_81 = __VERIFIER_nondet_uchar() [L187] input_81 = input_81 & mask_SORT_1 [L188] input_83 = __VERIFIER_nondet_uchar() [L189] input_83 = input_83 & mask_SORT_1 [L190] input_84 = __VERIFIER_nondet_uchar() [L191] input_84 = input_84 & mask_SORT_1 [L192] input_85 = __VERIFIER_nondet_uchar() [L193] input_85 = input_85 & mask_SORT_1 [L194] input_86 = __VERIFIER_nondet_uchar() [L195] input_86 = input_86 & mask_SORT_1 [L196] input_98 = __VERIFIER_nondet_uchar() [L197] input_98 = input_98 & mask_SORT_1 [L198] input_99 = __VERIFIER_nondet_uchar() [L199] input_99 = input_99 & mask_SORT_1 [L200] input_100 = __VERIFIER_nondet_uchar() [L201] input_100 = input_100 & mask_SORT_1 [L202] input_101 = __VERIFIER_nondet_uchar() [L203] input_101 = input_101 & mask_SORT_1 [L204] input_102 = __VERIFIER_nondet_uchar() [L205] input_102 = input_102 & mask_SORT_1 [L206] input_103 = __VERIFIER_nondet_uchar() [L207] input_103 = input_103 & mask_SORT_1 [L208] input_104 = __VERIFIER_nondet_uchar() [L209] input_104 = input_104 & mask_SORT_1 [L210] input_105 = __VERIFIER_nondet_uchar() [L211] input_105 = input_105 & mask_SORT_1 [L212] input_106 = __VERIFIER_nondet_uchar() [L213] input_106 = input_106 & mask_SORT_1 [L214] input_149 = __VERIFIER_nondet_uchar() [L215] input_149 = input_149 & mask_SORT_1 [L216] input_151 = __VERIFIER_nondet_uchar() [L217] input_151 = input_151 & mask_SORT_1 [L218] input_154 = __VERIFIER_nondet_uchar() [L219] input_154 = input_154 & mask_SORT_1 [L220] input_156 = __VERIFIER_nondet_uchar() [L221] input_156 = input_156 & mask_SORT_1 [L222] input_192 = __VERIFIER_nondet_uchar() [L223] input_192 = input_192 & mask_SORT_1 [L224] input_222 = __VERIFIER_nondet_uchar() [L225] input_225 = __VERIFIER_nondet_uchar() [L228] SORT_1 var_75_arg_0 = state_57; [L229] SORT_1 var_75_arg_1 = state_67; [L230] SORT_1 var_75 = var_75_arg_0 & var_75_arg_1; [L231] SORT_1 var_76_arg_0 = ~state_73; [L232] var_76_arg_0 = var_76_arg_0 & mask_SORT_1 [L233] SORT_1 var_76_arg_1 = var_75; [L234] SORT_1 var_76 = var_76_arg_0 & var_76_arg_1; [L235] var_76 = var_76 & mask_SORT_1 [L236] SORT_1 bad_77_arg_0 = var_76; [L237] CALL __VERIFIER_assert(!(bad_77_arg_0)) [L20] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L20] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 1 procedures, 7 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 417.4s, OverallIterations: 2, TraceHistogramMax: 2, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 2.5s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 1 mSolverCounterUnknown, 3 SdHoareTripleChecker+Valid, 2.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3 mSDsluCounter, 6 SdHoareTripleChecker+Invalid, 2.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 5 mSDsCounter, 1 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 7 IncrementalHoareTripleChecker+Invalid, 9 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1 mSolverCounterUnsat, 2 mSDtfsCounter, 7 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=8occurred in iteration=1, InterpolantAutomatonStates: 5, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 1 MinimizatonAttempts, 1 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 227.4s SatisfiabilityAnalysisTime, 1.6s InterpolantComputationTime, 11 NumberOfCodeBlocks, 11 NumberOfCodeBlocksAsserted, 2 NumberOfCheckSat, 3 ConstructedInterpolants, 0 QuantifiedInterpolants, 15 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 1 InterpolantComputations, 1 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces [2022-11-03 02:49:30,530 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis ### Bit-precise run ### Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/TaipanReach.xml -i ../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash cf45e19d1839caf080de34cfa9fd4f236bd55e600d76c016a3ed5d411a793a9e --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-5e519f3 [2022-11-03 02:49:33,182 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-03 02:49:33,184 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-03 02:49:33,215 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-03 02:49:33,216 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-03 02:49:33,217 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-03 02:49:33,218 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-03 02:49:33,220 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-03 02:49:33,222 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-03 02:49:33,223 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-03 02:49:33,224 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-03 02:49:33,226 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-03 02:49:33,226 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-03 02:49:33,232 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-03 02:49:33,233 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-03 02:49:33,234 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-03 02:49:33,236 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-03 02:49:33,239 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-03 02:49:33,243 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-03 02:49:33,245 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-03 02:49:33,253 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-03 02:49:33,254 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-03 02:49:33,256 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-03 02:49:33,257 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-03 02:49:33,260 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-03 02:49:33,260 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-03 02:49:33,261 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-03 02:49:33,262 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-03 02:49:33,262 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-03 02:49:33,263 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-03 02:49:33,263 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-03 02:49:33,264 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-03 02:49:33,265 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-03 02:49:33,266 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-03 02:49:33,267 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-03 02:49:33,267 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-03 02:49:33,268 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-03 02:49:33,269 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-03 02:49:33,269 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-03 02:49:33,270 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-03 02:49:33,271 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-03 02:49:33,272 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/config/svcomp-Reach-64bit-Taipan_Bitvector.epf [2022-11-03 02:49:33,300 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-03 02:49:33,301 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-03 02:49:33,301 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-03 02:49:33,301 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-03 02:49:33,302 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-03 02:49:33,302 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-03 02:49:33,303 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-03 02:49:33,303 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-03 02:49:33,303 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-03 02:49:33,303 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-03 02:49:33,304 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-03 02:49:33,304 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-03 02:49:33,305 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-03 02:49:33,305 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-03 02:49:33,305 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-03 02:49:33,305 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-03 02:49:33,306 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-03 02:49:33,306 INFO L138 SettingsManager]: * Adapt memory model on pointer casts if necessary=true [2022-11-03 02:49:33,306 INFO L138 SettingsManager]: * Use bitvectors instead of ints=true [2022-11-03 02:49:33,306 INFO L138 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2022-11-03 02:49:33,306 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-03 02:49:33,307 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-03 02:49:33,307 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-03 02:49:33,307 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-03 02:49:33,307 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-11-03 02:49:33,308 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-03 02:49:33,308 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:49:33,308 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-03 02:49:33,308 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-03 02:49:33,309 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-03 02:49:33,309 INFO L138 SettingsManager]: * Trace refinement strategy=WALRUS [2022-11-03 02:49:33,309 INFO L138 SettingsManager]: * Command for external solver=cvc4 --incremental --print-success --lang smt [2022-11-03 02:49:33,309 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-03 02:49:33,309 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-03 02:49:33,310 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-11-03 02:49:33,310 INFO L138 SettingsManager]: * Logic for external solver=AUFBV WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> cf45e19d1839caf080de34cfa9fd4f236bd55e600d76c016a3ed5d411a793a9e [2022-11-03 02:49:33,736 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-03 02:49:33,772 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-03 02:49:33,775 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-03 02:49:33,777 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-03 02:49:33,780 INFO L275 PluginConnector]: CDTParser initialized [2022-11-03 02:49:33,782 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/../../sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:49:33,865 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/f4d68ad1e/37d011688c034bca8edefcda7fad2bbe/FLAG942e26737 [2022-11-03 02:49:34,677 INFO L306 CDTParser]: Found 1 translation units. [2022-11-03 02:49:34,678 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:49:34,700 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/f4d68ad1e/37d011688c034bca8edefcda7fad2bbe/FLAG942e26737 [2022-11-03 02:49:34,831 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/data/f4d68ad1e/37d011688c034bca8edefcda7fad2bbe [2022-11-03 02:49:34,834 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-03 02:49:34,835 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-03 02:49:34,837 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-03 02:49:34,838 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-03 02:49:34,842 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-03 02:49:34,843 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:49:34" (1/1) ... [2022-11-03 02:49:34,844 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@328313f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:34, skipping insertion in model container [2022-11-03 02:49:34,844 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 03.11 02:49:34" (1/1) ... [2022-11-03 02:49:34,853 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-03 02:49:34,924 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-03 02:49:35,115 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c[1014,1027] [2022-11-03 02:49:35,567 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:49:35,572 INFO L203 MainTranslator]: Completed pre-run [2022-11-03 02:49:35,584 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/sv-benchmarks/c/hardware-verification-bv/btor2c-lazyMod.train-gate.1.prop1-func-interl.c[1014,1027] [2022-11-03 02:49:35,773 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-03 02:49:35,787 INFO L208 MainTranslator]: Completed translation [2022-11-03 02:49:35,788 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35 WrapperNode [2022-11-03 02:49:35,788 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-03 02:49:35,789 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-03 02:49:35,789 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-03 02:49:35,790 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-03 02:49:35,797 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:35,850 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:35,986 INFO L138 Inliner]: procedures = 11, calls = 3, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 2014 [2022-11-03 02:49:35,986 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-03 02:49:35,987 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-03 02:49:35,987 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-03 02:49:35,987 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-03 02:49:35,997 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:35,998 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,009 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,009 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,049 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,076 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,083 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,091 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,107 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-03 02:49:36,108 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-03 02:49:36,108 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-03 02:49:36,108 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-03 02:49:36,109 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (1/1) ... [2022-11-03 02:49:36,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-03 02:49:36,130 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:49:36,143 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-03 02:49:36,211 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-03 02:49:36,239 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-03 02:49:36,240 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-03 02:49:36,775 INFO L235 CfgBuilder]: Building ICFG [2022-11-03 02:49:36,792 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-03 02:49:39,671 INFO L276 CfgBuilder]: Performing block encoding [2022-11-03 02:49:39,682 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-03 02:49:39,683 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-03 02:49:39,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:49:39 BoogieIcfgContainer [2022-11-03 02:49:39,685 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-03 02:49:39,687 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-03 02:49:39,687 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-03 02:49:39,690 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-03 02:49:39,691 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 03.11 02:49:34" (1/3) ... [2022-11-03 02:49:39,692 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@737bb7e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:49:39, skipping insertion in model container [2022-11-03 02:49:39,692 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 03.11 02:49:35" (2/3) ... [2022-11-03 02:49:39,692 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@737bb7e3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 03.11 02:49:39, skipping insertion in model container [2022-11-03 02:49:39,692 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 03.11 02:49:39" (3/3) ... [2022-11-03 02:49:39,694 INFO L112 eAbstractionObserver]: Analyzing ICFG btor2c-lazyMod.train-gate.1.prop1-func-interl.c [2022-11-03 02:49:39,712 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-03 02:49:39,713 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-03 02:49:39,765 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-03 02:49:39,772 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@c12f9fc, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-03 02:49:39,772 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-03 02:49:39,777 INFO L276 IsEmpty]: Start isEmpty. Operand has 123 states, 121 states have (on average 1.4958677685950412) internal successors, (181), 122 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:39,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 6 [2022-11-03 02:49:39,783 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:39,784 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1] [2022-11-03 02:49:39,785 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:39,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:39,790 INFO L85 PathProgramCache]: Analyzing trace with hash 28698761, now seen corresponding path program 1 times [2022-11-03 02:49:39,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:39,804 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [783318660] [2022-11-03 02:49:39,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:39,805 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:39,805 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:39,811 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:39,849 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Waiting until timeout for monitored process [2022-11-03 02:49:40,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:40,295 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:49:40,304 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:40,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:40,431 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:40,432 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:40,432 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [783318660] [2022-11-03 02:49:40,433 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [783318660] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:40,433 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:40,433 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:49:40,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640257893] [2022-11-03 02:49:40,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:40,443 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:49:40,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:40,478 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:49:40,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:49:40,484 INFO L87 Difference]: Start difference. First operand has 123 states, 121 states have (on average 1.4958677685950412) internal successors, (181), 122 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:40,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:40,789 INFO L93 Difference]: Finished difference Result 356 states and 534 transitions. [2022-11-03 02:49:40,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:49:40,792 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 5 [2022-11-03 02:49:40,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:40,802 INFO L225 Difference]: With dead ends: 356 [2022-11-03 02:49:40,803 INFO L226 Difference]: Without dead ends: 235 [2022-11-03 02:49:40,806 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:49:40,810 INFO L413 NwaCegarLoop]: 170 mSDtfsCounter, 339 mSDsluCounter, 341 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 339 SdHoareTripleChecker+Valid, 511 SdHoareTripleChecker+Invalid, 15 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:40,811 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [339 Valid, 511 Invalid, 15 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:49:40,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2022-11-03 02:49:40,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 121. [2022-11-03 02:49:40,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121 states, 120 states have (on average 1.475) internal successors, (177), 120 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:40,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121 states to 121 states and 177 transitions. [2022-11-03 02:49:40,854 INFO L78 Accepts]: Start accepts. Automaton has 121 states and 177 transitions. Word has length 5 [2022-11-03 02:49:40,855 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:40,855 INFO L495 AbstractCegarLoop]: Abstraction has 121 states and 177 transitions. [2022-11-03 02:49:40,855 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.25) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:40,856 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 177 transitions. [2022-11-03 02:49:40,859 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:40,859 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:40,860 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:40,880 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (2)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:41,079 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:41,080 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:41,080 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:41,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1504819055, now seen corresponding path program 1 times [2022-11-03 02:49:41,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:41,087 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1571228665] [2022-11-03 02:49:41,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:41,088 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:41,088 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:41,089 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:41,092 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Waiting until timeout for monitored process [2022-11-03 02:49:42,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:42,087 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:49:42,099 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:42,317 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:42,318 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:42,318 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:42,318 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1571228665] [2022-11-03 02:49:42,319 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1571228665] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:42,319 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:42,319 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:49:42,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405945607] [2022-11-03 02:49:42,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:42,325 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:49:42,327 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:42,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:49:42,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:49:42,329 INFO L87 Difference]: Start difference. First operand 121 states and 177 transitions. Second operand has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:42,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:42,749 INFO L93 Difference]: Finished difference Result 468 states and 691 transitions. [2022-11-03 02:49:42,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:49:42,750 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:42,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:42,752 INFO L225 Difference]: With dead ends: 468 [2022-11-03 02:49:42,752 INFO L226 Difference]: Without dead ends: 351 [2022-11-03 02:49:42,753 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:49:42,754 INFO L413 NwaCegarLoop]: 209 mSDtfsCounter, 467 mSDsluCounter, 1187 mSDsCounter, 0 mSdLazyCounter, 28 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 467 SdHoareTripleChecker+Valid, 1396 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 28 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 15 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:42,755 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [467 Valid, 1396 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 28 Invalid, 0 Unknown, 15 Unchecked, 0.3s Time] [2022-11-03 02:49:42,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 351 states. [2022-11-03 02:49:42,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 351 to 149. [2022-11-03 02:49:42,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 149 states, 148 states have (on average 1.472972972972973) internal successors, (218), 148 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:42,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 218 transitions. [2022-11-03 02:49:42,769 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 218 transitions. Word has length 120 [2022-11-03 02:49:42,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:42,770 INFO L495 AbstractCegarLoop]: Abstraction has 149 states and 218 transitions. [2022-11-03 02:49:42,770 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:42,770 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 218 transitions. [2022-11-03 02:49:42,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:42,773 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:42,774 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:42,801 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (3)] Ended with exit code 0 [2022-11-03 02:49:42,998 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:42,999 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:43,000 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:43,000 INFO L85 PathProgramCache]: Analyzing trace with hash 2019414675, now seen corresponding path program 1 times [2022-11-03 02:49:43,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:43,002 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [974106656] [2022-11-03 02:49:43,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:43,003 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:43,003 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:43,004 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:43,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Waiting until timeout for monitored process [2022-11-03 02:49:43,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:43,910 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:49:43,930 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:44,168 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:44,169 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:44,169 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:44,169 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [974106656] [2022-11-03 02:49:44,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [974106656] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:44,170 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:44,170 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:49:44,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488509735] [2022-11-03 02:49:44,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:44,171 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:49:44,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:44,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:49:44,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:49:44,172 INFO L87 Difference]: Start difference. First operand 149 states and 218 transitions. Second operand has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:44,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:44,468 INFO L93 Difference]: Finished difference Result 502 states and 740 transitions. [2022-11-03 02:49:44,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:49:44,469 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:44,469 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:44,471 INFO L225 Difference]: With dead ends: 502 [2022-11-03 02:49:44,471 INFO L226 Difference]: Without dead ends: 385 [2022-11-03 02:49:44,472 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:49:44,474 INFO L413 NwaCegarLoop]: 237 mSDtfsCounter, 562 mSDsluCounter, 870 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 562 SdHoareTripleChecker+Valid, 1107 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 14 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:44,474 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [562 Valid, 1107 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 18 Invalid, 0 Unknown, 14 Unchecked, 0.3s Time] [2022-11-03 02:49:44,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385 states. [2022-11-03 02:49:44,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385 to 201. [2022-11-03 02:49:44,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 200 states have (on average 1.47) internal successors, (294), 200 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:44,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 294 transitions. [2022-11-03 02:49:44,487 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 294 transitions. Word has length 120 [2022-11-03 02:49:44,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:44,487 INFO L495 AbstractCegarLoop]: Abstraction has 201 states and 294 transitions. [2022-11-03 02:49:44,487 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:44,488 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 294 transitions. [2022-11-03 02:49:44,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:44,491 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:44,491 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:44,522 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (4)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:44,714 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:44,714 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:44,714 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:44,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1052064021, now seen corresponding path program 1 times [2022-11-03 02:49:44,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:44,716 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [325396557] [2022-11-03 02:49:44,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:44,717 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:44,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:44,720 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:44,723 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Waiting until timeout for monitored process [2022-11-03 02:49:45,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:45,560 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:49:45,568 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:46,008 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:46,009 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:46,009 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:46,009 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [325396557] [2022-11-03 02:49:46,010 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [325396557] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:46,010 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:46,010 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:49:46,010 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [354457460] [2022-11-03 02:49:46,011 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:46,011 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:49:46,011 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:46,012 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:49:46,012 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:49:46,013 INFO L87 Difference]: Start difference. First operand 201 states and 294 transitions. Second operand has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:46,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:46,276 INFO L93 Difference]: Finished difference Result 428 states and 629 transitions. [2022-11-03 02:49:46,277 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:49:46,277 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:46,278 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:46,279 INFO L225 Difference]: With dead ends: 428 [2022-11-03 02:49:46,279 INFO L226 Difference]: Without dead ends: 311 [2022-11-03 02:49:46,280 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:49:46,281 INFO L413 NwaCegarLoop]: 168 mSDtfsCounter, 93 mSDsluCounter, 662 mSDsCounter, 0 mSdLazyCounter, 6 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 93 SdHoareTripleChecker+Valid, 830 SdHoareTripleChecker+Invalid, 22 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 6 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:46,282 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [93 Valid, 830 Invalid, 22 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 6 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-11-03 02:49:46,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311 states. [2022-11-03 02:49:46,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 311. [2022-11-03 02:49:46,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 310 states have (on average 1.467741935483871) internal successors, (455), 310 states have internal predecessors, (455), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:46,297 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 455 transitions. [2022-11-03 02:49:46,297 INFO L78 Accepts]: Start accepts. Automaton has 311 states and 455 transitions. Word has length 120 [2022-11-03 02:49:46,297 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:46,298 INFO L495 AbstractCegarLoop]: Abstraction has 311 states and 455 transitions. [2022-11-03 02:49:46,298 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:46,298 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 455 transitions. [2022-11-03 02:49:46,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:46,302 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:46,302 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:46,334 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (5)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:46,527 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:46,527 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:46,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:46,528 INFO L85 PathProgramCache]: Analyzing trace with hash -2026749549, now seen corresponding path program 1 times [2022-11-03 02:49:46,529 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:46,529 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1397269320] [2022-11-03 02:49:46,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:46,530 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:46,530 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:46,531 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:46,532 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Waiting until timeout for monitored process [2022-11-03 02:49:47,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:47,391 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:49:47,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:47,607 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:47,607 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:47,607 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:47,607 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1397269320] [2022-11-03 02:49:47,607 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1397269320] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:47,608 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:47,608 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:49:47,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001425206] [2022-11-03 02:49:47,608 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:47,609 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:49:47,609 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:47,609 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:49:47,609 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:49:47,610 INFO L87 Difference]: Start difference. First operand 311 states and 455 transitions. Second operand has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:47,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:47,973 INFO L93 Difference]: Finished difference Result 688 states and 1011 transitions. [2022-11-03 02:49:47,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:49:47,974 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:47,974 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:47,976 INFO L225 Difference]: With dead ends: 688 [2022-11-03 02:49:47,976 INFO L226 Difference]: Without dead ends: 571 [2022-11-03 02:49:47,977 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:49:47,978 INFO L413 NwaCegarLoop]: 245 mSDtfsCounter, 430 mSDsluCounter, 1300 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 430 SdHoareTripleChecker+Valid, 1545 SdHoareTripleChecker+Invalid, 60 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 30 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:47,979 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [430 Valid, 1545 Invalid, 60 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 29 Invalid, 0 Unknown, 30 Unchecked, 0.3s Time] [2022-11-03 02:49:47,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2022-11-03 02:49:47,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 393. [2022-11-03 02:49:47,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 393 states, 392 states have (on average 1.4642857142857142) internal successors, (574), 392 states have internal predecessors, (574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:47,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 393 states to 393 states and 574 transitions. [2022-11-03 02:49:47,993 INFO L78 Accepts]: Start accepts. Automaton has 393 states and 574 transitions. Word has length 120 [2022-11-03 02:49:47,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:47,993 INFO L495 AbstractCegarLoop]: Abstraction has 393 states and 574 transitions. [2022-11-03 02:49:47,994 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:47,994 INFO L276 IsEmpty]: Start isEmpty. Operand 393 states and 574 transitions. [2022-11-03 02:49:47,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:47,998 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:47,998 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:48,020 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (6)] Ended with exit code 0 [2022-11-03 02:49:48,215 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:48,215 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:48,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:48,216 INFO L85 PathProgramCache]: Analyzing trace with hash 582037909, now seen corresponding path program 1 times [2022-11-03 02:49:48,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:48,217 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1565643904] [2022-11-03 02:49:48,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:48,217 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:48,217 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:48,218 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:48,246 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Waiting until timeout for monitored process [2022-11-03 02:49:49,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:49,073 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:49:49,083 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:50,310 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:50,311 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:50,311 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:50,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1565643904] [2022-11-03 02:49:50,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1565643904] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:50,312 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:50,312 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:49:50,312 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363310378] [2022-11-03 02:49:50,313 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:50,313 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:49:50,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:50,314 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:49:50,314 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:49:50,315 INFO L87 Difference]: Start difference. First operand 393 states and 574 transitions. Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:50,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:50,662 INFO L93 Difference]: Finished difference Result 798 states and 1173 transitions. [2022-11-03 02:49:50,664 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:49:50,664 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:50,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:50,667 INFO L225 Difference]: With dead ends: 798 [2022-11-03 02:49:50,668 INFO L226 Difference]: Without dead ends: 681 [2022-11-03 02:49:50,669 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:49:50,670 INFO L413 NwaCegarLoop]: 280 mSDtfsCounter, 602 mSDsluCounter, 724 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 602 SdHoareTripleChecker+Valid, 1004 SdHoareTripleChecker+Invalid, 32 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:50,670 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [602 Valid, 1004 Invalid, 32 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-11-03 02:49:50,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 681 states. [2022-11-03 02:49:50,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 681 to 451. [2022-11-03 02:49:50,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 451 states, 450 states have (on average 1.4666666666666666) internal successors, (660), 450 states have internal predecessors, (660), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:50,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 660 transitions. [2022-11-03 02:49:50,686 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 660 transitions. Word has length 120 [2022-11-03 02:49:50,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:50,687 INFO L495 AbstractCegarLoop]: Abstraction has 451 states and 660 transitions. [2022-11-03 02:49:50,687 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:50,688 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 660 transitions. [2022-11-03 02:49:50,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:50,690 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:50,691 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:50,722 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (7)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:50,916 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:50,916 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:50,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:50,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1005684631, now seen corresponding path program 1 times [2022-11-03 02:49:50,919 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:50,919 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1450446589] [2022-11-03 02:49:50,919 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:50,919 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:50,920 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:50,921 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:50,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Waiting until timeout for monitored process [2022-11-03 02:49:51,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:51,820 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:49:51,830 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:52,664 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:52,666 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:52,666 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:52,666 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1450446589] [2022-11-03 02:49:52,666 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1450446589] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:52,667 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:52,667 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:49:52,667 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1360581055] [2022-11-03 02:49:52,667 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:52,668 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:49:52,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:52,668 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:49:52,669 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:49:52,669 INFO L87 Difference]: Start difference. First operand 451 states and 660 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:52,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:52,893 INFO L93 Difference]: Finished difference Result 721 states and 1059 transitions. [2022-11-03 02:49:52,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:49:52,894 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:52,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:52,896 INFO L225 Difference]: With dead ends: 721 [2022-11-03 02:49:52,897 INFO L226 Difference]: Without dead ends: 604 [2022-11-03 02:49:52,897 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:49:52,898 INFO L413 NwaCegarLoop]: 293 mSDtfsCounter, 292 mSDsluCounter, 368 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 292 SdHoareTripleChecker+Valid, 661 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:52,898 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [292 Valid, 661 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:49:52,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 604 states. [2022-11-03 02:49:52,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 604 to 461. [2022-11-03 02:49:52,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 461 states, 460 states have (on average 1.4652173913043478) internal successors, (674), 460 states have internal predecessors, (674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:52,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 674 transitions. [2022-11-03 02:49:52,914 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 674 transitions. Word has length 120 [2022-11-03 02:49:52,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:52,914 INFO L495 AbstractCegarLoop]: Abstraction has 461 states and 674 transitions. [2022-11-03 02:49:52,915 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:52,915 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 674 transitions. [2022-11-03 02:49:52,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:52,917 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:52,917 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:52,940 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (8)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:53,130 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:53,131 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:53,131 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:53,131 INFO L85 PathProgramCache]: Analyzing trace with hash 1707284505, now seen corresponding path program 1 times [2022-11-03 02:49:53,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:53,133 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [255854461] [2022-11-03 02:49:53,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:53,133 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:53,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:53,134 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:53,135 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Waiting until timeout for monitored process [2022-11-03 02:49:53,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:53,935 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:49:53,944 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:54,838 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:54,838 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:54,838 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:54,839 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [255854461] [2022-11-03 02:49:54,839 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [255854461] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:54,839 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:54,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:49:54,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173383428] [2022-11-03 02:49:54,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:54,840 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:49:54,840 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:54,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:49:54,840 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:49:54,841 INFO L87 Difference]: Start difference. First operand 461 states and 674 transitions. Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:55,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:55,122 INFO L93 Difference]: Finished difference Result 810 states and 1189 transitions. [2022-11-03 02:49:55,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:49:55,123 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:55,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:55,126 INFO L225 Difference]: With dead ends: 810 [2022-11-03 02:49:55,126 INFO L226 Difference]: Without dead ends: 693 [2022-11-03 02:49:55,127 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:49:55,128 INFO L413 NwaCegarLoop]: 294 mSDtfsCounter, 587 mSDsluCounter, 698 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 587 SdHoareTripleChecker+Valid, 992 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:55,128 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [587 Valid, 992 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:49:55,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states. [2022-11-03 02:49:55,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 463. [2022-11-03 02:49:55,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 463 states, 462 states have (on average 1.4632034632034632) internal successors, (676), 462 states have internal predecessors, (676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:55,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 676 transitions. [2022-11-03 02:49:55,141 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 676 transitions. Word has length 120 [2022-11-03 02:49:55,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:55,142 INFO L495 AbstractCegarLoop]: Abstraction has 463 states and 676 transitions. [2022-11-03 02:49:55,142 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:55,142 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 676 transitions. [2022-11-03 02:49:55,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:55,144 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:55,144 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:55,174 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (9)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:55,368 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:55,368 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:55,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:55,369 INFO L85 PathProgramCache]: Analyzing trace with hash -1201479397, now seen corresponding path program 1 times [2022-11-03 02:49:55,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:55,371 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1464165822] [2022-11-03 02:49:55,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:55,371 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:55,371 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:55,373 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:55,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Waiting until timeout for monitored process [2022-11-03 02:49:56,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:56,192 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 02:49:56,202 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:57,130 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:57,130 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:57,131 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:57,131 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1464165822] [2022-11-03 02:49:57,131 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1464165822] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:57,131 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:57,132 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:49:57,132 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436361980] [2022-11-03 02:49:57,132 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:57,133 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:49:57,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:57,133 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:49:57,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:49:57,134 INFO L87 Difference]: Start difference. First operand 463 states and 676 transitions. Second operand has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:57,777 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:57,777 INFO L93 Difference]: Finished difference Result 588 states and 859 transitions. [2022-11-03 02:49:57,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:49:57,778 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:57,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:57,780 INFO L225 Difference]: With dead ends: 588 [2022-11-03 02:49:57,780 INFO L226 Difference]: Without dead ends: 471 [2022-11-03 02:49:57,781 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:49:57,782 INFO L413 NwaCegarLoop]: 151 mSDtfsCounter, 91 mSDsluCounter, 932 mSDsCounter, 0 mSdLazyCounter, 116 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 91 SdHoareTripleChecker+Valid, 1083 SdHoareTripleChecker+Invalid, 166 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 116 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:57,782 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [91 Valid, 1083 Invalid, 166 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 116 Invalid, 0 Unknown, 50 Unchecked, 0.5s Time] [2022-11-03 02:49:57,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states. [2022-11-03 02:49:57,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 471. [2022-11-03 02:49:57,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 471 states, 470 states have (on average 1.4574468085106382) internal successors, (685), 470 states have internal predecessors, (685), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:57,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 685 transitions. [2022-11-03 02:49:57,794 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 685 transitions. Word has length 120 [2022-11-03 02:49:57,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:57,794 INFO L495 AbstractCegarLoop]: Abstraction has 471 states and 685 transitions. [2022-11-03 02:49:57,795 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:57,795 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 685 transitions. [2022-11-03 02:49:57,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:57,796 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:57,797 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:57,826 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (10)] Forceful destruction successful, exit code 0 [2022-11-03 02:49:58,020 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:49:58,020 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:49:58,020 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:49:58,020 INFO L85 PathProgramCache]: Analyzing trace with hash 721748637, now seen corresponding path program 1 times [2022-11-03 02:49:58,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:49:58,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1725573694] [2022-11-03 02:49:58,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:49:58,022 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:49:58,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:49:58,024 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:49:58,025 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Waiting until timeout for monitored process [2022-11-03 02:49:58,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:49:58,874 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:49:58,902 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:49:59,679 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:49:59,679 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:49:59,680 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:49:59,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1725573694] [2022-11-03 02:49:59,680 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1725573694] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:49:59,680 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:49:59,680 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:49:59,680 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795734257] [2022-11-03 02:49:59,680 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:49:59,681 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:49:59,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:49:59,681 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:49:59,681 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:49:59,682 INFO L87 Difference]: Start difference. First operand 471 states and 685 transitions. Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:59,941 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:49:59,941 INFO L93 Difference]: Finished difference Result 818 states and 1197 transitions. [2022-11-03 02:49:59,942 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:49:59,943 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:49:59,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:49:59,945 INFO L225 Difference]: With dead ends: 818 [2022-11-03 02:49:59,945 INFO L226 Difference]: Without dead ends: 701 [2022-11-03 02:49:59,946 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:49:59,946 INFO L413 NwaCegarLoop]: 299 mSDtfsCounter, 575 mSDsluCounter, 686 mSDsCounter, 0 mSdLazyCounter, 39 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 575 SdHoareTripleChecker+Valid, 985 SdHoareTripleChecker+Invalid, 42 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 39 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:49:59,947 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [575 Valid, 985 Invalid, 42 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 39 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:49:59,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states. [2022-11-03 02:49:59,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 475. [2022-11-03 02:49:59,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 475 states, 474 states have (on average 1.4556962025316456) internal successors, (690), 474 states have internal predecessors, (690), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:59,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 475 states to 475 states and 690 transitions. [2022-11-03 02:49:59,959 INFO L78 Accepts]: Start accepts. Automaton has 475 states and 690 transitions. Word has length 120 [2022-11-03 02:49:59,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:49:59,959 INFO L495 AbstractCegarLoop]: Abstraction has 475 states and 690 transitions. [2022-11-03 02:49:59,960 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:49:59,960 INFO L276 IsEmpty]: Start isEmpty. Operand 475 states and 690 transitions. [2022-11-03 02:49:59,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:49:59,961 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:49:59,962 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:49:59,992 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (11)] Forceful destruction successful, exit code 0 [2022-11-03 02:50:00,174 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:50:00,175 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:00,175 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:00,175 INFO L85 PathProgramCache]: Analyzing trace with hash 862297247, now seen corresponding path program 1 times [2022-11-03 02:50:00,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:50:00,176 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1276655118] [2022-11-03 02:50:00,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:00,177 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:50:00,177 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:50:00,177 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:50:00,179 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Waiting until timeout for monitored process [2022-11-03 02:50:00,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:01,014 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:50:01,023 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:01,801 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:01,801 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:50:01,802 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:50:01,802 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1276655118] [2022-11-03 02:50:01,802 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1276655118] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:50:01,802 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:50:01,802 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-03 02:50:01,802 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257391252] [2022-11-03 02:50:01,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:50:01,803 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-03 02:50:01,803 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:50:01,803 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-03 02:50:01,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-03 02:50:01,804 INFO L87 Difference]: Start difference. First operand 475 states and 690 transitions. Second operand has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:02,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:50:02,028 INFO L93 Difference]: Finished difference Result 729 states and 1065 transitions. [2022-11-03 02:50:02,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-03 02:50:02,031 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:50:02,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:50:02,035 INFO L225 Difference]: With dead ends: 729 [2022-11-03 02:50:02,035 INFO L226 Difference]: Without dead ends: 612 [2022-11-03 02:50:02,036 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 117 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:50:02,037 INFO L413 NwaCegarLoop]: 302 mSDtfsCounter, 269 mSDsluCounter, 356 mSDsCounter, 0 mSdLazyCounter, 29 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 269 SdHoareTripleChecker+Valid, 658 SdHoareTripleChecker+Invalid, 31 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 29 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:50:02,037 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [269 Valid, 658 Invalid, 31 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 29 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:50:02,038 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 612 states. [2022-11-03 02:50:02,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 612 to 477. [2022-11-03 02:50:02,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 477 states, 476 states have (on average 1.453781512605042) internal successors, (692), 476 states have internal predecessors, (692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:02,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 692 transitions. [2022-11-03 02:50:02,050 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 692 transitions. Word has length 120 [2022-11-03 02:50:02,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:50:02,051 INFO L495 AbstractCegarLoop]: Abstraction has 477 states and 692 transitions. [2022-11-03 02:50:02,051 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 30.0) internal successors, (120), 4 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:02,051 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 692 transitions. [2022-11-03 02:50:02,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:50:02,053 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:02,053 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:50:02,087 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (12)] Forceful destruction successful, exit code 0 [2022-11-03 02:50:02,271 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:50:02,271 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:02,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:02,271 INFO L85 PathProgramCache]: Analyzing trace with hash -943141087, now seen corresponding path program 1 times [2022-11-03 02:50:02,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:50:02,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [406142602] [2022-11-03 02:50:02,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:02,273 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:50:02,273 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:50:02,274 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:50:02,281 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Waiting until timeout for monitored process [2022-11-03 02:50:02,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:03,006 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 12 conjunts are in the unsatisfiable core [2022-11-03 02:50:03,014 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:03,849 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:03,849 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:50:03,849 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:50:03,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [406142602] [2022-11-03 02:50:03,849 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [406142602] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:50:03,849 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:50:03,850 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-03 02:50:03,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1578780842] [2022-11-03 02:50:03,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:50:03,852 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-03 02:50:03,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:50:03,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-03 02:50:03,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-03 02:50:03,853 INFO L87 Difference]: Start difference. First operand 477 states and 692 transitions. Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:04,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:50:04,129 INFO L93 Difference]: Finished difference Result 826 states and 1207 transitions. [2022-11-03 02:50:04,130 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-03 02:50:04,130 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:50:04,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:50:04,133 INFO L225 Difference]: With dead ends: 826 [2022-11-03 02:50:04,133 INFO L226 Difference]: Without dead ends: 709 [2022-11-03 02:50:04,134 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 116 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:50:04,135 INFO L413 NwaCegarLoop]: 303 mSDtfsCounter, 576 mSDsluCounter, 685 mSDsCounter, 0 mSdLazyCounter, 40 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 576 SdHoareTripleChecker+Valid, 988 SdHoareTripleChecker+Invalid, 43 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 40 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:50:04,135 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [576 Valid, 988 Invalid, 43 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 40 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-03 02:50:04,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 709 states. [2022-11-03 02:50:04,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 709 to 479. [2022-11-03 02:50:04,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 479 states, 478 states have (on average 1.4518828451882846) internal successors, (694), 478 states have internal predecessors, (694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:04,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 479 states to 479 states and 694 transitions. [2022-11-03 02:50:04,148 INFO L78 Accepts]: Start accepts. Automaton has 479 states and 694 transitions. Word has length 120 [2022-11-03 02:50:04,149 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:50:04,149 INFO L495 AbstractCegarLoop]: Abstraction has 479 states and 694 transitions. [2022-11-03 02:50:04,149 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:04,149 INFO L276 IsEmpty]: Start isEmpty. Operand 479 states and 694 transitions. [2022-11-03 02:50:04,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:50:04,151 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:04,152 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:50:04,178 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (13)] Forceful destruction successful, exit code 0 [2022-11-03 02:50:04,374 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:50:04,375 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:04,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:04,375 INFO L85 PathProgramCache]: Analyzing trace with hash -520439261, now seen corresponding path program 1 times [2022-11-03 02:50:04,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:50:04,376 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [770883419] [2022-11-03 02:50:04,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:04,377 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:50:04,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:50:04,377 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:50:04,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Waiting until timeout for monitored process [2022-11-03 02:50:05,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:05,104 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-03 02:50:05,111 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:05,897 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:05,898 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:50:05,898 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:50:05,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [770883419] [2022-11-03 02:50:05,898 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [770883419] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:50:05,898 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:50:05,898 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:50:05,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616518344] [2022-11-03 02:50:05,899 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:50:05,899 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:50:05,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:50:05,900 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:50:05,900 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:50:05,900 INFO L87 Difference]: Start difference. First operand 479 states and 694 transitions. Second operand has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:06,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:50:06,504 INFO L93 Difference]: Finished difference Result 604 states and 876 transitions. [2022-11-03 02:50:06,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-11-03 02:50:06,505 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:50:06,505 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:50:06,506 INFO L225 Difference]: With dead ends: 604 [2022-11-03 02:50:06,507 INFO L226 Difference]: Without dead ends: 487 [2022-11-03 02:50:06,507 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2022-11-03 02:50:06,508 INFO L413 NwaCegarLoop]: 149 mSDtfsCounter, 142 mSDsluCounter, 894 mSDsCounter, 0 mSdLazyCounter, 119 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 1043 SdHoareTripleChecker+Invalid, 172 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 119 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 53 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-03 02:50:06,508 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 1043 Invalid, 172 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 119 Invalid, 0 Unknown, 53 Unchecked, 0.5s Time] [2022-11-03 02:50:06,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states. [2022-11-03 02:50:06,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 487. [2022-11-03 02:50:06,518 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 487 states, 486 states have (on average 1.4444444444444444) internal successors, (702), 486 states have internal predecessors, (702), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:06,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 487 states to 487 states and 702 transitions. [2022-11-03 02:50:06,520 INFO L78 Accepts]: Start accepts. Automaton has 487 states and 702 transitions. Word has length 120 [2022-11-03 02:50:06,520 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:50:06,520 INFO L495 AbstractCegarLoop]: Abstraction has 487 states and 702 transitions. [2022-11-03 02:50:06,521 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:06,521 INFO L276 IsEmpty]: Start isEmpty. Operand 487 states and 702 transitions. [2022-11-03 02:50:06,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:50:06,523 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:06,523 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:50:06,552 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (14)] Forceful destruction successful, exit code 0 [2022-11-03 02:50:06,744 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:50:06,744 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:06,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:06,744 INFO L85 PathProgramCache]: Analyzing trace with hash 2085584293, now seen corresponding path program 1 times [2022-11-03 02:50:06,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:50:06,745 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1858769715] [2022-11-03 02:50:06,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:06,746 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:50:06,746 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:50:06,746 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:50:06,748 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Waiting until timeout for monitored process [2022-11-03 02:50:07,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:07,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 16 conjunts are in the unsatisfiable core [2022-11-03 02:50:07,446 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:08,474 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:08,475 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:50:08,475 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:50:08,475 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1858769715] [2022-11-03 02:50:08,475 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1858769715] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:50:08,475 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:50:08,476 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-11-03 02:50:08,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097449383] [2022-11-03 02:50:08,476 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:50:08,476 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-03 02:50:08,477 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:50:08,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-03 02:50:08,477 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:50:08,477 INFO L87 Difference]: Start difference. First operand 487 states and 702 transitions. Second operand has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:08,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:50:08,649 INFO L93 Difference]: Finished difference Result 608 states and 881 transitions. [2022-11-03 02:50:08,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:50:08,651 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:50:08,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:50:08,653 INFO L225 Difference]: With dead ends: 608 [2022-11-03 02:50:08,653 INFO L226 Difference]: Without dead ends: 491 [2022-11-03 02:50:08,662 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 119 GetRequests, 113 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2022-11-03 02:50:08,663 INFO L413 NwaCegarLoop]: 152 mSDtfsCounter, 101 mSDsluCounter, 891 mSDsCounter, 0 mSdLazyCounter, 7 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 101 SdHoareTripleChecker+Valid, 1043 SdHoareTripleChecker+Invalid, 57 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 7 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-03 02:50:08,663 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [101 Valid, 1043 Invalid, 57 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 7 Invalid, 0 Unknown, 50 Unchecked, 0.2s Time] [2022-11-03 02:50:08,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2022-11-03 02:50:08,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 491. [2022-11-03 02:50:08,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 491 states, 490 states have (on average 1.4428571428571428) internal successors, (707), 490 states have internal predecessors, (707), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:08,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 491 states to 491 states and 707 transitions. [2022-11-03 02:50:08,674 INFO L78 Accepts]: Start accepts. Automaton has 491 states and 707 transitions. Word has length 120 [2022-11-03 02:50:08,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:50:08,675 INFO L495 AbstractCegarLoop]: Abstraction has 491 states and 707 transitions. [2022-11-03 02:50:08,675 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 15.0) internal successors, (120), 8 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:50:08,675 INFO L276 IsEmpty]: Start isEmpty. Operand 491 states and 707 transitions. [2022-11-03 02:50:08,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:50:08,677 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:50:08,677 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:50:08,703 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (15)] Forceful destruction successful, exit code 0 [2022-11-03 02:50:08,898 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:50:08,899 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:50:08,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:50:08,899 INFO L85 PathProgramCache]: Analyzing trace with hash 805720615, now seen corresponding path program 1 times [2022-11-03 02:50:08,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:50:08,901 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [659540526] [2022-11-03 02:50:08,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:08,901 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:50:08,901 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:50:08,903 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:50:08,948 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Waiting until timeout for monitored process [2022-11-03 02:50:09,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:09,754 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-03 02:50:09,759 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:11,865 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:11,865 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:50:34,541 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:34,541 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:50:34,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [659540526] [2022-11-03 02:50:34,541 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [659540526] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:50:34,541 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [280243043] [2022-11-03 02:50:34,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:50:34,542 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:50:34,542 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:50:34,545 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:50:34,546 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Waiting until timeout for monitored process [2022-11-03 02:50:36,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:50:36,084 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 39 conjunts are in the unsatisfiable core [2022-11-03 02:50:36,090 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:50:38,115 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:50:38,115 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:51:55,491 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:51:55,491 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleCvc4 [280243043] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:51:55,492 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1824638993] [2022-11-03 02:51:55,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:51:55,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:51:55,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 [2022-11-03 02:51:55,499 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-03 02:51:55,505 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2022-11-03 02:51:56,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:51:56,186 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 20 conjunts are in the unsatisfiable core [2022-11-03 02:51:56,191 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:51:57,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:51:57,682 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:51:59,488 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:51:59,488 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1824638993] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:51:59,488 INFO L184 FreeRefinementEngine]: Found 0 perfect and 6 imperfect interpolant sequences. [2022-11-03 02:51:59,489 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 9, 9] total 39 [2022-11-03 02:51:59,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663369480] [2022-11-03 02:51:59,489 INFO L85 oduleStraightlineAll]: Using 6 imperfect interpolants to construct interpolant automaton [2022-11-03 02:51:59,490 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 39 states [2022-11-03 02:51:59,490 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:51:59,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2022-11-03 02:51:59,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=229, Invalid=1217, Unknown=36, NotChecked=0, Total=1482 [2022-11-03 02:51:59,492 INFO L87 Difference]: Start difference. First operand 491 states and 707 transitions. Second operand has 39 states, 39 states have (on average 15.0) internal successors, (585), 39 states have internal predecessors, (585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:00,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:52:00,598 INFO L93 Difference]: Finished difference Result 956 states and 1377 transitions. [2022-11-03 02:52:00,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-11-03 02:52:00,599 INFO L78 Accepts]: Start accepts. Automaton has has 39 states, 39 states have (on average 15.0) internal successors, (585), 39 states have internal predecessors, (585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:52:00,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:52:00,602 INFO L225 Difference]: With dead ends: 956 [2022-11-03 02:52:00,602 INFO L226 Difference]: Without dead ends: 954 [2022-11-03 02:52:00,605 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 730 GetRequests, 677 SyntacticMatches, 4 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 791 ImplicationChecksByTransitivity, 100.0s TimeCoverageRelationStatistics Valid=455, Invalid=2059, Unknown=36, NotChecked=0, Total=2550 [2022-11-03 02:52:00,606 INFO L413 NwaCegarLoop]: 152 mSDtfsCounter, 1605 mSDsluCounter, 3168 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1605 SdHoareTripleChecker+Valid, 3320 SdHoareTripleChecker+Invalid, 59 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 56 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-03 02:52:00,607 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1605 Valid, 3320 Invalid, 59 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 3 Invalid, 0 Unknown, 56 Unchecked, 0.0s Time] [2022-11-03 02:52:00,609 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 954 states. [2022-11-03 02:52:00,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 954 to 954. [2022-11-03 02:52:00,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 954 states, 953 states have (on average 1.4428121720881426) internal successors, (1375), 953 states have internal predecessors, (1375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:00,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 954 states to 954 states and 1375 transitions. [2022-11-03 02:52:00,627 INFO L78 Accepts]: Start accepts. Automaton has 954 states and 1375 transitions. Word has length 120 [2022-11-03 02:52:00,627 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:52:00,627 INFO L495 AbstractCegarLoop]: Abstraction has 954 states and 1375 transitions. [2022-11-03 02:52:00,627 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 39 states, 39 states have (on average 15.0) internal successors, (585), 39 states have internal predecessors, (585), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:00,628 INFO L276 IsEmpty]: Start isEmpty. Operand 954 states and 1375 transitions. [2022-11-03 02:52:00,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:52:00,630 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:52:00,630 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:52:00,643 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (17)] Forceful destruction successful, exit code 0 [2022-11-03 02:52:00,856 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (16)] Ended with exit code 0 [2022-11-03 02:52:01,066 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Forceful destruction successful, exit code 0 [2022-11-03 02:52:01,241 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 17 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt,16 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3,18 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-03 02:52:01,241 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:52:01,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:52:01,242 INFO L85 PathProgramCache]: Analyzing trace with hash 832786217, now seen corresponding path program 1 times [2022-11-03 02:52:01,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:52:01,243 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1089377947] [2022-11-03 02:52:01,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:52:01,243 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:52:01,244 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:52:01,244 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:52:01,246 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Waiting until timeout for monitored process [2022-11-03 02:52:01,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:52:01,946 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 6 conjunts are in the unsatisfiable core [2022-11-03 02:52:01,949 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:52:02,167 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:52:02,167 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-03 02:52:02,167 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:52:02,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1089377947] [2022-11-03 02:52:02,167 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1089377947] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-03 02:52:02,167 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-03 02:52:02,167 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-03 02:52:02,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209012310] [2022-11-03 02:52:02,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-03 02:52:02,168 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-03 02:52:02,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy WALRUS [2022-11-03 02:52:02,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-03 02:52:02,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2022-11-03 02:52:02,169 INFO L87 Difference]: Start difference. First operand 954 states and 1375 transitions. Second operand has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:02,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-03 02:52:02,585 INFO L93 Difference]: Finished difference Result 1529 states and 2166 transitions. [2022-11-03 02:52:02,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-03 02:52:02,587 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Word has length 120 [2022-11-03 02:52:02,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-03 02:52:02,592 INFO L225 Difference]: With dead ends: 1529 [2022-11-03 02:52:02,592 INFO L226 Difference]: Without dead ends: 1366 [2022-11-03 02:52:02,593 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-11-03 02:52:02,610 INFO L413 NwaCegarLoop]: 394 mSDtfsCounter, 305 mSDsluCounter, 1555 mSDsCounter, 0 mSdLazyCounter, 32 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 305 SdHoareTripleChecker+Valid, 1949 SdHoareTripleChecker+Invalid, 46 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 32 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 13 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-03 02:52:02,610 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [305 Valid, 1949 Invalid, 46 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 32 Invalid, 0 Unknown, 13 Unchecked, 0.4s Time] [2022-11-03 02:52:02,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1366 states. [2022-11-03 02:52:02,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1366 to 1040. [2022-11-03 02:52:02,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1040 states, 1039 states have (on average 1.4398460057747835) internal successors, (1496), 1039 states have internal predecessors, (1496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:02,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1040 states to 1040 states and 1496 transitions. [2022-11-03 02:52:02,634 INFO L78 Accepts]: Start accepts. Automaton has 1040 states and 1496 transitions. Word has length 120 [2022-11-03 02:52:02,636 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-03 02:52:02,636 INFO L495 AbstractCegarLoop]: Abstraction has 1040 states and 1496 transitions. [2022-11-03 02:52:02,636 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 17.142857142857142) internal successors, (120), 7 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2022-11-03 02:52:02,637 INFO L276 IsEmpty]: Start isEmpty. Operand 1040 states and 1496 transitions. [2022-11-03 02:52:02,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2022-11-03 02:52:02,639 INFO L187 NwaCegarLoop]: Found error trace [2022-11-03 02:52:02,639 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-03 02:52:02,667 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (19)] Forceful destruction successful, exit code 0 [2022-11-03 02:52:02,863 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 19 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 [2022-11-03 02:52:02,863 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-03 02:52:02,864 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-03 02:52:02,864 INFO L85 PathProgramCache]: Analyzing trace with hash 479697835, now seen corresponding path program 1 times [2022-11-03 02:52:02,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy WALRUS [2022-11-03 02:52:02,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleMathsat [1143405283] [2022-11-03 02:52:02,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:52:02,865 INFO L173 SolverBuilder]: Constructing external solver with command: mathsat -unsat_core_generation=3 [2022-11-03 02:52:02,865 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat [2022-11-03 02:52:02,866 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (exit command is (exit), workingDir is null) [2022-11-03 02:52:02,872 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/mathsat -unsat_core_generation=3 (20)] Waiting until timeout for monitored process [2022-11-03 02:52:03,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:52:03,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-03 02:52:03,632 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:52:06,072 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:52:06,072 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-03 02:52:13,372 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:52:13,372 INFO L136 FreeRefinementEngine]: Strategy WALRUS found an infeasible trace [2022-11-03 02:52:13,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleMathsat [1143405283] [2022-11-03 02:52:13,373 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleMathsat [1143405283] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-03 02:52:13,373 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleCvc4 [1597663914] [2022-11-03 02:52:13,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-03 02:52:13,373 INFO L173 SolverBuilder]: Constructing external solver with command: cvc4 --incremental --print-success --lang smt [2022-11-03 02:52:13,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 [2022-11-03 02:52:13,375 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (exit command is (exit), workingDir is null) [2022-11-03 02:52:13,378 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d45650c0-e887-4c01-96c2-2e45cfd097a1/bin/utaipan-7li7fVZpFI/cvc4 --incremental --print-success --lang smt (21)] Waiting until timeout for monitored process [2022-11-03 02:52:14,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-03 02:52:14,851 INFO L263 TraceCheckSpWp]: Trace formula consists of 1668 conjuncts, 43 conjunts are in the unsatisfiable core [2022-11-03 02:52:14,856 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-03 02:52:16,752 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-03 02:52:16,753 INFO L328 TraceCheckSpWp]: Computing backward predicates...