./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/config/TaipanReach.xml -i ../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-26 00:52:04,667 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-26 00:52:04,669 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-26 00:52:04,704 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-26 00:52:04,704 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-26 00:52:04,705 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-26 00:52:04,707 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-26 00:52:04,714 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-26 00:52:04,717 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-26 00:52:04,723 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-26 00:52:04,725 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-26 00:52:04,728 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-26 00:52:04,728 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-26 00:52:04,731 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-26 00:52:04,735 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-26 00:52:04,738 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-26 00:52:04,740 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-26 00:52:04,741 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-26 00:52:04,743 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-26 00:52:04,751 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-26 00:52:04,752 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-26 00:52:04,757 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-26 00:52:04,759 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-26 00:52:04,761 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-26 00:52:04,771 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-26 00:52:04,771 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-26 00:52:04,771 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-26 00:52:04,772 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-26 00:52:04,773 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-26 00:52:04,774 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-26 00:52:04,774 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-26 00:52:04,775 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-26 00:52:04,776 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-26 00:52:04,777 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-26 00:52:04,778 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-26 00:52:04,779 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-26 00:52:04,779 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-26 00:52:04,780 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-26 00:52:04,784 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-26 00:52:04,786 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-26 00:52:04,787 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-26 00:52:04,788 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/config/svcomp-Reach-32bit-Taipan_Default.epf [2022-11-26 00:52:04,833 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-26 00:52:04,833 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-26 00:52:04,834 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-26 00:52:04,834 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-26 00:52:04,835 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-26 00:52:04,835 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-26 00:52:04,835 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-26 00:52:04,836 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-26 00:52:04,836 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-26 00:52:04,836 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-26 00:52:04,837 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-26 00:52:04,837 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-26 00:52:04,838 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-26 00:52:04,838 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-26 00:52:04,838 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-26 00:52:04,838 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-26 00:52:04,838 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-26 00:52:04,839 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-26 00:52:04,840 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-26 00:52:04,840 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-26 00:52:04,840 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-26 00:52:04,840 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-26 00:52:04,841 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-26 00:52:04,841 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-26 00:52:04,841 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-26 00:52:04,841 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-26 00:52:04,842 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-26 00:52:04,842 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-26 00:52:04,843 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-26 00:52:04,843 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-26 00:52:04,843 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-26 00:52:04,843 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-26 00:52:04,844 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-26 00:52:04,844 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-26 00:52:04,844 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-26 00:52:04,844 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-26 00:52:04,844 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-26 00:52:04,845 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-26 00:52:04,845 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-26 00:52:04,846 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-26 00:52:04,846 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-26 00:52:04,846 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0bd5c2784fe43830be309c722c3fa9fc4d3ef116c17a8343acb2a2dfbcf830c0 [2022-11-26 00:52:05,131 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-26 00:52:05,162 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-26 00:52:05,167 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-26 00:52:05,169 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-26 00:52:05,169 INFO L275 PluginConnector]: CDTParser initialized [2022-11-26 00:52:05,171 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/../../sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2022-11-26 00:52:08,358 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-26 00:52:08,579 INFO L351 CDTParser]: Found 1 translation units. [2022-11-26 00:52:08,580 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c [2022-11-26 00:52:08,590 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/data/6dc19568f/71864cb9a5904b90a3abe6ef704bf70c/FLAG87d7c32f9 [2022-11-26 00:52:08,609 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/data/6dc19568f/71864cb9a5904b90a3abe6ef704bf70c [2022-11-26 00:52:08,611 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-26 00:52:08,613 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-26 00:52:08,614 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-26 00:52:08,615 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-26 00:52:08,621 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-26 00:52:08,622 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,626 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4f9f83c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08, skipping insertion in model container [2022-11-26 00:52:08,627 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,635 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-26 00:52:08,650 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-26 00:52:08,796 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2022-11-26 00:52:08,828 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-26 00:52:08,844 INFO L203 MainTranslator]: Completed pre-run [2022-11-26 00:52:08,860 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/sv-benchmarks/c/nla-digbench-scaling/mannadiv_unwindbound100.c[573,586] [2022-11-26 00:52:08,876 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-26 00:52:08,895 INFO L208 MainTranslator]: Completed translation [2022-11-26 00:52:08,895 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08 WrapperNode [2022-11-26 00:52:08,896 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-26 00:52:08,897 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-26 00:52:08,897 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-26 00:52:08,897 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-26 00:52:08,905 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,914 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,934 INFO L138 Inliner]: procedures = 14, calls = 11, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 47 [2022-11-26 00:52:08,935 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-26 00:52:08,936 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-26 00:52:08,936 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-26 00:52:08,936 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-26 00:52:08,947 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,948 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,962 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,962 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,966 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,972 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,975 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,980 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,982 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-26 00:52:08,989 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-26 00:52:08,989 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-26 00:52:08,989 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-26 00:52:08,990 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (1/1) ... [2022-11-26 00:52:08,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-26 00:52:09,009 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:09,027 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-26 00:52:09,060 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-26 00:52:09,081 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-26 00:52:09,081 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-11-26 00:52:09,081 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-11-26 00:52:09,082 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-26 00:52:09,082 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-26 00:52:09,082 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-26 00:52:09,082 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-11-26 00:52:09,082 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-11-26 00:52:09,152 INFO L235 CfgBuilder]: Building ICFG [2022-11-26 00:52:09,155 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-26 00:52:09,355 INFO L276 CfgBuilder]: Performing block encoding [2022-11-26 00:52:09,385 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-26 00:52:09,386 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-11-26 00:52:09,388 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:52:09 BoogieIcfgContainer [2022-11-26 00:52:09,389 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-26 00:52:09,391 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-26 00:52:09,391 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-26 00:52:09,400 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-26 00:52:09,401 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.11 12:52:08" (1/3) ... [2022-11-26 00:52:09,401 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@687f6055 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 12:52:09, skipping insertion in model container [2022-11-26 00:52:09,402 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:52:08" (2/3) ... [2022-11-26 00:52:09,402 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@687f6055 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 12:52:09, skipping insertion in model container [2022-11-26 00:52:09,402 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:52:09" (3/3) ... [2022-11-26 00:52:09,404 INFO L112 eAbstractionObserver]: Analyzing ICFG mannadiv_unwindbound100.c [2022-11-26 00:52:09,443 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-26 00:52:09,456 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-26 00:52:09,547 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-26 00:52:09,558 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@760f94d5, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-26 00:52:09,558 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-26 00:52:09,563 INFO L276 IsEmpty]: Start isEmpty. Operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2022-11-26 00:52:09,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-11-26 00:52:09,576 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:09,577 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:09,578 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:09,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:09,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1046920148, now seen corresponding path program 1 times [2022-11-26 00:52:09,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:09,604 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [980001750] [2022-11-26 00:52:09,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:09,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:09,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:09,823 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:09,823 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [980001750] [2022-11-26 00:52:09,823 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-26 00:52:09,824 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [569697183] [2022-11-26 00:52:09,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:09,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:09,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:09,828 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:09,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-11-26 00:52:09,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:09,898 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 1 conjunts are in the unsatisfiable core [2022-11-26 00:52:09,905 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:09,927 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:09,927 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-26 00:52:09,928 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [569697183] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:52:09,928 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:52:09,928 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-11-26 00:52:09,931 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1591489623] [2022-11-26 00:52:09,931 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:52:09,936 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-11-26 00:52:09,936 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:09,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-11-26 00:52:09,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-26 00:52:09,971 INFO L87 Difference]: Start difference. First operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:10,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:10,010 INFO L93 Difference]: Finished difference Result 32 states and 43 transitions. [2022-11-26 00:52:10,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-11-26 00:52:10,013 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 13 [2022-11-26 00:52:10,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:10,022 INFO L225 Difference]: With dead ends: 32 [2022-11-26 00:52:10,022 INFO L226 Difference]: Without dead ends: 17 [2022-11-26 00:52:10,028 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-11-26 00:52:10,035 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 4 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:10,037 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 18 Invalid, 4 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 4 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-26 00:52:10,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-11-26 00:52:10,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-11-26 00:52:10,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 10 states have (on average 1.3) internal successors, (13), 11 states have internal predecessors, (13), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-26 00:52:10,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 20 transitions. [2022-11-26 00:52:10,083 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 20 transitions. Word has length 13 [2022-11-26 00:52:10,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:10,085 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 20 transitions. [2022-11-26 00:52:10,085 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:10,086 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 20 transitions. [2022-11-26 00:52:10,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-11-26 00:52:10,088 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:10,088 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:10,096 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:10,294 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0,2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:10,295 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:10,295 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:10,296 INFO L85 PathProgramCache]: Analyzing trace with hash 1317434454, now seen corresponding path program 1 times [2022-11-26 00:52:10,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:10,296 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213528718] [2022-11-26 00:52:10,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:10,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:10,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:10,376 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:10,376 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213528718] [2022-11-26 00:52:10,376 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: Unsupported non-linear arithmetic [2022-11-26 00:52:10,377 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1282302987] [2022-11-26 00:52:10,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:10,377 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:10,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:10,388 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:10,420 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-11-26 00:52:10,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:10,478 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 3 conjunts are in the unsatisfiable core [2022-11-26 00:52:10,480 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:10,564 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:10,564 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-26 00:52:10,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1282302987] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:52:10,566 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:52:10,566 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-11-26 00:52:10,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865770625] [2022-11-26 00:52:10,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:52:10,569 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-26 00:52:10,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:10,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-26 00:52:10,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:52:10,577 INFO L87 Difference]: Start difference. First operand 17 states and 20 transitions. Second operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:10,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:10,613 INFO L93 Difference]: Finished difference Result 26 states and 29 transitions. [2022-11-26 00:52:10,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-26 00:52:10,614 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 14 [2022-11-26 00:52:10,614 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:10,615 INFO L225 Difference]: With dead ends: 26 [2022-11-26 00:52:10,615 INFO L226 Difference]: Without dead ends: 19 [2022-11-26 00:52:10,615 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:52:10,621 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 0 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:10,622 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 39 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-11-26 00:52:10,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2022-11-26 00:52:10,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-11-26 00:52:10,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 12 states have (on average 1.25) internal successors, (15), 13 states have internal predecessors, (15), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-26 00:52:10,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 22 transitions. [2022-11-26 00:52:10,633 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 22 transitions. Word has length 14 [2022-11-26 00:52:10,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:10,634 INFO L495 AbstractCegarLoop]: Abstraction has 19 states and 22 transitions. [2022-11-26 00:52:10,634 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:10,634 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 22 transitions. [2022-11-26 00:52:10,635 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-11-26 00:52:10,635 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:10,635 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:10,651 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:10,840 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:10,841 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:10,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:10,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1319221914, now seen corresponding path program 1 times [2022-11-26 00:52:10,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:10,842 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936074792] [2022-11-26 00:52:10,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:10,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:10,874 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:10,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1451578876] [2022-11-26 00:52:10,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:10,875 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:10,875 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:10,883 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:10,888 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-11-26 00:52:10,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:10,963 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-26 00:52:10,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:11,096 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-26 00:52:11,097 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-11-26 00:52:11,097 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:11,097 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936074792] [2022-11-26 00:52:11,098 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:11,098 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1451578876] [2022-11-26 00:52:11,098 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1451578876] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:52:11,098 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:52:11,098 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2022-11-26 00:52:11,099 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1704222408] [2022-11-26 00:52:11,099 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:52:11,099 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-11-26 00:52:11,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:11,100 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-11-26 00:52:11,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-11-26 00:52:11,101 INFO L87 Difference]: Start difference. First operand 19 states and 22 transitions. Second operand has 7 states, 6 states have (on average 1.5) internal successors, (9), 5 states have internal predecessors, (9), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:11,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:11,177 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-11-26 00:52:11,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-11-26 00:52:11,178 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 6 states have (on average 1.5) internal successors, (9), 5 states have internal predecessors, (9), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) Word has length 14 [2022-11-26 00:52:11,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:11,179 INFO L225 Difference]: With dead ends: 28 [2022-11-26 00:52:11,179 INFO L226 Difference]: Without dead ends: 26 [2022-11-26 00:52:11,180 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 8 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2022-11-26 00:52:11,181 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 13 mSDsluCounter, 35 mSDsCounter, 0 mSdLazyCounter, 55 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 55 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:11,182 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 47 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 55 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:11,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-11-26 00:52:11,187 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2022-11-26 00:52:11,188 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 15 states have (on average 1.2) internal successors, (18), 17 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-11-26 00:52:11,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 27 transitions. [2022-11-26 00:52:11,189 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 27 transitions. Word has length 14 [2022-11-26 00:52:11,189 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:11,190 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 27 transitions. [2022-11-26 00:52:11,190 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 6 states have (on average 1.5) internal successors, (9), 5 states have internal predecessors, (9), 2 states have call successors, (3), 2 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 1 states have call successors, (2) [2022-11-26 00:52:11,190 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 27 transitions. [2022-11-26 00:52:11,191 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-11-26 00:52:11,191 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:11,191 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:11,213 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:11,396 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:11,397 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:11,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:11,398 INFO L85 PathProgramCache]: Analyzing trace with hash -1562521278, now seen corresponding path program 1 times [2022-11-26 00:52:11,398 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:11,398 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486614887] [2022-11-26 00:52:11,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:11,398 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:11,412 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:11,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [754842471] [2022-11-26 00:52:11,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:11,413 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:11,413 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:11,414 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:11,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-11-26 00:52:11,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:11,485 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 19 conjunts are in the unsatisfiable core [2022-11-26 00:52:11,488 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:11,700 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-26 00:52:11,700 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:11,916 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:11,916 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:11,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [486614887] [2022-11-26 00:52:11,917 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:11,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [754842471] [2022-11-26 00:52:11,917 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [754842471] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:11,917 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1507295421] [2022-11-26 00:52:11,943 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:11,948 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:11,952 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:11,957 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:11,957 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:12,486 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 40 for LOIs [2022-11-26 00:52:12,503 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:12,548 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:14,100 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSifa [1507295421] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:52:14,100 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:14,101 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [11, 7] total 26 [2022-11-26 00:52:14,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394772287] [2022-11-26 00:52:14,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:52:14,102 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-11-26 00:52:14,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:14,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-26 00:52:14,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=548, Unknown=0, NotChecked=0, Total=650 [2022-11-26 00:52:14,103 INFO L87 Difference]: Start difference. First operand 24 states and 27 transitions. Second operand has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-26 00:52:14,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:14,253 INFO L93 Difference]: Finished difference Result 32 states and 35 transitions. [2022-11-26 00:52:14,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-11-26 00:52:14,254 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 20 [2022-11-26 00:52:14,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:14,256 INFO L225 Difference]: With dead ends: 32 [2022-11-26 00:52:14,256 INFO L226 Difference]: Without dead ends: 25 [2022-11-26 00:52:14,256 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 31 SyntacticMatches, 3 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 186 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=102, Invalid=548, Unknown=0, NotChecked=0, Total=650 [2022-11-26 00:52:14,262 INFO L413 NwaCegarLoop]: 9 mSDtfsCounter, 0 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 92 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 36 SdHoareTripleChecker+Invalid, 92 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 92 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:14,265 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 36 Invalid, 92 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 92 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:14,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-11-26 00:52:14,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2022-11-26 00:52:14,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 16 states have (on average 1.1875) internal successors, (19), 17 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2022-11-26 00:52:14,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 28 transitions. [2022-11-26 00:52:14,283 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 28 transitions. Word has length 20 [2022-11-26 00:52:14,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:14,283 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 28 transitions. [2022-11-26 00:52:14,283 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-11-26 00:52:14,283 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 28 transitions. [2022-11-26 00:52:14,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-11-26 00:52:14,288 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:14,288 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:14,299 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2022-11-26 00:52:14,494 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:14,494 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:14,495 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:14,495 INFO L85 PathProgramCache]: Analyzing trace with hash -182192907, now seen corresponding path program 1 times [2022-11-26 00:52:14,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:14,495 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197377868] [2022-11-26 00:52:14,495 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:14,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:14,532 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:14,532 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1872517764] [2022-11-26 00:52:14,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:14,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:14,533 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:14,547 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:14,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-11-26 00:52:14,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:14,607 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 5 conjunts are in the unsatisfiable core [2022-11-26 00:52:14,609 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:14,653 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:14,654 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:14,694 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:14,694 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:14,694 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197377868] [2022-11-26 00:52:14,695 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:14,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872517764] [2022-11-26 00:52:14,695 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1872517764] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:14,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [511024962] [2022-11-26 00:52:14,698 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:14,698 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:14,699 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:14,699 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:14,699 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:15,419 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-11-26 00:52:15,572 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:15,605 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:16,826 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '709#(and (<= 0 |#NULL.base|) (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= |#NULL.base| 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|))' at error location [2022-11-26 00:52:16,826 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:16,826 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:16,826 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 8 [2022-11-26 00:52:16,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701187732] [2022-11-26 00:52:16,827 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:16,827 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-11-26 00:52:16,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:16,828 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-11-26 00:52:16,828 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=380, Unknown=0, NotChecked=0, Total=462 [2022-11-26 00:52:16,828 INFO L87 Difference]: Start difference. First operand 25 states and 28 transitions. Second operand has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-11-26 00:52:16,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:16,927 INFO L93 Difference]: Finished difference Result 56 states and 63 transitions. [2022-11-26 00:52:16,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-11-26 00:52:16,929 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) Word has length 22 [2022-11-26 00:52:16,929 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:16,930 INFO L225 Difference]: With dead ends: 56 [2022-11-26 00:52:16,932 INFO L226 Difference]: Without dead ends: 49 [2022-11-26 00:52:16,932 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 44 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 179 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=102, Invalid=498, Unknown=0, NotChecked=0, Total=600 [2022-11-26 00:52:16,934 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 25 mSDsluCounter, 59 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 25 SdHoareTripleChecker+Valid, 77 SdHoareTripleChecker+Invalid, 40 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:16,936 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [25 Valid, 77 Invalid, 40 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 37 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:16,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-11-26 00:52:16,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 45. [2022-11-26 00:52:16,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 30 states have (on average 1.2333333333333334) internal successors, (37), 33 states have internal predecessors, (37), 9 states have call successors, (9), 5 states have call predecessors, (9), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-11-26 00:52:16,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2022-11-26 00:52:16,957 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 22 [2022-11-26 00:52:16,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:16,958 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2022-11-26 00:52:16,958 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-11-26 00:52:16,958 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2022-11-26 00:52:16,959 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-11-26 00:52:16,960 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:16,960 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:16,970 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:17,165 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:17,166 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:17,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:17,166 INFO L85 PathProgramCache]: Analyzing trace with hash -180405447, now seen corresponding path program 1 times [2022-11-26 00:52:17,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:17,166 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042268187] [2022-11-26 00:52:17,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:17,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:17,178 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:17,178 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [645448401] [2022-11-26 00:52:17,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:17,178 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:17,178 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:17,181 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:17,187 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-11-26 00:52:17,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:17,234 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-26 00:52:17,236 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:17,519 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-11-26 00:52:17,520 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:17,677 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:17,677 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:17,677 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042268187] [2022-11-26 00:52:17,678 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:17,678 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [645448401] [2022-11-26 00:52:17,680 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [645448401] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:17,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1137600885] [2022-11-26 00:52:17,684 INFO L159 IcfgInterpreter]: Started Sifa with 16 locations of interest [2022-11-26 00:52:17,684 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:17,684 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:17,685 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:17,685 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:18,254 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 37 for LOIs [2022-11-26 00:52:18,304 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:18,340 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:19,379 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1009#(and (< ~counter~0 101) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:19,379 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:19,379 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:19,379 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 6] total 13 [2022-11-26 00:52:19,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944151975] [2022-11-26 00:52:19,380 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:19,380 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-11-26 00:52:19,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:19,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-11-26 00:52:19,381 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=565, Unknown=0, NotChecked=0, Total=650 [2022-11-26 00:52:19,381 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand has 13 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 11 states have internal predecessors, (25), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-26 00:52:19,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:19,562 INFO L93 Difference]: Finished difference Result 59 states and 65 transitions. [2022-11-26 00:52:19,563 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-11-26 00:52:19,563 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 11 states have internal predecessors, (25), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) Word has length 22 [2022-11-26 00:52:19,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:19,564 INFO L225 Difference]: With dead ends: 59 [2022-11-26 00:52:19,564 INFO L226 Difference]: Without dead ends: 51 [2022-11-26 00:52:19,565 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 39 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 179 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=108, Invalid=704, Unknown=0, NotChecked=0, Total=812 [2022-11-26 00:52:19,565 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 26 mSDsluCounter, 38 mSDsCounter, 0 mSdLazyCounter, 109 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 50 SdHoareTripleChecker+Invalid, 113 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 109 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:19,566 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 50 Invalid, 113 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 109 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:19,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2022-11-26 00:52:19,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 45. [2022-11-26 00:52:19,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 32 states have (on average 1.125) internal successors, (36), 32 states have internal predecessors, (36), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-11-26 00:52:19,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2022-11-26 00:52:19,577 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 22 [2022-11-26 00:52:19,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:19,577 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2022-11-26 00:52:19,578 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 11 states have internal predecessors, (25), 5 states have call successors, (7), 3 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-26 00:52:19,578 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2022-11-26 00:52:19,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-11-26 00:52:19,578 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:19,579 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:19,589 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:19,789 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-11-26 00:52:19,789 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:19,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:19,790 INFO L85 PathProgramCache]: Analyzing trace with hash 408559265, now seen corresponding path program 1 times [2022-11-26 00:52:19,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:19,790 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021736065] [2022-11-26 00:52:19,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:19,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:19,800 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:19,800 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1771377294] [2022-11-26 00:52:19,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:19,801 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:19,801 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:19,802 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:19,813 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-11-26 00:52:19,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:19,860 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 17 conjunts are in the unsatisfiable core [2022-11-26 00:52:19,862 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:20,059 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-11-26 00:52:20,059 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:20,182 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 7 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-11-26 00:52:20,182 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:20,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021736065] [2022-11-26 00:52:20,182 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:20,182 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1771377294] [2022-11-26 00:52:20,183 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1771377294] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:20,183 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [757235207] [2022-11-26 00:52:20,185 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:20,185 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:20,185 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:20,186 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:20,186 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:20,993 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:20,998 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:21,026 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:22,117 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1349#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:22,118 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:22,118 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:22,118 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 14 [2022-11-26 00:52:22,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [717708782] [2022-11-26 00:52:22,118 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:22,118 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-26 00:52:22,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:22,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-26 00:52:22,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=665, Unknown=0, NotChecked=0, Total=756 [2022-11-26 00:52:22,120 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand has 14 states, 12 states have (on average 2.25) internal successors, (27), 11 states have internal predecessors, (27), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-26 00:52:22,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:22,331 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2022-11-26 00:52:22,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-11-26 00:52:22,333 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 12 states have (on average 2.25) internal successors, (27), 11 states have internal predecessors, (27), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) Word has length 28 [2022-11-26 00:52:22,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:22,333 INFO L225 Difference]: With dead ends: 51 [2022-11-26 00:52:22,334 INFO L226 Difference]: Without dead ends: 45 [2022-11-26 00:52:22,334 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 56 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 207 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=118, Invalid=874, Unknown=0, NotChecked=0, Total=992 [2022-11-26 00:52:22,335 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 15 mSDsluCounter, 53 mSDsCounter, 0 mSdLazyCounter, 92 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 69 SdHoareTripleChecker+Invalid, 96 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 92 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:22,335 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 69 Invalid, 96 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 92 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:22,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2022-11-26 00:52:22,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2022-11-26 00:52:22,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 32 states have (on average 1.03125) internal successors, (33), 32 states have internal predecessors, (33), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-11-26 00:52:22,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 46 transitions. [2022-11-26 00:52:22,349 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 46 transitions. Word has length 28 [2022-11-26 00:52:22,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:22,350 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 46 transitions. [2022-11-26 00:52:22,350 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 12 states have (on average 2.25) internal successors, (27), 11 states have internal predecessors, (27), 5 states have call successors, (7), 3 states have call predecessors, (7), 2 states have return successors, (6), 4 states have call predecessors, (6), 3 states have call successors, (6) [2022-11-26 00:52:22,350 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 46 transitions. [2022-11-26 00:52:22,353 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-11-26 00:52:22,354 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:22,354 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:22,360 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:22,559 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:22,560 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:22,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:22,561 INFO L85 PathProgramCache]: Analyzing trace with hash -235004718, now seen corresponding path program 2 times [2022-11-26 00:52:22,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:22,561 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304486129] [2022-11-26 00:52:22,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:22,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:22,576 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:22,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1284645593] [2022-11-26 00:52:22,576 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-26 00:52:22,577 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:22,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:22,578 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:22,580 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-11-26 00:52:22,639 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-11-26 00:52:22,640 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-26 00:52:22,641 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 11 conjunts are in the unsatisfiable core [2022-11-26 00:52:22,643 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:22,729 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 8 proven. 56 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:22,729 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:22,828 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 8 proven. 32 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2022-11-26 00:52:22,828 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:22,828 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304486129] [2022-11-26 00:52:22,828 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:22,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1284645593] [2022-11-26 00:52:22,829 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1284645593] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:22,829 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [696129214] [2022-11-26 00:52:22,831 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:22,831 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:22,832 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:22,832 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:22,832 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:23,603 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:23,608 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:23,633 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:24,515 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1790#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:24,515 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:24,515 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:24,516 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 14 [2022-11-26 00:52:24,516 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425251389] [2022-11-26 00:52:24,516 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:24,517 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-11-26 00:52:24,517 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:24,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-11-26 00:52:24,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=164, Invalid=538, Unknown=0, NotChecked=0, Total=702 [2022-11-26 00:52:24,518 INFO L87 Difference]: Start difference. First operand 45 states and 46 transitions. Second operand has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-11-26 00:52:24,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:24,745 INFO L93 Difference]: Finished difference Result 98 states and 104 transitions. [2022-11-26 00:52:24,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-11-26 00:52:24,748 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) Word has length 46 [2022-11-26 00:52:24,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:24,749 INFO L225 Difference]: With dead ends: 98 [2022-11-26 00:52:24,750 INFO L226 Difference]: Without dead ends: 93 [2022-11-26 00:52:24,751 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 401 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=277, Invalid=983, Unknown=0, NotChecked=0, Total=1260 [2022-11-26 00:52:24,751 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 47 mSDsluCounter, 80 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 47 SdHoareTripleChecker+Valid, 103 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:24,752 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [47 Valid, 103 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 75 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-11-26 00:52:24,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2022-11-26 00:52:24,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2022-11-26 00:52:24,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 68 states have (on average 1.0147058823529411) internal successors, (69), 68 states have internal predecessors, (69), 13 states have call successors, (13), 12 states have call predecessors, (13), 11 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2022-11-26 00:52:24,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 94 transitions. [2022-11-26 00:52:24,767 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 94 transitions. Word has length 46 [2022-11-26 00:52:24,767 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:24,767 INFO L495 AbstractCegarLoop]: Abstraction has 93 states and 94 transitions. [2022-11-26 00:52:24,768 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-11-26 00:52:24,768 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 94 transitions. [2022-11-26 00:52:24,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-11-26 00:52:24,769 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:24,769 INFO L195 NwaCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:24,781 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:24,975 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:24,975 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:24,976 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:24,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1419782260, now seen corresponding path program 3 times [2022-11-26 00:52:24,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:24,976 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67778305] [2022-11-26 00:52:24,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:24,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:24,991 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:24,991 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1360949746] [2022-11-26 00:52:24,992 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-26 00:52:24,992 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:24,993 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:24,994 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:25,011 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-11-26 00:52:25,103 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-26 00:52:25,104 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-26 00:52:25,105 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 23 conjunts are in the unsatisfiable core [2022-11-26 00:52:25,109 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:25,346 INFO L134 CoverageAnalysis]: Checked inductivity of 402 backedges. 20 proven. 380 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:25,346 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:25,680 INFO L134 CoverageAnalysis]: Checked inductivity of 402 backedges. 20 proven. 200 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2022-11-26 00:52:25,680 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:25,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67778305] [2022-11-26 00:52:25,680 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:25,680 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1360949746] [2022-11-26 00:52:25,681 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1360949746] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:25,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [918485803] [2022-11-26 00:52:25,682 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:25,683 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:25,683 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:25,683 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:25,683 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:26,400 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:26,406 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:26,428 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:27,273 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '2670#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:27,274 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:27,274 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:27,274 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 26 [2022-11-26 00:52:27,274 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732368411] [2022-11-26 00:52:27,274 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:27,275 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-11-26 00:52:27,275 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:27,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-11-26 00:52:27,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=434, Invalid=1048, Unknown=0, NotChecked=0, Total=1482 [2022-11-26 00:52:27,277 INFO L87 Difference]: Start difference. First operand 93 states and 94 transitions. Second operand has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-11-26 00:52:27,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:27,856 INFO L93 Difference]: Finished difference Result 194 states and 206 transitions. [2022-11-26 00:52:27,856 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-11-26 00:52:27,856 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) Word has length 94 [2022-11-26 00:52:27,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:27,858 INFO L225 Difference]: With dead ends: 194 [2022-11-26 00:52:27,858 INFO L226 Difference]: Without dead ends: 189 [2022-11-26 00:52:27,860 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1016 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=949, Invalid=2591, Unknown=0, NotChecked=0, Total=3540 [2022-11-26 00:52:27,860 INFO L413 NwaCegarLoop]: 35 mSDtfsCounter, 77 mSDsluCounter, 155 mSDsCounter, 0 mSdLazyCounter, 150 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 77 SdHoareTripleChecker+Valid, 190 SdHoareTripleChecker+Invalid, 161 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 150 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:27,861 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [77 Valid, 190 Invalid, 161 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 150 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-11-26 00:52:27,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2022-11-26 00:52:27,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2022-11-26 00:52:27,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 189 states, 140 states have (on average 1.0071428571428571) internal successors, (141), 140 states have internal predecessors, (141), 25 states have call successors, (25), 24 states have call predecessors, (25), 23 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2022-11-26 00:52:27,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 190 transitions. [2022-11-26 00:52:27,885 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 190 transitions. Word has length 94 [2022-11-26 00:52:27,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:27,886 INFO L495 AbstractCegarLoop]: Abstraction has 189 states and 190 transitions. [2022-11-26 00:52:27,886 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-11-26 00:52:27,886 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 190 transitions. [2022-11-26 00:52:27,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2022-11-26 00:52:27,889 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:27,889 INFO L195 NwaCegarLoop]: trace histogram [23, 23, 22, 22, 22, 22, 22, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:27,901 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:28,095 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable8 [2022-11-26 00:52:28,095 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:28,096 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:28,096 INFO L85 PathProgramCache]: Analyzing trace with hash -1763378944, now seen corresponding path program 4 times [2022-11-26 00:52:28,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:28,096 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217809031] [2022-11-26 00:52:28,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:28,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:28,114 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:28,114 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [481698916] [2022-11-26 00:52:28,115 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-26 00:52:28,115 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:28,115 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:28,116 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:28,148 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-11-26 00:52:28,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:52:28,276 INFO L263 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 47 conjunts are in the unsatisfiable core [2022-11-26 00:52:28,282 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:28,878 INFO L134 CoverageAnalysis]: Checked inductivity of 1938 backedges. 44 proven. 1892 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:28,879 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:29,868 INFO L134 CoverageAnalysis]: Checked inductivity of 1938 backedges. 44 proven. 968 refuted. 0 times theorem prover too weak. 926 trivial. 0 not checked. [2022-11-26 00:52:29,868 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:29,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217809031] [2022-11-26 00:52:29,868 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:29,868 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [481698916] [2022-11-26 00:52:29,869 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [481698916] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:29,869 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [13500915] [2022-11-26 00:52:29,870 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:29,871 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:29,871 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:29,871 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:29,871 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:30,563 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:30,568 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:30,592 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:31,479 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '4438#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:31,480 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:31,480 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:31,480 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 50 [2022-11-26 00:52:31,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417928761] [2022-11-26 00:52:31,480 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:31,481 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-11-26 00:52:31,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:31,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-11-26 00:52:31,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1406, Invalid=2500, Unknown=0, NotChecked=0, Total=3906 [2022-11-26 00:52:31,485 INFO L87 Difference]: Start difference. First operand 189 states and 190 transitions. Second operand has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-11-26 00:52:33,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:33,531 INFO L93 Difference]: Finished difference Result 386 states and 410 transitions. [2022-11-26 00:52:33,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2022-11-26 00:52:33,532 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) Word has length 190 [2022-11-26 00:52:33,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:33,540 INFO L225 Difference]: With dead ends: 386 [2022-11-26 00:52:33,544 INFO L226 Difference]: Without dead ends: 381 [2022-11-26 00:52:33,547 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 613 GetRequests, 507 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2786 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=3589, Invalid=7967, Unknown=0, NotChecked=0, Total=11556 [2022-11-26 00:52:33,549 INFO L413 NwaCegarLoop]: 59 mSDtfsCounter, 230 mSDsluCounter, 227 mSDsCounter, 0 mSdLazyCounter, 373 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 230 SdHoareTripleChecker+Valid, 286 SdHoareTripleChecker+Invalid, 419 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 373 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:33,550 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [230 Valid, 286 Invalid, 419 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 373 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-26 00:52:33,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2022-11-26 00:52:33,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 381. [2022-11-26 00:52:33,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 284 states have (on average 1.0035211267605635) internal successors, (285), 284 states have internal predecessors, (285), 49 states have call successors, (49), 48 states have call predecessors, (49), 47 states have return successors, (48), 48 states have call predecessors, (48), 48 states have call successors, (48) [2022-11-26 00:52:33,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 382 transitions. [2022-11-26 00:52:33,619 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 382 transitions. Word has length 190 [2022-11-26 00:52:33,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:33,620 INFO L495 AbstractCegarLoop]: Abstraction has 381 states and 382 transitions. [2022-11-26 00:52:33,621 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-11-26 00:52:33,621 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 382 transitions. [2022-11-26 00:52:33,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 383 [2022-11-26 00:52:33,634 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:33,634 INFO L195 NwaCegarLoop]: trace histogram [47, 47, 46, 46, 46, 46, 46, 46, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:33,651 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:33,840 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-11-26 00:52:33,841 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:33,841 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:33,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1767238632, now seen corresponding path program 5 times [2022-11-26 00:52:33,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:33,841 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496330414] [2022-11-26 00:52:33,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:33,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:33,869 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:33,870 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1089357166] [2022-11-26 00:52:33,870 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-11-26 00:52:33,870 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:33,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:33,871 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:33,892 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-11-26 00:52:34,427 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 47 check-sat command(s) [2022-11-26 00:52:34,427 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-26 00:52:34,438 INFO L263 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 95 conjunts are in the unsatisfiable core [2022-11-26 00:52:34,445 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:36,203 INFO L134 CoverageAnalysis]: Checked inductivity of 8466 backedges. 92 proven. 8372 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:36,203 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:39,402 INFO L134 CoverageAnalysis]: Checked inductivity of 8466 backedges. 92 proven. 4232 refuted. 0 times theorem prover too weak. 4142 trivial. 0 not checked. [2022-11-26 00:52:39,402 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:39,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496330414] [2022-11-26 00:52:39,402 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:39,402 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1089357166] [2022-11-26 00:52:39,402 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1089357166] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:39,403 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1263738095] [2022-11-26 00:52:39,405 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:39,405 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:39,405 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:39,406 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:39,406 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:40,072 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:40,077 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:52:40,101 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:52:41,123 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '7982#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:52:41,124 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:52:41,124 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:52:41,124 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 50] total 98 [2022-11-26 00:52:41,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373741243] [2022-11-26 00:52:41,124 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:52:41,125 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-11-26 00:52:41,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:52:41,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-11-26 00:52:41,131 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5078, Invalid=7132, Unknown=0, NotChecked=0, Total=12210 [2022-11-26 00:52:41,132 INFO L87 Difference]: Start difference. First operand 381 states and 382 transitions. Second operand has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-11-26 00:52:47,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:52:47,384 INFO L93 Difference]: Finished difference Result 770 states and 818 transitions. [2022-11-26 00:52:47,384 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2022-11-26 00:52:47,385 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) Word has length 382 [2022-11-26 00:52:47,386 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:52:47,389 INFO L225 Difference]: With dead ends: 770 [2022-11-26 00:52:47,390 INFO L226 Difference]: Without dead ends: 765 [2022-11-26 00:52:47,396 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1237 GetRequests, 1035 SyntacticMatches, 0 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8486 ImplicationChecksByTransitivity, 8.8s TimeCoverageRelationStatistics Valid=14053, Invalid=27359, Unknown=0, NotChecked=0, Total=41412 [2022-11-26 00:52:47,397 INFO L413 NwaCegarLoop]: 107 mSDtfsCounter, 554 mSDsluCounter, 414 mSDsCounter, 0 mSdLazyCounter, 819 mSolverCounterSat, 122 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 554 SdHoareTripleChecker+Valid, 521 SdHoareTripleChecker+Invalid, 941 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 122 IncrementalHoareTripleChecker+Valid, 819 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-11-26 00:52:47,397 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [554 Valid, 521 Invalid, 941 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [122 Valid, 819 Invalid, 0 Unknown, 0 Unchecked, 0.9s Time] [2022-11-26 00:52:47,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states. [2022-11-26 00:52:47,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 765. [2022-11-26 00:52:47,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 765 states, 572 states have (on average 1.0017482517482517) internal successors, (573), 572 states have internal predecessors, (573), 97 states have call successors, (97), 96 states have call predecessors, (97), 95 states have return successors, (96), 96 states have call predecessors, (96), 96 states have call successors, (96) [2022-11-26 00:52:47,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 765 states to 765 states and 766 transitions. [2022-11-26 00:52:47,462 INFO L78 Accepts]: Start accepts. Automaton has 765 states and 766 transitions. Word has length 382 [2022-11-26 00:52:47,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:52:47,464 INFO L495 AbstractCegarLoop]: Abstraction has 765 states and 766 transitions. [2022-11-26 00:52:47,464 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-11-26 00:52:47,465 INFO L276 IsEmpty]: Start isEmpty. Operand 765 states and 766 transitions. [2022-11-26 00:52:47,487 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2022-11-26 00:52:47,487 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:52:47,488 INFO L195 NwaCegarLoop]: trace histogram [95, 95, 94, 94, 94, 94, 94, 94, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:52:47,501 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-11-26 00:52:47,701 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:47,701 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:52:47,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:52:47,702 INFO L85 PathProgramCache]: Analyzing trace with hash 1053987256, now seen corresponding path program 6 times [2022-11-26 00:52:47,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:52:47,702 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [858311605] [2022-11-26 00:52:47,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:52:47,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:52:47,740 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:52:47,740 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1449707560] [2022-11-26 00:52:47,740 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-11-26 00:52:47,740 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:52:47,741 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:52:47,742 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:52:47,768 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-11-26 00:52:49,449 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-11-26 00:52:49,449 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-11-26 00:52:49,463 INFO L263 TraceCheckSpWp]: Trace formula consists of 1571 conjuncts, 191 conjunts are in the unsatisfiable core [2022-11-26 00:52:49,482 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-11-26 00:52:54,318 INFO L134 CoverageAnalysis]: Checked inductivity of 35346 backedges. 188 proven. 35156 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-11-26 00:52:54,319 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-11-26 00:52:59,291 INFO L134 CoverageAnalysis]: Checked inductivity of 35346 backedges. 188 proven. 17672 refuted. 0 times theorem prover too weak. 17486 trivial. 0 not checked. [2022-11-26 00:52:59,291 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:52:59,291 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [858311605] [2022-11-26 00:52:59,291 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-11-26 00:52:59,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1449707560] [2022-11-26 00:52:59,292 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1449707560] provided 0 perfect and 2 imperfect interpolant sequences [2022-11-26 00:52:59,292 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1662828164] [2022-11-26 00:52:59,294 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-11-26 00:52:59,294 INFO L166 IcfgInterpreter]: Building call graph [2022-11-26 00:52:59,295 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-11-26 00:52:59,295 INFO L176 IcfgInterpreter]: Starting interpretation [2022-11-26 00:52:59,295 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-11-26 00:52:59,993 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 11 for LOIs [2022-11-26 00:52:59,997 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 70 for LOIs [2022-11-26 00:53:00,017 INFO L180 IcfgInterpreter]: Interpretation finished [2022-11-26 00:53:01,329 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '14988#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-11-26 00:53:01,329 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-11-26 00:53:01,329 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-11-26 00:53:01,329 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 98] total 104 [2022-11-26 00:53:01,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97522490] [2022-11-26 00:53:01,330 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-11-26 00:53:01,331 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 104 states [2022-11-26 00:53:01,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:53:01,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2022-11-26 00:53:01,338 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5699, Invalid=7873, Unknown=0, NotChecked=0, Total=13572 [2022-11-26 00:53:01,339 INFO L87 Difference]: Start difference. First operand 765 states and 766 transitions. Second operand has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-11-26 00:53:07,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:53:07,508 INFO L93 Difference]: Finished difference Result 818 states and 824 transitions. [2022-11-26 00:53:07,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2022-11-26 00:53:07,510 INFO L78 Accepts]: Start accepts. Automaton has has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) Word has length 766 [2022-11-26 00:53:07,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:53:07,520 INFO L225 Difference]: With dead ends: 818 [2022-11-26 00:53:07,520 INFO L226 Difference]: Without dead ends: 813 [2022-11-26 00:53:07,525 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2395 GetRequests, 2091 SyntacticMatches, 90 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12371 ImplicationChecksByTransitivity, 13.9s TimeCoverageRelationStatistics Valid=15892, Invalid=30548, Unknown=0, NotChecked=0, Total=46440 [2022-11-26 00:53:07,526 INFO L413 NwaCegarLoop]: 113 mSDtfsCounter, 32 mSDsluCounter, 433 mSDsCounter, 0 mSdLazyCounter, 762 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 546 SdHoareTripleChecker+Invalid, 766 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 762 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-11-26 00:53:07,526 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 546 Invalid, 766 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 762 Invalid, 0 Unknown, 0 Unchecked, 0.8s Time] [2022-11-26 00:53:07,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 813 states. [2022-11-26 00:53:07,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 813 to 813. [2022-11-26 00:53:07,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 813 states, 608 states have (on average 1.0016447368421053) internal successors, (609), 608 states have internal predecessors, (609), 103 states have call successors, (103), 102 states have call predecessors, (103), 101 states have return successors, (102), 102 states have call predecessors, (102), 102 states have call successors, (102) [2022-11-26 00:53:07,589 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 813 states to 813 states and 814 transitions. [2022-11-26 00:53:07,589 INFO L78 Accepts]: Start accepts. Automaton has 813 states and 814 transitions. Word has length 766 [2022-11-26 00:53:07,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:53:07,591 INFO L495 AbstractCegarLoop]: Abstraction has 813 states and 814 transitions. [2022-11-26 00:53:07,592 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-11-26 00:53:07,592 INFO L276 IsEmpty]: Start isEmpty. Operand 813 states and 814 transitions. [2022-11-26 00:53:07,615 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 815 [2022-11-26 00:53:07,615 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:53:07,615 INFO L195 NwaCegarLoop]: trace histogram [101, 101, 100, 100, 100, 100, 100, 100, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:53:07,626 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-11-26 00:53:07,825 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:53:07,826 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:53:07,826 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:53:07,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1872537714, now seen corresponding path program 7 times [2022-11-26 00:53:07,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:53:07,826 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734361270] [2022-11-26 00:53:07,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:53:07,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:53:07,866 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-11-26 00:53:07,866 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [2017395616] [2022-11-26 00:53:07,866 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-11-26 00:53:07,866 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-11-26 00:53:07,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:53:07,868 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-11-26 00:53:07,877 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-11-26 00:53:08,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-26 00:53:08,746 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-26 00:53:09,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-26 00:53:09,573 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-26 00:53:09,574 INFO L360 BasicCegarLoop]: Counterexample is feasible [2022-11-26 00:53:09,575 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-26 00:53:09,587 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-11-26 00:53:09,776 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-11-26 00:53:09,779 INFO L445 BasicCegarLoop]: Path program histogram: [7, 1, 1, 1, 1, 1, 1] [2022-11-26 00:53:09,784 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-26 00:53:10,031 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.11 12:53:10 BoogieIcfgContainer [2022-11-26 00:53:10,031 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-26 00:53:10,032 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-26 00:53:10,032 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-26 00:53:10,032 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-26 00:53:10,032 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:52:09" (3/4) ... [2022-11-26 00:53:10,034 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-26 00:53:10,237 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/witness.graphml [2022-11-26 00:53:10,237 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-26 00:53:10,238 INFO L158 Benchmark]: Toolchain (without parser) took 61624.92ms. Allocated memory was 134.2MB in the beginning and 453.0MB in the end (delta: 318.8MB). Free memory was 92.3MB in the beginning and 184.1MB in the end (delta: -91.8MB). Peak memory consumption was 228.7MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,238 INFO L158 Benchmark]: CDTParser took 0.34ms. Allocated memory is still 134.2MB. Free memory is still 78.7MB. There was no memory consumed. Max. memory is 16.1GB. [2022-11-26 00:53:10,238 INFO L158 Benchmark]: CACSL2BoogieTranslator took 281.68ms. Allocated memory is still 134.2MB. Free memory was 91.9MB in the beginning and 81.5MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,239 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.10ms. Allocated memory is still 134.2MB. Free memory was 81.5MB in the beginning and 80.1MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,239 INFO L158 Benchmark]: Boogie Preprocessor took 52.47ms. Allocated memory is still 134.2MB. Free memory was 80.1MB in the beginning and 79.0MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-26 00:53:10,239 INFO L158 Benchmark]: RCFGBuilder took 399.81ms. Allocated memory is still 134.2MB. Free memory was 79.0MB in the beginning and 67.2MB in the end (delta: 11.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,240 INFO L158 Benchmark]: TraceAbstraction took 60640.22ms. Allocated memory was 134.2MB in the beginning and 453.0MB in the end (delta: 318.8MB). Free memory was 66.4MB in the beginning and 214.5MB in the end (delta: -148.1MB). Peak memory consumption was 172.1MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,240 INFO L158 Benchmark]: Witness Printer took 205.53ms. Allocated memory is still 453.0MB. Free memory was 214.5MB in the beginning and 184.1MB in the end (delta: 30.4MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. [2022-11-26 00:53:10,245 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34ms. Allocated memory is still 134.2MB. Free memory is still 78.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 281.68ms. Allocated memory is still 134.2MB. Free memory was 91.9MB in the beginning and 81.5MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.10ms. Allocated memory is still 134.2MB. Free memory was 81.5MB in the beginning and 80.1MB in the end (delta: 1.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 52.47ms. Allocated memory is still 134.2MB. Free memory was 80.1MB in the beginning and 79.0MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 399.81ms. Allocated memory is still 134.2MB. Free memory was 79.0MB in the beginning and 67.2MB in the end (delta: 11.8MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * TraceAbstraction took 60640.22ms. Allocated memory was 134.2MB in the beginning and 453.0MB in the end (delta: 318.8MB). Free memory was 66.4MB in the beginning and 214.5MB in the end (delta: -148.1MB). Peak memory consumption was 172.1MB. Max. memory is 16.1GB. * Witness Printer took 205.53ms. Allocated memory is still 453.0MB. Free memory was 214.5MB in the beginning and 184.1MB in the end (delta: 30.4MB). Peak memory consumption was 31.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 18]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L22] int counter = 0; [L24] int x1, x2; [L25] int y1, y2, y3; [L26] x1 = __VERIFIER_nondet_int() [L27] x2 = __VERIFIER_nondet_int() [L29] CALL assume_abort_if_not(x1 >= 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) [L29] RET assume_abort_if_not(x1 >= 0) VAL [counter=0, x1=101, x2=1] [L30] CALL assume_abort_if_not(x2 != 0) VAL [\old(cond)=1, counter=0] [L13] COND FALSE !(!cond) [L30] RET assume_abort_if_not(x2 != 0) VAL [counter=0, x1=101, x2=1] [L32] y1 = 0 [L33] y2 = 0 [L34] y3 = x1 VAL [counter=0, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] EXPR counter++ VAL [counter=1, counter++=0, x1=101, x2=1, y1=0, y2=0, y3=101] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=1] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=1] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=1, x1=101, x2=1, y1=0, y2=0, y3=101] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=1, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] EXPR counter++ VAL [counter=2, counter++=1, x1=101, x2=1, y1=1, y2=0, y3=100] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=2] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=2] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=2, x1=101, x2=1, y1=1, y2=0, y3=100] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=2, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] EXPR counter++ VAL [counter=3, counter++=2, x1=101, x2=1, y1=2, y2=0, y3=99] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=3] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=3] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=3, x1=101, x2=1, y1=2, y2=0, y3=99] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=3, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] EXPR counter++ VAL [counter=4, counter++=3, x1=101, x2=1, y1=3, y2=0, y3=98] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=4] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=4] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=4, x1=101, x2=1, y1=3, y2=0, y3=98] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=4, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] EXPR counter++ VAL [counter=5, counter++=4, x1=101, x2=1, y1=4, y2=0, y3=97] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=5] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=5] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=5, x1=101, x2=1, y1=4, y2=0, y3=97] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=5, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] EXPR counter++ VAL [counter=6, counter++=5, x1=101, x2=1, y1=5, y2=0, y3=96] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=6] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=6] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=6, x1=101, x2=1, y1=5, y2=0, y3=96] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=6, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] EXPR counter++ VAL [counter=7, counter++=6, x1=101, x2=1, y1=6, y2=0, y3=95] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=7] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=7] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=7, x1=101, x2=1, y1=6, y2=0, y3=95] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=7, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] EXPR counter++ VAL [counter=8, counter++=7, x1=101, x2=1, y1=7, y2=0, y3=94] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=8] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=8] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=8, x1=101, x2=1, y1=7, y2=0, y3=94] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=8, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] EXPR counter++ VAL [counter=9, counter++=8, x1=101, x2=1, y1=8, y2=0, y3=93] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=9] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=9] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=9, x1=101, x2=1, y1=8, y2=0, y3=93] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=9, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] EXPR counter++ VAL [counter=10, counter++=9, x1=101, x2=1, y1=9, y2=0, y3=92] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=10] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=10] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=10, x1=101, x2=1, y1=9, y2=0, y3=92] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=10, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] EXPR counter++ VAL [counter=11, counter++=10, x1=101, x2=1, y1=10, y2=0, y3=91] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=11] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=11] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=11, x1=101, x2=1, y1=10, y2=0, y3=91] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=11, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] EXPR counter++ VAL [counter=12, counter++=11, x1=101, x2=1, y1=11, y2=0, y3=90] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=12] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=12] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=12, x1=101, x2=1, y1=11, y2=0, y3=90] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=12, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] EXPR counter++ VAL [counter=13, counter++=12, x1=101, x2=1, y1=12, y2=0, y3=89] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=13] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=13] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=13, x1=101, x2=1, y1=12, y2=0, y3=89] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=13, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] EXPR counter++ VAL [counter=14, counter++=13, x1=101, x2=1, y1=13, y2=0, y3=88] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=14] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=14] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=14, x1=101, x2=1, y1=13, y2=0, y3=88] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=14, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] EXPR counter++ VAL [counter=15, counter++=14, x1=101, x2=1, y1=14, y2=0, y3=87] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=15] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=15] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=15, x1=101, x2=1, y1=14, y2=0, y3=87] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=15, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] EXPR counter++ VAL [counter=16, counter++=15, x1=101, x2=1, y1=15, y2=0, y3=86] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=16] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=16] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=16, x1=101, x2=1, y1=15, y2=0, y3=86] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=16, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] EXPR counter++ VAL [counter=17, counter++=16, x1=101, x2=1, y1=16, y2=0, y3=85] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=17] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=17] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=17, x1=101, x2=1, y1=16, y2=0, y3=85] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=17, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] EXPR counter++ VAL [counter=18, counter++=17, x1=101, x2=1, y1=17, y2=0, y3=84] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=18] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=18] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=18, x1=101, x2=1, y1=17, y2=0, y3=84] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=18, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] EXPR counter++ VAL [counter=19, counter++=18, x1=101, x2=1, y1=18, y2=0, y3=83] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=19] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=19] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=19, x1=101, x2=1, y1=18, y2=0, y3=83] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=19, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] EXPR counter++ VAL [counter=20, counter++=19, x1=101, x2=1, y1=19, y2=0, y3=82] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=20] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=20] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=20, x1=101, x2=1, y1=19, y2=0, y3=82] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=20, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] EXPR counter++ VAL [counter=21, counter++=20, x1=101, x2=1, y1=20, y2=0, y3=81] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=21] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=21] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=21, x1=101, x2=1, y1=20, y2=0, y3=81] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=21, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] EXPR counter++ VAL [counter=22, counter++=21, x1=101, x2=1, y1=21, y2=0, y3=80] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=22] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=22] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=22, x1=101, x2=1, y1=21, y2=0, y3=80] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=22, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] EXPR counter++ VAL [counter=23, counter++=22, x1=101, x2=1, y1=22, y2=0, y3=79] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=23] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=23] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=23, x1=101, x2=1, y1=22, y2=0, y3=79] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=23, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] EXPR counter++ VAL [counter=24, counter++=23, x1=101, x2=1, y1=23, y2=0, y3=78] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=24] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=24] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=24, x1=101, x2=1, y1=23, y2=0, y3=78] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=24, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] EXPR counter++ VAL [counter=25, counter++=24, x1=101, x2=1, y1=24, y2=0, y3=77] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=25] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=25] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=25, x1=101, x2=1, y1=24, y2=0, y3=77] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=25, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] EXPR counter++ VAL [counter=26, counter++=25, x1=101, x2=1, y1=25, y2=0, y3=76] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=26] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=26] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=26, x1=101, x2=1, y1=25, y2=0, y3=76] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=26, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] EXPR counter++ VAL [counter=27, counter++=26, x1=101, x2=1, y1=26, y2=0, y3=75] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=27] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=27] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=27, x1=101, x2=1, y1=26, y2=0, y3=75] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=27, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] EXPR counter++ VAL [counter=28, counter++=27, x1=101, x2=1, y1=27, y2=0, y3=74] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=28] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=28] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=28, x1=101, x2=1, y1=27, y2=0, y3=74] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=28, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] EXPR counter++ VAL [counter=29, counter++=28, x1=101, x2=1, y1=28, y2=0, y3=73] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=29] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=29] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=29, x1=101, x2=1, y1=28, y2=0, y3=73] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=29, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] EXPR counter++ VAL [counter=30, counter++=29, x1=101, x2=1, y1=29, y2=0, y3=72] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=30] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=30] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=30, x1=101, x2=1, y1=29, y2=0, y3=72] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=30, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] EXPR counter++ VAL [counter=31, counter++=30, x1=101, x2=1, y1=30, y2=0, y3=71] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=31] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=31] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=31, x1=101, x2=1, y1=30, y2=0, y3=71] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=31, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] EXPR counter++ VAL [counter=32, counter++=31, x1=101, x2=1, y1=31, y2=0, y3=70] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=32] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=32] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=32, x1=101, x2=1, y1=31, y2=0, y3=70] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=32, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] EXPR counter++ VAL [counter=33, counter++=32, x1=101, x2=1, y1=32, y2=0, y3=69] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=33] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=33] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=33, x1=101, x2=1, y1=32, y2=0, y3=69] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=33, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] EXPR counter++ VAL [counter=34, counter++=33, x1=101, x2=1, y1=33, y2=0, y3=68] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=34] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=34] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=34, x1=101, x2=1, y1=33, y2=0, y3=68] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=34, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] EXPR counter++ VAL [counter=35, counter++=34, x1=101, x2=1, y1=34, y2=0, y3=67] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=35] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=35] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=35, x1=101, x2=1, y1=34, y2=0, y3=67] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=35, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] EXPR counter++ VAL [counter=36, counter++=35, x1=101, x2=1, y1=35, y2=0, y3=66] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=36] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=36] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=36, x1=101, x2=1, y1=35, y2=0, y3=66] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=36, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] EXPR counter++ VAL [counter=37, counter++=36, x1=101, x2=1, y1=36, y2=0, y3=65] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=37] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=37] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=37, x1=101, x2=1, y1=36, y2=0, y3=65] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=37, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] EXPR counter++ VAL [counter=38, counter++=37, x1=101, x2=1, y1=37, y2=0, y3=64] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=38] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=38] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=38, x1=101, x2=1, y1=37, y2=0, y3=64] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=38, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] EXPR counter++ VAL [counter=39, counter++=38, x1=101, x2=1, y1=38, y2=0, y3=63] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=39] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=39] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=39, x1=101, x2=1, y1=38, y2=0, y3=63] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=39, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] EXPR counter++ VAL [counter=40, counter++=39, x1=101, x2=1, y1=39, y2=0, y3=62] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=40] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=40] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=40, x1=101, x2=1, y1=39, y2=0, y3=62] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=40, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] EXPR counter++ VAL [counter=41, counter++=40, x1=101, x2=1, y1=40, y2=0, y3=61] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=41] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=41] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=41, x1=101, x2=1, y1=40, y2=0, y3=61] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=41, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] EXPR counter++ VAL [counter=42, counter++=41, x1=101, x2=1, y1=41, y2=0, y3=60] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=42] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=42] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=42, x1=101, x2=1, y1=41, y2=0, y3=60] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=42, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] EXPR counter++ VAL [counter=43, counter++=42, x1=101, x2=1, y1=42, y2=0, y3=59] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=43] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=43] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=43, x1=101, x2=1, y1=42, y2=0, y3=59] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=43, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] EXPR counter++ VAL [counter=44, counter++=43, x1=101, x2=1, y1=43, y2=0, y3=58] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=44] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=44] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=44, x1=101, x2=1, y1=43, y2=0, y3=58] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=44, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] EXPR counter++ VAL [counter=45, counter++=44, x1=101, x2=1, y1=44, y2=0, y3=57] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=45] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=45] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=45, x1=101, x2=1, y1=44, y2=0, y3=57] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=45, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] EXPR counter++ VAL [counter=46, counter++=45, x1=101, x2=1, y1=45, y2=0, y3=56] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=46] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=46] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=46, x1=101, x2=1, y1=45, y2=0, y3=56] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=46, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] EXPR counter++ VAL [counter=47, counter++=46, x1=101, x2=1, y1=46, y2=0, y3=55] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=47] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=47] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=47, x1=101, x2=1, y1=46, y2=0, y3=55] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=47, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] EXPR counter++ VAL [counter=48, counter++=47, x1=101, x2=1, y1=47, y2=0, y3=54] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=48] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=48] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=48, x1=101, x2=1, y1=47, y2=0, y3=54] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=48, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] EXPR counter++ VAL [counter=49, counter++=48, x1=101, x2=1, y1=48, y2=0, y3=53] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=49] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=49] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=49, x1=101, x2=1, y1=48, y2=0, y3=53] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=49, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] EXPR counter++ VAL [counter=50, counter++=49, x1=101, x2=1, y1=49, y2=0, y3=52] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=50] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=50] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=50, x1=101, x2=1, y1=49, y2=0, y3=52] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=50, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] EXPR counter++ VAL [counter=51, counter++=50, x1=101, x2=1, y1=50, y2=0, y3=51] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=51] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=51] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=51, x1=101, x2=1, y1=50, y2=0, y3=51] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=51, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] EXPR counter++ VAL [counter=52, counter++=51, x1=101, x2=1, y1=51, y2=0, y3=50] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=52] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=52] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=52, x1=101, x2=1, y1=51, y2=0, y3=50] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=52, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] EXPR counter++ VAL [counter=53, counter++=52, x1=101, x2=1, y1=52, y2=0, y3=49] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=53] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=53] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=53, x1=101, x2=1, y1=52, y2=0, y3=49] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=53, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] EXPR counter++ VAL [counter=54, counter++=53, x1=101, x2=1, y1=53, y2=0, y3=48] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=54] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=54] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=54, x1=101, x2=1, y1=53, y2=0, y3=48] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=54, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] EXPR counter++ VAL [counter=55, counter++=54, x1=101, x2=1, y1=54, y2=0, y3=47] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=55] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=55] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=55, x1=101, x2=1, y1=54, y2=0, y3=47] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=55, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] EXPR counter++ VAL [counter=56, counter++=55, x1=101, x2=1, y1=55, y2=0, y3=46] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=56] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=56] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=56, x1=101, x2=1, y1=55, y2=0, y3=46] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=56, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] EXPR counter++ VAL [counter=57, counter++=56, x1=101, x2=1, y1=56, y2=0, y3=45] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=57] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=57] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=57, x1=101, x2=1, y1=56, y2=0, y3=45] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=57, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] EXPR counter++ VAL [counter=58, counter++=57, x1=101, x2=1, y1=57, y2=0, y3=44] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=58] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=58] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=58, x1=101, x2=1, y1=57, y2=0, y3=44] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=58, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] EXPR counter++ VAL [counter=59, counter++=58, x1=101, x2=1, y1=58, y2=0, y3=43] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=59] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=59] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=59, x1=101, x2=1, y1=58, y2=0, y3=43] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=59, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] EXPR counter++ VAL [counter=60, counter++=59, x1=101, x2=1, y1=59, y2=0, y3=42] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=60] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=60] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=60, x1=101, x2=1, y1=59, y2=0, y3=42] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=60, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] EXPR counter++ VAL [counter=61, counter++=60, x1=101, x2=1, y1=60, y2=0, y3=41] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=61] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=61] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=61, x1=101, x2=1, y1=60, y2=0, y3=41] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=61, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] EXPR counter++ VAL [counter=62, counter++=61, x1=101, x2=1, y1=61, y2=0, y3=40] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=62] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=62] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=62, x1=101, x2=1, y1=61, y2=0, y3=40] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=62, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] EXPR counter++ VAL [counter=63, counter++=62, x1=101, x2=1, y1=62, y2=0, y3=39] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=63] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=63] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=63, x1=101, x2=1, y1=62, y2=0, y3=39] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=63, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] EXPR counter++ VAL [counter=64, counter++=63, x1=101, x2=1, y1=63, y2=0, y3=38] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=64] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=64] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=64, x1=101, x2=1, y1=63, y2=0, y3=38] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=64, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] EXPR counter++ VAL [counter=65, counter++=64, x1=101, x2=1, y1=64, y2=0, y3=37] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=65] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=65] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=65, x1=101, x2=1, y1=64, y2=0, y3=37] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=65, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] EXPR counter++ VAL [counter=66, counter++=65, x1=101, x2=1, y1=65, y2=0, y3=36] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=66] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=66] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=66, x1=101, x2=1, y1=65, y2=0, y3=36] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=66, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] EXPR counter++ VAL [counter=67, counter++=66, x1=101, x2=1, y1=66, y2=0, y3=35] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=67] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=67] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=67, x1=101, x2=1, y1=66, y2=0, y3=35] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=67, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] EXPR counter++ VAL [counter=68, counter++=67, x1=101, x2=1, y1=67, y2=0, y3=34] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=68] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=68] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=68, x1=101, x2=1, y1=67, y2=0, y3=34] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=68, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] EXPR counter++ VAL [counter=69, counter++=68, x1=101, x2=1, y1=68, y2=0, y3=33] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=69] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=69] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=69, x1=101, x2=1, y1=68, y2=0, y3=33] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=69, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] EXPR counter++ VAL [counter=70, counter++=69, x1=101, x2=1, y1=69, y2=0, y3=32] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=70] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=70] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=70, x1=101, x2=1, y1=69, y2=0, y3=32] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=70, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] EXPR counter++ VAL [counter=71, counter++=70, x1=101, x2=1, y1=70, y2=0, y3=31] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=71] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=71] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=71, x1=101, x2=1, y1=70, y2=0, y3=31] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=71, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] EXPR counter++ VAL [counter=72, counter++=71, x1=101, x2=1, y1=71, y2=0, y3=30] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=72] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=72] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=72, x1=101, x2=1, y1=71, y2=0, y3=30] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=72, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] EXPR counter++ VAL [counter=73, counter++=72, x1=101, x2=1, y1=72, y2=0, y3=29] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=73] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=73] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=73, x1=101, x2=1, y1=72, y2=0, y3=29] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=73, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] EXPR counter++ VAL [counter=74, counter++=73, x1=101, x2=1, y1=73, y2=0, y3=28] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=74] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=74] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=74, x1=101, x2=1, y1=73, y2=0, y3=28] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=74, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] EXPR counter++ VAL [counter=75, counter++=74, x1=101, x2=1, y1=74, y2=0, y3=27] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=75] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=75] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=75, x1=101, x2=1, y1=74, y2=0, y3=27] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=75, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] EXPR counter++ VAL [counter=76, counter++=75, x1=101, x2=1, y1=75, y2=0, y3=26] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=76] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=76] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=76, x1=101, x2=1, y1=75, y2=0, y3=26] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=76, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] EXPR counter++ VAL [counter=77, counter++=76, x1=101, x2=1, y1=76, y2=0, y3=25] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=77] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=77] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=77, x1=101, x2=1, y1=76, y2=0, y3=25] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=77, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] EXPR counter++ VAL [counter=78, counter++=77, x1=101, x2=1, y1=77, y2=0, y3=24] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=78] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=78] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=78, x1=101, x2=1, y1=77, y2=0, y3=24] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=78, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] EXPR counter++ VAL [counter=79, counter++=78, x1=101, x2=1, y1=78, y2=0, y3=23] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=79] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=79] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=79, x1=101, x2=1, y1=78, y2=0, y3=23] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=79, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] EXPR counter++ VAL [counter=80, counter++=79, x1=101, x2=1, y1=79, y2=0, y3=22] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=80] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=80] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=80, x1=101, x2=1, y1=79, y2=0, y3=22] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=80, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] EXPR counter++ VAL [counter=81, counter++=80, x1=101, x2=1, y1=80, y2=0, y3=21] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=81] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=81] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=81, x1=101, x2=1, y1=80, y2=0, y3=21] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=81, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] EXPR counter++ VAL [counter=82, counter++=81, x1=101, x2=1, y1=81, y2=0, y3=20] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=82] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=82] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=82, x1=101, x2=1, y1=81, y2=0, y3=20] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=82, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] EXPR counter++ VAL [counter=83, counter++=82, x1=101, x2=1, y1=82, y2=0, y3=19] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=83] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=83] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=83, x1=101, x2=1, y1=82, y2=0, y3=19] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=83, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] EXPR counter++ VAL [counter=84, counter++=83, x1=101, x2=1, y1=83, y2=0, y3=18] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=84] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=84] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=84, x1=101, x2=1, y1=83, y2=0, y3=18] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=84, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] EXPR counter++ VAL [counter=85, counter++=84, x1=101, x2=1, y1=84, y2=0, y3=17] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=85] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=85] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=85, x1=101, x2=1, y1=84, y2=0, y3=17] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=85, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] EXPR counter++ VAL [counter=86, counter++=85, x1=101, x2=1, y1=85, y2=0, y3=16] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=86] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=86] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=86, x1=101, x2=1, y1=85, y2=0, y3=16] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=86, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] EXPR counter++ VAL [counter=87, counter++=86, x1=101, x2=1, y1=86, y2=0, y3=15] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=87] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=87] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=87, x1=101, x2=1, y1=86, y2=0, y3=15] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=87, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] EXPR counter++ VAL [counter=88, counter++=87, x1=101, x2=1, y1=87, y2=0, y3=14] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=88] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=88] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=88, x1=101, x2=1, y1=87, y2=0, y3=14] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=88, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] EXPR counter++ VAL [counter=89, counter++=88, x1=101, x2=1, y1=88, y2=0, y3=13] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=89] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=89] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=89, x1=101, x2=1, y1=88, y2=0, y3=13] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=89, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] EXPR counter++ VAL [counter=90, counter++=89, x1=101, x2=1, y1=89, y2=0, y3=12] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=90] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=90] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=90, x1=101, x2=1, y1=89, y2=0, y3=12] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=90, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] EXPR counter++ VAL [counter=91, counter++=90, x1=101, x2=1, y1=90, y2=0, y3=11] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=91] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=91] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=91, x1=101, x2=1, y1=90, y2=0, y3=11] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=91, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] EXPR counter++ VAL [counter=92, counter++=91, x1=101, x2=1, y1=91, y2=0, y3=10] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=92] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=92] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=92, x1=101, x2=1, y1=91, y2=0, y3=10] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=92, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] EXPR counter++ VAL [counter=93, counter++=92, x1=101, x2=1, y1=92, y2=0, y3=9] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=93] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=93] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=93, x1=101, x2=1, y1=92, y2=0, y3=9] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=93, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] EXPR counter++ VAL [counter=94, counter++=93, x1=101, x2=1, y1=93, y2=0, y3=8] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=94] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=94] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=94, x1=101, x2=1, y1=93, y2=0, y3=8] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=94, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] EXPR counter++ VAL [counter=95, counter++=94, x1=101, x2=1, y1=94, y2=0, y3=7] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=95] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=95] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=95, x1=101, x2=1, y1=94, y2=0, y3=7] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=95, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] EXPR counter++ VAL [counter=96, counter++=95, x1=101, x2=1, y1=95, y2=0, y3=6] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=96] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=96] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=96, x1=101, x2=1, y1=95, y2=0, y3=6] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=96, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] EXPR counter++ VAL [counter=97, counter++=96, x1=101, x2=1, y1=96, y2=0, y3=5] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=97] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=97] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=97, x1=101, x2=1, y1=96, y2=0, y3=5] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=97, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] EXPR counter++ VAL [counter=98, counter++=97, x1=101, x2=1, y1=97, y2=0, y3=4] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=98] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=98] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=98, x1=101, x2=1, y1=97, y2=0, y3=4] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=98, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] EXPR counter++ VAL [counter=99, counter++=98, x1=101, x2=1, y1=98, y2=0, y3=3] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=99] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=99] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=99, x1=101, x2=1, y1=98, y2=0, y3=3] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=99, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] EXPR counter++ VAL [counter=100, counter++=99, x1=101, x2=1, y1=99, y2=0, y3=2] [L36] COND TRUE counter++<100 [L37] CALL __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [\old(cond)=1, counter=100] [L16] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=100] [L37] RET __VERIFIER_assert(y1*x2 + y2 + y3 == x1) VAL [counter=100, x1=101, x2=1, y1=99, y2=0, y3=2] [L39] COND FALSE !(!(y3 != 0)) [L41] COND TRUE y2 + 1 == x2 [L42] y1 = y1 + 1 [L43] y2 = 0 [L44] y3 = y3 - 1 VAL [counter=100, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] EXPR counter++ VAL [counter=101, counter++=100, x1=101, x2=1, y1=100, y2=0, y3=1] [L36] COND FALSE !(counter++<100) [L50] CALL __VERIFIER_assert(y1*x2 + y2 == x1) VAL [\old(cond)=0, counter=101] [L16] COND TRUE !(cond) VAL [\old(cond)=0, cond=0, counter=101] [L18] reach_error() VAL [\old(cond)=0, cond=0, counter=101] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 19 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 60.3s, OverallIterations: 13, TraceHistogramMax: 101, PathProgramHistogramMax: 7, EmptinessCheckTime: 0.1s, AutomataDifference: 16.3s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1022 SdHoareTripleChecker+Valid, 2.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1019 mSDsluCounter, 1982 SdHoareTripleChecker+Invalid, 2.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1545 mSDsCounter, 204 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2582 IncrementalHoareTripleChecker+Invalid, 2786 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 204 mSolverCounterUnsat, 437 mSDtfsCounter, 2582 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 5009 GetRequests, 4188 SyntacticMatches, 95 SemanticMatches, 726 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25814 ImplicationChecksByTransitivity, 34.0s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=813occurred in iteration=12, InterpolantAutomatonStates: 613, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 12 StatesRemovedByMinimization, 3 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.4s SsaConstructionTime, 3.2s SatisfiabilityAnalysisTime, 18.8s InterpolantComputationTime, 2452 NumberOfCodeBlocks, 2452 NumberOfCodeBlocksAsserted, 67 NumberOfCheckSat, 3160 ConstructedInterpolants, 0 QuantifiedInterpolants, 8122 SizeOfPredicates, 192 NumberOfNonLiveVariables, 3686 ConjunctsInSsa, 452 ConjunctsInUnsatCore, 21 InterpolantComputations, 3 PerfectInterpolantSequences, 23525/92504 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: OVERALL_TIME: 0.6s, ICFG_INTERPRETER_ENTERED_PROCEDURES: 3, DAG_INTERPRETER_EARLY_EXIT_QUERIES_NONTRIVIAL: 17, DAG_INTERPRETER_EARLY_EXITS: 1, TOOLS_POST_APPLICATIONS: 14, TOOLS_POST_TIME: 0.1s, TOOLS_POST_CALL_APPLICATIONS: 10, TOOLS_POST_CALL_TIME: 0.2s, TOOLS_POST_RETURN_APPLICATIONS: 6, TOOLS_POST_RETURN_TIME: 0.0s, TOOLS_QUANTIFIERELIM_APPLICATIONS: 30, TOOLS_QUANTIFIERELIM_TIME: 0.4s, TOOLS_QUANTIFIERELIM_MAX_TIME: 0.0s, FLUID_QUERY_TIME: 0.0s, FLUID_QUERIES: 46, FLUID_YES_ANSWERS: 0, DOMAIN_JOIN_APPLICATIONS: 10, DOMAIN_JOIN_TIME: 0.1s, DOMAIN_ALPHA_APPLICATIONS: 0, DOMAIN_ALPHA_TIME: 0.0s, DOMAIN_WIDEN_APPLICATIONS: 0, DOMAIN_WIDEN_TIME: 0.0s, DOMAIN_ISSUBSETEQ_APPLICATIONS: 0, DOMAIN_ISSUBSETEQ_TIME: 0.0s, DOMAIN_ISBOTTOM_APPLICATIONS: 17, DOMAIN_ISBOTTOM_TIME: 0.0s, LOOP_SUMMARIZER_APPLICATIONS: 0, LOOP_SUMMARIZER_CACHE_MISSES: 0, LOOP_SUMMARIZER_OVERALL_TIME: 0.0s, LOOP_SUMMARIZER_NEW_COMPUTATION_TIME: 0.0s, LOOP_SUMMARIZER_FIXPOINT_ITERATIONS: 0, CALL_SUMMARIZER_APPLICATIONS: 6, CALL_SUMMARIZER_CACHE_MISSES: 2, CALL_SUMMARIZER_OVERALL_TIME: 0.0s, CALL_SUMMARIZER_NEW_COMPUTATION_TIME: 0.0s, PROCEDURE_GRAPH_BUILDER_TIME: 0.0s, PATH_EXPR_TIME: 0.0s, REGEX_TO_DAG_TIME: 0.0s, DAG_COMPRESSION_TIME: 0.0s, DAG_COMPRESSION_PROCESSED_NODES: 138, DAG_COMPRESSION_RETAINED_NODES: 50, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-26 00:53:10,309 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_671278f5-ccaf-4361-b9c6-1df30f2de609/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE