./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 38b53e6a Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-38b53e6 [2022-11-26 00:31:07,004 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-11-26 00:31:07,006 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-11-26 00:31:07,027 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-11-26 00:31:07,027 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-11-26 00:31:07,029 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-11-26 00:31:07,030 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-11-26 00:31:07,032 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-11-26 00:31:07,034 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-11-26 00:31:07,035 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-11-26 00:31:07,036 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-11-26 00:31:07,037 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-11-26 00:31:07,037 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-11-26 00:31:07,039 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-11-26 00:31:07,040 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-11-26 00:31:07,041 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-11-26 00:31:07,042 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-11-26 00:31:07,043 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-11-26 00:31:07,045 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-11-26 00:31:07,047 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-11-26 00:31:07,049 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-11-26 00:31:07,050 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-11-26 00:31:07,051 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-11-26 00:31:07,052 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-11-26 00:31:07,056 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-11-26 00:31:07,057 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-11-26 00:31:07,057 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-11-26 00:31:07,058 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-11-26 00:31:07,059 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-11-26 00:31:07,060 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-11-26 00:31:07,060 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-11-26 00:31:07,061 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-11-26 00:31:07,062 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-11-26 00:31:07,063 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-11-26 00:31:07,064 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-11-26 00:31:07,064 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-11-26 00:31:07,065 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-11-26 00:31:07,066 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-11-26 00:31:07,066 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-11-26 00:31:07,067 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-11-26 00:31:07,068 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-11-26 00:31:07,069 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/config/svcomp-Reach-32bit-Taipan_Default.epf [2022-11-26 00:31:07,094 INFO L113 SettingsManager]: Loading preferences was successful [2022-11-26 00:31:07,095 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-11-26 00:31:07,095 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-11-26 00:31:07,095 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-11-26 00:31:07,096 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-11-26 00:31:07,096 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-11-26 00:31:07,097 INFO L138 SettingsManager]: * User list type=DISABLED [2022-11-26 00:31:07,097 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-11-26 00:31:07,097 INFO L138 SettingsManager]: * Explicit value domain=true [2022-11-26 00:31:07,097 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-11-26 00:31:07,098 INFO L138 SettingsManager]: * Octagon Domain=false [2022-11-26 00:31:07,098 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-11-26 00:31:07,098 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-11-26 00:31:07,099 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-11-26 00:31:07,099 INFO L138 SettingsManager]: * Interval Domain=false [2022-11-26 00:31:07,099 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-11-26 00:31:07,099 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-11-26 00:31:07,100 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-11-26 00:31:07,101 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-11-26 00:31:07,101 INFO L138 SettingsManager]: * sizeof long=4 [2022-11-26 00:31:07,101 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-11-26 00:31:07,101 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-11-26 00:31:07,102 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-11-26 00:31:07,102 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-11-26 00:31:07,102 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-11-26 00:31:07,102 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-11-26 00:31:07,103 INFO L138 SettingsManager]: * sizeof long double=12 [2022-11-26 00:31:07,103 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-11-26 00:31:07,103 INFO L138 SettingsManager]: * Use constant arrays=true [2022-11-26 00:31:07,103 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-11-26 00:31:07,104 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-11-26 00:31:07,104 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-11-26 00:31:07,104 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-26 00:31:07,105 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-11-26 00:31:07,105 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-11-26 00:31:07,105 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-11-26 00:31:07,105 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-11-26 00:31:07,106 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-11-26 00:31:07,106 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-11-26 00:31:07,106 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-11-26 00:31:07,106 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-11-26 00:31:07,107 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05397c7941b2acd95b1b6d02c6c64b476ab8b290a5b56301ff8db7ca1986067b [2022-11-26 00:31:07,381 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-11-26 00:31:07,410 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-11-26 00:31:07,414 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-11-26 00:31:07,415 INFO L271 PluginConnector]: Initializing CDTParser... [2022-11-26 00:31:07,416 INFO L275 PluginConnector]: CDTParser initialized [2022-11-26 00:31:07,417 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/../../sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-11-26 00:31:10,471 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-11-26 00:31:10,802 INFO L351 CDTParser]: Found 1 translation units. [2022-11-26 00:31:10,803 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/sv-benchmarks/c/systemc/transmitter.15.cil.c [2022-11-26 00:31:10,816 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/data/a0818fb0e/1037c1e6804c4b408cedf36c48df1d59/FLAGc7974ef46 [2022-11-26 00:31:10,837 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/data/a0818fb0e/1037c1e6804c4b408cedf36c48df1d59 [2022-11-26 00:31:10,845 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-11-26 00:31:10,847 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-11-26 00:31:10,853 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-11-26 00:31:10,854 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-11-26 00:31:10,857 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-11-26 00:31:10,858 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:31:10" (1/1) ... [2022-11-26 00:31:10,860 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7da89510 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:10, skipping insertion in model container [2022-11-26 00:31:10,861 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 26.11 12:31:10" (1/1) ... [2022-11-26 00:31:10,868 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-11-26 00:31:10,936 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-11-26 00:31:11,169 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-11-26 00:31:11,380 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-26 00:31:11,393 INFO L203 MainTranslator]: Completed pre-run [2022-11-26 00:31:11,405 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/sv-benchmarks/c/systemc/transmitter.15.cil.c[706,719] [2022-11-26 00:31:11,507 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-11-26 00:31:11,534 INFO L208 MainTranslator]: Completed translation [2022-11-26 00:31:11,534 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11 WrapperNode [2022-11-26 00:31:11,534 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-11-26 00:31:11,536 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-11-26 00:31:11,536 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-11-26 00:31:11,536 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-11-26 00:31:11,543 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,556 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,611 INFO L138 Inliner]: procedures = 54, calls = 69, calls flagged for inlining = 38, calls inlined = 38, statements flattened = 891 [2022-11-26 00:31:11,619 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-11-26 00:31:11,620 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-11-26 00:31:11,620 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-11-26 00:31:11,620 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-11-26 00:31:11,631 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,632 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,644 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,655 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,668 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,708 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,711 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,714 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,720 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-11-26 00:31:11,727 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-11-26 00:31:11,728 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-11-26 00:31:11,728 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-11-26 00:31:11,729 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (1/1) ... [2022-11-26 00:31:11,736 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-11-26 00:31:11,752 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/z3 [2022-11-26 00:31:11,767 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-11-26 00:31:11,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-11-26 00:31:11,815 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-11-26 00:31:11,815 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2022-11-26 00:31:11,816 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2022-11-26 00:31:11,816 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2022-11-26 00:31:11,816 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2022-11-26 00:31:11,816 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2022-11-26 00:31:11,816 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2022-11-26 00:31:11,816 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2022-11-26 00:31:11,817 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2022-11-26 00:31:11,817 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2022-11-26 00:31:11,817 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2022-11-26 00:31:11,817 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2022-11-26 00:31:11,817 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2022-11-26 00:31:11,818 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-11-26 00:31:11,818 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-11-26 00:31:11,818 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-11-26 00:31:12,017 INFO L235 CfgBuilder]: Building ICFG [2022-11-26 00:31:12,019 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-11-26 00:31:12,932 INFO L276 CfgBuilder]: Performing block encoding [2022-11-26 00:31:13,638 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-11-26 00:31:13,638 INFO L300 CfgBuilder]: Removed 17 assume(true) statements. [2022-11-26 00:31:13,642 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:31:13 BoogieIcfgContainer [2022-11-26 00:31:13,642 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-11-26 00:31:13,645 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-11-26 00:31:13,645 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-11-26 00:31:13,649 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-11-26 00:31:13,649 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 26.11 12:31:10" (1/3) ... [2022-11-26 00:31:13,651 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@72cc3edf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 12:31:13, skipping insertion in model container [2022-11-26 00:31:13,651 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 26.11 12:31:11" (2/3) ... [2022-11-26 00:31:13,652 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@72cc3edf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 26.11 12:31:13, skipping insertion in model container [2022-11-26 00:31:13,653 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:31:13" (3/3) ... [2022-11-26 00:31:13,654 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.15.cil.c [2022-11-26 00:31:13,675 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-11-26 00:31:13,675 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-11-26 00:31:13,749 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-11-26 00:31:13,757 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@371906b, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-11-26 00:31:13,757 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-11-26 00:31:13,764 INFO L276 IsEmpty]: Start isEmpty. Operand has 193 states, 159 states have (on average 1.5534591194968554) internal successors, (247), 161 states have internal predecessors, (247), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2022-11-26 00:31:13,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:13,776 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:13,777 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:13,778 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:13,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:13,785 INFO L85 PathProgramCache]: Analyzing trace with hash 1444001915, now seen corresponding path program 1 times [2022-11-26 00:31:13,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:13,796 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926101435] [2022-11-26 00:31:13,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:13,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:14,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:14,475 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:14,476 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:14,476 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926101435] [2022-11-26 00:31:14,477 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926101435] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:14,478 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:14,478 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-26 00:31:14,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972059696] [2022-11-26 00:31:14,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:14,486 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-26 00:31:14,487 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:14,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-26 00:31:14,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:14,534 INFO L87 Difference]: Start difference. First operand has 193 states, 159 states have (on average 1.5534591194968554) internal successors, (247), 161 states have internal predecessors, (247), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:15,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:15,157 INFO L93 Difference]: Finished difference Result 562 states and 901 transitions. [2022-11-26 00:31:15,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-26 00:31:15,160 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:15,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:15,173 INFO L225 Difference]: With dead ends: 562 [2022-11-26 00:31:15,173 INFO L226 Difference]: Without dead ends: 370 [2022-11-26 00:31:15,183 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:15,188 INFO L413 NwaCegarLoop]: 460 mSDtfsCounter, 516 mSDsluCounter, 366 mSDsCounter, 0 mSdLazyCounter, 302 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 516 SdHoareTripleChecker+Valid, 826 SdHoareTripleChecker+Invalid, 316 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 302 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:15,189 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [516 Valid, 826 Invalid, 316 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 302 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-11-26 00:31:15,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370 states. [2022-11-26 00:31:15,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370 to 367. [2022-11-26 00:31:15,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 367 states, 307 states have (on average 1.511400651465798) internal successors, (464), 308 states have internal predecessors, (464), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-11-26 00:31:15,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367 states to 367 states and 558 transitions. [2022-11-26 00:31:15,284 INFO L78 Accepts]: Start accepts. Automaton has 367 states and 558 transitions. Word has length 67 [2022-11-26 00:31:15,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:15,285 INFO L495 AbstractCegarLoop]: Abstraction has 367 states and 558 transitions. [2022-11-26 00:31:15,285 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:15,286 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 558 transitions. [2022-11-26 00:31:15,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:15,288 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:15,288 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:15,289 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-11-26 00:31:15,289 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:15,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:15,290 INFO L85 PathProgramCache]: Analyzing trace with hash 1684269244, now seen corresponding path program 1 times [2022-11-26 00:31:15,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:15,290 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369200834] [2022-11-26 00:31:15,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:15,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:15,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:15,667 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:15,668 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:15,668 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369200834] [2022-11-26 00:31:15,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369200834] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:15,669 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:15,669 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-26 00:31:15,669 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733871291] [2022-11-26 00:31:15,669 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:15,671 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-26 00:31:15,672 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:15,673 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-26 00:31:15,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-26 00:31:15,674 INFO L87 Difference]: Start difference. First operand 367 states and 558 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:16,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:16,586 INFO L93 Difference]: Finished difference Result 1259 states and 1939 transitions. [2022-11-26 00:31:16,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-26 00:31:16,590 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:16,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:16,598 INFO L225 Difference]: With dead ends: 1259 [2022-11-26 00:31:16,598 INFO L226 Difference]: Without dead ends: 870 [2022-11-26 00:31:16,605 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-11-26 00:31:16,608 INFO L413 NwaCegarLoop]: 493 mSDtfsCounter, 1096 mSDsluCounter, 827 mSDsCounter, 0 mSdLazyCounter, 499 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1110 SdHoareTripleChecker+Valid, 1320 SdHoareTripleChecker+Invalid, 709 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 499 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:16,609 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1110 Valid, 1320 Invalid, 709 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 499 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-26 00:31:16,613 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 870 states. [2022-11-26 00:31:16,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 870 to 858. [2022-11-26 00:31:16,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 858 states, 737 states have (on average 1.5006784260515604) internal successors, (1106), 726 states have internal predecessors, (1106), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2022-11-26 00:31:16,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 858 states to 858 states and 1304 transitions. [2022-11-26 00:31:16,700 INFO L78 Accepts]: Start accepts. Automaton has 858 states and 1304 transitions. Word has length 67 [2022-11-26 00:31:16,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:16,701 INFO L495 AbstractCegarLoop]: Abstraction has 858 states and 1304 transitions. [2022-11-26 00:31:16,701 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:16,701 INFO L276 IsEmpty]: Start isEmpty. Operand 858 states and 1304 transitions. [2022-11-26 00:31:16,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:16,703 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:16,703 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:16,703 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-11-26 00:31:16,703 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:16,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:16,704 INFO L85 PathProgramCache]: Analyzing trace with hash -416571971, now seen corresponding path program 1 times [2022-11-26 00:31:16,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:16,705 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024270526] [2022-11-26 00:31:16,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:16,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:16,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:16,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:16,886 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:16,886 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024270526] [2022-11-26 00:31:16,887 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024270526] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:16,887 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:16,887 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-26 00:31:16,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412446504] [2022-11-26 00:31:16,888 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:16,888 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-26 00:31:16,888 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:16,889 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-26 00:31:16,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-26 00:31:16,890 INFO L87 Difference]: Start difference. First operand 858 states and 1304 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:17,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:17,735 INFO L93 Difference]: Finished difference Result 3017 states and 4652 transitions. [2022-11-26 00:31:17,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-26 00:31:17,736 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:17,737 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:17,751 INFO L225 Difference]: With dead ends: 3017 [2022-11-26 00:31:17,752 INFO L226 Difference]: Without dead ends: 2113 [2022-11-26 00:31:17,758 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-11-26 00:31:17,763 INFO L413 NwaCegarLoop]: 493 mSDtfsCounter, 1096 mSDsluCounter, 802 mSDsCounter, 0 mSdLazyCounter, 495 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1110 SdHoareTripleChecker+Valid, 1295 SdHoareTripleChecker+Invalid, 705 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 495 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:17,764 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1110 Valid, 1295 Invalid, 705 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 495 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-26 00:31:17,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2113 states. [2022-11-26 00:31:17,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2113 to 1645. [2022-11-26 00:31:17,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1645 states, 1416 states have (on average 1.502824858757062) internal successors, (2128), 1406 states have internal predecessors, (2128), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2022-11-26 00:31:17,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1645 states to 1645 states and 2513 transitions. [2022-11-26 00:31:17,910 INFO L78 Accepts]: Start accepts. Automaton has 1645 states and 2513 transitions. Word has length 67 [2022-11-26 00:31:17,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:17,911 INFO L495 AbstractCegarLoop]: Abstraction has 1645 states and 2513 transitions. [2022-11-26 00:31:17,911 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:17,911 INFO L276 IsEmpty]: Start isEmpty. Operand 1645 states and 2513 transitions. [2022-11-26 00:31:17,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:17,919 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:17,919 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:17,919 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-11-26 00:31:17,920 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:17,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:17,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1016262748, now seen corresponding path program 1 times [2022-11-26 00:31:17,921 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:17,921 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368808648] [2022-11-26 00:31:17,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:17,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:17,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:18,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:18,052 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:18,052 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368808648] [2022-11-26 00:31:18,052 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368808648] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:18,052 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:18,052 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-26 00:31:18,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978607076] [2022-11-26 00:31:18,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:18,053 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-26 00:31:18,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:18,054 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-26 00:31:18,054 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:18,054 INFO L87 Difference]: Start difference. First operand 1645 states and 2513 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:18,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:18,659 INFO L93 Difference]: Finished difference Result 4896 states and 7618 transitions. [2022-11-26 00:31:18,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-26 00:31:18,660 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:18,660 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:18,681 INFO L225 Difference]: With dead ends: 4896 [2022-11-26 00:31:18,682 INFO L226 Difference]: Without dead ends: 3256 [2022-11-26 00:31:18,690 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:18,691 INFO L413 NwaCegarLoop]: 459 mSDtfsCounter, 531 mSDsluCounter, 365 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 531 SdHoareTripleChecker+Valid, 824 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:18,692 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [531 Valid, 824 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-26 00:31:18,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3256 states. [2022-11-26 00:31:18,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3256 to 3244. [2022-11-26 00:31:18,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3244 states, 2799 states have (on average 1.4948195784208647) internal successors, (4184), 2779 states have internal predecessors, (4184), 332 states have call successors, (332), 100 states have call predecessors, (332), 112 states have return successors, (411), 365 states have call predecessors, (411), 332 states have call successors, (411) [2022-11-26 00:31:18,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3244 states to 3244 states and 4927 transitions. [2022-11-26 00:31:18,912 INFO L78 Accepts]: Start accepts. Automaton has 3244 states and 4927 transitions. Word has length 67 [2022-11-26 00:31:18,912 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:18,912 INFO L495 AbstractCegarLoop]: Abstraction has 3244 states and 4927 transitions. [2022-11-26 00:31:18,912 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:18,913 INFO L276 IsEmpty]: Start isEmpty. Operand 3244 states and 4927 transitions. [2022-11-26 00:31:18,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:18,915 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:18,916 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:18,916 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-11-26 00:31:18,916 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:18,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:18,917 INFO L85 PathProgramCache]: Analyzing trace with hash -1139251653, now seen corresponding path program 1 times [2022-11-26 00:31:18,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:18,917 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886948721] [2022-11-26 00:31:18,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:18,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:18,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:19,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:19,063 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:19,063 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886948721] [2022-11-26 00:31:19,063 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886948721] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:19,063 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:19,063 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-26 00:31:19,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953218459] [2022-11-26 00:31:19,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:19,066 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-26 00:31:19,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:19,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-26 00:31:19,072 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:19,072 INFO L87 Difference]: Start difference. First operand 3244 states and 4927 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:19,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:19,791 INFO L93 Difference]: Finished difference Result 9665 states and 14945 transitions. [2022-11-26 00:31:19,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-26 00:31:19,792 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:19,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:19,825 INFO L225 Difference]: With dead ends: 9665 [2022-11-26 00:31:19,825 INFO L226 Difference]: Without dead ends: 6426 [2022-11-26 00:31:19,836 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:19,837 INFO L413 NwaCegarLoop]: 459 mSDtfsCounter, 537 mSDsluCounter, 365 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 537 SdHoareTripleChecker+Valid, 824 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:19,837 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [537 Valid, 824 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-26 00:31:19,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6426 states. [2022-11-26 00:31:20,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6426 to 6404. [2022-11-26 00:31:20,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6404 states, 5535 states have (on average 1.4863595302619692) internal successors, (8227), 5496 states have internal predecessors, (8227), 644 states have call successors, (644), 200 states have call predecessors, (644), 224 states have return successors, (796), 708 states have call predecessors, (796), 644 states have call successors, (796) [2022-11-26 00:31:20,257 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6404 states to 6404 states and 9667 transitions. [2022-11-26 00:31:20,258 INFO L78 Accepts]: Start accepts. Automaton has 6404 states and 9667 transitions. Word has length 67 [2022-11-26 00:31:20,258 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:20,258 INFO L495 AbstractCegarLoop]: Abstraction has 6404 states and 9667 transitions. [2022-11-26 00:31:20,258 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:20,259 INFO L276 IsEmpty]: Start isEmpty. Operand 6404 states and 9667 transitions. [2022-11-26 00:31:20,259 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:20,260 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:20,260 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:20,260 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-11-26 00:31:20,260 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:20,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:20,261 INFO L85 PathProgramCache]: Analyzing trace with hash 1390899034, now seen corresponding path program 1 times [2022-11-26 00:31:20,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:20,261 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1279182395] [2022-11-26 00:31:20,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:20,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:20,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:20,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:20,390 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:20,390 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1279182395] [2022-11-26 00:31:20,390 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1279182395] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:20,390 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:20,391 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-26 00:31:20,391 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1958220753] [2022-11-26 00:31:20,391 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:20,391 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-26 00:31:20,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:20,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-26 00:31:20,392 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-26 00:31:20,393 INFO L87 Difference]: Start difference. First operand 6404 states and 9667 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:21,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:21,837 INFO L93 Difference]: Finished difference Result 21857 states and 33614 transitions. [2022-11-26 00:31:21,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-26 00:31:21,838 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:21,839 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:21,953 INFO L225 Difference]: With dead ends: 21857 [2022-11-26 00:31:21,953 INFO L226 Difference]: Without dead ends: 15082 [2022-11-26 00:31:21,987 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-11-26 00:31:21,989 INFO L413 NwaCegarLoop]: 487 mSDtfsCounter, 1096 mSDsluCounter, 602 mSDsCounter, 0 mSdLazyCounter, 444 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1110 SdHoareTripleChecker+Valid, 1089 SdHoareTripleChecker+Invalid, 654 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 444 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:21,989 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1110 Valid, 1089 Invalid, 654 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 444 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-11-26 00:31:22,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15082 states. [2022-11-26 00:31:22,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15082 to 12392. [2022-11-26 00:31:22,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12392 states, 10707 states have (on average 1.4852899971980946) internal successors, (15903), 10684 states have internal predecessors, (15903), 1236 states have call successors, (1236), 392 states have call predecessors, (1236), 448 states have return successors, (1580), 1316 states have call predecessors, (1580), 1236 states have call successors, (1580) [2022-11-26 00:31:22,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12392 states to 12392 states and 18719 transitions. [2022-11-26 00:31:22,874 INFO L78 Accepts]: Start accepts. Automaton has 12392 states and 18719 transitions. Word has length 67 [2022-11-26 00:31:22,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:22,874 INFO L495 AbstractCegarLoop]: Abstraction has 12392 states and 18719 transitions. [2022-11-26 00:31:22,875 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:22,875 INFO L276 IsEmpty]: Start isEmpty. Operand 12392 states and 18719 transitions. [2022-11-26 00:31:22,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:22,876 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:22,876 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:22,876 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-11-26 00:31:22,876 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:22,877 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:22,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1333754809, now seen corresponding path program 1 times [2022-11-26 00:31:22,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:22,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412960262] [2022-11-26 00:31:22,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:22,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:22,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:23,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:23,153 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:23,154 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412960262] [2022-11-26 00:31:23,154 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412960262] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:23,154 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:23,154 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-11-26 00:31:23,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [112195371] [2022-11-26 00:31:23,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:23,155 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-11-26 00:31:23,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:23,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-11-26 00:31:23,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-11-26 00:31:23,157 INFO L87 Difference]: Start difference. First operand 12392 states and 18719 transitions. Second operand has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:25,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:25,208 INFO L93 Difference]: Finished difference Result 41661 states and 64226 transitions. [2022-11-26 00:31:25,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-11-26 00:31:25,208 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:25,209 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:25,339 INFO L225 Difference]: With dead ends: 41661 [2022-11-26 00:31:25,340 INFO L226 Difference]: Without dead ends: 28546 [2022-11-26 00:31:25,396 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-11-26 00:31:25,397 INFO L413 NwaCegarLoop]: 487 mSDtfsCounter, 1096 mSDsluCounter, 602 mSDsCounter, 0 mSdLazyCounter, 444 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1110 SdHoareTripleChecker+Valid, 1089 SdHoareTripleChecker+Invalid, 654 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 444 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:25,397 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1110 Valid, 1089 Invalid, 654 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 444 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-11-26 00:31:25,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28546 states. [2022-11-26 00:31:27,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28546 to 24208. [2022-11-26 00:31:27,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24208 states, 20923 states have (on average 1.4831047172967549) internal successors, (31031), 20932 states have internal predecessors, (31031), 2388 states have call successors, (2388), 776 states have call predecessors, (2388), 896 states have return successors, (3100), 2500 states have call predecessors, (3100), 2388 states have call successors, (3100) [2022-11-26 00:31:27,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24208 states to 24208 states and 36519 transitions. [2022-11-26 00:31:27,398 INFO L78 Accepts]: Start accepts. Automaton has 24208 states and 36519 transitions. Word has length 67 [2022-11-26 00:31:27,398 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:27,398 INFO L495 AbstractCegarLoop]: Abstraction has 24208 states and 36519 transitions. [2022-11-26 00:31:27,399 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 11.4) internal successors, (57), 5 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:27,400 INFO L276 IsEmpty]: Start isEmpty. Operand 24208 states and 36519 transitions. [2022-11-26 00:31:27,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:27,406 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:27,406 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:27,407 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-11-26 00:31:27,407 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:27,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:27,407 INFO L85 PathProgramCache]: Analyzing trace with hash -256640168, now seen corresponding path program 1 times [2022-11-26 00:31:27,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:27,408 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [204930998] [2022-11-26 00:31:27,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:27,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:27,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:27,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:27,531 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:27,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [204930998] [2022-11-26 00:31:27,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [204930998] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:27,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:27,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-11-26 00:31:27,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1245359889] [2022-11-26 00:31:27,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:27,532 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-11-26 00:31:27,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:27,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-11-26 00:31:27,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:27,534 INFO L87 Difference]: Start difference. First operand 24208 states and 36519 transitions. Second operand has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:30,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:30,111 INFO L93 Difference]: Finished difference Result 72165 states and 110840 transitions. [2022-11-26 00:31:30,112 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-11-26 00:31:30,112 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:30,113 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:30,356 INFO L225 Difference]: With dead ends: 72165 [2022-11-26 00:31:30,357 INFO L226 Difference]: Without dead ends: 47962 [2022-11-26 00:31:30,441 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-11-26 00:31:30,442 INFO L413 NwaCegarLoop]: 459 mSDtfsCounter, 552 mSDsluCounter, 365 mSDsCounter, 0 mSdLazyCounter, 304 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 552 SdHoareTripleChecker+Valid, 824 SdHoareTripleChecker+Invalid, 309 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 304 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:30,442 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [552 Valid, 824 Invalid, 309 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 304 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-11-26 00:31:30,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47962 states. [2022-11-26 00:31:32,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47962 to 47824. [2022-11-26 00:31:33,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47824 states, 41387 states have (on average 1.4730954164351124) internal successors, (60967), 41408 states have internal predecessors, (60967), 4644 states have call successors, (4644), 1552 states have call predecessors, (4644), 1792 states have return successors, (6008), 4864 states have call predecessors, (6008), 4644 states have call successors, (6008) [2022-11-26 00:31:33,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47824 states to 47824 states and 71619 transitions. [2022-11-26 00:31:33,252 INFO L78 Accepts]: Start accepts. Automaton has 47824 states and 71619 transitions. Word has length 67 [2022-11-26 00:31:33,253 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:33,253 INFO L495 AbstractCegarLoop]: Abstraction has 47824 states and 71619 transitions. [2022-11-26 00:31:33,253 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 14.25) internal successors, (57), 4 states have internal predecessors, (57), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:33,253 INFO L276 IsEmpty]: Start isEmpty. Operand 47824 states and 71619 transitions. [2022-11-26 00:31:33,254 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2022-11-26 00:31:33,254 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:33,254 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:33,255 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-11-26 00:31:33,255 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:33,255 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:33,255 INFO L85 PathProgramCache]: Analyzing trace with hash -1230129127, now seen corresponding path program 1 times [2022-11-26 00:31:33,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:33,256 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234168216] [2022-11-26 00:31:33,256 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:33,256 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:33,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-11-26 00:31:33,787 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-11-26 00:31:33,787 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-11-26 00:31:33,788 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234168216] [2022-11-26 00:31:33,788 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234168216] provided 1 perfect and 0 imperfect interpolant sequences [2022-11-26 00:31:33,788 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-11-26 00:31:33,788 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-11-26 00:31:33,789 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [855279019] [2022-11-26 00:31:33,789 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-11-26 00:31:33,790 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-11-26 00:31:33,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-11-26 00:31:33,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-11-26 00:31:33,791 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-11-26 00:31:33,791 INFO L87 Difference]: Start difference. First operand 47824 states and 71619 transitions. Second operand has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:39,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-11-26 00:31:39,786 INFO L93 Difference]: Finished difference Result 152068 states and 227817 transitions. [2022-11-26 00:31:39,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-11-26 00:31:39,786 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 67 [2022-11-26 00:31:39,787 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-11-26 00:31:40,589 INFO L225 Difference]: With dead ends: 152068 [2022-11-26 00:31:40,589 INFO L226 Difference]: Without dead ends: 104250 [2022-11-26 00:31:40,724 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2022-11-26 00:31:40,726 INFO L413 NwaCegarLoop]: 259 mSDtfsCounter, 1145 mSDsluCounter, 484 mSDsCounter, 0 mSdLazyCounter, 298 mSolverCounterSat, 157 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1152 SdHoareTripleChecker+Valid, 743 SdHoareTripleChecker+Invalid, 455 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 157 IncrementalHoareTripleChecker+Valid, 298 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-11-26 00:31:40,727 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1152 Valid, 743 Invalid, 455 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [157 Valid, 298 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-11-26 00:31:40,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104250 states. [2022-11-26 00:31:45,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104250 to 81344. [2022-11-26 00:31:46,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81344 states, 71227 states have (on average 1.4598256279219959) internal successors, (103979), 71268 states have internal predecessors, (103979), 7044 states have call successors, (7044), 2592 states have call predecessors, (7044), 3072 states have return successors, (9772), 7484 states have call predecessors, (9772), 7044 states have call successors, (9772) [2022-11-26 00:31:46,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81344 states to 81344 states and 120795 transitions. [2022-11-26 00:31:46,835 INFO L78 Accepts]: Start accepts. Automaton has 81344 states and 120795 transitions. Word has length 67 [2022-11-26 00:31:46,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-11-26 00:31:46,835 INFO L495 AbstractCegarLoop]: Abstraction has 81344 states and 120795 transitions. [2022-11-26 00:31:46,836 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 9.5) internal successors, (57), 6 states have internal predecessors, (57), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-11-26 00:31:46,836 INFO L276 IsEmpty]: Start isEmpty. Operand 81344 states and 120795 transitions. [2022-11-26 00:31:46,837 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2022-11-26 00:31:46,837 INFO L187 NwaCegarLoop]: Found error trace [2022-11-26 00:31:46,837 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:46,837 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2022-11-26 00:31:46,837 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-11-26 00:31:46,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-11-26 00:31:46,843 INFO L85 PathProgramCache]: Analyzing trace with hash 473361867, now seen corresponding path program 1 times [2022-11-26 00:31:46,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-11-26 00:31:46,847 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326260505] [2022-11-26 00:31:46,847 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-11-26 00:31:46,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-11-26 00:31:46,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-26 00:31:46,891 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-11-26 00:31:46,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-11-26 00:31:47,046 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-11-26 00:31:47,046 INFO L360 BasicCegarLoop]: Counterexample is feasible [2022-11-26 00:31:47,047 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-11-26 00:31:47,050 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-11-26 00:31:47,053 INFO L445 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-11-26 00:31:47,057 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-11-26 00:31:47,241 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 26.11 12:31:47 BoogieIcfgContainer [2022-11-26 00:31:47,242 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-11-26 00:31:47,243 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-11-26 00:31:47,243 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-11-26 00:31:47,243 INFO L275 PluginConnector]: Witness Printer initialized [2022-11-26 00:31:47,244 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 26.11 12:31:13" (3/4) ... [2022-11-26 00:31:47,246 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-11-26 00:31:47,432 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/witness.graphml [2022-11-26 00:31:47,432 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-11-26 00:31:47,433 INFO L158 Benchmark]: Toolchain (without parser) took 36585.87ms. Allocated memory was 138.4MB in the beginning and 10.5GB in the end (delta: 10.3GB). Free memory was 78.9MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 810.9MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,433 INFO L158 Benchmark]: CDTParser took 0.23ms. Allocated memory is still 138.4MB. Free memory was 112.6MB in the beginning and 112.5MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. [2022-11-26 00:31:47,434 INFO L158 Benchmark]: CACSL2BoogieTranslator took 681.51ms. Allocated memory was 138.4MB in the beginning and 203.4MB in the end (delta: 65.0MB). Free memory was 78.6MB in the beginning and 164.8MB in the end (delta: -86.2MB). Peak memory consumption was 16.3MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,434 INFO L158 Benchmark]: Boogie Procedure Inliner took 83.49ms. Allocated memory is still 203.4MB. Free memory was 163.8MB in the beginning and 160.6MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,434 INFO L158 Benchmark]: Boogie Preprocessor took 106.84ms. Allocated memory is still 203.4MB. Free memory was 160.6MB in the beginning and 156.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,435 INFO L158 Benchmark]: RCFGBuilder took 1914.82ms. Allocated memory is still 203.4MB. Free memory was 156.4MB in the beginning and 133.7MB in the end (delta: 22.7MB). Peak memory consumption was 85.6MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,436 INFO L158 Benchmark]: TraceAbstraction took 33596.97ms. Allocated memory was 203.4MB in the beginning and 10.5GB in the end (delta: 10.3GB). Free memory was 132.6MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 778.2MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,436 INFO L158 Benchmark]: Witness Printer took 189.42ms. Allocated memory is still 10.5GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 22.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-11-26 00:31:47,438 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23ms. Allocated memory is still 138.4MB. Free memory was 112.6MB in the beginning and 112.5MB in the end (delta: 146.9kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 681.51ms. Allocated memory was 138.4MB in the beginning and 203.4MB in the end (delta: 65.0MB). Free memory was 78.6MB in the beginning and 164.8MB in the end (delta: -86.2MB). Peak memory consumption was 16.3MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 83.49ms. Allocated memory is still 203.4MB. Free memory was 163.8MB in the beginning and 160.6MB in the end (delta: 3.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 106.84ms. Allocated memory is still 203.4MB. Free memory was 160.6MB in the beginning and 156.4MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1914.82ms. Allocated memory is still 203.4MB. Free memory was 156.4MB in the beginning and 133.7MB in the end (delta: 22.7MB). Peak memory consumption was 85.6MB. Max. memory is 16.1GB. * TraceAbstraction took 33596.97ms. Allocated memory was 203.4MB in the beginning and 10.5GB in the end (delta: 10.3GB). Free memory was 132.6MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 778.2MB. Max. memory is 16.1GB. * Witness Printer took 189.42ms. Allocated memory is still 10.5GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 22.0MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int m_st ; [L40] int t1_st ; [L41] int t2_st ; [L42] int t3_st ; [L43] int t4_st ; [L44] int t5_st ; [L45] int t6_st ; [L46] int t7_st ; [L47] int t8_st ; [L48] int t9_st ; [L49] int t10_st ; [L50] int t11_st ; [L51] int t12_st ; [L52] int t13_st ; [L53] int m_i ; [L54] int t1_i ; [L55] int t2_i ; [L56] int t3_i ; [L57] int t4_i ; [L58] int t5_i ; [L59] int t6_i ; [L60] int t7_i ; [L61] int t8_i ; [L62] int t9_i ; [L63] int t10_i ; [L64] int t11_i ; [L65] int t12_i ; [L66] int t13_i ; [L67] int M_E = 2; [L68] int T1_E = 2; [L69] int T2_E = 2; [L70] int T3_E = 2; [L71] int T4_E = 2; [L72] int T5_E = 2; [L73] int T6_E = 2; [L74] int T7_E = 2; [L75] int T8_E = 2; [L76] int T9_E = 2; [L77] int T10_E = 2; [L78] int T11_E = 2; [L79] int T12_E = 2; [L80] int T13_E = 2; [L81] int E_1 = 2; [L82] int E_2 = 2; [L83] int E_3 = 2; [L84] int E_4 = 2; [L85] int E_5 = 2; [L86] int E_6 = 2; [L87] int E_7 = 2; [L88] int E_8 = 2; [L89] int E_9 = 2; [L90] int E_10 = 2; [L91] int E_11 = 2; [L92] int E_12 = 2; [L93] int E_13 = 2; [L1937] int __retres1 ; [L1941] CALL init_model() [L1840] m_i = 1 [L1841] t1_i = 1 [L1842] t2_i = 1 [L1843] t3_i = 1 [L1844] t4_i = 1 [L1845] t5_i = 1 [L1846] t6_i = 1 [L1847] t7_i = 1 [L1848] t8_i = 1 [L1849] t9_i = 1 [L1850] t10_i = 1 [L1851] t11_i = 1 [L1852] t12_i = 1 [L1853] t13_i = 1 [L1941] RET init_model() [L1942] CALL start_simulation() [L1878] int kernel_st ; [L1879] int tmp ; [L1880] int tmp___0 ; [L1884] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1885] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1886] CALL init_threads() [L881] COND TRUE m_i == 1 [L882] m_st = 0 [L886] COND TRUE t1_i == 1 [L887] t1_st = 0 [L891] COND TRUE t2_i == 1 [L892] t2_st = 0 [L896] COND TRUE t3_i == 1 [L897] t3_st = 0 [L901] COND TRUE t4_i == 1 [L902] t4_st = 0 [L906] COND TRUE t5_i == 1 [L907] t5_st = 0 [L911] COND TRUE t6_i == 1 [L912] t6_st = 0 [L916] COND TRUE t7_i == 1 [L917] t7_st = 0 [L921] COND TRUE t8_i == 1 [L922] t8_st = 0 [L926] COND TRUE t9_i == 1 [L927] t9_st = 0 [L931] COND TRUE t10_i == 1 [L932] t10_st = 0 [L936] COND TRUE t11_i == 1 [L937] t11_st = 0 [L941] COND TRUE t12_i == 1 [L942] t12_st = 0 [L946] COND TRUE t13_i == 1 [L947] t13_st = 0 [L1886] RET init_threads() [L1887] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1258] COND FALSE !(M_E == 0) [L1263] COND FALSE !(T1_E == 0) [L1268] COND FALSE !(T2_E == 0) [L1273] COND FALSE !(T3_E == 0) [L1278] COND FALSE !(T4_E == 0) [L1283] COND FALSE !(T5_E == 0) [L1288] COND FALSE !(T6_E == 0) [L1293] COND FALSE !(T7_E == 0) [L1298] COND FALSE !(T8_E == 0) [L1303] COND FALSE !(T9_E == 0) [L1308] COND FALSE !(T10_E == 0) [L1313] COND FALSE !(T11_E == 0) [L1318] COND FALSE !(T12_E == 0) [L1323] COND FALSE !(T13_E == 0) [L1328] COND FALSE !(E_1 == 0) [L1333] COND FALSE !(E_2 == 0) [L1338] COND FALSE !(E_3 == 0) [L1343] COND FALSE !(E_4 == 0) [L1348] COND FALSE !(E_5 == 0) [L1353] COND FALSE !(E_6 == 0) [L1358] COND FALSE !(E_7 == 0) [L1363] COND FALSE !(E_8 == 0) [L1368] COND FALSE !(E_9 == 0) [L1373] COND FALSE !(E_10 == 0) [L1378] COND FALSE !(E_11 == 0) [L1383] COND FALSE !(E_12 == 0) [L1388] COND FALSE !(E_13 == 0) [L1887] RET fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1888] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1541] int tmp ; [L1542] int tmp___0 ; [L1543] int tmp___1 ; [L1544] int tmp___2 ; [L1545] int tmp___3 ; [L1546] int tmp___4 ; [L1547] int tmp___5 ; [L1548] int tmp___6 ; [L1549] int tmp___7 ; [L1550] int tmp___8 ; [L1551] int tmp___9 ; [L1552] int tmp___10 ; [L1553] int tmp___11 ; [L1554] int tmp___12 ; [L1558] CALL, EXPR is_master_triggered() [L604] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L607] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L617] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L619] return (__retres1); [L1558] RET, EXPR is_master_triggered() [L1558] tmp = is_master_triggered() [L1560] COND FALSE !(\read(tmp)) [L1566] CALL, EXPR is_transmit1_triggered() [L623] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L626] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L636] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L638] return (__retres1); [L1566] RET, EXPR is_transmit1_triggered() [L1566] tmp___0 = is_transmit1_triggered() [L1568] COND FALSE !(\read(tmp___0)) [L1574] CALL, EXPR is_transmit2_triggered() [L642] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L645] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L655] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L657] return (__retres1); [L1574] RET, EXPR is_transmit2_triggered() [L1574] tmp___1 = is_transmit2_triggered() [L1576] COND FALSE !(\read(tmp___1)) [L1582] CALL, EXPR is_transmit3_triggered() [L661] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L664] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L674] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L676] return (__retres1); [L1582] RET, EXPR is_transmit3_triggered() [L1582] tmp___2 = is_transmit3_triggered() [L1584] COND FALSE !(\read(tmp___2)) [L1590] CALL, EXPR is_transmit4_triggered() [L680] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L683] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L693] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L695] return (__retres1); [L1590] RET, EXPR is_transmit4_triggered() [L1590] tmp___3 = is_transmit4_triggered() [L1592] COND FALSE !(\read(tmp___3)) [L1598] CALL, EXPR is_transmit5_triggered() [L699] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L702] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L712] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L714] return (__retres1); [L1598] RET, EXPR is_transmit5_triggered() [L1598] tmp___4 = is_transmit5_triggered() [L1600] COND FALSE !(\read(tmp___4)) [L1606] CALL, EXPR is_transmit6_triggered() [L718] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L721] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L731] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L733] return (__retres1); [L1606] RET, EXPR is_transmit6_triggered() [L1606] tmp___5 = is_transmit6_triggered() [L1608] COND FALSE !(\read(tmp___5)) [L1614] CALL, EXPR is_transmit7_triggered() [L737] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L740] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L750] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L752] return (__retres1); [L1614] RET, EXPR is_transmit7_triggered() [L1614] tmp___6 = is_transmit7_triggered() [L1616] COND FALSE !(\read(tmp___6)) [L1622] CALL, EXPR is_transmit8_triggered() [L756] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L759] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L769] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L771] return (__retres1); [L1622] RET, EXPR is_transmit8_triggered() [L1622] tmp___7 = is_transmit8_triggered() [L1624] COND FALSE !(\read(tmp___7)) [L1630] CALL, EXPR is_transmit9_triggered() [L775] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L778] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L788] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L790] return (__retres1); [L1630] RET, EXPR is_transmit9_triggered() [L1630] tmp___8 = is_transmit9_triggered() [L1632] COND FALSE !(\read(tmp___8)) [L1638] CALL, EXPR is_transmit10_triggered() [L794] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L797] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L807] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L809] return (__retres1); [L1638] RET, EXPR is_transmit10_triggered() [L1638] tmp___9 = is_transmit10_triggered() [L1640] COND FALSE !(\read(tmp___9)) [L1646] CALL, EXPR is_transmit11_triggered() [L813] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L816] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L826] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L828] return (__retres1); [L1646] RET, EXPR is_transmit11_triggered() [L1646] tmp___10 = is_transmit11_triggered() [L1648] COND FALSE !(\read(tmp___10)) [L1654] CALL, EXPR is_transmit12_triggered() [L832] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L835] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L845] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L847] return (__retres1); [L1654] RET, EXPR is_transmit12_triggered() [L1654] tmp___11 = is_transmit12_triggered() [L1656] COND FALSE !(\read(tmp___11)) [L1662] CALL, EXPR is_transmit13_triggered() [L851] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L854] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L864] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L866] return (__retres1); [L1662] RET, EXPR is_transmit13_triggered() [L1662] tmp___12 = is_transmit13_triggered() [L1664] COND FALSE !(\read(tmp___12)) [L1888] RET activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1889] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1401] COND FALSE !(M_E == 1) [L1406] COND FALSE !(T1_E == 1) [L1411] COND FALSE !(T2_E == 1) [L1416] COND FALSE !(T3_E == 1) [L1421] COND FALSE !(T4_E == 1) [L1426] COND FALSE !(T5_E == 1) [L1431] COND FALSE !(T6_E == 1) [L1436] COND FALSE !(T7_E == 1) [L1441] COND FALSE !(T8_E == 1) [L1446] COND FALSE !(T9_E == 1) [L1451] COND FALSE !(T10_E == 1) [L1456] COND FALSE !(T11_E == 1) [L1461] COND FALSE !(T12_E == 1) [L1466] COND FALSE !(T13_E == 1) [L1471] COND FALSE !(E_1 == 1) [L1476] COND FALSE !(E_2 == 1) [L1481] COND FALSE !(E_3 == 1) [L1486] COND FALSE !(E_4 == 1) [L1491] COND FALSE !(E_5 == 1) [L1496] COND FALSE !(E_6 == 1) [L1501] COND FALSE !(E_7 == 1) [L1506] COND FALSE !(E_8 == 1) [L1511] COND FALSE !(E_9 == 1) [L1516] COND FALSE !(E_10 == 1) [L1521] COND FALSE !(E_11 == 1) [L1526] COND FALSE !(E_12 == 1) [L1531] COND FALSE !(E_13 == 1) [L1889] RET reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1892] COND TRUE 1 [L1895] kernel_st = 1 [L1896] CALL eval() [L1037] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1041] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1044] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L956] int __retres1 ; [L959] COND TRUE m_st == 0 [L960] __retres1 = 1 [L1032] return (__retres1); [L1044] RET, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1044] tmp = exists_runnable_thread() [L1046] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1051] COND TRUE m_st == 0 [L1052] int tmp_ndt_1; [L1053] tmp_ndt_1 = __VERIFIER_nondet_int() [L1054] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1, tmp_ndt_1=0] [L1065] COND TRUE t1_st == 0 [L1066] int tmp_ndt_2; [L1067] tmp_ndt_2 = __VERIFIER_nondet_int() [L1068] COND FALSE !(\read(tmp_ndt_2)) [L1074] CALL error() [L21] reach_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 193 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 33.3s, OverallIterations: 10, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 17.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 7728 SdHoareTripleChecker+Valid, 4.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 7665 mSDsluCounter, 8834 SdHoareTripleChecker+Invalid, 4.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4778 mSDsCounter, 1026 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3394 IncrementalHoareTripleChecker+Invalid, 4420 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1026 mSolverCounterUnsat, 4056 mSDtfsCounter, 3394 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 67 GetRequests, 30 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=81344occurred in iteration=9, InterpolantAutomatonStates: 44, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 12.7s AutomataMinimizationTime, 9 MinimizatonAttempts, 30589 StatesRemovedByMinimization, 9 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.3s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 671 NumberOfCodeBlocks, 671 NumberOfCodeBlocksAsserted, 10 NumberOfCheckSat, 594 ConstructedInterpolants, 0 QuantifiedInterpolants, 1468 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 9 InterpolantComputations, 9 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-11-26 00:31:47,480 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b93c588d-1d02-4641-bf3b-a1fe6d9d72a8/bin/utaipan-ByfvJB40ur/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE