./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/config/TaipanReach.xml -i ../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 36da946a83103a61b88f0f1db9af94484aad5eefbde5313f974f53b267bd14bf --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-14 07:50:26,359 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-14 07:50:26,361 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-14 07:50:26,381 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-14 07:50:26,381 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-14 07:50:26,382 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-14 07:50:26,384 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-14 07:50:26,386 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-14 07:50:26,387 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-14 07:50:26,388 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-14 07:50:26,389 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-14 07:50:26,390 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-14 07:50:26,390 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-14 07:50:26,391 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-14 07:50:26,393 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-14 07:50:26,393 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-14 07:50:26,394 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-14 07:50:26,395 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-14 07:50:26,397 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-14 07:50:26,399 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-14 07:50:26,400 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-14 07:50:26,402 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-14 07:50:26,403 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-14 07:50:26,404 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-14 07:50:26,407 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-14 07:50:26,408 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-14 07:50:26,408 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-14 07:50:26,409 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-14 07:50:26,409 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-14 07:50:26,411 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-14 07:50:26,411 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-14 07:50:26,412 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-14 07:50:26,413 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-14 07:50:26,413 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-14 07:50:26,414 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-14 07:50:26,414 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-14 07:50:26,415 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-14 07:50:26,415 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-14 07:50:26,416 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-14 07:50:26,416 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-14 07:50:26,417 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-14 07:50:26,418 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/config/svcomp-Reach-32bit-Taipan_Default.epf [2022-12-14 07:50:26,439 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-14 07:50:26,440 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-14 07:50:26,440 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-14 07:50:26,440 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-14 07:50:26,441 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-12-14 07:50:26,441 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-12-14 07:50:26,441 INFO L138 SettingsManager]: * User list type=DISABLED [2022-12-14 07:50:26,441 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Explicit value domain=true [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Octagon Domain=false [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-12-14 07:50:26,442 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-12-14 07:50:26,443 INFO L138 SettingsManager]: * Interval Domain=false [2022-12-14 07:50:26,443 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-12-14 07:50:26,443 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-12-14 07:50:26,443 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-12-14 07:50:26,444 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-12-14 07:50:26,444 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-12-14 07:50:26,445 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-12-14 07:50:26,445 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-14 07:50:26,445 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-14 07:50:26,445 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-14 07:50:26,445 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-12-14 07:50:26,446 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-14 07:50:26,446 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-12-14 07:50:26,446 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-12-14 07:50:26,446 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-14 07:50:26,446 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-12-14 07:50:26,446 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-12-14 07:50:26,447 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 36da946a83103a61b88f0f1db9af94484aad5eefbde5313f974f53b267bd14bf [2022-12-14 07:50:26,641 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-14 07:50:26,661 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-14 07:50:26,664 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-14 07:50:26,664 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-14 07:50:26,665 INFO L275 PluginConnector]: CDTParser initialized [2022-12-14 07:50:26,666 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/../../sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c [2022-12-14 07:50:29,213 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-14 07:50:29,379 INFO L351 CDTParser]: Found 1 translation units. [2022-12-14 07:50:29,379 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c [2022-12-14 07:50:29,385 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/data/f22997f71/bf55817315b04a2fb890a25b6c39b913/FLAG97725f634 [2022-12-14 07:50:29,799 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/data/f22997f71/bf55817315b04a2fb890a25b6c39b913 [2022-12-14 07:50:29,801 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-14 07:50:29,802 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-14 07:50:29,803 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-14 07:50:29,803 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-14 07:50:29,805 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-14 07:50:29,806 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:29,807 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4a4bfbd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29, skipping insertion in model container [2022-12-14 07:50:29,807 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:29,812 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-14 07:50:29,822 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-14 07:50:29,920 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c[524,537] [2022-12-14 07:50:29,933 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 07:50:29,941 INFO L203 MainTranslator]: Completed pre-run [2022-12-14 07:50:29,950 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/sv-benchmarks/c/nla-digbench-scaling/fermat2-ll_unwindbound100.c[524,537] [2022-12-14 07:50:29,956 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 07:50:29,967 INFO L208 MainTranslator]: Completed translation [2022-12-14 07:50:29,967 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29 WrapperNode [2022-12-14 07:50:29,967 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-14 07:50:29,968 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-14 07:50:29,968 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-14 07:50:29,968 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-14 07:50:29,974 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:29,979 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:29,992 INFO L138 Inliner]: procedures = 14, calls = 11, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 46 [2022-12-14 07:50:29,992 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-14 07:50:29,993 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-14 07:50:29,993 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-14 07:50:29,993 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-14 07:50:30,001 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,001 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,002 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,002 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,004 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,006 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,007 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,007 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,008 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-14 07:50:30,009 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-14 07:50:30,009 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-14 07:50:30,009 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-14 07:50:30,010 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (1/1) ... [2022-12-14 07:50:30,015 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-12-14 07:50:30,024 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:30,034 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-12-14 07:50:30,036 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-12-14 07:50:30,066 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-14 07:50:30,066 INFO L130 BoogieDeclarations]: Found specification of procedure assume_abort_if_not [2022-12-14 07:50:30,066 INFO L138 BoogieDeclarations]: Found implementation of procedure assume_abort_if_not [2022-12-14 07:50:30,066 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-14 07:50:30,066 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-14 07:50:30,066 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-14 07:50:30,066 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-12-14 07:50:30,066 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-12-14 07:50:30,117 INFO L235 CfgBuilder]: Building ICFG [2022-12-14 07:50:30,118 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-14 07:50:30,218 INFO L276 CfgBuilder]: Performing block encoding [2022-12-14 07:50:30,247 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-14 07:50:30,247 INFO L300 CfgBuilder]: Removed 1 assume(true) statements. [2022-12-14 07:50:30,250 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 07:50:30 BoogieIcfgContainer [2022-12-14 07:50:30,250 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-14 07:50:30,253 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-12-14 07:50:30,253 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-12-14 07:50:30,256 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-12-14 07:50:30,256 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.12 07:50:29" (1/3) ... [2022-12-14 07:50:30,257 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@45fdddca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.12 07:50:30, skipping insertion in model container [2022-12-14 07:50:30,257 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 07:50:29" (2/3) ... [2022-12-14 07:50:30,258 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@45fdddca and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.12 07:50:30, skipping insertion in model container [2022-12-14 07:50:30,258 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 07:50:30" (3/3) ... [2022-12-14 07:50:30,259 INFO L112 eAbstractionObserver]: Analyzing ICFG fermat2-ll_unwindbound100.c [2022-12-14 07:50:30,279 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-12-14 07:50:30,279 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-12-14 07:50:30,327 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-12-14 07:50:30,334 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@ec5211e, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-12-14 07:50:30,334 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-12-14 07:50:30,338 INFO L276 IsEmpty]: Start isEmpty. Operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2022-12-14 07:50:30,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-12-14 07:50:30,346 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:30,347 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:30,347 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:30,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:30,353 INFO L85 PathProgramCache]: Analyzing trace with hash -1046920148, now seen corresponding path program 1 times [2022-12-14 07:50:30,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:30,363 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1763532476] [2022-12-14 07:50:30,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:30,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:30,440 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:30,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1739014250] [2022-12-14 07:50:30,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:30,441 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:30,441 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:30,442 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:30,443 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-12-14 07:50:30,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:30,508 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 1 conjunts are in the unsatisfiable core [2022-12-14 07:50:30,513 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:30,543 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:30,543 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-14 07:50:30,544 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:30,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1763532476] [2022-12-14 07:50:30,544 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:30,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1739014250] [2022-12-14 07:50:30,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1739014250] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 07:50:30,545 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 07:50:30,545 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2022-12-14 07:50:30,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032488973] [2022-12-14 07:50:30,548 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 07:50:30,552 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 2 states [2022-12-14 07:50:30,553 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:30,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2022-12-14 07:50:30,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-14 07:50:30,584 INFO L87 Difference]: Start difference. First operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:30,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:50:30,615 INFO L93 Difference]: Finished difference Result 32 states and 43 transitions. [2022-12-14 07:50:30,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2022-12-14 07:50:30,618 INFO L78 Accepts]: Start accepts. Automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 13 [2022-12-14 07:50:30,619 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:50:30,627 INFO L225 Difference]: With dead ends: 32 [2022-12-14 07:50:30,627 INFO L226 Difference]: Without dead ends: 17 [2022-12-14 07:50:30,630 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2022-12-14 07:50:30,633 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 0 mSDsluCounter, 0 mSDsCounter, 0 mSdLazyCounter, 4 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 4 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 4 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-12-14 07:50:30,635 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 18 Invalid, 4 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 4 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-12-14 07:50:30,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-12-14 07:50:30,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-12-14 07:50:30,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 10 states have (on average 1.3) internal successors, (13), 11 states have internal predecessors, (13), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-14 07:50:30,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 20 transitions. [2022-12-14 07:50:30,671 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 20 transitions. Word has length 13 [2022-12-14 07:50:30,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:50:30,673 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 20 transitions. [2022-12-14 07:50:30,673 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:30,674 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 20 transitions. [2022-12-14 07:50:30,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-12-14 07:50:30,675 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:30,675 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:30,681 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-12-14 07:50:30,876 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 2 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable0 [2022-12-14 07:50:30,878 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:30,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:30,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1317434454, now seen corresponding path program 1 times [2022-12-14 07:50:30,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:30,883 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617480019] [2022-12-14 07:50:30,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:30,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:30,925 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:30,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1632358217] [2022-12-14 07:50:30,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:30,926 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:30,926 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:30,927 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:30,929 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-12-14 07:50:30,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:30,986 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 3 conjunts are in the unsatisfiable core [2022-12-14 07:50:30,987 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:31,039 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:31,039 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-14 07:50:31,039 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:31,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617480019] [2022-12-14 07:50:31,040 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:31,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1632358217] [2022-12-14 07:50:31,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1632358217] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 07:50:31,040 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 07:50:31,041 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-12-14 07:50:31,041 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351057751] [2022-12-14 07:50:31,041 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 07:50:31,042 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-12-14 07:50:31,042 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:31,042 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-14 07:50:31,042 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 07:50:31,043 INFO L87 Difference]: Start difference. First operand 17 states and 20 transitions. Second operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:31,061 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:50:31,062 INFO L93 Difference]: Finished difference Result 26 states and 29 transitions. [2022-12-14 07:50:31,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-14 07:50:31,062 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 14 [2022-12-14 07:50:31,063 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:50:31,063 INFO L225 Difference]: With dead ends: 26 [2022-12-14 07:50:31,063 INFO L226 Difference]: Without dead ends: 19 [2022-12-14 07:50:31,064 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 11 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 07:50:31,065 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 0 mSDsluCounter, 24 mSDsCounter, 0 mSdLazyCounter, 14 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 39 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 14 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-12-14 07:50:31,066 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 39 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 14 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-12-14 07:50:31,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2022-12-14 07:50:31,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-12-14 07:50:31,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 12 states have (on average 1.25) internal successors, (15), 13 states have internal predecessors, (15), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-14 07:50:31,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 22 transitions. [2022-12-14 07:50:31,072 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 22 transitions. Word has length 14 [2022-12-14 07:50:31,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:50:31,072 INFO L495 AbstractCegarLoop]: Abstraction has 19 states and 22 transitions. [2022-12-14 07:50:31,072 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:31,072 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 22 transitions. [2022-12-14 07:50:31,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-12-14 07:50:31,073 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:31,073 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:31,077 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2022-12-14 07:50:31,273 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1,3 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:31,275 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:31,276 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:31,277 INFO L85 PathProgramCache]: Analyzing trace with hash 1319221914, now seen corresponding path program 1 times [2022-12-14 07:50:31,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:31,278 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302422762] [2022-12-14 07:50:31,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:31,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:31,324 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:31,325 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1897466748] [2022-12-14 07:50:31,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:31,327 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:31,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:31,331 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:31,335 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-12-14 07:50:31,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:31,439 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 12 conjunts are in the unsatisfiable core [2022-12-14 07:50:31,442 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:31,545 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:31,545 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-12-14 07:50:31,545 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:31,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302422762] [2022-12-14 07:50:31,546 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:31,546 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1897466748] [2022-12-14 07:50:31,546 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1897466748] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 07:50:31,546 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 07:50:31,546 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 07:50:31,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978548771] [2022-12-14 07:50:31,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 07:50:31,547 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 07:50:31,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:31,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 07:50:31,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 07:50:31,548 INFO L87 Difference]: Start difference. First operand 19 states and 22 transitions. Second operand has 5 states, 5 states have (on average 1.6) internal successors, (8), 4 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:31,716 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:50:31,716 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-12-14 07:50:31,716 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 07:50:31,717 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 1.6) internal successors, (8), 4 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) Word has length 14 [2022-12-14 07:50:31,717 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:50:31,717 INFO L225 Difference]: With dead ends: 28 [2022-12-14 07:50:31,717 INFO L226 Difference]: Without dead ends: 26 [2022-12-14 07:50:31,718 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 10 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-12-14 07:50:31,718 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 6 mSDsluCounter, 33 mSDsCounter, 0 mSdLazyCounter, 35 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 7 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 35 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 35 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-12-14 07:50:31,719 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [7 Valid, 47 Invalid, 35 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 35 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-12-14 07:50:31,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-12-14 07:50:31,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 24. [2022-12-14 07:50:31,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 15 states have (on average 1.2) internal successors, (18), 17 states have internal predecessors, (18), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-12-14 07:50:31,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 27 transitions. [2022-12-14 07:50:31,724 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 27 transitions. Word has length 14 [2022-12-14 07:50:31,724 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:50:31,724 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 27 transitions. [2022-12-14 07:50:31,725 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 1.6) internal successors, (8), 4 states have internal predecessors, (8), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (2), 1 states have call predecessors, (2), 1 states have call successors, (2) [2022-12-14 07:50:31,725 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 27 transitions. [2022-12-14 07:50:31,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-12-14 07:50:31,725 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:31,725 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:31,730 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2022-12-14 07:50:31,926 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,4 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:31,927 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:31,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:31,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1562521278, now seen corresponding path program 1 times [2022-12-14 07:50:31,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:31,930 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919840248] [2022-12-14 07:50:31,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:31,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:31,958 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:31,959 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1795936135] [2022-12-14 07:50:31,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:31,960 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:31,960 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:31,962 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:31,964 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-12-14 07:50:32,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:32,030 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 13 conjunts are in the unsatisfiable core [2022-12-14 07:50:32,032 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:32,119 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:32,119 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:50:32,221 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:32,222 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:32,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1919840248] [2022-12-14 07:50:32,222 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:32,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1795936135] [2022-12-14 07:50:32,222 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1795936135] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:50:32,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1504684909] [2022-12-14 07:50:32,237 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:50:32,237 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:50:32,239 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:50:32,244 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:50:32,244 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:50:32,535 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 40 for LOIs [2022-12-14 07:50:32,545 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:50:32,578 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:50:37,238 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSifa [1504684909] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 07:50:37,238 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:50:37,238 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [8, 7] total 22 [2022-12-14 07:50:37,239 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29830126] [2022-12-14 07:50:37,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 07:50:37,239 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-12-14 07:50:37,240 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:37,240 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-12-14 07:50:37,241 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=386, Unknown=0, NotChecked=0, Total=462 [2022-12-14 07:50:37,241 INFO L87 Difference]: Start difference. First operand 24 states and 27 transitions. Second operand has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-14 07:50:37,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:50:37,639 INFO L93 Difference]: Finished difference Result 32 states and 35 transitions. [2022-12-14 07:50:37,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-12-14 07:50:37,640 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 20 [2022-12-14 07:50:37,640 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:50:37,640 INFO L225 Difference]: With dead ends: 32 [2022-12-14 07:50:37,640 INFO L226 Difference]: Without dead ends: 25 [2022-12-14 07:50:37,640 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 35 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 124 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=76, Invalid=386, Unknown=0, NotChecked=0, Total=462 [2022-12-14 07:50:37,641 INFO L413 NwaCegarLoop]: 9 mSDtfsCounter, 0 mSDsluCounter, 31 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 0 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 106 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-12-14 07:50:37,641 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [0 Valid, 40 Invalid, 106 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 106 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-12-14 07:50:37,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-12-14 07:50:37,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2022-12-14 07:50:37,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 16 states have (on average 1.1875) internal successors, (19), 17 states have internal predecessors, (19), 5 states have call successors, (5), 3 states have call predecessors, (5), 3 states have return successors, (4), 4 states have call predecessors, (4), 4 states have call successors, (4) [2022-12-14 07:50:37,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 28 transitions. [2022-12-14 07:50:37,647 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 28 transitions. Word has length 20 [2022-12-14 07:50:37,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:50:37,648 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 28 transitions. [2022-12-14 07:50:37,648 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 4 states have call successors, (4), 2 states have call predecessors, (4), 2 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-12-14 07:50:37,648 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 28 transitions. [2022-12-14 07:50:37,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-12-14 07:50:37,648 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:37,648 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:37,654 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2022-12-14 07:50:37,849 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3,5 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:37,850 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:37,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:37,851 INFO L85 PathProgramCache]: Analyzing trace with hash -182192907, now seen corresponding path program 1 times [2022-12-14 07:50:37,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:37,852 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091293638] [2022-12-14 07:50:37,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:37,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:37,874 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:37,874 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1067139709] [2022-12-14 07:50:37,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:37,875 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:37,876 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:37,879 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:37,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-12-14 07:50:37,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:37,926 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 5 conjunts are in the unsatisfiable core [2022-12-14 07:50:37,927 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:37,955 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:37,955 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:50:37,983 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:37,984 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:37,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091293638] [2022-12-14 07:50:37,984 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:37,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1067139709] [2022-12-14 07:50:37,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1067139709] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:50:37,984 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1472689564] [2022-12-14 07:50:37,986 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:50:37,987 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:50:37,987 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:50:37,987 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:50:37,987 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:50:38,564 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:50:38,643 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:50:38,692 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:50:39,733 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '703#(and (<= 0 |#NULL.base|) (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= |#NULL.base| 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|))' at error location [2022-12-14 07:50:39,733 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:50:39,733 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:50:39,733 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 5] total 8 [2022-12-14 07:50:39,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911067914] [2022-12-14 07:50:39,734 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:50:39,734 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-12-14 07:50:39,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:39,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-12-14 07:50:39,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=340, Unknown=0, NotChecked=0, Total=420 [2022-12-14 07:50:39,735 INFO L87 Difference]: Start difference. First operand 25 states and 28 transitions. Second operand has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-12-14 07:50:39,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:50:39,804 INFO L93 Difference]: Finished difference Result 56 states and 63 transitions. [2022-12-14 07:50:39,804 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-12-14 07:50:39,805 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) Word has length 22 [2022-12-14 07:50:39,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:50:39,806 INFO L225 Difference]: With dead ends: 56 [2022-12-14 07:50:39,806 INFO L226 Difference]: Without dead ends: 49 [2022-12-14 07:50:39,806 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 165 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=100, Invalid=452, Unknown=0, NotChecked=0, Total=552 [2022-12-14 07:50:39,807 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 19 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 64 SdHoareTripleChecker+Invalid, 34 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-12-14 07:50:39,808 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 64 Invalid, 34 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 33 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-12-14 07:50:39,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-12-14 07:50:39,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 45. [2022-12-14 07:50:39,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 30 states have (on average 1.2333333333333334) internal successors, (37), 33 states have internal predecessors, (37), 9 states have call successors, (9), 5 states have call predecessors, (9), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-14 07:50:39,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2022-12-14 07:50:39,819 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 22 [2022-12-14 07:50:39,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:50:39,819 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2022-12-14 07:50:39,819 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 3.125) internal successors, (25), 8 states have internal predecessors, (25), 5 states have call successors, (7), 4 states have call predecessors, (7), 3 states have return successors, (6), 4 states have call predecessors, (6), 4 states have call successors, (6) [2022-12-14 07:50:39,819 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2022-12-14 07:50:39,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2022-12-14 07:50:39,819 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:50:39,819 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:50:39,823 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-12-14 07:50:40,020 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,6 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:40,021 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:50:40,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:50:40,022 INFO L85 PathProgramCache]: Analyzing trace with hash -180405447, now seen corresponding path program 1 times [2022-12-14 07:50:40,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:50:40,022 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410034770] [2022-12-14 07:50:40,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:40,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:50:40,029 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:50:40,029 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1756712680] [2022-12-14 07:50:40,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:50:40,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:50:40,030 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:50:40,030 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:50:40,031 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-12-14 07:50:40,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:50:40,075 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 16 conjunts are in the unsatisfiable core [2022-12-14 07:50:40,076 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:50:46,783 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:46,784 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:50:48,888 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 1 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:50:48,888 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:50:48,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410034770] [2022-12-14 07:50:48,888 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:50:48,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1756712680] [2022-12-14 07:50:48,889 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1756712680] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:50:48,889 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1277167951] [2022-12-14 07:50:48,891 INFO L159 IcfgInterpreter]: Started Sifa with 16 locations of interest [2022-12-14 07:50:48,891 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:50:48,891 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:50:48,891 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:50:48,891 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:50:49,272 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 40 for LOIs [2022-12-14 07:50:49,301 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:50:49,333 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:50:52,923 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1001#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-12-14 07:50:52,923 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:50:52,923 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:50:52,923 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 6] total 12 [2022-12-14 07:50:52,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1133448851] [2022-12-14 07:50:52,923 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:50:52,923 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-12-14 07:50:52,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:50:52,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-12-14 07:50:52,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=519, Unknown=2, NotChecked=0, Total=600 [2022-12-14 07:50:52,924 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand has 12 states, 12 states have (on average 2.0) internal successors, (24), 10 states have internal predecessors, (24), 4 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (4), 3 states have call predecessors, (4), 2 states have call successors, (4) [2022-12-14 07:50:54,949 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=true, quantifiers [] [2022-12-14 07:50:59,453 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.32s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=true, quantifiers [] [2022-12-14 07:51:02,188 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 2.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=true, quantifiers [] [2022-12-14 07:51:02,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:51:02,194 INFO L93 Difference]: Finished difference Result 59 states and 65 transitions. [2022-12-14 07:51:02,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-12-14 07:51:02,195 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.0) internal successors, (24), 10 states have internal predecessors, (24), 4 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (4), 3 states have call predecessors, (4), 2 states have call successors, (4) Word has length 22 [2022-12-14 07:51:02,195 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:51:02,195 INFO L225 Difference]: With dead ends: 59 [2022-12-14 07:51:02,195 INFO L226 Difference]: Without dead ends: 51 [2022-12-14 07:51:02,196 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 11.8s TimeCoverageRelationStatistics Valid=100, Invalid=654, Unknown=2, NotChecked=0, Total=756 [2022-12-14 07:51:02,196 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 18 mSDsluCounter, 93 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 6 mSolverCounterUnsat, 2 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 6.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 108 SdHoareTripleChecker+Invalid, 140 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 2 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 6.2s IncrementalHoareTripleChecker+Time [2022-12-14 07:51:02,196 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 108 Invalid, 140 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 132 Invalid, 2 Unknown, 0 Unchecked, 6.2s Time] [2022-12-14 07:51:02,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2022-12-14 07:51:02,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 45. [2022-12-14 07:51:02,208 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 32 states have (on average 1.125) internal successors, (36), 32 states have internal predecessors, (36), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-14 07:51:02,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2022-12-14 07:51:02,209 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 22 [2022-12-14 07:51:02,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:51:02,209 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2022-12-14 07:51:02,209 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 2.0) internal successors, (24), 10 states have internal predecessors, (24), 4 states have call successors, (6), 3 states have call predecessors, (6), 2 states have return successors, (4), 3 states have call predecessors, (4), 2 states have call successors, (4) [2022-12-14 07:51:02,209 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2022-12-14 07:51:02,210 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-12-14 07:51:02,210 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:51:02,210 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:51:02,214 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-12-14 07:51:02,410 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 7 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable5 [2022-12-14 07:51:02,412 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:51:02,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:51:02,413 INFO L85 PathProgramCache]: Analyzing trace with hash 408559265, now seen corresponding path program 1 times [2022-12-14 07:51:02,413 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:51:02,413 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711239273] [2022-12-14 07:51:02,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:02,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:51:02,431 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:51:02,432 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1926063638] [2022-12-14 07:51:02,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:02,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:02,433 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:51:02,435 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:51:02,438 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-12-14 07:51:02,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:51:02,490 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 13 conjunts are in the unsatisfiable core [2022-12-14 07:51:02,491 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:51:02,530 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 7 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-12-14 07:51:02,530 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:51:02,595 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 7 proven. 1 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-12-14 07:51:02,595 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:51:02,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1711239273] [2022-12-14 07:51:02,595 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:51:02,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1926063638] [2022-12-14 07:51:02,595 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1926063638] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:51:02,595 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1709562742] [2022-12-14 07:51:02,597 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:51:02,597 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:51:02,598 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:51:02,598 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:51:02,598 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:51:03,011 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 70 for LOIs [2022-12-14 07:51:03,079 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:51:03,107 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:51:09,437 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1338#(and (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-12-14 07:51:09,437 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:51:09,437 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:51:09,437 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7] total 11 [2022-12-14 07:51:09,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1795194536] [2022-12-14 07:51:09,437 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:51:09,438 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-12-14 07:51:09,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:51:09,438 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-12-14 07:51:09,439 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=86, Invalid=514, Unknown=0, NotChecked=0, Total=600 [2022-12-14 07:51:09,439 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand has 11 states, 10 states have (on average 2.1) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 3 states have call predecessors, (5), 1 states have call successors, (5) [2022-12-14 07:51:09,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:51:09,561 INFO L93 Difference]: Finished difference Result 50 states and 53 transitions. [2022-12-14 07:51:09,561 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-12-14 07:51:09,561 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 10 states have (on average 2.1) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 3 states have call predecessors, (5), 1 states have call successors, (5) Word has length 28 [2022-12-14 07:51:09,561 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:51:09,562 INFO L225 Difference]: With dead ends: 50 [2022-12-14 07:51:09,562 INFO L226 Difference]: Without dead ends: 45 [2022-12-14 07:51:09,563 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 6.4s TimeCoverageRelationStatistics Valid=101, Invalid=601, Unknown=0, NotChecked=0, Total=702 [2022-12-14 07:51:09,563 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 20 mSDsluCounter, 26 mSDsCounter, 0 mSdLazyCounter, 41 mSolverCounterSat, 6 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 47 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 6 IncrementalHoareTripleChecker+Valid, 41 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-12-14 07:51:09,564 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 38 Invalid, 47 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [6 Valid, 41 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-12-14 07:51:09,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2022-12-14 07:51:09,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2022-12-14 07:51:09,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 32 states have (on average 1.03125) internal successors, (33), 32 states have internal predecessors, (33), 7 states have call successors, (7), 6 states have call predecessors, (7), 5 states have return successors, (6), 6 states have call predecessors, (6), 6 states have call successors, (6) [2022-12-14 07:51:09,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 46 transitions. [2022-12-14 07:51:09,573 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 46 transitions. Word has length 28 [2022-12-14 07:51:09,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:51:09,573 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 46 transitions. [2022-12-14 07:51:09,573 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 10 states have (on average 2.1) internal successors, (21), 8 states have internal predecessors, (21), 2 states have call successors, (5), 3 states have call predecessors, (5), 2 states have return successors, (5), 3 states have call predecessors, (5), 1 states have call successors, (5) [2022-12-14 07:51:09,573 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 46 transitions. [2022-12-14 07:51:09,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-12-14 07:51:09,574 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:51:09,574 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:51:09,578 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2022-12-14 07:51:09,774 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 8 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable6 [2022-12-14 07:51:09,775 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:51:09,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:51:09,777 INFO L85 PathProgramCache]: Analyzing trace with hash -235004718, now seen corresponding path program 2 times [2022-12-14 07:51:09,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:51:09,777 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029635532] [2022-12-14 07:51:09,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:09,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:51:09,799 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:51:09,799 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [862465490] [2022-12-14 07:51:09,799 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-12-14 07:51:09,800 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:09,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:51:09,803 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:51:09,806 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-12-14 07:51:09,901 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-12-14 07:51:09,901 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-12-14 07:51:09,902 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 11 conjunts are in the unsatisfiable core [2022-12-14 07:51:09,904 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:51:09,950 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 8 proven. 56 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:51:09,950 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:51:10,008 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 8 proven. 32 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2022-12-14 07:51:10,008 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:51:10,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029635532] [2022-12-14 07:51:10,008 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:51:10,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [862465490] [2022-12-14 07:51:10,008 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [862465490] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:51:10,008 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1107120510] [2022-12-14 07:51:10,010 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:51:10,010 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:51:10,011 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:51:10,011 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:51:10,011 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:51:10,408 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:51:10,459 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:51:10,478 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:51:12,294 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '1773#(and (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-12-14 07:51:12,294 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:51:12,294 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:51:12,294 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 14 [2022-12-14 07:51:12,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [942819392] [2022-12-14 07:51:12,294 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:51:12,295 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-12-14 07:51:12,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:51:12,296 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-12-14 07:51:12,296 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=161, Invalid=541, Unknown=0, NotChecked=0, Total=702 [2022-12-14 07:51:12,296 INFO L87 Difference]: Start difference. First operand 45 states and 46 transitions. Second operand has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-12-14 07:51:12,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:51:12,438 INFO L93 Difference]: Finished difference Result 98 states and 104 transitions. [2022-12-14 07:51:12,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2022-12-14 07:51:12,439 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) Word has length 46 [2022-12-14 07:51:12,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:51:12,439 INFO L225 Difference]: With dead ends: 98 [2022-12-14 07:51:12,440 INFO L226 Difference]: Without dead ends: 93 [2022-12-14 07:51:12,440 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 405 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=274, Invalid=986, Unknown=0, NotChecked=0, Total=1260 [2022-12-14 07:51:12,440 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 35 mSDsluCounter, 68 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 91 SdHoareTripleChecker+Invalid, 73 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-12-14 07:51:12,441 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [35 Valid, 91 Invalid, 73 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 68 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-12-14 07:51:12,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2022-12-14 07:51:12,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2022-12-14 07:51:12,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 68 states have (on average 1.0147058823529411) internal successors, (69), 68 states have internal predecessors, (69), 13 states have call successors, (13), 12 states have call predecessors, (13), 11 states have return successors, (12), 12 states have call predecessors, (12), 12 states have call successors, (12) [2022-12-14 07:51:12,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 94 transitions. [2022-12-14 07:51:12,452 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 94 transitions. Word has length 46 [2022-12-14 07:51:12,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:51:12,452 INFO L495 AbstractCegarLoop]: Abstraction has 93 states and 94 transitions. [2022-12-14 07:51:12,452 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 3.7142857142857144) internal successors, (52), 14 states have internal predecessors, (52), 11 states have call successors, (13), 7 states have call predecessors, (13), 6 states have return successors, (12), 10 states have call predecessors, (12), 10 states have call successors, (12) [2022-12-14 07:51:12,452 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 94 transitions. [2022-12-14 07:51:12,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2022-12-14 07:51:12,454 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:51:12,454 INFO L195 NwaCegarLoop]: trace histogram [11, 11, 10, 10, 10, 10, 10, 10, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:51:12,458 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-12-14 07:51:12,654 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,9 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:12,655 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:51:12,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:51:12,656 INFO L85 PathProgramCache]: Analyzing trace with hash -1419782260, now seen corresponding path program 3 times [2022-12-14 07:51:12,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:51:12,657 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446863209] [2022-12-14 07:51:12,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:12,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:51:12,683 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:51:12,684 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [901260843] [2022-12-14 07:51:12,684 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-12-14 07:51:12,684 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:12,685 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:51:12,687 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:51:12,688 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-12-14 07:51:13,082 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-12-14 07:51:13,082 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-12-14 07:51:13,083 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 23 conjunts are in the unsatisfiable core [2022-12-14 07:51:13,085 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:51:13,190 INFO L134 CoverageAnalysis]: Checked inductivity of 402 backedges. 20 proven. 380 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:51:13,191 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:51:13,358 INFO L134 CoverageAnalysis]: Checked inductivity of 402 backedges. 20 proven. 200 refuted. 0 times theorem prover too weak. 182 trivial. 0 not checked. [2022-12-14 07:51:13,358 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:51:13,358 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446863209] [2022-12-14 07:51:13,358 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:51:13,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [901260843] [2022-12-14 07:51:13,359 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [901260843] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:51:13,359 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1390817112] [2022-12-14 07:51:13,361 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:51:13,361 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:51:13,361 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:51:13,361 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:51:13,361 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:51:13,723 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:51:13,783 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:51:13,805 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:51:15,145 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '2653#(and (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (= |#NULL.offset| 0) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-12-14 07:51:15,146 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:51:15,146 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:51:15,146 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 14] total 26 [2022-12-14 07:51:15,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840150499] [2022-12-14 07:51:15,146 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:51:15,147 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-12-14 07:51:15,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:51:15,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-12-14 07:51:15,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=431, Invalid=1051, Unknown=0, NotChecked=0, Total=1482 [2022-12-14 07:51:15,148 INFO L87 Difference]: Start difference. First operand 93 states and 94 transitions. Second operand has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-12-14 07:51:15,515 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:51:15,515 INFO L93 Difference]: Finished difference Result 194 states and 206 transitions. [2022-12-14 07:51:15,515 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2022-12-14 07:51:15,515 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) Word has length 94 [2022-12-14 07:51:15,516 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:51:15,517 INFO L225 Difference]: With dead ends: 194 [2022-12-14 07:51:15,517 INFO L226 Difference]: Without dead ends: 189 [2022-12-14 07:51:15,518 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 301 GetRequests, 243 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1020 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=946, Invalid=2594, Unknown=0, NotChecked=0, Total=3540 [2022-12-14 07:51:15,519 INFO L413 NwaCegarLoop]: 35 mSDtfsCounter, 107 mSDsluCounter, 145 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 107 SdHoareTripleChecker+Valid, 180 SdHoareTripleChecker+Invalid, 175 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-12-14 07:51:15,519 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [107 Valid, 180 Invalid, 175 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [21 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-12-14 07:51:15,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2022-12-14 07:51:15,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2022-12-14 07:51:15,542 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 189 states, 140 states have (on average 1.0071428571428571) internal successors, (141), 140 states have internal predecessors, (141), 25 states have call successors, (25), 24 states have call predecessors, (25), 23 states have return successors, (24), 24 states have call predecessors, (24), 24 states have call successors, (24) [2022-12-14 07:51:15,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 190 transitions. [2022-12-14 07:51:15,544 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 190 transitions. Word has length 94 [2022-12-14 07:51:15,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:51:15,545 INFO L495 AbstractCegarLoop]: Abstraction has 189 states and 190 transitions. [2022-12-14 07:51:15,545 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 4.076923076923077) internal successors, (106), 26 states have internal predecessors, (106), 23 states have call successors, (25), 13 states have call predecessors, (25), 12 states have return successors, (24), 22 states have call predecessors, (24), 22 states have call successors, (24) [2022-12-14 07:51:15,545 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 190 transitions. [2022-12-14 07:51:15,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 191 [2022-12-14 07:51:15,548 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:51:15,548 INFO L195 NwaCegarLoop]: trace histogram [23, 23, 22, 22, 22, 22, 22, 22, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:51:15,553 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2022-12-14 07:51:15,749 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,10 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:15,750 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:51:15,751 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:51:15,751 INFO L85 PathProgramCache]: Analyzing trace with hash -1763378944, now seen corresponding path program 4 times [2022-12-14 07:51:15,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:51:15,752 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267694367] [2022-12-14 07:51:15,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:15,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:51:15,792 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:51:15,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1683225779] [2022-12-14 07:51:15,793 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-12-14 07:51:15,793 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:15,793 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:51:15,794 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:51:15,796 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-12-14 07:51:15,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 07:51:15,875 INFO L263 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 47 conjunts are in the unsatisfiable core [2022-12-14 07:51:15,878 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:51:16,200 INFO L134 CoverageAnalysis]: Checked inductivity of 1938 backedges. 44 proven. 1892 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:51:16,200 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:51:16,755 INFO L134 CoverageAnalysis]: Checked inductivity of 1938 backedges. 44 proven. 968 refuted. 0 times theorem prover too weak. 926 trivial. 0 not checked. [2022-12-14 07:51:16,755 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:51:16,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267694367] [2022-12-14 07:51:16,755 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:51:16,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1683225779] [2022-12-14 07:51:16,755 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1683225779] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:51:16,755 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1546501068] [2022-12-14 07:51:16,757 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:51:16,757 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:51:16,757 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:51:16,758 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:51:16,758 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:51:17,128 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:51:17,178 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:51:17,196 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:51:18,953 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '4421#(and (<= 0 |#NULL.base|) (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= |#NULL.base| 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|))' at error location [2022-12-14 07:51:18,953 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:51:18,953 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:51:18,953 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 26] total 50 [2022-12-14 07:51:18,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061845918] [2022-12-14 07:51:18,953 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:51:18,954 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-12-14 07:51:18,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:51:18,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-12-14 07:51:18,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1403, Invalid=2503, Unknown=0, NotChecked=0, Total=3906 [2022-12-14 07:51:18,956 INFO L87 Difference]: Start difference. First operand 189 states and 190 transitions. Second operand has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-12-14 07:51:20,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:51:20,375 INFO L93 Difference]: Finished difference Result 386 states and 410 transitions. [2022-12-14 07:51:20,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2022-12-14 07:51:20,376 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) Word has length 190 [2022-12-14 07:51:20,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:51:20,377 INFO L225 Difference]: With dead ends: 386 [2022-12-14 07:51:20,377 INFO L226 Difference]: Without dead ends: 381 [2022-12-14 07:51:20,379 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 613 GetRequests, 507 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2790 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=3586, Invalid=7970, Unknown=0, NotChecked=0, Total=11556 [2022-12-14 07:51:20,379 INFO L413 NwaCegarLoop]: 59 mSDtfsCounter, 173 mSDsluCounter, 290 mSDsCounter, 0 mSdLazyCounter, 356 mSolverCounterSat, 27 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 173 SdHoareTripleChecker+Valid, 349 SdHoareTripleChecker+Invalid, 383 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 27 IncrementalHoareTripleChecker+Valid, 356 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-12-14 07:51:20,380 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [173 Valid, 349 Invalid, 383 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [27 Valid, 356 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-12-14 07:51:20,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 381 states. [2022-12-14 07:51:20,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 381 to 381. [2022-12-14 07:51:20,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 284 states have (on average 1.0035211267605635) internal successors, (285), 284 states have internal predecessors, (285), 49 states have call successors, (49), 48 states have call predecessors, (49), 47 states have return successors, (48), 48 states have call predecessors, (48), 48 states have call successors, (48) [2022-12-14 07:51:20,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 382 transitions. [2022-12-14 07:51:20,407 INFO L78 Accepts]: Start accepts. Automaton has 381 states and 382 transitions. Word has length 190 [2022-12-14 07:51:20,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:51:20,407 INFO L495 AbstractCegarLoop]: Abstraction has 381 states and 382 transitions. [2022-12-14 07:51:20,407 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 4.28) internal successors, (214), 50 states have internal predecessors, (214), 47 states have call successors, (49), 25 states have call predecessors, (49), 24 states have return successors, (48), 46 states have call predecessors, (48), 46 states have call successors, (48) [2022-12-14 07:51:20,407 INFO L276 IsEmpty]: Start isEmpty. Operand 381 states and 382 transitions. [2022-12-14 07:51:20,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 383 [2022-12-14 07:51:20,412 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:51:20,412 INFO L195 NwaCegarLoop]: trace histogram [47, 47, 46, 46, 46, 46, 46, 46, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:51:20,417 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2022-12-14 07:51:20,612 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-12-14 07:51:20,614 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:51:20,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:51:20,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1767238632, now seen corresponding path program 5 times [2022-12-14 07:51:20,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:51:20,616 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269566280] [2022-12-14 07:51:20,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:51:20,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:51:20,662 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:51:20,662 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [207956135] [2022-12-14 07:51:20,662 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-12-14 07:51:20,663 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:51:20,663 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:51:20,664 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:51:20,665 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-12-14 07:56:58,026 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 47 check-sat command(s) [2022-12-14 07:56:58,026 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-12-14 07:56:58,099 INFO L263 TraceCheckSpWp]: Trace formula consists of 803 conjuncts, 95 conjunts are in the unsatisfiable core [2022-12-14 07:56:58,108 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:56:59,026 INFO L134 CoverageAnalysis]: Checked inductivity of 8466 backedges. 92 proven. 8372 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:56:59,027 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:57:01,108 INFO L134 CoverageAnalysis]: Checked inductivity of 8466 backedges. 92 proven. 4232 refuted. 0 times theorem prover too weak. 4142 trivial. 0 not checked. [2022-12-14 07:57:01,109 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:57:01,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269566280] [2022-12-14 07:57:01,109 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:57:01,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [207956135] [2022-12-14 07:57:01,109 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [207956135] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:57:01,109 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1253175677] [2022-12-14 07:57:01,110 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:57:01,110 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:57:01,110 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:57:01,110 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:57:01,110 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:57:01,581 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:57:01,639 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:57:01,662 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:57:03,290 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '7965#(and (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|) (= |#NULL.base| 0))' at error location [2022-12-14 07:57:03,290 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:57:03,290 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:57:03,290 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 50] total 98 [2022-12-14 07:57:03,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567654745] [2022-12-14 07:57:03,291 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:57:03,291 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-12-14 07:57:03,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:57:03,293 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-12-14 07:57:03,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5075, Invalid=7135, Unknown=0, NotChecked=0, Total=12210 [2022-12-14 07:57:03,295 INFO L87 Difference]: Start difference. First operand 381 states and 382 transitions. Second operand has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-12-14 07:57:07,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:57:07,565 INFO L93 Difference]: Finished difference Result 770 states and 818 transitions. [2022-12-14 07:57:07,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 190 states. [2022-12-14 07:57:07,565 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) Word has length 382 [2022-12-14 07:57:07,566 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:57:07,573 INFO L225 Difference]: With dead ends: 770 [2022-12-14 07:57:07,574 INFO L226 Difference]: Without dead ends: 765 [2022-12-14 07:57:07,578 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 1237 GetRequests, 1035 SyntacticMatches, 0 SemanticMatches, 202 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8490 ImplicationChecksByTransitivity, 6.6s TimeCoverageRelationStatistics Valid=14050, Invalid=27362, Unknown=0, NotChecked=0, Total=41412 [2022-12-14 07:57:07,579 INFO L413 NwaCegarLoop]: 107 mSDtfsCounter, 608 mSDsluCounter, 515 mSDsCounter, 0 mSdLazyCounter, 762 mSolverCounterSat, 140 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 608 SdHoareTripleChecker+Valid, 622 SdHoareTripleChecker+Invalid, 902 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 140 IncrementalHoareTripleChecker+Valid, 762 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-12-14 07:57:07,579 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [608 Valid, 622 Invalid, 902 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [140 Valid, 762 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-12-14 07:57:07,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 765 states. [2022-12-14 07:57:07,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 765 to 765. [2022-12-14 07:57:07,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 765 states, 572 states have (on average 1.0017482517482517) internal successors, (573), 572 states have internal predecessors, (573), 97 states have call successors, (97), 96 states have call predecessors, (97), 95 states have return successors, (96), 96 states have call predecessors, (96), 96 states have call successors, (96) [2022-12-14 07:57:07,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 765 states to 765 states and 766 transitions. [2022-12-14 07:57:07,622 INFO L78 Accepts]: Start accepts. Automaton has 765 states and 766 transitions. Word has length 382 [2022-12-14 07:57:07,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:57:07,622 INFO L495 AbstractCegarLoop]: Abstraction has 765 states and 766 transitions. [2022-12-14 07:57:07,623 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 98 states, 98 states have (on average 4.387755102040816) internal successors, (430), 98 states have internal predecessors, (430), 95 states have call successors, (97), 49 states have call predecessors, (97), 48 states have return successors, (96), 94 states have call predecessors, (96), 94 states have call successors, (96) [2022-12-14 07:57:07,623 INFO L276 IsEmpty]: Start isEmpty. Operand 765 states and 766 transitions. [2022-12-14 07:57:07,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 767 [2022-12-14 07:57:07,637 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:57:07,637 INFO L195 NwaCegarLoop]: trace histogram [95, 95, 94, 94, 94, 94, 94, 94, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:57:07,662 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Ended with exit code 0 [2022-12-14 07:57:07,838 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-12-14 07:57:07,838 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:57:07,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:57:07,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1053987256, now seen corresponding path program 6 times [2022-12-14 07:57:07,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:57:07,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099676183] [2022-12-14 07:57:07,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:57:07,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:57:07,902 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:57:07,902 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [1427810998] [2022-12-14 07:57:07,902 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-12-14 07:57:07,903 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:57:07,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:57:07,903 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:57:07,904 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-12-14 07:58:23,572 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-12-14 07:58:23,572 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-12-14 07:58:23,594 INFO L263 TraceCheckSpWp]: Trace formula consists of 1571 conjuncts, 191 conjunts are in the unsatisfiable core [2022-12-14 07:58:23,610 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-12-14 07:58:26,581 INFO L134 CoverageAnalysis]: Checked inductivity of 35346 backedges. 188 proven. 35156 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-12-14 07:58:26,581 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-12-14 07:58:29,703 INFO L134 CoverageAnalysis]: Checked inductivity of 35346 backedges. 188 proven. 17672 refuted. 0 times theorem prover too weak. 17486 trivial. 0 not checked. [2022-12-14 07:58:29,703 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 07:58:29,703 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099676183] [2022-12-14 07:58:29,703 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: SMT_SOLVER_CANNOT_INTERPOLATE_INPUT [2022-12-14 07:58:29,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1427810998] [2022-12-14 07:58:29,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1427810998] provided 0 perfect and 2 imperfect interpolant sequences [2022-12-14 07:58:29,704 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSifa [1874357116] [2022-12-14 07:58:29,706 INFO L159 IcfgInterpreter]: Started Sifa with 17 locations of interest [2022-12-14 07:58:29,706 INFO L166 IcfgInterpreter]: Building call graph [2022-12-14 07:58:29,706 INFO L171 IcfgInterpreter]: Initial procedures are [ULTIMATE.start] [2022-12-14 07:58:29,706 INFO L176 IcfgInterpreter]: Starting interpretation [2022-12-14 07:58:29,707 INFO L197 IcfgInterpreter]: Interpreting procedure ULTIMATE.start with input of size 1 for LOIs [2022-12-14 07:58:30,086 INFO L197 IcfgInterpreter]: Interpreting procedure __VERIFIER_assert with input of size 68 for LOIs [2022-12-14 07:58:30,138 INFO L197 IcfgInterpreter]: Interpreting procedure assume_abort_if_not with input of size 97 for LOIs [2022-12-14 07:58:30,161 INFO L180 IcfgInterpreter]: Interpretation finished [2022-12-14 07:58:32,473 INFO L133 SifaRunner]: Sifa could not show that error location is unreachable, found '14971#(and (<= 0 |#NULL.base|) (<= |#NULL.offset| 0) (= |__VERIFIER_assert_#in~cond| __VERIFIER_assert_~cond) (<= 1 ~counter~0) (= __VERIFIER_assert_~cond 0) (<= |#NULL.base| 0) (<= 0 |#NULL.offset|) (<= 0 |#StackHeapBarrier|))' at error location [2022-12-14 07:58:32,473 WARN L310 FreeRefinementEngine]: Interpolation failed due to KNOWN_IGNORE: ALGORITHM_FAILED [2022-12-14 07:58:32,473 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-12-14 07:58:32,474 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 98] total 104 [2022-12-14 07:58:32,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1790754944] [2022-12-14 07:58:32,474 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-12-14 07:58:32,475 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 104 states [2022-12-14 07:58:32,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 07:58:32,477 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2022-12-14 07:58:32,478 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5696, Invalid=7876, Unknown=0, NotChecked=0, Total=13572 [2022-12-14 07:58:32,478 INFO L87 Difference]: Start difference. First operand 765 states and 766 transitions. Second operand has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-12-14 07:58:36,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 07:58:36,823 INFO L93 Difference]: Finished difference Result 818 states and 824 transitions. [2022-12-14 07:58:36,823 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 202 states. [2022-12-14 07:58:36,824 INFO L78 Accepts]: Start accepts. Automaton has has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) Word has length 766 [2022-12-14 07:58:36,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 07:58:36,826 INFO L225 Difference]: With dead ends: 818 [2022-12-14 07:58:36,826 INFO L226 Difference]: Without dead ends: 813 [2022-12-14 07:58:36,830 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 2395 GetRequests, 2091 SyntacticMatches, 90 SemanticMatches, 214 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12375 ImplicationChecksByTransitivity, 10.5s TimeCoverageRelationStatistics Valid=15889, Invalid=30551, Unknown=0, NotChecked=0, Total=46440 [2022-12-14 07:58:36,830 INFO L413 NwaCegarLoop]: 113 mSDtfsCounter, 23 mSDsluCounter, 555 mSDsCounter, 0 mSdLazyCounter, 922 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 668 SdHoareTripleChecker+Invalid, 923 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 922 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-12-14 07:58:36,830 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 668 Invalid, 923 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 922 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-12-14 07:58:36,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 813 states. [2022-12-14 07:58:36,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 813 to 813. [2022-12-14 07:58:36,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 813 states, 608 states have (on average 1.0016447368421053) internal successors, (609), 608 states have internal predecessors, (609), 103 states have call successors, (103), 102 states have call predecessors, (103), 101 states have return successors, (102), 102 states have call predecessors, (102), 102 states have call successors, (102) [2022-12-14 07:58:36,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 813 states to 813 states and 814 transitions. [2022-12-14 07:58:36,878 INFO L78 Accepts]: Start accepts. Automaton has 813 states and 814 transitions. Word has length 766 [2022-12-14 07:58:36,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 07:58:36,879 INFO L495 AbstractCegarLoop]: Abstraction has 813 states and 814 transitions. [2022-12-14 07:58:36,879 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 104 states, 104 states have (on average 5.721153846153846) internal successors, (595), 104 states have internal predecessors, (595), 101 states have call successors, (193), 97 states have call predecessors, (193), 96 states have return successors, (192), 100 states have call predecessors, (192), 100 states have call successors, (192) [2022-12-14 07:58:36,879 INFO L276 IsEmpty]: Start isEmpty. Operand 813 states and 814 transitions. [2022-12-14 07:58:36,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 815 [2022-12-14 07:58:36,884 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 07:58:36,884 INFO L195 NwaCegarLoop]: trace histogram [101, 101, 100, 100, 100, 100, 100, 100, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 07:58:36,899 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2022-12-14 07:58:37,085 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,13 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:58:37,086 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 07:58:37,087 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 07:58:37,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1872537714, now seen corresponding path program 7 times [2022-12-14 07:58:37,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 07:58:37,088 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892641597] [2022-12-14 07:58:37,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 07:58:37,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 07:58:37,150 ERROR L245 FreeRefinementEngine]: Caught known exception: Unsupported non-linear arithmetic [2022-12-14 07:58:37,151 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleZ3 [777820030] [2022-12-14 07:58:37,151 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2022-12-14 07:58:37,151 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 07:58:37,151 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 07:58:37,152 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-12-14 07:58:37,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-12-14 07:58:52,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 07:58:52,750 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-14 08:00:42,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 08:00:42,718 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-12-14 08:00:42,718 INFO L360 BasicCegarLoop]: Counterexample is feasible [2022-12-14 08:00:42,719 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-12-14 08:00:42,736 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Ended with exit code 0 [2022-12-14 08:00:42,920 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable12,14 /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-12-14 08:00:42,930 INFO L445 BasicCegarLoop]: Path program histogram: [7, 1, 1, 1, 1, 1, 1] [2022-12-14 08:00:42,943 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-12-14 08:00:43,080 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.12 08:00:43 BoogieIcfgContainer [2022-12-14 08:00:43,080 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-12-14 08:00:43,081 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-14 08:00:43,081 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-14 08:00:43,081 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-14 08:00:43,081 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 07:50:30" (3/4) ... [2022-12-14 08:00:43,082 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-12-14 08:00:43,232 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/witness.graphml [2022-12-14 08:00:43,232 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-14 08:00:43,232 INFO L158 Benchmark]: Toolchain (without parser) took 613430.66ms. Allocated memory was 119.5MB in the beginning and 172.0MB in the end (delta: 52.4MB). Free memory was 83.9MB in the beginning and 86.3MB in the end (delta: -2.5MB). Peak memory consumption was 110.7MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,233 INFO L158 Benchmark]: CDTParser took 0.11ms. Allocated memory is still 119.5MB. Free memory was 83.9MB in the beginning and 83.8MB in the end (delta: 30.3kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-14 08:00:43,233 INFO L158 Benchmark]: CACSL2BoogieTranslator took 165.10ms. Allocated memory is still 119.5MB. Free memory was 83.4MB in the beginning and 73.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,233 INFO L158 Benchmark]: Boogie Procedure Inliner took 24.42ms. Allocated memory is still 119.5MB. Free memory was 72.9MB in the beginning and 71.7MB in the end (delta: 1.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,233 INFO L158 Benchmark]: Boogie Preprocessor took 15.44ms. Allocated memory is still 119.5MB. Free memory was 71.7MB in the beginning and 70.7MB in the end (delta: 998.0kB). There was no memory consumed. Max. memory is 16.1GB. [2022-12-14 08:00:43,234 INFO L158 Benchmark]: RCFGBuilder took 241.09ms. Allocated memory is still 119.5MB. Free memory was 70.3MB in the beginning and 58.2MB in the end (delta: 12.0MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,234 INFO L158 Benchmark]: TraceAbstraction took 612827.33ms. Allocated memory was 119.5MB in the beginning and 172.0MB in the end (delta: 52.4MB). Free memory was 57.8MB in the beginning and 36.9MB in the end (delta: 20.9MB). Peak memory consumption was 76.2MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,234 INFO L158 Benchmark]: Witness Printer took 151.46ms. Allocated memory is still 172.0MB. Free memory was 36.9MB in the beginning and 86.3MB in the end (delta: -49.4MB). Peak memory consumption was 9.3MB. Max. memory is 16.1GB. [2022-12-14 08:00:43,236 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11ms. Allocated memory is still 119.5MB. Free memory was 83.9MB in the beginning and 83.8MB in the end (delta: 30.3kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 165.10ms. Allocated memory is still 119.5MB. Free memory was 83.4MB in the beginning and 73.4MB in the end (delta: 10.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 24.42ms. Allocated memory is still 119.5MB. Free memory was 72.9MB in the beginning and 71.7MB in the end (delta: 1.2MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 15.44ms. Allocated memory is still 119.5MB. Free memory was 71.7MB in the beginning and 70.7MB in the end (delta: 998.0kB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 241.09ms. Allocated memory is still 119.5MB. Free memory was 70.3MB in the beginning and 58.2MB in the end (delta: 12.0MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * TraceAbstraction took 612827.33ms. Allocated memory was 119.5MB in the beginning and 172.0MB in the end (delta: 52.4MB). Free memory was 57.8MB in the beginning and 36.9MB in the end (delta: 20.9MB). Peak memory consumption was 76.2MB. Max. memory is 16.1GB. * Witness Printer took 151.46ms. Allocated memory is still 172.0MB. Free memory was 36.9MB in the beginning and 86.3MB in the end (delta: -49.4MB). Peak memory consumption was 9.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 14]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L19] int counter = 0; [L21] int A, R; [L22] long long u, v, r; [L23] A = __VERIFIER_nondet_int() [L24] R = __VERIFIER_nondet_int() [L26] CALL assume_abort_if_not(((long long) R - 1) * ((long long) R - 1) < A) VAL [\old(cond)=1, counter=0] [L9] COND FALSE !(!cond) [L26] RET assume_abort_if_not(((long long) R - 1) * ((long long) R - 1) < A) VAL [A=241, counter=0, R=3] [L28] CALL assume_abort_if_not(A % 2 == 1) VAL [\old(cond)=1, counter=0] [L9] COND FALSE !(!cond) [L28] RET assume_abort_if_not(A % 2 == 1) VAL [A=241, counter=0, R=3] [L30] u = ((long long) 2 * R) + 1 [L31] v = 1 [L32] r = ((long long) R * R) - A VAL [A=241, counter=0, R=3, r=-232, u=7, v=1] [L34] EXPR counter++ VAL [A=241, counter=1, counter++=0, R=3, r=-232, u=7, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=1] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=1] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=1, r=-232, R=3, u=7, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=1, r=-225, R=3, u=9, v=1] [L34] EXPR counter++ VAL [A=241, counter=2, counter++=1, R=3, r=-225, u=9, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=2] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=2] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=2, r=-225, R=3, u=9, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=2, R=3, r=-216, u=11, v=1] [L34] EXPR counter++ VAL [A=241, counter=3, counter++=2, R=3, r=-216, u=11, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=3] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=3] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=3, r=-216, R=3, u=11, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=3, R=3, r=-205, u=13, v=1] [L34] EXPR counter++ VAL [A=241, counter=4, counter++=3, r=-205, R=3, u=13, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=4] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=4] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=4, r=-205, R=3, u=13, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=4, r=-192, R=3, u=15, v=1] [L34] EXPR counter++ VAL [A=241, counter=5, counter++=4, r=-192, R=3, u=15, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=5] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=5] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=5, r=-192, R=3, u=15, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=5, r=-177, R=3, u=17, v=1] [L34] EXPR counter++ VAL [A=241, counter=6, counter++=5, R=3, r=-177, u=17, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=6] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=6] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=6, R=3, r=-177, u=17, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=6, R=3, r=-160, u=19, v=1] [L34] EXPR counter++ VAL [A=241, counter=7, counter++=6, r=-160, R=3, u=19, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=7] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=7] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=7, r=-160, R=3, u=19, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=7, R=3, r=-141, u=21, v=1] [L34] EXPR counter++ VAL [A=241, counter=8, counter++=7, r=-141, R=3, u=21, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=8] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=8] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=8, r=-141, R=3, u=21, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=8, r=-120, R=3, u=23, v=1] [L34] EXPR counter++ VAL [A=241, counter=9, counter++=8, r=-120, R=3, u=23, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=9] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=9] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=9, R=3, r=-120, u=23, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=9, R=3, r=-97, u=25, v=1] [L34] EXPR counter++ VAL [A=241, counter=10, counter++=9, R=3, r=-97, u=25, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=10] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=10] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=10, r=-97, R=3, u=25, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=10, r=-72, R=3, u=27, v=1] [L34] EXPR counter++ VAL [A=241, counter=11, counter++=10, r=-72, R=3, u=27, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=11] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=11] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=11, r=-72, R=3, u=27, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=11, R=3, r=-45, u=29, v=1] [L34] EXPR counter++ VAL [A=241, counter=12, counter++=11, r=-45, R=3, u=29, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=12] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=12] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=12, R=3, r=-45, u=29, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=12, r=-16, R=3, u=31, v=1] [L34] EXPR counter++ VAL [A=241, counter=13, counter++=12, r=-16, R=3, u=31, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=13] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=13] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=13, r=-16, R=3, u=31, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=13, r=15, R=3, u=33, v=1] [L34] EXPR counter++ VAL [A=241, counter=14, counter++=13, R=3, r=15, u=33, v=1] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=14] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=14] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=14, R=3, r=15, u=33, v=1] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=14, R=3, r=14, u=33, v=3] [L34] EXPR counter++ VAL [A=241, counter=15, counter++=14, r=14, R=3, u=33, v=3] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=15] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=15] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=15, r=14, R=3, u=33, v=3] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=15, R=3, r=11, u=33, v=5] [L34] EXPR counter++ VAL [A=241, counter=16, counter++=15, R=3, r=11, u=33, v=5] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=16] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=16] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=16, R=3, r=11, u=33, v=5] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=16, R=3, r=6, u=33, v=7] [L34] EXPR counter++ VAL [A=241, counter=17, counter++=16, r=6, R=3, u=33, v=7] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=17] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=17] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=17, r=6, R=3, u=33, v=7] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=17, r=-1, R=3, u=33, v=9] [L34] EXPR counter++ VAL [A=241, counter=18, counter++=17, r=-1, R=3, u=33, v=9] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=18] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=18] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=18, R=3, r=-1, u=33, v=9] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=18, R=3, r=32, u=35, v=9] [L34] EXPR counter++ VAL [A=241, counter=19, counter++=18, R=3, r=32, u=35, v=9] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=19] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=19] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=19, R=3, r=32, u=35, v=9] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=19, r=23, R=3, u=35, v=11] [L34] EXPR counter++ VAL [A=241, counter=20, counter++=19, R=3, r=23, u=35, v=11] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=20] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=20] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=20, r=23, R=3, u=35, v=11] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=20, R=3, r=12, u=35, v=13] [L34] EXPR counter++ VAL [A=241, counter=21, counter++=20, r=12, R=3, u=35, v=13] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=21] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=21] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=21, r=12, R=3, u=35, v=13] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=21, r=-1, R=3, u=35, v=15] [L34] EXPR counter++ VAL [A=241, counter=22, counter++=21, r=-1, R=3, u=35, v=15] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=22] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=22] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=22, r=-1, R=3, u=35, v=15] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=22, R=3, r=34, u=37, v=15] [L34] EXPR counter++ VAL [A=241, counter=23, counter++=22, r=34, R=3, u=37, v=15] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=23] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=23] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=23, r=34, R=3, u=37, v=15] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=23, r=19, R=3, u=37, v=17] [L34] EXPR counter++ VAL [A=241, counter=24, counter++=23, r=19, R=3, u=37, v=17] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=24] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=24] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=24, r=19, R=3, u=37, v=17] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=24, r=2, R=3, u=37, v=19] [L34] EXPR counter++ VAL [A=241, counter=25, counter++=24, R=3, r=2, u=37, v=19] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=25] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=25] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=25, R=3, r=2, u=37, v=19] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=25, R=3, r=-17, u=37, v=21] [L34] EXPR counter++ VAL [A=241, counter=26, counter++=25, r=-17, R=3, u=37, v=21] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=26] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=26] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=26, r=-17, R=3, u=37, v=21] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=26, r=20, R=3, u=39, v=21] [L34] EXPR counter++ VAL [A=241, counter=27, counter++=26, r=20, R=3, u=39, v=21] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=27] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=27] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=27, r=20, R=3, u=39, v=21] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=27, r=-1, R=3, u=39, v=23] [L34] EXPR counter++ VAL [A=241, counter=28, counter++=27, R=3, r=-1, u=39, v=23] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=28] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=28] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=28, r=-1, R=3, u=39, v=23] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=28, R=3, r=38, u=41, v=23] [L34] EXPR counter++ VAL [A=241, counter=29, counter++=28, r=38, R=3, u=41, v=23] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=29] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=29] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=29, R=3, r=38, u=41, v=23] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=29, R=3, r=15, u=41, v=25] [L34] EXPR counter++ VAL [A=241, counter=30, counter++=29, r=15, R=3, u=41, v=25] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=30] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=30] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=30, r=15, R=3, u=41, v=25] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=30, R=3, r=-10, u=41, v=27] [L34] EXPR counter++ VAL [A=241, counter=31, counter++=30, r=-10, R=3, u=41, v=27] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=31] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=31] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=31, R=3, r=-10, u=41, v=27] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=31, r=31, R=3, u=43, v=27] [L34] EXPR counter++ VAL [A=241, counter=32, counter++=31, r=31, R=3, u=43, v=27] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=32] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=32] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=32, r=31, R=3, u=43, v=27] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=32, R=3, r=4, u=43, v=29] [L34] EXPR counter++ VAL [A=241, counter=33, counter++=32, R=3, r=4, u=43, v=29] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=33] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=33] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=33, R=3, r=4, u=43, v=29] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=33, r=-25, R=3, u=43, v=31] [L34] EXPR counter++ VAL [A=241, counter=34, counter++=33, r=-25, R=3, u=43, v=31] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=34] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=34] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=34, R=3, r=-25, u=43, v=31] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=34, R=3, r=18, u=45, v=31] [L34] EXPR counter++ VAL [A=241, counter=35, counter++=34, r=18, R=3, u=45, v=31] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=35] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=35] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=35, r=18, R=3, u=45, v=31] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=35, r=-13, R=3, u=45, v=33] [L34] EXPR counter++ VAL [A=241, counter=36, counter++=35, r=-13, R=3, u=45, v=33] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=36] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=36] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=36, R=3, r=-13, u=45, v=33] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=36, r=32, R=3, u=47, v=33] [L34] EXPR counter++ VAL [A=241, counter=37, counter++=36, r=32, R=3, u=47, v=33] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=37] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=37] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=37, r=32, R=3, u=47, v=33] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=37, r=-1, R=3, u=47, v=35] [L34] EXPR counter++ VAL [A=241, counter=38, counter++=37, R=3, r=-1, u=47, v=35] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=38] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=38] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=38, r=-1, R=3, u=47, v=35] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=38, r=46, R=3, u=49, v=35] [L34] EXPR counter++ VAL [A=241, counter=39, counter++=38, R=3, r=46, u=49, v=35] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=39] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=39] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=39, r=46, R=3, u=49, v=35] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=39, R=3, r=11, u=49, v=37] [L34] EXPR counter++ VAL [A=241, counter=40, counter++=39, R=3, r=11, u=49, v=37] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=40] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=40] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=40, R=3, r=11, u=49, v=37] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=40, R=3, r=-26, u=49, v=39] [L34] EXPR counter++ VAL [A=241, counter=41, counter++=40, R=3, r=-26, u=49, v=39] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=41] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=41] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=41, R=3, r=-26, u=49, v=39] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=41, R=3, r=23, u=51, v=39] [L34] EXPR counter++ VAL [A=241, counter=42, counter++=41, r=23, R=3, u=51, v=39] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=42] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=42] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=42, r=23, R=3, u=51, v=39] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=42, r=-16, R=3, u=51, v=41] [L34] EXPR counter++ VAL [A=241, counter=43, counter++=42, r=-16, R=3, u=51, v=41] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=43] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=43] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=43, R=3, r=-16, u=51, v=41] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=43, R=3, r=35, u=53, v=41] [L34] EXPR counter++ VAL [A=241, counter=44, counter++=43, R=3, r=35, u=53, v=41] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=44] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=44] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=44, r=35, R=3, u=53, v=41] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=44, R=3, r=-6, u=53, v=43] [L34] EXPR counter++ VAL [A=241, counter=45, counter++=44, r=-6, R=3, u=53, v=43] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=45] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=45] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=45, r=-6, R=3, u=53, v=43] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=45, r=47, R=3, u=55, v=43] [L34] EXPR counter++ VAL [A=241, counter=46, counter++=45, r=47, R=3, u=55, v=43] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=46] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=46] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=46, r=47, R=3, u=55, v=43] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=46, R=3, r=4, u=55, v=45] [L34] EXPR counter++ VAL [A=241, counter=47, counter++=46, r=4, R=3, u=55, v=45] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=47] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=47] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=47, r=4, R=3, u=55, v=45] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=47, r=-41, R=3, u=55, v=47] [L34] EXPR counter++ VAL [A=241, counter=48, counter++=47, r=-41, R=3, u=55, v=47] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=48] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=48] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=48, r=-41, R=3, u=55, v=47] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=48, r=14, R=3, u=57, v=47] [L34] EXPR counter++ VAL [A=241, counter=49, counter++=48, R=3, r=14, u=57, v=47] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=49] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=49] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=49, R=3, r=14, u=57, v=47] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=49, r=-33, R=3, u=57, v=49] [L34] EXPR counter++ VAL [A=241, counter=50, counter++=49, R=3, r=-33, u=57, v=49] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=50] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=50] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=50, r=-33, R=3, u=57, v=49] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=50, r=24, R=3, u=59, v=49] [L34] EXPR counter++ VAL [A=241, counter=51, counter++=50, R=3, r=24, u=59, v=49] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=51] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=51] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=51, r=24, R=3, u=59, v=49] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=51, R=3, r=-25, u=59, v=51] [L34] EXPR counter++ VAL [A=241, counter=52, counter++=51, r=-25, R=3, u=59, v=51] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=52] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=52] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=52, R=3, r=-25, u=59, v=51] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=52, R=3, r=34, u=61, v=51] [L34] EXPR counter++ VAL [A=241, counter=53, counter++=52, r=34, R=3, u=61, v=51] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=53] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=53] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=53, r=34, R=3, u=61, v=51] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=53, r=-17, R=3, u=61, v=53] [L34] EXPR counter++ VAL [A=241, counter=54, counter++=53, R=3, r=-17, u=61, v=53] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=54] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=54] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=54, R=3, r=-17, u=61, v=53] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=54, r=44, R=3, u=63, v=53] [L34] EXPR counter++ VAL [A=241, counter=55, counter++=54, r=44, R=3, u=63, v=53] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=55] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=55] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=55, r=44, R=3, u=63, v=53] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=55, R=3, r=-9, u=63, v=55] [L34] EXPR counter++ VAL [A=241, counter=56, counter++=55, r=-9, R=3, u=63, v=55] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=56] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=56] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=56, R=3, r=-9, u=63, v=55] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=56, R=3, r=54, u=65, v=55] [L34] EXPR counter++ VAL [A=241, counter=57, counter++=56, R=3, r=54, u=65, v=55] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=57] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=57] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=57, r=54, R=3, u=65, v=55] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=57, r=-1, R=3, u=65, v=57] [L34] EXPR counter++ VAL [A=241, counter=58, counter++=57, r=-1, R=3, u=65, v=57] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=58] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=58] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=58, R=3, r=-1, u=65, v=57] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=58, R=3, r=64, u=67, v=57] [L34] EXPR counter++ VAL [A=241, counter=59, counter++=58, R=3, r=64, u=67, v=57] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=59] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=59] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=59, r=64, R=3, u=67, v=57] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=59, R=3, r=7, u=67, v=59] [L34] EXPR counter++ VAL [A=241, counter=60, counter++=59, R=3, r=7, u=67, v=59] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=60] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=60] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=60, R=3, r=7, u=67, v=59] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=60, R=3, r=-52, u=67, v=61] [L34] EXPR counter++ VAL [A=241, counter=61, counter++=60, R=3, r=-52, u=67, v=61] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=61] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=61] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=61, r=-52, R=3, u=67, v=61] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=61, r=15, R=3, u=69, v=61] [L34] EXPR counter++ VAL [A=241, counter=62, counter++=61, R=3, r=15, u=69, v=61] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=62] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=62] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=62, R=3, r=15, u=69, v=61] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=62, r=-46, R=3, u=69, v=63] [L34] EXPR counter++ VAL [A=241, counter=63, counter++=62, r=-46, R=3, u=69, v=63] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=63] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=63] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=63, r=-46, R=3, u=69, v=63] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=63, r=23, R=3, u=71, v=63] [L34] EXPR counter++ VAL [A=241, counter=64, counter++=63, r=23, R=3, u=71, v=63] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=64] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=64] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=64, r=23, R=3, u=71, v=63] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=64, r=-40, R=3, u=71, v=65] [L34] EXPR counter++ VAL [A=241, counter=65, counter++=64, R=3, r=-40, u=71, v=65] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=65] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=65] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=65, R=3, r=-40, u=71, v=65] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=65, r=31, R=3, u=73, v=65] [L34] EXPR counter++ VAL [A=241, counter=66, counter++=65, R=3, r=31, u=73, v=65] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=66] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=66] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=66, r=31, R=3, u=73, v=65] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=66, r=-34, R=3, u=73, v=67] [L34] EXPR counter++ VAL [A=241, counter=67, counter++=66, R=3, r=-34, u=73, v=67] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=67] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=67] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=67, R=3, r=-34, u=73, v=67] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=67, r=39, R=3, u=75, v=67] [L34] EXPR counter++ VAL [A=241, counter=68, counter++=67, R=3, r=39, u=75, v=67] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=68] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=68] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=68, R=3, r=39, u=75, v=67] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=68, R=3, r=-28, u=75, v=69] [L34] EXPR counter++ VAL [A=241, counter=69, counter++=68, R=3, r=-28, u=75, v=69] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=69] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=69] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=69, R=3, r=-28, u=75, v=69] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=69, R=3, r=47, u=77, v=69] [L34] EXPR counter++ VAL [A=241, counter=70, counter++=69, R=3, r=47, u=77, v=69] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=70] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=70] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=70, R=3, r=47, u=77, v=69] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=70, r=-22, R=3, u=77, v=71] [L34] EXPR counter++ VAL [A=241, counter=71, counter++=70, r=-22, R=3, u=77, v=71] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=71] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=71] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=71, R=3, r=-22, u=77, v=71] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=71, R=3, r=55, u=79, v=71] [L34] EXPR counter++ VAL [A=241, counter=72, counter++=71, R=3, r=55, u=79, v=71] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=72] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=72] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=72, r=55, R=3, u=79, v=71] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=72, R=3, r=-16, u=79, v=73] [L34] EXPR counter++ VAL [A=241, counter=73, counter++=72, R=3, r=-16, u=79, v=73] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=73] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=73] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=73, R=3, r=-16, u=79, v=73] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=73, r=63, R=3, u=81, v=73] [L34] EXPR counter++ VAL [A=241, counter=74, counter++=73, R=3, r=63, u=81, v=73] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=74] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=74] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=74, R=3, r=63, u=81, v=73] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=74, r=-10, R=3, u=81, v=75] [L34] EXPR counter++ VAL [A=241, counter=75, counter++=74, R=3, r=-10, u=81, v=75] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=75] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=75] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=75, r=-10, R=3, u=81, v=75] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=75, R=3, r=71, u=83, v=75] [L34] EXPR counter++ VAL [A=241, counter=76, counter++=75, r=71, R=3, u=83, v=75] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=76] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=76] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=76, R=3, r=71, u=83, v=75] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=76, R=3, r=-4, u=83, v=77] [L34] EXPR counter++ VAL [A=241, counter=77, counter++=76, r=-4, R=3, u=83, v=77] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=77] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=77] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=77, r=-4, R=3, u=83, v=77] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=77, R=3, r=79, u=85, v=77] [L34] EXPR counter++ VAL [A=241, counter=78, counter++=77, r=79, R=3, u=85, v=77] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=78] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=78] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=78, R=3, r=79, u=85, v=77] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=78, r=2, R=3, u=85, v=79] [L34] EXPR counter++ VAL [A=241, counter=79, counter++=78, r=2, R=3, u=85, v=79] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=79] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=79] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=79, R=3, r=2, u=85, v=79] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=79, R=3, r=-77, u=85, v=81] [L34] EXPR counter++ VAL [A=241, counter=80, counter++=79, R=3, r=-77, u=85, v=81] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=80] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=80] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=80, r=-77, R=3, u=85, v=81] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=80, R=3, r=8, u=87, v=81] [L34] EXPR counter++ VAL [A=241, counter=81, counter++=80, R=3, r=8, u=87, v=81] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=81] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=81] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=81, R=3, r=8, u=87, v=81] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=81, r=-73, R=3, u=87, v=83] [L34] EXPR counter++ VAL [A=241, counter=82, counter++=81, r=-73, R=3, u=87, v=83] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=82] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=82] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=82, R=3, r=-73, u=87, v=83] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=82, R=3, r=14, u=89, v=83] [L34] EXPR counter++ VAL [A=241, counter=83, counter++=82, R=3, r=14, u=89, v=83] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=83] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=83] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=83, R=3, r=14, u=89, v=83] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=83, R=3, r=-69, u=89, v=85] [L34] EXPR counter++ VAL [A=241, counter=84, counter++=83, R=3, r=-69, u=89, v=85] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=84] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=84] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=84, R=3, r=-69, u=89, v=85] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=84, R=3, r=20, u=91, v=85] [L34] EXPR counter++ VAL [A=241, counter=85, counter++=84, r=20, R=3, u=91, v=85] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=85] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=85] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=85, r=20, R=3, u=91, v=85] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=85, r=-65, R=3, u=91, v=87] [L34] EXPR counter++ VAL [A=241, counter=86, counter++=85, r=-65, R=3, u=91, v=87] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=86] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=86] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=86, r=-65, R=3, u=91, v=87] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=86, R=3, r=26, u=93, v=87] [L34] EXPR counter++ VAL [A=241, counter=87, counter++=86, R=3, r=26, u=93, v=87] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=87] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=87] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=87, R=3, r=26, u=93, v=87] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=87, R=3, r=-61, u=93, v=89] [L34] EXPR counter++ VAL [A=241, counter=88, counter++=87, R=3, r=-61, u=93, v=89] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=88] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=88] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=88, R=3, r=-61, u=93, v=89] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=88, R=3, r=32, u=95, v=89] [L34] EXPR counter++ VAL [A=241, counter=89, counter++=88, R=3, r=32, u=95, v=89] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=89] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=89] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=89, R=3, r=32, u=95, v=89] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=89, R=3, r=-57, u=95, v=91] [L34] EXPR counter++ VAL [A=241, counter=90, counter++=89, r=-57, R=3, u=95, v=91] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=90] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=90] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=90, R=3, r=-57, u=95, v=91] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=90, r=38, R=3, u=97, v=91] [L34] EXPR counter++ VAL [A=241, counter=91, counter++=90, R=3, r=38, u=97, v=91] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=91] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=91] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=91, r=38, R=3, u=97, v=91] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=91, R=3, r=-53, u=97, v=93] [L34] EXPR counter++ VAL [A=241, counter=92, counter++=91, r=-53, R=3, u=97, v=93] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=92] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=92] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=92, r=-53, R=3, u=97, v=93] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=92, r=44, R=3, u=99, v=93] [L34] EXPR counter++ VAL [A=241, counter=93, counter++=92, R=3, r=44, u=99, v=93] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=93] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=93] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=93, R=3, r=44, u=99, v=93] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=93, R=3, r=-49, u=99, v=95] [L34] EXPR counter++ VAL [A=241, counter=94, counter++=93, R=3, r=-49, u=99, v=95] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=94] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=94] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=94, R=3, r=-49, u=99, v=95] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=94, r=50, R=3, u=101, v=95] [L34] EXPR counter++ VAL [A=241, counter=95, counter++=94, R=3, r=50, u=101, v=95] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=95] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=95] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=95, r=50, R=3, u=101, v=95] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=95, r=-45, R=3, u=101, v=97] [L34] EXPR counter++ VAL [A=241, counter=96, counter++=95, R=3, r=-45, u=101, v=97] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=96] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=96] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=96, r=-45, R=3, u=101, v=97] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=96, R=3, r=56, u=103, v=97] [L34] EXPR counter++ VAL [A=241, counter=97, counter++=96, R=3, r=56, u=103, v=97] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=97] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=97] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=97, r=56, R=3, u=103, v=97] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=97, R=3, r=-41, u=103, v=99] [L34] EXPR counter++ VAL [A=241, counter=98, counter++=97, r=-41, R=3, u=103, v=99] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=98] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=98] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=98, R=3, r=-41, u=103, v=99] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=98, r=62, R=3, u=105, v=99] [L34] EXPR counter++ VAL [A=241, counter=99, counter++=98, r=62, R=3, u=105, v=99] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=99] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=99] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=99, r=62, R=3, u=105, v=99] [L36] COND FALSE !(!(r != 0)) [L38] COND TRUE r > 0 [L39] r = r - v [L40] v = v + 2 VAL [A=241, counter=99, r=-37, R=3, u=105, v=101] [L34] EXPR counter++ VAL [A=241, counter=100, counter++=99, r=-37, R=3, u=105, v=101] [L34] COND TRUE counter++<100 [L35] CALL __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=1, counter=100] [L12] COND FALSE !(!(cond)) VAL [\old(cond)=1, cond=1, counter=100] [L35] RET __VERIFIER_assert(4*(A+r) == u*u - v*v - 2*u + 2*v) VAL [A=241, counter=100, R=3, r=-37, u=105, v=101] [L36] COND FALSE !(!(r != 0)) [L38] COND FALSE !(r > 0) [L42] r = r + u [L43] u = u + 2 VAL [A=241, counter=100, r=68, R=3, u=107, v=101] [L34] EXPR counter++ VAL [A=241, counter=101, counter++=100, r=68, R=3, u=107, v=101] [L34] COND FALSE !(counter++<100) [L48] CALL __VERIFIER_assert(((long long) 4*A) == u*u - v*v - 2*u + 2*v) VAL [\old(cond)=0, counter=101] [L12] COND TRUE !(cond) VAL [\old(cond)=0, cond=0, counter=101] [L14] reach_error() VAL [\old(cond)=0, cond=0, counter=101] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 19 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 612.6s, OverallIterations: 13, TraceHistogramMax: 101, PathProgramHistogramMax: 7, EmptinessCheckTime: 0.0s, AutomataDifference: 20.7s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 2 mSolverCounterUnknown, 1010 SdHoareTripleChecker+Valid, 8.8s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1009 mSDsluCounter, 2264 SdHoareTripleChecker+Invalid, 8.5s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1826 mSDsCounter, 207 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 2627 IncrementalHoareTripleChecker+Invalid, 2836 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 207 mSolverCounterUnsat, 438 mSDtfsCounter, 2627 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 5007 GetRequests, 4201 SyntacticMatches, 93 SemanticMatches, 713 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25680 ImplicationChecksByTransitivity, 47.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=813occurred in iteration=12, InterpolantAutomatonStates: 604, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 12 MinimizatonAttempts, 12 StatesRemovedByMinimization, 3 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.3s SsaConstructionTime, 429.0s SatisfiabilityAnalysisTime, 19.8s InterpolantComputationTime, 2425 NumberOfCodeBlocks, 2425 NumberOfCodeBlocksAsserted, 65 NumberOfCheckSat, 3160 ConstructedInterpolants, 0 QuantifiedInterpolants, 8377 SizeOfPredicates, 196 NumberOfNonLiveVariables, 3686 ConjunctsInSsa, 430 ConjunctsInUnsatCore, 21 InterpolantComputations, 3 PerfectInterpolantSequences, 23531/92504 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: OVERALL_TIME: 0.3s, ICFG_INTERPRETER_ENTERED_PROCEDURES: 3, DAG_INTERPRETER_EARLY_EXIT_QUERIES_NONTRIVIAL: 17, DAG_INTERPRETER_EARLY_EXITS: 1, TOOLS_POST_APPLICATIONS: 14, TOOLS_POST_TIME: 0.1s, TOOLS_POST_CALL_APPLICATIONS: 10, TOOLS_POST_CALL_TIME: 0.1s, TOOLS_POST_RETURN_APPLICATIONS: 6, TOOLS_POST_RETURN_TIME: 0.0s, TOOLS_QUANTIFIERELIM_APPLICATIONS: 30, TOOLS_QUANTIFIERELIM_TIME: 0.2s, TOOLS_QUANTIFIERELIM_MAX_TIME: 0.0s, FLUID_QUERY_TIME: 0.0s, FLUID_QUERIES: 46, FLUID_YES_ANSWERS: 0, DOMAIN_JOIN_APPLICATIONS: 10, DOMAIN_JOIN_TIME: 0.1s, DOMAIN_ALPHA_APPLICATIONS: 0, DOMAIN_ALPHA_TIME: 0.0s, DOMAIN_WIDEN_APPLICATIONS: 0, DOMAIN_WIDEN_TIME: 0.0s, DOMAIN_ISSUBSETEQ_APPLICATIONS: 0, DOMAIN_ISSUBSETEQ_TIME: 0.0s, DOMAIN_ISBOTTOM_APPLICATIONS: 17, DOMAIN_ISBOTTOM_TIME: 0.0s, LOOP_SUMMARIZER_APPLICATIONS: 0, LOOP_SUMMARIZER_CACHE_MISSES: 0, LOOP_SUMMARIZER_OVERALL_TIME: 0.0s, LOOP_SUMMARIZER_NEW_COMPUTATION_TIME: 0.0s, LOOP_SUMMARIZER_FIXPOINT_ITERATIONS: 0, CALL_SUMMARIZER_APPLICATIONS: 6, CALL_SUMMARIZER_CACHE_MISSES: 2, CALL_SUMMARIZER_OVERALL_TIME: 0.0s, CALL_SUMMARIZER_NEW_COMPUTATION_TIME: 0.0s, PROCEDURE_GRAPH_BUILDER_TIME: 0.0s, PATH_EXPR_TIME: 0.0s, REGEX_TO_DAG_TIME: 0.0s, DAG_COMPRESSION_TIME: 0.0s, DAG_COMPRESSION_PROCESSED_NODES: 145, DAG_COMPRESSION_RETAINED_NODES: 50, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-12-14 08:00:43,264 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_24fd6b12-f687-4232-ac05-23af3b2f04f2/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE