./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/systemc/transmitter.16.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version 2329fc70 Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/config/TaipanReach.xml -i ../../sv-benchmarks/c/systemc/transmitter.16.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/config/svcomp-Reach-32bit-Taipan_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(reach_error())) ) --witnessprinter.graph.data.producer Taipan --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 --- Real Ultimate output --- [0.001s][warning][os,container] Duplicate cpuset controllers detected. Picking /sys/fs/cgroup/cpuset, skipping /sys/fs/cgroup/cpuset. This is Ultimate 0.2.2-dev-2329fc7 [2022-12-14 14:09:51,819 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-12-14 14:09:51,821 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-12-14 14:09:51,837 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-12-14 14:09:51,837 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-12-14 14:09:51,838 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-12-14 14:09:51,839 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-12-14 14:09:51,841 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-12-14 14:09:51,842 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-12-14 14:09:51,843 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-12-14 14:09:51,844 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-12-14 14:09:51,845 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-12-14 14:09:51,845 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-12-14 14:09:51,846 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-12-14 14:09:51,847 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-12-14 14:09:51,848 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-12-14 14:09:51,849 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-12-14 14:09:51,850 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-12-14 14:09:51,851 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-12-14 14:09:51,853 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-12-14 14:09:51,854 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-12-14 14:09:51,855 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-12-14 14:09:51,856 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-12-14 14:09:51,857 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-12-14 14:09:51,860 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2022-12-14 14:09:51,861 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2022-12-14 14:09:51,861 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2022-12-14 14:09:51,862 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2022-12-14 14:09:51,862 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2022-12-14 14:09:51,863 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2022-12-14 14:09:51,863 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2022-12-14 14:09:51,864 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2022-12-14 14:09:51,864 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2022-12-14 14:09:51,865 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2022-12-14 14:09:51,866 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2022-12-14 14:09:51,866 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2022-12-14 14:09:51,867 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2022-12-14 14:09:51,867 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2022-12-14 14:09:51,867 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-12-14 14:09:51,868 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-12-14 14:09:51,868 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-12-14 14:09:51,869 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/config/svcomp-Reach-32bit-Taipan_Default.epf [2022-12-14 14:09:51,884 INFO L113 SettingsManager]: Loading preferences was successful [2022-12-14 14:09:51,884 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-12-14 14:09:51,884 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2022-12-14 14:09:51,884 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2022-12-14 14:09:51,885 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-12-14 14:09:51,885 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-12-14 14:09:51,885 INFO L138 SettingsManager]: * User list type=DISABLED [2022-12-14 14:09:51,885 INFO L136 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2022-12-14 14:09:51,885 INFO L138 SettingsManager]: * Explicit value domain=true [2022-12-14 14:09:51,885 INFO L138 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Octagon Domain=false [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Abstract domain=CompoundDomain [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Use the RCFG-of-the-future interface=true [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Interval Domain=false [2022-12-14 14:09:51,886 INFO L136 SettingsManager]: Preferences of Sifa differ from their defaults: [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Call Summarizer=TopInputCallSummarizer [2022-12-14 14:09:51,886 INFO L138 SettingsManager]: * Simplification Technique=POLY_PAC [2022-12-14 14:09:51,887 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-12-14 14:09:51,887 INFO L138 SettingsManager]: * sizeof long=4 [2022-12-14 14:09:51,887 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-12-14 14:09:51,887 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * sizeof long double=12 [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Use constant arrays=true [2022-12-14 14:09:51,888 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-12-14 14:09:51,889 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-12-14 14:09:51,889 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-12-14 14:09:51,889 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-12-14 14:09:51,889 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-12-14 14:09:51,889 INFO L138 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Trace refinement strategy=SIFA_TAIPAN [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-12-14 14:09:51,890 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(reach_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Taipan Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 45519c8273c53879cf6a170ed74d5bc0be814b1f3243ce6c30d1d3efe9a3cf32 [2022-12-14 14:09:52,082 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-12-14 14:09:52,098 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-12-14 14:09:52,100 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-12-14 14:09:52,101 INFO L271 PluginConnector]: Initializing CDTParser... [2022-12-14 14:09:52,101 INFO L275 PluginConnector]: CDTParser initialized [2022-12-14 14:09:52,103 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/../../sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-12-14 14:09:54,542 INFO L500 CDTParser]: Created temporary CDT project at NULL [2022-12-14 14:09:54,725 INFO L351 CDTParser]: Found 1 translation units. [2022-12-14 14:09:54,726 INFO L172 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/sv-benchmarks/c/systemc/transmitter.16.cil.c [2022-12-14 14:09:54,734 INFO L394 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/data/a644e08fa/117cb314395c4c36b13d209c8d143b9d/FLAG0949d67f5 [2022-12-14 14:09:55,116 INFO L402 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/data/a644e08fa/117cb314395c4c36b13d209c8d143b9d [2022-12-14 14:09:55,118 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-12-14 14:09:55,119 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2022-12-14 14:09:55,120 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-12-14 14:09:55,120 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-12-14 14:09:55,123 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-12-14 14:09:55,123 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,124 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1032545a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55, skipping insertion in model container [2022-12-14 14:09:55,124 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,130 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-12-14 14:09:55,159 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-12-14 14:09:55,258 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-12-14 14:09:55,350 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 14:09:55,360 INFO L203 MainTranslator]: Completed pre-run [2022-12-14 14:09:55,368 WARN L237 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/sv-benchmarks/c/systemc/transmitter.16.cil.c[706,719] [2022-12-14 14:09:55,414 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-12-14 14:09:55,434 INFO L208 MainTranslator]: Completed translation [2022-12-14 14:09:55,434 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55 WrapperNode [2022-12-14 14:09:55,434 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-12-14 14:09:55,435 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2022-12-14 14:09:55,435 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2022-12-14 14:09:55,435 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2022-12-14 14:09:55,441 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,451 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,483 INFO L138 Inliner]: procedures = 56, calls = 71, calls flagged for inlining = 40, calls inlined = 40, statements flattened = 945 [2022-12-14 14:09:55,483 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2022-12-14 14:09:55,483 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-12-14 14:09:55,484 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-12-14 14:09:55,484 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-12-14 14:09:55,491 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,491 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,494 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,494 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,502 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,512 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,514 INFO L185 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,516 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,520 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-12-14 14:09:55,521 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-12-14 14:09:55,521 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-12-14 14:09:55,521 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-12-14 14:09:55,522 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (1/1) ... [2022-12-14 14:09:55,527 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-12-14 14:09:55,535 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/z3 [2022-12-14 14:09:55,545 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-12-14 14:09:55,547 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-12-14 14:09:55,585 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-12-14 14:09:55,585 INFO L130 BoogieDeclarations]: Found specification of procedure activate_threads [2022-12-14 14:09:55,585 INFO L138 BoogieDeclarations]: Found implementation of procedure activate_threads [2022-12-14 14:09:55,585 INFO L130 BoogieDeclarations]: Found specification of procedure immediate_notify [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure immediate_notify [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure update_channels [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure update_channels [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure fire_delta_events [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure fire_delta_events [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure exists_runnable_thread [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure exists_runnable_thread [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure reset_delta_events [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure reset_delta_events [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-12-14 14:09:55,586 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-12-14 14:09:55,586 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-12-14 14:09:55,685 INFO L235 CfgBuilder]: Building ICFG [2022-12-14 14:09:55,687 INFO L261 CfgBuilder]: Building CFG for each procedure with an implementation [2022-12-14 14:09:56,354 INFO L276 CfgBuilder]: Performing block encoding [2022-12-14 14:09:56,776 INFO L295 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-12-14 14:09:56,776 INFO L300 CfgBuilder]: Removed 18 assume(true) statements. [2022-12-14 14:09:56,778 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 02:09:56 BoogieIcfgContainer [2022-12-14 14:09:56,779 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-12-14 14:09:56,780 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-12-14 14:09:56,780 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-12-14 14:09:56,783 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-12-14 14:09:56,783 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.12 02:09:55" (1/3) ... [2022-12-14 14:09:56,783 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@156c3415 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.12 02:09:56, skipping insertion in model container [2022-12-14 14:09:56,783 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.12 02:09:55" (2/3) ... [2022-12-14 14:09:56,784 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@156c3415 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.12 02:09:56, skipping insertion in model container [2022-12-14 14:09:56,784 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 02:09:56" (3/3) ... [2022-12-14 14:09:56,785 INFO L112 eAbstractionObserver]: Analyzing ICFG transmitter.16.cil.c [2022-12-14 14:09:56,799 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-12-14 14:09:56,800 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-12-14 14:09:56,837 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-12-14 14:09:56,842 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=[Lde.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings;@1b5a0f25, mLbeIndependenceSettings=[IndependenceType=SEMANTIC, AbstractionType=NONE, UseConditional=false, UseSemiCommutativity=true, Solver=Z3, SolverTimeout=1000ms] [2022-12-14 14:09:56,842 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-12-14 14:09:56,846 INFO L276 IsEmpty]: Start isEmpty. Operand has 197 states, 163 states have (on average 1.5521472392638036) internal successors, (253), 165 states have internal predecessors, (253), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) [2022-12-14 14:09:56,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:09:56,853 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:09:56,853 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:09:56,854 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:09:56,858 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:09:56,858 INFO L85 PathProgramCache]: Analyzing trace with hash -1674658219, now seen corresponding path program 1 times [2022-12-14 14:09:56,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:09:56,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459094270] [2022-12-14 14:09:56,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:09:56,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:09:57,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:09:57,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:09:57,200 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:09:57,200 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459094270] [2022-12-14 14:09:57,201 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459094270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:09:57,201 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:09:57,201 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-14 14:09:57,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [51354433] [2022-12-14 14:09:57,203 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:09:57,207 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-12-14 14:09:57,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:09:57,227 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-14 14:09:57,228 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:09:57,231 INFO L87 Difference]: Start difference. First operand has 197 states, 163 states have (on average 1.5521472392638036) internal successors, (253), 165 states have internal predecessors, (253), 26 states have call successors, (26), 6 states have call predecessors, (26), 6 states have return successors, (26), 26 states have call predecessors, (26), 26 states have call successors, (26) Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:57,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:09:57,637 INFO L93 Difference]: Finished difference Result 574 states and 919 transitions. [2022-12-14 14:09:57,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-14 14:09:57,640 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:09:57,640 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:09:57,647 INFO L225 Difference]: With dead ends: 574 [2022-12-14 14:09:57,647 INFO L226 Difference]: Without dead ends: 378 [2022-12-14 14:09:57,652 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:09:57,654 INFO L413 NwaCegarLoop]: 470 mSDtfsCounter, 525 mSDsluCounter, 376 mSDsCounter, 0 mSdLazyCounter, 306 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 525 SdHoareTripleChecker+Valid, 846 SdHoareTripleChecker+Invalid, 320 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 306 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-12-14 14:09:57,654 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [525 Valid, 846 Invalid, 320 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 306 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-12-14 14:09:57,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 378 states. [2022-12-14 14:09:57,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 378 to 375. [2022-12-14 14:09:57,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 375 states, 315 states have (on average 1.511111111111111) internal successors, (476), 316 states have internal predecessors, (476), 47 states have call successors, (47), 12 states have call predecessors, (47), 12 states have return successors, (47), 47 states have call predecessors, (47), 47 states have call successors, (47) [2022-12-14 14:09:57,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 375 states to 375 states and 570 transitions. [2022-12-14 14:09:57,706 INFO L78 Accepts]: Start accepts. Automaton has 375 states and 570 transitions. Word has length 70 [2022-12-14 14:09:57,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:09:57,706 INFO L495 AbstractCegarLoop]: Abstraction has 375 states and 570 transitions. [2022-12-14 14:09:57,707 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:57,707 INFO L276 IsEmpty]: Start isEmpty. Operand 375 states and 570 transitions. [2022-12-14 14:09:57,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:09:57,708 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:09:57,708 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:09:57,709 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-12-14 14:09:57,709 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:09:57,709 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:09:57,709 INFO L85 PathProgramCache]: Analyzing trace with hash 713824884, now seen corresponding path program 1 times [2022-12-14 14:09:57,710 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:09:57,710 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659773904] [2022-12-14 14:09:57,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:09:57,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:09:57,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:09:57,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:09:57,831 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:09:57,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [659773904] [2022-12-14 14:09:57,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [659773904] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:09:57,832 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:09:57,832 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:09:57,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410155730] [2022-12-14 14:09:57,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:09:57,833 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:09:57,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:09:57,834 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:09:57,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:09:57,835 INFO L87 Difference]: Start difference. First operand 375 states and 570 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:58,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:09:58,409 INFO L93 Difference]: Finished difference Result 1287 states and 1981 transitions. [2022-12-14 14:09:58,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:09:58,409 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:09:58,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:09:58,417 INFO L225 Difference]: With dead ends: 1287 [2022-12-14 14:09:58,417 INFO L226 Difference]: Without dead ends: 890 [2022-12-14 14:09:58,419 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:09:58,420 INFO L413 NwaCegarLoop]: 503 mSDtfsCounter, 1120 mSDsluCounter, 847 mSDsCounter, 0 mSdLazyCounter, 505 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1350 SdHoareTripleChecker+Invalid, 715 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 505 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-12-14 14:09:58,421 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1350 Invalid, 715 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 505 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-12-14 14:09:58,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states. [2022-12-14 14:09:58,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 878. [2022-12-14 14:09:58,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 878 states, 757 states have (on average 1.500660501981506) internal successors, (1136), 746 states have internal predecessors, (1136), 92 states have call successors, (92), 26 states have call predecessors, (92), 28 states have return successors, (106), 106 states have call predecessors, (106), 92 states have call successors, (106) [2022-12-14 14:09:58,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 878 states to 878 states and 1334 transitions. [2022-12-14 14:09:58,466 INFO L78 Accepts]: Start accepts. Automaton has 878 states and 1334 transitions. Word has length 70 [2022-12-14 14:09:58,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:09:58,466 INFO L495 AbstractCegarLoop]: Abstraction has 878 states and 1334 transitions. [2022-12-14 14:09:58,466 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:58,466 INFO L276 IsEmpty]: Start isEmpty. Operand 878 states and 1334 transitions. [2022-12-14 14:09:58,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:09:58,467 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:09:58,467 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:09:58,467 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-12-14 14:09:58,467 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:09:58,468 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:09:58,468 INFO L85 PathProgramCache]: Analyzing trace with hash 816626131, now seen corresponding path program 1 times [2022-12-14 14:09:58,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:09:58,468 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61346383] [2022-12-14 14:09:58,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:09:58,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:09:58,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:09:58,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:09:58,632 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:09:58,632 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [61346383] [2022-12-14 14:09:58,632 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [61346383] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:09:58,632 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:09:58,632 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:09:58,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [362228194] [2022-12-14 14:09:58,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:09:58,633 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:09:58,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:09:58,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:09:58,634 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:09:58,634 INFO L87 Difference]: Start difference. First operand 878 states and 1334 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:59,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:09:59,203 INFO L93 Difference]: Finished difference Result 3089 states and 4760 transitions. [2022-12-14 14:09:59,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:09:59,204 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:09:59,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:09:59,211 INFO L225 Difference]: With dead ends: 3089 [2022-12-14 14:09:59,211 INFO L226 Difference]: Without dead ends: 2165 [2022-12-14 14:09:59,214 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:09:59,215 INFO L413 NwaCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-12-14 14:09:59,215 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-12-14 14:09:59,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2165 states. [2022-12-14 14:09:59,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2165 to 1689. [2022-12-14 14:09:59,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1689 states, 1460 states have (on average 1.5027397260273974) internal successors, (2194), 1450 states have internal predecessors, (2194), 172 states have call successors, (172), 50 states have call predecessors, (172), 56 states have return successors, (213), 189 states have call predecessors, (213), 172 states have call successors, (213) [2022-12-14 14:09:59,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1689 states to 1689 states and 2579 transitions. [2022-12-14 14:09:59,277 INFO L78 Accepts]: Start accepts. Automaton has 1689 states and 2579 transitions. Word has length 70 [2022-12-14 14:09:59,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:09:59,278 INFO L495 AbstractCegarLoop]: Abstraction has 1689 states and 2579 transitions. [2022-12-14 14:09:59,278 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:09:59,278 INFO L276 IsEmpty]: Start isEmpty. Operand 1689 states and 2579 transitions. [2022-12-14 14:09:59,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:09:59,279 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:09:59,279 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:09:59,279 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2 [2022-12-14 14:09:59,279 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:09:59,279 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:09:59,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1284215084, now seen corresponding path program 1 times [2022-12-14 14:09:59,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:09:59,280 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1053762788] [2022-12-14 14:09:59,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:09:59,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:09:59,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:09:59,380 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:09:59,380 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:09:59,381 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1053762788] [2022-12-14 14:09:59,381 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1053762788] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:09:59,381 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:09:59,381 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:09:59,381 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [531639922] [2022-12-14 14:09:59,381 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:09:59,382 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:09:59,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:09:59,382 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:09:59,383 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:09:59,383 INFO L87 Difference]: Start difference. First operand 1689 states and 2579 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:00,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:00,068 INFO L93 Difference]: Finished difference Result 5878 states and 9131 transitions. [2022-12-14 14:10:00,068 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:10:00,068 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:00,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:00,090 INFO L225 Difference]: With dead ends: 5878 [2022-12-14 14:10:00,091 INFO L226 Difference]: Without dead ends: 4096 [2022-12-14 14:10:00,098 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:10:00,099 INFO L413 NwaCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:00,099 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-12-14 14:10:00,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4096 states. [2022-12-14 14:10:00,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4096 to 3285. [2022-12-14 14:10:00,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3285 states, 2844 states have (on average 1.5028129395218002) internal successors, (4274), 2838 states have internal predecessors, (4274), 328 states have call successors, (328), 98 states have call predecessors, (328), 112 states have return successors, (421), 349 states have call predecessors, (421), 328 states have call successors, (421) [2022-12-14 14:10:00,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3285 states to 3285 states and 5023 transitions. [2022-12-14 14:10:00,229 INFO L78 Accepts]: Start accepts. Automaton has 3285 states and 5023 transitions. Word has length 70 [2022-12-14 14:10:00,229 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:00,230 INFO L495 AbstractCegarLoop]: Abstraction has 3285 states and 5023 transitions. [2022-12-14 14:10:00,230 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:00,230 INFO L276 IsEmpty]: Start isEmpty. Operand 3285 states and 5023 transitions. [2022-12-14 14:10:00,230 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:00,231 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:00,231 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:00,231 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-12-14 14:10:00,231 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:00,231 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:00,231 INFO L85 PathProgramCache]: Analyzing trace with hash 2137274517, now seen corresponding path program 1 times [2022-12-14 14:10:00,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:00,232 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828741281] [2022-12-14 14:10:00,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:00,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:00,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:00,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:00,302 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:00,303 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828741281] [2022-12-14 14:10:00,303 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828741281] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:00,303 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:00,303 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-14 14:10:00,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [397258816] [2022-12-14 14:10:00,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:00,303 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-12-14 14:10:00,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:00,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-14 14:10:00,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:10:00,304 INFO L87 Difference]: Start difference. First operand 3285 states and 5023 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:00,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:00,812 INFO L93 Difference]: Finished difference Result 9788 states and 15244 transitions. [2022-12-14 14:10:00,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-14 14:10:00,813 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:00,813 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:00,849 INFO L225 Difference]: With dead ends: 9788 [2022-12-14 14:10:00,849 INFO L226 Difference]: Without dead ends: 6508 [2022-12-14 14:10:00,857 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:10:00,858 INFO L413 NwaCegarLoop]: 469 mSDtfsCounter, 546 mSDsluCounter, 375 mSDsCounter, 0 mSdLazyCounter, 308 mSolverCounterSat, 5 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 546 SdHoareTripleChecker+Valid, 844 SdHoareTripleChecker+Invalid, 313 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 5 IncrementalHoareTripleChecker+Valid, 308 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:00,858 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [546 Valid, 844 Invalid, 313 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [5 Valid, 308 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-12-14 14:10:00,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6508 states. [2022-12-14 14:10:01,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6508 to 6488. [2022-12-14 14:10:01,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6488 states, 5627 states have (on average 1.4942242758130442) internal successors, (8408), 5615 states have internal predecessors, (8408), 636 states have call successors, (636), 196 states have call predecessors, (636), 224 states have return successors, (815), 677 states have call predecessors, (815), 636 states have call successors, (815) [2022-12-14 14:10:01,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6488 states to 6488 states and 9859 transitions. [2022-12-14 14:10:01,077 INFO L78 Accepts]: Start accepts. Automaton has 6488 states and 9859 transitions. Word has length 70 [2022-12-14 14:10:01,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:01,077 INFO L495 AbstractCegarLoop]: Abstraction has 6488 states and 9859 transitions. [2022-12-14 14:10:01,078 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:01,078 INFO L276 IsEmpty]: Start isEmpty. Operand 6488 states and 9859 transitions. [2022-12-14 14:10:01,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:01,078 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:01,078 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:01,078 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4 [2022-12-14 14:10:01,078 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:01,079 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:01,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1180346134, now seen corresponding path program 1 times [2022-12-14 14:10:01,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:01,079 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827589552] [2022-12-14 14:10:01,079 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:01,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:01,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:01,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:01,163 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:01,163 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1827589552] [2022-12-14 14:10:01,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1827589552] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:01,163 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:01,163 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:10:01,163 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1153315944] [2022-12-14 14:10:01,163 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:01,164 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:10:01,164 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:01,164 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:10:01,164 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:10:01,164 INFO L87 Difference]: Start difference. First operand 6488 states and 9859 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:02,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:02,128 INFO L93 Difference]: Finished difference Result 22090 states and 34226 transitions. [2022-12-14 14:10:02,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:10:02,129 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:02,129 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:02,201 INFO L225 Difference]: With dead ends: 22090 [2022-12-14 14:10:02,201 INFO L226 Difference]: Without dead ends: 15235 [2022-12-14 14:10:02,227 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:10:02,228 INFO L413 NwaCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:02,228 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-12-14 14:10:02,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15235 states. [2022-12-14 14:10:02,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15235 to 12705. [2022-12-14 14:10:02,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12705 states, 11028 states have (on average 1.4924737033006892) internal successors, (16459), 11032 states have internal predecessors, (16459), 1228 states have call successors, (1228), 388 states have call predecessors, (1228), 448 states have return successors, (1599), 1285 states have call predecessors, (1599), 1228 states have call successors, (1599) [2022-12-14 14:10:02,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12705 states to 12705 states and 19286 transitions. [2022-12-14 14:10:02,796 INFO L78 Accepts]: Start accepts. Automaton has 12705 states and 19286 transitions. Word has length 70 [2022-12-14 14:10:02,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:02,796 INFO L495 AbstractCegarLoop]: Abstraction has 12705 states and 19286 transitions. [2022-12-14 14:10:02,796 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:02,796 INFO L276 IsEmpty]: Start isEmpty. Operand 12705 states and 19286 transitions. [2022-12-14 14:10:02,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:02,797 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:02,797 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:02,797 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-12-14 14:10:02,797 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:02,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:02,797 INFO L85 PathProgramCache]: Analyzing trace with hash -396211625, now seen corresponding path program 1 times [2022-12-14 14:10:02,797 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:02,797 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749091270] [2022-12-14 14:10:02,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:02,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:02,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:02,881 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:02,881 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:02,882 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749091270] [2022-12-14 14:10:02,882 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749091270] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:02,882 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:02,882 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:10:02,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989015752] [2022-12-14 14:10:02,882 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:02,882 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:10:02,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:02,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:10:02,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:10:02,883 INFO L87 Difference]: Start difference. First operand 12705 states and 19286 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:04,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:04,409 INFO L93 Difference]: Finished difference Result 42693 states and 66139 transitions. [2022-12-14 14:10:04,409 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:10:04,409 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:04,410 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:04,488 INFO L225 Difference]: With dead ends: 42693 [2022-12-14 14:10:04,488 INFO L226 Difference]: Without dead ends: 29269 [2022-12-14 14:10:04,524 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:10:04,524 INFO L413 NwaCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:04,525 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-12-14 14:10:04,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29269 states. [2022-12-14 14:10:05,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29269 to 24995. [2022-12-14 14:10:05,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24995 states, 21718 states have (on average 1.4900543328114928) internal successors, (32361), 21754 states have internal predecessors, (32361), 2380 states have call successors, (2380), 772 states have call predecessors, (2380), 896 states have return successors, (3119), 2469 states have call predecessors, (3119), 2380 states have call successors, (3119) [2022-12-14 14:10:05,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24995 states to 24995 states and 37860 transitions. [2022-12-14 14:10:05,539 INFO L78 Accepts]: Start accepts. Automaton has 24995 states and 37860 transitions. Word has length 70 [2022-12-14 14:10:05,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:05,540 INFO L495 AbstractCegarLoop]: Abstraction has 24995 states and 37860 transitions. [2022-12-14 14:10:05,540 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:05,541 INFO L276 IsEmpty]: Start isEmpty. Operand 24995 states and 37860 transitions. [2022-12-14 14:10:05,541 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:05,541 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:05,541 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:05,542 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-12-14 14:10:05,542 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:05,542 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:05,542 INFO L85 PathProgramCache]: Analyzing trace with hash -2068729256, now seen corresponding path program 1 times [2022-12-14 14:10:05,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:05,543 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [741213783] [2022-12-14 14:10:05,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:05,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:05,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:05,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:05,655 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:05,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [741213783] [2022-12-14 14:10:05,655 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [741213783] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:05,655 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:05,655 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2022-12-14 14:10:05,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142753054] [2022-12-14 14:10:05,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:05,656 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-12-14 14:10:05,656 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:05,656 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-12-14 14:10:05,657 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2022-12-14 14:10:05,657 INFO L87 Difference]: Start difference. First operand 24995 states and 37860 transitions. Second operand has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:07,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:07,815 INFO L93 Difference]: Finished difference Result 83395 states and 128945 transitions. [2022-12-14 14:10:07,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-12-14 14:10:07,816 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:07,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:07,987 INFO L225 Difference]: With dead ends: 83395 [2022-12-14 14:10:07,988 INFO L226 Difference]: Without dead ends: 56993 [2022-12-14 14:10:08,049 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2022-12-14 14:10:08,050 INFO L413 NwaCegarLoop]: 497 mSDtfsCounter, 1120 mSDsluCounter, 617 mSDsCounter, 0 mSdLazyCounter, 449 mSolverCounterSat, 210 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1134 SdHoareTripleChecker+Valid, 1114 SdHoareTripleChecker+Invalid, 659 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 210 IncrementalHoareTripleChecker+Valid, 449 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:08,050 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1134 Valid, 1114 Invalid, 659 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [210 Valid, 449 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-12-14 14:10:08,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56993 states. [2022-12-14 14:10:10,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56993 to 49311. [2022-12-14 14:10:10,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49311 states, 42898 states have (on average 1.4872721338990162) internal successors, (63801), 42998 states have internal predecessors, (63801), 4620 states have call successors, (4620), 1540 states have call predecessors, (4620), 1792 states have return successors, (6063), 4773 states have call predecessors, (6063), 4620 states have call successors, (6063) [2022-12-14 14:10:10,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49311 states to 49311 states and 74484 transitions. [2022-12-14 14:10:10,316 INFO L78 Accepts]: Start accepts. Automaton has 49311 states and 74484 transitions. Word has length 70 [2022-12-14 14:10:10,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:10,317 INFO L495 AbstractCegarLoop]: Abstraction has 49311 states and 74484 transitions. [2022-12-14 14:10:10,317 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 12.0) internal successors, (60), 5 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:10,317 INFO L276 IsEmpty]: Start isEmpty. Operand 49311 states and 74484 transitions. [2022-12-14 14:10:10,317 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:10,317 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:10,317 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:10,317 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-12-14 14:10:10,318 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:10,318 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:10,318 INFO L85 PathProgramCache]: Analyzing trace with hash 635843063, now seen corresponding path program 1 times [2022-12-14 14:10:10,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:10,318 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001490133] [2022-12-14 14:10:10,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:10,318 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:10,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:10,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:10,374 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:10,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001490133] [2022-12-14 14:10:10,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001490133] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:10,375 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:10,375 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-12-14 14:10:10,375 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22530931] [2022-12-14 14:10:10,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:10,375 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-12-14 14:10:10,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:10,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-12-14 14:10:10,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:10:10,376 INFO L87 Difference]: Start difference. First operand 49311 states and 74484 transitions. Second operand has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:14,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:14,317 INFO L93 Difference]: Finished difference Result 155298 states and 238567 transitions. [2022-12-14 14:10:14,317 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-12-14 14:10:14,317 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:14,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:14,747 INFO L225 Difference]: With dead ends: 155298 [2022-12-14 14:10:14,747 INFO L226 Difference]: Without dead ends: 105992 [2022-12-14 14:10:14,865 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-12-14 14:10:14,866 INFO L413 NwaCegarLoop]: 494 mSDtfsCounter, 558 mSDsluCounter, 624 mSDsCounter, 0 mSdLazyCounter, 352 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 558 SdHoareTripleChecker+Valid, 1118 SdHoareTripleChecker+Invalid, 354 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 352 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:14,866 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [558 Valid, 1118 Invalid, 354 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 352 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-12-14 14:10:14,942 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105992 states. [2022-12-14 14:10:17,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105992 to 55633. [2022-12-14 14:10:17,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55633 states, 48829 states have (on average 1.4798992402056155) internal successors, (72262), 49025 states have internal predecessors, (72262), 4815 states have call successors, (4815), 1672 states have call predecessors, (4815), 1988 states have return successors, (6351), 4936 states have call predecessors, (6351), 4815 states have call successors, (6351) [2022-12-14 14:10:17,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55633 states to 55633 states and 83428 transitions. [2022-12-14 14:10:17,777 INFO L78 Accepts]: Start accepts. Automaton has 55633 states and 83428 transitions. Word has length 70 [2022-12-14 14:10:17,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:17,777 INFO L495 AbstractCegarLoop]: Abstraction has 55633 states and 83428 transitions. [2022-12-14 14:10:17,778 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 15.0) internal successors, (60), 4 states have internal predecessors, (60), 2 states have call successors, (5), 1 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:17,778 INFO L276 IsEmpty]: Start isEmpty. Operand 55633 states and 83428 transitions. [2022-12-14 14:10:17,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2022-12-14 14:10:17,778 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:17,778 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:17,778 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8 [2022-12-14 14:10:17,778 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:17,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:17,779 INFO L85 PathProgramCache]: Analyzing trace with hash 1776194774, now seen corresponding path program 1 times [2022-12-14 14:10:17,779 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:17,779 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415866864] [2022-12-14 14:10:17,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:17,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:17,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-12-14 14:10:17,948 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-12-14 14:10:17,948 INFO L136 FreeRefinementEngine]: Strategy SIFA_TAIPAN found an infeasible trace [2022-12-14 14:10:17,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [415866864] [2022-12-14 14:10:17,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [415866864] provided 1 perfect and 0 imperfect interpolant sequences [2022-12-14 14:10:17,948 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-12-14 14:10:17,949 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-12-14 14:10:17,949 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999108087] [2022-12-14 14:10:17,949 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-12-14 14:10:17,949 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-12-14 14:10:17,949 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy SIFA_TAIPAN [2022-12-14 14:10:17,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-12-14 14:10:17,950 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-12-14 14:10:17,950 INFO L87 Difference]: Start difference. First operand 55633 states and 83428 transitions. Second operand has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:22,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-12-14 14:10:22,595 INFO L93 Difference]: Finished difference Result 171545 states and 258300 transitions. [2022-12-14 14:10:22,595 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-12-14 14:10:22,596 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) Word has length 70 [2022-12-14 14:10:22,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-12-14 14:10:22,955 INFO L225 Difference]: With dead ends: 171545 [2022-12-14 14:10:22,955 INFO L226 Difference]: Without dead ends: 119850 [2022-12-14 14:10:23,073 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 6 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2022-12-14 14:10:23,074 INFO L413 NwaCegarLoop]: 267 mSDtfsCounter, 1112 mSDsluCounter, 696 mSDsCounter, 0 mSdLazyCounter, 398 mSolverCounterSat, 157 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 1119 SdHoareTripleChecker+Valid, 963 SdHoareTripleChecker+Invalid, 555 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 157 IncrementalHoareTripleChecker+Valid, 398 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-12-14 14:10:23,074 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [1119 Valid, 963 Invalid, 555 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [157 Valid, 398 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-12-14 14:10:23,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119850 states. [2022-12-14 14:10:27,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119850 to 90714. [2022-12-14 14:10:27,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90714 states, 80251 states have (on average 1.4712340033146005) internal successors, (118068), 80546 states have internal predecessors, (118068), 7192 states have call successors, (7192), 2702 states have call predecessors, (7192), 3270 states have return successors, (10171), 7466 states have call predecessors, (10171), 7192 states have call successors, (10171) [2022-12-14 14:10:27,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90714 states to 90714 states and 135431 transitions. [2022-12-14 14:10:27,871 INFO L78 Accepts]: Start accepts. Automaton has 90714 states and 135431 transitions. Word has length 70 [2022-12-14 14:10:27,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-12-14 14:10:27,871 INFO L495 AbstractCegarLoop]: Abstraction has 90714 states and 135431 transitions. [2022-12-14 14:10:27,871 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 10.0) internal successors, (60), 6 states have internal predecessors, (60), 2 states have call successors, (5), 2 states have call predecessors, (5), 2 states have return successors, (5), 2 states have call predecessors, (5), 2 states have call successors, (5) [2022-12-14 14:10:27,871 INFO L276 IsEmpty]: Start isEmpty. Operand 90714 states and 135431 transitions. [2022-12-14 14:10:27,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2022-12-14 14:10:27,872 INFO L187 NwaCegarLoop]: Found error trace [2022-12-14 14:10:27,872 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:27,872 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-12-14 14:10:27,872 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION === [ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-12-14 14:10:27,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-12-14 14:10:27,872 INFO L85 PathProgramCache]: Analyzing trace with hash -819877656, now seen corresponding path program 1 times [2022-12-14 14:10:27,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy SIFA_TAIPAN [2022-12-14 14:10:27,872 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727026737] [2022-12-14 14:10:27,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-12-14 14:10:27,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-12-14 14:10:27,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 14:10:27,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-12-14 14:10:27,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-12-14 14:10:27,983 INFO L130 FreeRefinementEngine]: Strategy SIFA_TAIPAN found a feasible trace [2022-12-14 14:10:27,983 INFO L360 BasicCegarLoop]: Counterexample is feasible [2022-12-14 14:10:27,984 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location ULTIMATE.startErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-12-14 14:10:27,986 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10 [2022-12-14 14:10:27,989 INFO L445 BasicCegarLoop]: Path program histogram: [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-12-14 14:10:27,993 INFO L178 ceAbstractionStarter]: Computing trace abstraction results [2022-12-14 14:10:28,118 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.12 02:10:28 BoogieIcfgContainer [2022-12-14 14:10:28,118 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-12-14 14:10:28,119 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2022-12-14 14:10:28,119 INFO L271 PluginConnector]: Initializing Witness Printer... [2022-12-14 14:10:28,119 INFO L275 PluginConnector]: Witness Printer initialized [2022-12-14 14:10:28,119 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.12 02:09:56" (3/4) ... [2022-12-14 14:10:28,121 INFO L131 WitnessPrinter]: Generating witness for reachability counterexample [2022-12-14 14:10:28,244 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/witness.graphml [2022-12-14 14:10:28,244 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2022-12-14 14:10:28,244 INFO L158 Benchmark]: Toolchain (without parser) took 33125.33ms. Allocated memory was 138.4MB in the beginning and 5.1GB in the end (delta: 5.0GB). Free memory was 101.9MB in the beginning and 2.6GB in the end (delta: -2.5GB). Peak memory consumption was 2.5GB. Max. memory is 16.1GB. [2022-12-14 14:10:28,245 INFO L158 Benchmark]: CDTParser took 0.14ms. Allocated memory is still 138.4MB. Free memory is still 110.6MB. There was no memory consumed. Max. memory is 16.1GB. [2022-12-14 14:10:28,245 INFO L158 Benchmark]: CACSL2BoogieTranslator took 314.59ms. Allocated memory is still 138.4MB. Free memory was 101.7MB in the beginning and 77.2MB in the end (delta: 24.5MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2022-12-14 14:10:28,245 INFO L158 Benchmark]: Boogie Procedure Inliner took 47.96ms. Allocated memory is still 138.4MB. Free memory was 77.2MB in the beginning and 73.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-14 14:10:28,245 INFO L158 Benchmark]: Boogie Preprocessor took 36.90ms. Allocated memory is still 138.4MB. Free memory was 73.0MB in the beginning and 68.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2022-12-14 14:10:28,246 INFO L158 Benchmark]: RCFGBuilder took 1257.90ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 68.8MB in the beginning and 109.8MB in the end (delta: -41.0MB). Peak memory consumption was 58.0MB. Max. memory is 16.1GB. [2022-12-14 14:10:28,246 INFO L158 Benchmark]: TraceAbstraction took 31338.06ms. Allocated memory was 167.8MB in the beginning and 5.1GB in the end (delta: 4.9GB). Free memory was 108.7MB in the beginning and 2.6GB in the end (delta: -2.5GB). Peak memory consumption was 2.4GB. Max. memory is 16.1GB. [2022-12-14 14:10:28,246 INFO L158 Benchmark]: Witness Printer took 125.22ms. Allocated memory is still 5.1GB. Free memory was 2.6GB in the beginning and 2.6GB in the end (delta: 21.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. [2022-12-14 14:10:28,248 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14ms. Allocated memory is still 138.4MB. Free memory is still 110.6MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 314.59ms. Allocated memory is still 138.4MB. Free memory was 101.7MB in the beginning and 77.2MB in the end (delta: 24.5MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 47.96ms. Allocated memory is still 138.4MB. Free memory was 77.2MB in the beginning and 73.0MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 36.90ms. Allocated memory is still 138.4MB. Free memory was 73.0MB in the beginning and 68.8MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1257.90ms. Allocated memory was 138.4MB in the beginning and 167.8MB in the end (delta: 29.4MB). Free memory was 68.8MB in the beginning and 109.8MB in the end (delta: -41.0MB). Peak memory consumption was 58.0MB. Max. memory is 16.1GB. * TraceAbstraction took 31338.06ms. Allocated memory was 167.8MB in the beginning and 5.1GB in the end (delta: 4.9GB). Free memory was 108.7MB in the beginning and 2.6GB in the end (delta: -2.5GB). Peak memory consumption was 2.4GB. Max. memory is 16.1GB. * Witness Printer took 125.22ms. Allocated memory is still 5.1GB. Free memory was 2.6GB in the beginning and 2.6GB in the end (delta: 21.9MB). Peak memory consumption was 21.0MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 21]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int t8_pc = 0; [L34] int t9_pc = 0; [L35] int t10_pc = 0; [L36] int t11_pc = 0; [L37] int t12_pc = 0; [L38] int t13_pc = 0; [L39] int t14_pc = 0; [L40] int m_st ; [L41] int t1_st ; [L42] int t2_st ; [L43] int t3_st ; [L44] int t4_st ; [L45] int t5_st ; [L46] int t6_st ; [L47] int t7_st ; [L48] int t8_st ; [L49] int t9_st ; [L50] int t10_st ; [L51] int t11_st ; [L52] int t12_st ; [L53] int t13_st ; [L54] int t14_st ; [L55] int m_i ; [L56] int t1_i ; [L57] int t2_i ; [L58] int t3_i ; [L59] int t4_i ; [L60] int t5_i ; [L61] int t6_i ; [L62] int t7_i ; [L63] int t8_i ; [L64] int t9_i ; [L65] int t10_i ; [L66] int t11_i ; [L67] int t12_i ; [L68] int t13_i ; [L69] int t14_i ; [L70] int M_E = 2; [L71] int T1_E = 2; [L72] int T2_E = 2; [L73] int T3_E = 2; [L74] int T4_E = 2; [L75] int T5_E = 2; [L76] int T6_E = 2; [L77] int T7_E = 2; [L78] int T8_E = 2; [L79] int T9_E = 2; [L80] int T10_E = 2; [L81] int T11_E = 2; [L82] int T12_E = 2; [L83] int T13_E = 2; [L84] int T14_E = 2; [L85] int E_1 = 2; [L86] int E_2 = 2; [L87] int E_3 = 2; [L88] int E_4 = 2; [L89] int E_5 = 2; [L90] int E_6 = 2; [L91] int E_7 = 2; [L92] int E_8 = 2; [L93] int E_9 = 2; [L94] int E_10 = 2; [L95] int E_11 = 2; [L96] int E_12 = 2; [L97] int E_13 = 2; [L98] int E_14 = 2; [L2062] int __retres1 ; [L2066] CALL init_model() [L1964] m_i = 1 [L1965] t1_i = 1 [L1966] t2_i = 1 [L1967] t3_i = 1 [L1968] t4_i = 1 [L1969] t5_i = 1 [L1970] t6_i = 1 [L1971] t7_i = 1 [L1972] t8_i = 1 [L1973] t9_i = 1 [L1974] t10_i = 1 [L1975] t11_i = 1 [L1976] t12_i = 1 [L1977] t13_i = 1 [L1978] t14_i = 1 [L2066] RET init_model() [L2067] CALL start_simulation() [L2003] int kernel_st ; [L2004] int tmp ; [L2005] int tmp___0 ; [L2009] kernel_st = 0 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2010] FCALL update_channels() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2011] CALL init_threads() [L939] COND TRUE m_i == 1 [L940] m_st = 0 [L944] COND TRUE t1_i == 1 [L945] t1_st = 0 [L949] COND TRUE t2_i == 1 [L950] t2_st = 0 [L954] COND TRUE t3_i == 1 [L955] t3_st = 0 [L959] COND TRUE t4_i == 1 [L960] t4_st = 0 [L964] COND TRUE t5_i == 1 [L965] t5_st = 0 [L969] COND TRUE t6_i == 1 [L970] t6_st = 0 [L974] COND TRUE t7_i == 1 [L975] t7_st = 0 [L979] COND TRUE t8_i == 1 [L980] t8_st = 0 [L984] COND TRUE t9_i == 1 [L985] t9_st = 0 [L989] COND TRUE t10_i == 1 [L990] t10_st = 0 [L994] COND TRUE t11_i == 1 [L995] t11_st = 0 [L999] COND TRUE t12_i == 1 [L1000] t12_st = 0 [L1004] COND TRUE t13_i == 1 [L1005] t13_st = 0 [L1009] COND TRUE t14_i == 1 [L1010] t14_st = 0 [L2011] RET init_threads() [L2012] CALL fire_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1342] COND FALSE !(M_E == 0) [L1347] COND FALSE !(T1_E == 0) [L1352] COND FALSE !(T2_E == 0) [L1357] COND FALSE !(T3_E == 0) [L1362] COND FALSE !(T4_E == 0) [L1367] COND FALSE !(T5_E == 0) [L1372] COND FALSE !(T6_E == 0) [L1377] COND FALSE !(T7_E == 0) [L1382] COND FALSE !(T8_E == 0) [L1387] COND FALSE !(T9_E == 0) [L1392] COND FALSE !(T10_E == 0) [L1397] COND FALSE !(T11_E == 0) [L1402] COND FALSE !(T12_E == 0) [L1407] COND FALSE !(T13_E == 0) [L1412] COND FALSE !(T14_E == 0) [L1417] COND FALSE !(E_1 == 0) [L1422] COND FALSE !(E_2 == 0) [L1427] COND FALSE !(E_3 == 0) [L1432] COND FALSE !(E_4 == 0) [L1437] COND FALSE !(E_5 == 0) [L1442] COND FALSE !(E_6 == 0) [L1447] COND FALSE !(E_7 == 0) [L1452] COND FALSE !(E_8 == 0) [L1457] COND FALSE !(E_9 == 0) [L1462] COND FALSE !(E_10 == 0) [L1467] COND FALSE !(E_11 == 0) [L1472] COND FALSE !(E_12 == 0) [L1477] COND FALSE !(E_13 == 0) [L1482] COND FALSE !(E_14 == 0) [L2012] RET fire_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2013] CALL activate_threads() VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1645] int tmp ; [L1646] int tmp___0 ; [L1647] int tmp___1 ; [L1648] int tmp___2 ; [L1649] int tmp___3 ; [L1650] int tmp___4 ; [L1651] int tmp___5 ; [L1652] int tmp___6 ; [L1653] int tmp___7 ; [L1654] int tmp___8 ; [L1655] int tmp___9 ; [L1656] int tmp___10 ; [L1657] int tmp___11 ; [L1658] int tmp___12 ; [L1659] int tmp___13 ; [L1664] CALL, EXPR is_master_triggered() [L643] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L646] COND FALSE !(m_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L656] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L658] return (__retres1); [L1664] RET, EXPR is_master_triggered() [L1664] tmp = is_master_triggered() [L1666] COND FALSE !(\read(tmp)) [L1672] CALL, EXPR is_transmit1_triggered() [L662] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L665] COND FALSE !(t1_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L675] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L677] return (__retres1); [L1672] RET, EXPR is_transmit1_triggered() [L1672] tmp___0 = is_transmit1_triggered() [L1674] COND FALSE !(\read(tmp___0)) [L1680] CALL, EXPR is_transmit2_triggered() [L681] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L684] COND FALSE !(t2_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L694] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L696] return (__retres1); [L1680] RET, EXPR is_transmit2_triggered() [L1680] tmp___1 = is_transmit2_triggered() [L1682] COND FALSE !(\read(tmp___1)) [L1688] CALL, EXPR is_transmit3_triggered() [L700] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L703] COND FALSE !(t3_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L713] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L715] return (__retres1); [L1688] RET, EXPR is_transmit3_triggered() [L1688] tmp___2 = is_transmit3_triggered() [L1690] COND FALSE !(\read(tmp___2)) [L1696] CALL, EXPR is_transmit4_triggered() [L719] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L722] COND FALSE !(t4_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L732] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L734] return (__retres1); [L1696] RET, EXPR is_transmit4_triggered() [L1696] tmp___3 = is_transmit4_triggered() [L1698] COND FALSE !(\read(tmp___3)) [L1704] CALL, EXPR is_transmit5_triggered() [L738] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L741] COND FALSE !(t5_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L751] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L753] return (__retres1); [L1704] RET, EXPR is_transmit5_triggered() [L1704] tmp___4 = is_transmit5_triggered() [L1706] COND FALSE !(\read(tmp___4)) [L1712] CALL, EXPR is_transmit6_triggered() [L757] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L760] COND FALSE !(t6_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L770] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L772] return (__retres1); [L1712] RET, EXPR is_transmit6_triggered() [L1712] tmp___5 = is_transmit6_triggered() [L1714] COND FALSE !(\read(tmp___5)) [L1720] CALL, EXPR is_transmit7_triggered() [L776] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L779] COND FALSE !(t7_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L789] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L791] return (__retres1); [L1720] RET, EXPR is_transmit7_triggered() [L1720] tmp___6 = is_transmit7_triggered() [L1722] COND FALSE !(\read(tmp___6)) [L1728] CALL, EXPR is_transmit8_triggered() [L795] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L798] COND FALSE !(t8_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L808] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L810] return (__retres1); [L1728] RET, EXPR is_transmit8_triggered() [L1728] tmp___7 = is_transmit8_triggered() [L1730] COND FALSE !(\read(tmp___7)) [L1736] CALL, EXPR is_transmit9_triggered() [L814] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L817] COND FALSE !(t9_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L827] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L829] return (__retres1); [L1736] RET, EXPR is_transmit9_triggered() [L1736] tmp___8 = is_transmit9_triggered() [L1738] COND FALSE !(\read(tmp___8)) [L1744] CALL, EXPR is_transmit10_triggered() [L833] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L836] COND FALSE !(t10_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L846] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L848] return (__retres1); [L1744] RET, EXPR is_transmit10_triggered() [L1744] tmp___9 = is_transmit10_triggered() [L1746] COND FALSE !(\read(tmp___9)) [L1752] CALL, EXPR is_transmit11_triggered() [L852] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L855] COND FALSE !(t11_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L865] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L867] return (__retres1); [L1752] RET, EXPR is_transmit11_triggered() [L1752] tmp___10 = is_transmit11_triggered() [L1754] COND FALSE !(\read(tmp___10)) [L1760] CALL, EXPR is_transmit12_triggered() [L871] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L874] COND FALSE !(t12_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L884] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L886] return (__retres1); [L1760] RET, EXPR is_transmit12_triggered() [L1760] tmp___11 = is_transmit12_triggered() [L1762] COND FALSE !(\read(tmp___11)) [L1768] CALL, EXPR is_transmit13_triggered() [L890] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L893] COND FALSE !(t13_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L903] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L905] return (__retres1); [L1768] RET, EXPR is_transmit13_triggered() [L1768] tmp___12 = is_transmit13_triggered() [L1770] COND FALSE !(\read(tmp___12)) [L1776] CALL, EXPR is_transmit14_triggered() [L909] int __retres1 ; VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L912] COND FALSE !(t14_pc == 1) VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L922] __retres1 = 0 VAL [\old(m_st)=0, \old(t10_st)=0, \old(t11_st)=0, \old(t12_st)=0, \old(t13_st)=0, \old(t14_st)=0, \old(t1_st)=0, \old(t2_st)=0, \old(t3_st)=0, \old(t4_st)=0, \old(t5_st)=0, \old(t6_st)=0, \old(t7_st)=0, \old(t8_st)=0, \old(t9_st)=0, __retres1=0, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L924] return (__retres1); [L1776] RET, EXPR is_transmit14_triggered() [L1776] tmp___13 = is_transmit14_triggered() [L1778] COND FALSE !(\read(tmp___13)) [L2013] RET activate_threads() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2014] CALL reset_delta_events() VAL [\old(E_1)=2, \old(E_10)=2, \old(E_11)=2, \old(E_12)=2, \old(E_13)=2, \old(E_14)=2, \old(E_2)=2, \old(E_3)=2, \old(E_4)=2, \old(E_5)=2, \old(E_6)=2, \old(E_7)=2, \old(E_8)=2, \old(E_9)=2, \old(M_E)=2, \old(T10_E)=2, \old(T11_E)=2, \old(T12_E)=2, \old(T13_E)=2, \old(T14_E)=2, \old(T1_E)=2, \old(T2_E)=2, \old(T3_E)=2, \old(T4_E)=2, \old(T5_E)=2, \old(T6_E)=2, \old(T7_E)=2, \old(T8_E)=2, \old(T9_E)=2, E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1495] COND FALSE !(M_E == 1) [L1500] COND FALSE !(T1_E == 1) [L1505] COND FALSE !(T2_E == 1) [L1510] COND FALSE !(T3_E == 1) [L1515] COND FALSE !(T4_E == 1) [L1520] COND FALSE !(T5_E == 1) [L1525] COND FALSE !(T6_E == 1) [L1530] COND FALSE !(T7_E == 1) [L1535] COND FALSE !(T8_E == 1) [L1540] COND FALSE !(T9_E == 1) [L1545] COND FALSE !(T10_E == 1) [L1550] COND FALSE !(T11_E == 1) [L1555] COND FALSE !(T12_E == 1) [L1560] COND FALSE !(T13_E == 1) [L1565] COND FALSE !(T14_E == 1) [L1570] COND FALSE !(E_1 == 1) [L1575] COND FALSE !(E_2 == 1) [L1580] COND FALSE !(E_3 == 1) [L1585] COND FALSE !(E_4 == 1) [L1590] COND FALSE !(E_5 == 1) [L1595] COND FALSE !(E_6 == 1) [L1600] COND FALSE !(E_7 == 1) [L1605] COND FALSE !(E_8 == 1) [L1610] COND FALSE !(E_9 == 1) [L1615] COND FALSE !(E_10 == 1) [L1620] COND FALSE !(E_11 == 1) [L1625] COND FALSE !(E_12 == 1) [L1630] COND FALSE !(E_13 == 1) [L1635] COND FALSE !(E_14 == 1) [L2014] RET reset_delta_events() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, kernel_st=0, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L2017] COND TRUE 1 [L2020] kernel_st = 1 [L2021] CALL eval() [L1106] int tmp ; VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1110] COND TRUE 1 VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1113] CALL, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1019] int __retres1 ; [L1022] COND TRUE m_st == 0 [L1023] __retres1 = 1 [L1101] return (__retres1); [L1113] RET, EXPR exists_runnable_thread() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, exists_runnable_thread()=1, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] [L1113] tmp = exists_runnable_thread() [L1115] COND TRUE \read(tmp) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1] [L1120] COND TRUE m_st == 0 [L1121] int tmp_ndt_1; [L1122] tmp_ndt_1 = __VERIFIER_nondet_int() [L1123] COND FALSE !(\read(tmp_ndt_1)) VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0, tmp=1, tmp_ndt_1=0] [L1134] COND TRUE t1_st == 0 [L1135] int tmp_ndt_2; [L1136] tmp_ndt_2 = __VERIFIER_nondet_int() [L1137] COND FALSE !(\read(tmp_ndt_2)) [L1143] CALL error() [L21] reach_error() VAL [E_1=2, E_10=2, E_11=2, E_12=2, E_13=2, E_14=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, E_8=2, E_9=2, M_E=2, m_i=1, m_pc=0, m_st=0, T10_E=2, t10_i=1, t10_pc=0, t10_st=0, T11_E=2, t11_i=1, t11_pc=0, t11_st=0, T12_E=2, t12_i=1, t12_pc=0, t12_st=0, T13_E=2, t13_i=1, t13_pc=0, t13_st=0, T14_E=2, t14_i=1, t14_pc=0, t14_st=0, T1_E=2, t1_i=1, t1_pc=0, t1_st=0, T2_E=2, t2_i=1, t2_pc=0, t2_st=0, T3_E=2, t3_i=1, t3_pc=0, t3_st=0, T4_E=2, t4_i=1, t4_pc=0, t4_st=0, T5_E=2, t5_i=1, t5_pc=0, t5_st=0, T6_E=2, t6_i=1, t6_pc=0, t6_st=0, T7_E=2, t7_i=1, t7_pc=0, t7_st=0, T8_E=2, t8_i=1, t8_pc=0, t8_st=0, T9_E=2, t9_i=1, t9_pc=0, t9_st=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 7 procedures, 197 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 31.2s, OverallIterations: 11, TraceHistogramMax: 1, PathProgramHistogramMax: 1, EmptinessCheckTime: 0.0s, AutomataDifference: 17.6s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 9552 SdHoareTripleChecker+Valid, 4.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 9461 mSDsluCounter, 10691 SdHoareTripleChecker+Invalid, 3.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 6003 mSDsCounter, 1438 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 4114 IncrementalHoareTripleChecker+Invalid, 5552 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1438 mSolverCounterUnsat, 4688 mSDtfsCounter, 4114 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 81 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=90714occurred in iteration=10, InterpolantAutomatonStates: 50, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 12.0s AutomataMinimizationTime, 10 MinimizatonAttempts, 95303 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.1s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 1.0s InterpolantComputationTime, 771 NumberOfCodeBlocks, 771 NumberOfCodeBlocksAsserted, 11 NumberOfCheckSat, 690 ConstructedInterpolants, 0 QuantifiedInterpolants, 1836 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 10 InterpolantComputations, 10 PerfectInterpolantSequences, 0/0 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-12-14 14:10:28,264 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7195f8ee-bdee-40ce-9950-3dbc3244323b/bin/utaipan-gh47qXpMRh/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE