./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ef4a52e45666a829b602608a46cff9c8137910dd58bdfaebe016ce17984d1ac8 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:36:18,314 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:36:18,444 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:36:18,454 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:36:18,455 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:36:18,499 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:36:18,500 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:36:18,501 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:36:18,502 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:36:18,507 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:36:18,508 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:36:18,509 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:36:18,509 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:36:18,511 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:36:18,512 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:36:18,512 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:36:18,513 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:36:18,514 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:36:18,514 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:36:18,515 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:36:18,515 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:36:18,516 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:36:18,516 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:36:18,517 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:36:18,517 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:36:18,517 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:36:18,518 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:36:18,518 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:36:18,519 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:36:18,519 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:36:18,520 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:36:18,521 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:36:18,521 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:36:18,521 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:36:18,522 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:36:18,522 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:36:18,523 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ef4a52e45666a829b602608a46cff9c8137910dd58bdfaebe016ce17984d1ac8 [2023-11-06 22:36:18,893 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:36:18,935 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:36:18,938 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:36:18,940 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:36:18,941 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:36:18,942 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c [2023-11-06 22:36:22,286 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:36:22,588 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:36:22,589 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/sv-benchmarks/c/ldv-memsafety/ArraysWithLenghtAtDeclaration.c [2023-11-06 22:36:22,601 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/data/af083e9a2/3dda54545ef243fb8fc638112d2854d1/FLAG503439a93 [2023-11-06 22:36:22,619 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/data/af083e9a2/3dda54545ef243fb8fc638112d2854d1 [2023-11-06 22:36:22,625 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:36:22,628 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:36:22,631 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:36:22,633 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:36:22,639 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:36:22,640 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,641 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3364e0ff and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22, skipping insertion in model container [2023-11-06 22:36:22,641 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,666 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:36:22,844 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:36:22,859 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:36:22,877 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:36:22,894 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:36:22,895 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22 WrapperNode [2023-11-06 22:36:22,895 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:36:22,896 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:36:22,897 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:36:22,897 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:36:22,906 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,917 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,941 INFO L138 Inliner]: procedures = 8, calls = 14, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 65 [2023-11-06 22:36:22,941 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:36:22,942 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:36:22,942 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:36:22,943 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:36:22,953 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,953 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,955 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,956 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,961 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,966 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,967 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,969 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,971 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:36:22,972 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:36:22,972 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:36:22,972 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:36:22,974 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (1/1) ... [2023-11-06 22:36:22,981 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:23,001 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:23,015 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:23,022 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:36:23,056 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2023-11-06 22:36:23,056 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:36:23,057 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:36:23,057 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2023-11-06 22:36:23,057 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-06 22:36:23,057 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-06 22:36:23,151 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:36:23,153 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:36:23,400 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:36:23,406 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:36:23,407 INFO L302 CfgBuilder]: Removed 3 assume(true) statements. [2023-11-06 22:36:23,409 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:36:23 BoogieIcfgContainer [2023-11-06 22:36:23,409 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:36:23,411 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:36:23,411 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:36:23,416 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:36:23,417 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:36:23,417 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:36:22" (1/3) ... [2023-11-06 22:36:23,419 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4284ba5f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:36:23, skipping insertion in model container [2023-11-06 22:36:23,422 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:36:23,422 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:36:22" (2/3) ... [2023-11-06 22:36:23,423 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4284ba5f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:36:23, skipping insertion in model container [2023-11-06 22:36:23,423 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:36:23,423 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:36:23" (3/3) ... [2023-11-06 22:36:23,425 INFO L332 chiAutomizerObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration.c [2023-11-06 22:36:23,495 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:36:23,495 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:36:23,495 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:36:23,496 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:36:23,500 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:36:23,500 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:36:23,501 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:36:23,501 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:36:23,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:23,528 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-06 22:36:23,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:23,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:23,536 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-06 22:36:23,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-06 22:36:23,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:36:23,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:23,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-06 22:36:23,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:23,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:23,540 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-06 22:36:23,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-06 22:36:23,550 INFO L748 eck$LassoCheckResult]: Stem: 15#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 16#L26-3true [2023-11-06 22:36:23,551 INFO L750 eck$LassoCheckResult]: Loop: 16#L26-3true assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8#L17-3true assume !(foo_~i~0#1 <= foo_~size#1); 9#L17-4true foo_#res#1 := foo_~i~0#1; 3#foo_returnLabel#1true main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 14#L26-2true main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L26-3true [2023-11-06 22:36:23,558 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:23,558 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-06 22:36:23,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:23,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934041265] [2023-11-06 22:36:23,571 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:23,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:23,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:23,743 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:23,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:23,793 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:23,798 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:23,798 INFO L85 PathProgramCache]: Analyzing trace with hash 38364915, now seen corresponding path program 1 times [2023-11-06 22:36:23,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:23,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928944674] [2023-11-06 22:36:23,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:23,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:23,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:23,869 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:23,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:23,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:23,911 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:23,911 INFO L85 PathProgramCache]: Analyzing trace with hash 1809804401, now seen corresponding path program 1 times [2023-11-06 22:36:23,912 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:23,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [729023216] [2023-11-06 22:36:23,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:23,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:23,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:24,261 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:24,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:24,262 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [729023216] [2023-11-06 22:36:24,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [729023216] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:36:24,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:36:24,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-06 22:36:24,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1690862579] [2023-11-06 22:36:24,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:36:24,476 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:24,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:36:24,541 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:36:24,544 INFO L87 Difference]: Start difference. First operand has 17 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 4 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:24,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:24,660 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2023-11-06 22:36:24,662 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 35 transitions. [2023-11-06 22:36:24,665 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 11 [2023-11-06 22:36:24,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 23 states and 26 transitions. [2023-11-06 22:36:24,671 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2023-11-06 22:36:24,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2023-11-06 22:36:24,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 26 transitions. [2023-11-06 22:36:24,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:36:24,673 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 26 transitions. [2023-11-06 22:36:24,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 26 transitions. [2023-11-06 22:36:24,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 14. [2023-11-06 22:36:24,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.1428571428571428) internal successors, (16), 13 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:24,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 16 transitions. [2023-11-06 22:36:24,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 16 transitions. [2023-11-06 22:36:24,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:36:24,715 INFO L428 stractBuchiCegarLoop]: Abstraction has 14 states and 16 transitions. [2023-11-06 22:36:24,715 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:36:24,716 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 16 transitions. [2023-11-06 22:36:24,717 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-06 22:36:24,717 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:24,717 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:24,718 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2023-11-06 22:36:24,718 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:36:24,719 INFO L748 eck$LassoCheckResult]: Stem: 70#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 71#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 73#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 72#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 61#L17-2 [2023-11-06 22:36:24,719 INFO L750 eck$LassoCheckResult]: Loop: 61#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 62#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 61#L17-2 [2023-11-06 22:36:24,720 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:24,720 INFO L85 PathProgramCache]: Analyzing trace with hash 925771, now seen corresponding path program 1 times [2023-11-06 22:36:24,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:24,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1194271638] [2023-11-06 22:36:24,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:24,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:24,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:24,755 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:24,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:24,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:24,792 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:24,792 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 1 times [2023-11-06 22:36:24,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:24,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086775888] [2023-11-06 22:36:24,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:24,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:24,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:24,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:24,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:24,811 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:24,812 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:24,812 INFO L85 PathProgramCache]: Analyzing trace with hash 889666569, now seen corresponding path program 1 times [2023-11-06 22:36:24,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:24,813 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [489743257] [2023-11-06 22:36:24,813 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:24,813 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:24,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:24,980 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:24,981 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:24,981 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [489743257] [2023-11-06 22:36:24,982 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [489743257] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:24,982 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1974853453] [2023-11-06 22:36:24,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:24,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:24,983 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:24,995 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:25,000 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2023-11-06 22:36:25,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:25,089 INFO L262 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-06 22:36:25,093 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:25,202 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:25,203 INFO L323 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2023-11-06 22:36:25,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1974853453] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:36:25,205 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2023-11-06 22:36:25,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [4] total 7 [2023-11-06 22:36:25,208 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2518095] [2023-11-06 22:36:25,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:36:25,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:25,299 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:36:25,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2023-11-06 22:36:25,300 INFO L87 Difference]: Start difference. First operand 14 states and 16 transitions. cyclomatic complexity: 4 Second operand has 5 states, 4 states have (on average 1.5) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:25,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:25,413 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2023-11-06 22:36:25,414 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 24 transitions. [2023-11-06 22:36:25,421 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-06 22:36:25,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 24 transitions. [2023-11-06 22:36:25,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-06 22:36:25,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2023-11-06 22:36:25,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 24 transitions. [2023-11-06 22:36:25,424 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:36:25,424 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 24 transitions. [2023-11-06 22:36:25,424 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 24 transitions. [2023-11-06 22:36:25,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 16. [2023-11-06 22:36:25,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.125) internal successors, (18), 15 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:25,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 18 transitions. [2023-11-06 22:36:25,428 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 18 transitions. [2023-11-06 22:36:25,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2023-11-06 22:36:25,429 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 18 transitions. [2023-11-06 22:36:25,429 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:36:25,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 18 transitions. [2023-11-06 22:36:25,431 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2023-11-06 22:36:25,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:25,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:25,432 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2023-11-06 22:36:25,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2023-11-06 22:36:25,432 INFO L748 eck$LassoCheckResult]: Stem: 138#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 140#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 141#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 142#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 144#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 143#L17-4 [2023-11-06 22:36:25,433 INFO L750 eck$LassoCheckResult]: Loop: 143#L17-4 foo_#res#1 := foo_~i~0#1; 131#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 132#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 136#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 130#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 143#L17-4 [2023-11-06 22:36:25,433 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:25,433 INFO L85 PathProgramCache]: Analyzing trace with hash 889666567, now seen corresponding path program 1 times [2023-11-06 22:36:25,434 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:25,434 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81803542] [2023-11-06 22:36:25,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:25,435 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:25,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:25,455 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:25,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:25,472 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:25,473 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:25,473 INFO L85 PathProgramCache]: Analyzing trace with hash 51595455, now seen corresponding path program 2 times [2023-11-06 22:36:25,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:25,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831633618] [2023-11-06 22:36:25,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:25,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:25,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:25,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:25,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:25,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:25,500 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:25,500 INFO L85 PathProgramCache]: Analyzing trace with hash 1198432377, now seen corresponding path program 1 times [2023-11-06 22:36:25,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:25,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103473281] [2023-11-06 22:36:25,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:25,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:25,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:25,640 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:25,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:25,641 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103473281] [2023-11-06 22:36:25,641 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103473281] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:25,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [945696306] [2023-11-06 22:36:25,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:25,642 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:25,642 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:25,671 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:25,676 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2023-11-06 22:36:25,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:25,743 INFO L262 TraceCheckSpWp]: Trace formula consists of 84 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-06 22:36:25,744 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:25,803 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:25,803 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:25,911 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:25,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [945696306] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:25,911 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:25,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 8 [2023-11-06 22:36:25,912 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209502367] [2023-11-06 22:36:25,912 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:26,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:26,154 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2023-11-06 22:36:26,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2023-11-06 22:36:26,155 INFO L87 Difference]: Start difference. First operand 16 states and 18 transitions. cyclomatic complexity: 4 Second operand has 9 states, 8 states have (on average 3.875) internal successors, (31), 9 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:26,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:26,312 INFO L93 Difference]: Finished difference Result 25 states and 27 transitions. [2023-11-06 22:36:26,312 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 27 transitions. [2023-11-06 22:36:26,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:36:26,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 27 transitions. [2023-11-06 22:36:26,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2023-11-06 22:36:26,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2023-11-06 22:36:26,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 27 transitions. [2023-11-06 22:36:26,327 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:36:26,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 27 transitions. [2023-11-06 22:36:26,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 27 transitions. [2023-11-06 22:36:26,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 19. [2023-11-06 22:36:26,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.105263157894737) internal successors, (21), 18 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:26,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2023-11-06 22:36:26,333 INFO L240 hiAutomatonCegarLoop]: Abstraction has 19 states and 21 transitions. [2023-11-06 22:36:26,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:36:26,336 INFO L428 stractBuchiCegarLoop]: Abstraction has 19 states and 21 transitions. [2023-11-06 22:36:26,336 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:36:26,336 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 21 transitions. [2023-11-06 22:36:26,338 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:36:26,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:26,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:26,339 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2023-11-06 22:36:26,339 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1, 1, 1, 1] [2023-11-06 22:36:26,339 INFO L748 eck$LassoCheckResult]: Stem: 259#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 260#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 261#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 263#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 268#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 266#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 264#L17-4 [2023-11-06 22:36:26,339 INFO L750 eck$LassoCheckResult]: Loop: 264#L17-4 foo_#res#1 := foo_~i~0#1; 252#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 253#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 257#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 265#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 250#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 251#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 262#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 267#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 264#L17-4 [2023-11-06 22:36:26,340 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:26,340 INFO L85 PathProgramCache]: Analyzing trace with hash 889666567, now seen corresponding path program 2 times [2023-11-06 22:36:26,340 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:26,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [650500926] [2023-11-06 22:36:26,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:26,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:26,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,374 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:26,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:26,386 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:26,387 INFO L85 PathProgramCache]: Analyzing trace with hash 1121476027, now seen corresponding path program 1 times [2023-11-06 22:36:26,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:26,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498978473] [2023-11-06 22:36:26,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:26,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:26,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:26,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:26,425 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:26,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1242740619, now seen corresponding path program 2 times [2023-11-06 22:36:26,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:26,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147703121] [2023-11-06 22:36:26,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:26,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:26,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,487 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:26,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:26,533 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:26,882 INFO L351 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 21 [2023-11-06 22:36:27,224 INFO L351 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2023-11-06 22:36:27,354 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:36:27,355 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:36:27,355 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:36:27,355 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:36:27,356 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-06 22:36:27,356 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:27,356 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:36:27,356 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:36:27,356 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration4_Lasso [2023-11-06 22:36:27,357 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:36:27,357 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:36:27,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,397 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,404 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:27,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:28,309 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:36:28,314 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-06 22:36:28,316 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:28,316 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:28,320 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:28,323 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:28,336 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-06 22:36:28,338 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:28,339 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:28,339 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:28,339 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:28,350 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:28,351 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:28,367 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-06 22:36:28,386 INFO L443 ModelExtractionUtils]: Simplification made 4 calls to the SMT solver. [2023-11-06 22:36:28,386 INFO L444 ModelExtractionUtils]: 3 out of 7 variables were initially zero. Simplification set additionally 1 variables to zero. [2023-11-06 22:36:28,388 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:28,388 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:28,403 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:28,421 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-06 22:36:28,422 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-06 22:36:28,457 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-06 22:36:28,458 INFO L513 LassoAnalysis]: Proved termination. [2023-11-06 22:36:28,459 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~1#1) = -2*ULTIMATE.start_main_~i~1#1 + 1 Supporting invariants [] [2023-11-06 22:36:28,467 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:28,497 INFO L156 tatePredicateManager]: 7 out of 7 supporting invariants were superfluous and have been removed [2023-11-06 22:36:28,520 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:28,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:28,542 INFO L262 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:36:28,544 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:28,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:28,577 INFO L262 TraceCheckSpWp]: Trace formula consists of 52 conjuncts, 9 conjunts are in the unsatisfiable core [2023-11-06 22:36:28,579 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:28,697 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:28,701 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 5 loop predicates [2023-11-06 22:36:28,703 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 19 states and 21 transitions. cyclomatic complexity: 4 Second operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:28,850 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 19 states and 21 transitions. cyclomatic complexity: 4. Second operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 41 states and 47 transitions. Complement of second has 13 states. [2023-11-06 22:36:28,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 7 states 1 stem states 5 non-accepting loop states 1 accepting loop states [2023-11-06 22:36:28,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 2.142857142857143) internal successors, (15), 7 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:28,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 24 transitions. [2023-11-06 22:36:28,856 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 6 letters. Loop has 9 letters. [2023-11-06 22:36:28,857 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:28,858 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 15 letters. Loop has 9 letters. [2023-11-06 22:36:28,858 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:28,858 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 7 states and 24 transitions. Stem has 6 letters. Loop has 18 letters. [2023-11-06 22:36:28,859 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:28,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 47 transitions. [2023-11-06 22:36:28,863 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2023-11-06 22:36:28,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 40 states and 46 transitions. [2023-11-06 22:36:28,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2023-11-06 22:36:28,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2023-11-06 22:36:28,866 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 46 transitions. [2023-11-06 22:36:28,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:28,866 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40 states and 46 transitions. [2023-11-06 22:36:28,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 46 transitions. [2023-11-06 22:36:28,871 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 34. [2023-11-06 22:36:28,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.1764705882352942) internal successors, (40), 33 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:28,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 40 transitions. [2023-11-06 22:36:28,874 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-06 22:36:28,874 INFO L428 stractBuchiCegarLoop]: Abstraction has 34 states and 40 transitions. [2023-11-06 22:36:28,875 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:36:28,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 40 transitions. [2023-11-06 22:36:28,876 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:28,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:28,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:28,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:36:28,880 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2023-11-06 22:36:28,880 INFO L748 eck$LassoCheckResult]: Stem: 432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 437#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 438#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 448#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 443#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 444#L17-4 foo_#res#1 := foo_~i~0#1; 422#foo_returnLabel#1 [2023-11-06 22:36:28,880 INFO L750 eck$LassoCheckResult]: Loop: 422#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 423#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 430#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 442#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 418#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 419#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 449#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 434#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 435#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 447#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 440#L17-4 foo_#res#1 := foo_~i~0#1; 422#foo_returnLabel#1 [2023-11-06 22:36:28,880 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:28,881 INFO L85 PathProgramCache]: Analyzing trace with hash 1809859825, now seen corresponding path program 1 times [2023-11-06 22:36:28,881 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:28,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578169031] [2023-11-06 22:36:28,881 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:28,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:28,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:28,913 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:28,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:28,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:28,942 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:28,942 INFO L85 PathProgramCache]: Analyzing trace with hash 961271861, now seen corresponding path program 2 times [2023-11-06 22:36:28,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:28,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [743197205] [2023-11-06 22:36:28,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:28,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:28,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:28,964 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:28,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:28,994 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:28,996 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:29,000 INFO L85 PathProgramCache]: Analyzing trace with hash 132390213, now seen corresponding path program 3 times [2023-11-06 22:36:29,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:29,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981621746] [2023-11-06 22:36:29,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:29,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:29,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:29,211 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 10 proven. 12 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:29,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:29,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981621746] [2023-11-06 22:36:29,213 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981621746] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:29,215 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [723896927] [2023-11-06 22:36:29,215 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:36:29,215 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:29,216 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:29,217 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:29,243 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2023-11-06 22:36:29,310 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2023-11-06 22:36:29,310 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:29,312 INFO L262 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-06 22:36:29,313 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:29,447 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:29,458 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:29,459 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:29,541 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 9 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:29,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [723896927] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:29,548 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:29,548 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2023-11-06 22:36:29,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [268809708] [2023-11-06 22:36:29,552 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:29,919 INFO L351 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 32 [2023-11-06 22:36:30,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:30,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2023-11-06 22:36:30,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=94, Unknown=0, NotChecked=0, Total=132 [2023-11-06 22:36:30,097 INFO L87 Difference]: Start difference. First operand 34 states and 40 transitions. cyclomatic complexity: 9 Second operand has 12 states, 12 states have (on average 2.9166666666666665) internal successors, (35), 12 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:30,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:30,274 INFO L93 Difference]: Finished difference Result 62 states and 69 transitions. [2023-11-06 22:36:30,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 69 transitions. [2023-11-06 22:36:30,276 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:30,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 57 states and 64 transitions. [2023-11-06 22:36:30,277 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2023-11-06 22:36:30,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34 [2023-11-06 22:36:30,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 64 transitions. [2023-11-06 22:36:30,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:30,277 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 64 transitions. [2023-11-06 22:36:30,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 64 transitions. [2023-11-06 22:36:30,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 45. [2023-11-06 22:36:30,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1333333333333333) internal successors, (51), 44 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:30,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 51 transitions. [2023-11-06 22:36:30,282 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 51 transitions. [2023-11-06 22:36:30,282 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2023-11-06 22:36:30,283 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 51 transitions. [2023-11-06 22:36:30,283 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:36:30,283 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 51 transitions. [2023-11-06 22:36:30,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:30,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:30,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:30,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:36:30,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:36:30,285 INFO L748 eck$LassoCheckResult]: Stem: 657#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 659#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 663#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 672#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 668#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 669#L17-4 foo_#res#1 := foo_~i~0#1; 647#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 648#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 654#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 656#L26-4 main_~i~1#1 := 0; 651#L29-3 [2023-11-06 22:36:30,286 INFO L750 eck$LassoCheckResult]: Loop: 651#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 652#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 653#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 651#L29-3 [2023-11-06 22:36:30,286 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:30,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1198432331, now seen corresponding path program 1 times [2023-11-06 22:36:30,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:30,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023645506] [2023-11-06 22:36:30,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:30,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:30,349 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:30,349 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:30,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023645506] [2023-11-06 22:36:30,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023645506] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:30,350 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [369390764] [2023-11-06 22:36:30,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:30,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:30,352 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:30,379 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2023-11-06 22:36:30,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:30,428 INFO L262 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-06 22:36:30,429 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:30,448 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:30,448 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:30,500 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2023-11-06 22:36:30,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [369390764] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:30,501 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:30,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 7 [2023-11-06 22:36:30,502 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489019868] [2023-11-06 22:36:30,502 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:30,503 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:36:30,503 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:30,503 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 1 times [2023-11-06 22:36:30,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:30,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273866226] [2023-11-06 22:36:30,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:30,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:30,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:30,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:30,582 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-06 22:36:30,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2023-11-06 22:36:30,582 INFO L87 Difference]: Start difference. First operand 45 states and 51 transitions. cyclomatic complexity: 9 Second operand has 7 states, 7 states have (on average 3.142857142857143) internal successors, (22), 7 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:30,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:30,693 INFO L93 Difference]: Finished difference Result 85 states and 95 transitions. [2023-11-06 22:36:30,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 95 transitions. [2023-11-06 22:36:30,695 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2023-11-06 22:36:30,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 82 states and 92 transitions. [2023-11-06 22:36:30,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2023-11-06 22:36:30,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2023-11-06 22:36:30,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 92 transitions. [2023-11-06 22:36:30,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:30,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 92 transitions. [2023-11-06 22:36:30,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 92 transitions. [2023-11-06 22:36:30,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 66. [2023-11-06 22:36:30,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1363636363636365) internal successors, (75), 65 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:30,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 75 transitions. [2023-11-06 22:36:30,705 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 75 transitions. [2023-11-06 22:36:30,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-06 22:36:30,711 INFO L428 stractBuchiCegarLoop]: Abstraction has 66 states and 75 transitions. [2023-11-06 22:36:30,711 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:36:30,711 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 75 transitions. [2023-11-06 22:36:30,712 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 16 [2023-11-06 22:36:30,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:30,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:30,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 3, 2, 2, 2, 2, 1, 1] [2023-11-06 22:36:30,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:36:30,714 INFO L748 eck$LassoCheckResult]: Stem: 861#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 862#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 865#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 863#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 845#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 846#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 867#L17-4 foo_#res#1 := foo_~i~0#1; 868#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 906#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 904#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 902#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 900#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 898#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 896#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 895#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 891#L17-4 foo_#res#1 := foo_~i~0#1; 890#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 856#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 857#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 905#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 903#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 901#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 899#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 897#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 894#L17-2 [2023-11-06 22:36:30,714 INFO L750 eck$LassoCheckResult]: Loop: 894#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 893#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 894#L17-2 [2023-11-06 22:36:30,714 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:30,714 INFO L85 PathProgramCache]: Analyzing trace with hash 1084446665, now seen corresponding path program 4 times [2023-11-06 22:36:30,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:30,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1519242504] [2023-11-06 22:36:30,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,716 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:30,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,763 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:30,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,788 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:30,789 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:30,789 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 2 times [2023-11-06 22:36:30,789 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:30,789 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1214724962] [2023-11-06 22:36:30,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:30,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,793 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:30,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:30,797 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:30,798 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:30,798 INFO L85 PathProgramCache]: Analyzing trace with hash -1523807225, now seen corresponding path program 5 times [2023-11-06 22:36:30,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:30,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028303362] [2023-11-06 22:36:30,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:30,798 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:30,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:30,990 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 4 proven. 48 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2023-11-06 22:36:30,990 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:30,990 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028303362] [2023-11-06 22:36:30,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028303362] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:30,990 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [622877554] [2023-11-06 22:36:30,991 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:36:30,991 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:30,991 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:30,995 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:31,015 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2023-11-06 22:36:31,109 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2023-11-06 22:36:31,109 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:31,111 INFO L262 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-06 22:36:31,130 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:31,308 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 11 proven. 42 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2023-11-06 22:36:31,308 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:31,462 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 11 proven. 42 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2023-11-06 22:36:31,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [622877554] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:31,462 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:31,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 10, 10] total 18 [2023-11-06 22:36:31,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309585052] [2023-11-06 22:36:31,464 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:31,518 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:31,519 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2023-11-06 22:36:31,519 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=268, Unknown=0, NotChecked=0, Total=342 [2023-11-06 22:36:31,519 INFO L87 Difference]: Start difference. First operand 66 states and 75 transitions. cyclomatic complexity: 13 Second operand has 19 states, 18 states have (on average 2.611111111111111) internal successors, (47), 19 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:31,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:31,892 INFO L93 Difference]: Finished difference Result 82 states and 90 transitions. [2023-11-06 22:36:31,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 90 transitions. [2023-11-06 22:36:31,894 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:31,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 82 states and 90 transitions. [2023-11-06 22:36:31,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2023-11-06 22:36:31,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2023-11-06 22:36:31,895 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 90 transitions. [2023-11-06 22:36:31,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:31,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82 states and 90 transitions. [2023-11-06 22:36:31,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 90 transitions. [2023-11-06 22:36:31,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 68. [2023-11-06 22:36:31,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1176470588235294) internal successors, (76), 67 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:31,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 76 transitions. [2023-11-06 22:36:31,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 76 transitions. [2023-11-06 22:36:31,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2023-11-06 22:36:31,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 76 transitions. [2023-11-06 22:36:31,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:36:31,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 76 transitions. [2023-11-06 22:36:31,909 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:31,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:31,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:31,910 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 3, 3, 3, 3, 1, 1] [2023-11-06 22:36:31,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2023-11-06 22:36:31,911 INFO L748 eck$LassoCheckResult]: Stem: 1205#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1206#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1210#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1245#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1241#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1240#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1238#L17-4 foo_#res#1 := foo_~i~0#1; 1233#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1202#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1203#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1249#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1248#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1247#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1244#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1243#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1235#L17-4 foo_#res#1 := foo_~i~0#1; 1237#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1250#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1211#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1212#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1256#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1255#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1254#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1252#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1251#L17-4 foo_#res#1 := foo_~i~0#1; 1189#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1190#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1232#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1215#L17-3 [2023-11-06 22:36:31,911 INFO L750 eck$LassoCheckResult]: Loop: 1215#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1230#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1228#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1226#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1224#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1221#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1220#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1218#L17-4 foo_#res#1 := foo_~i~0#1; 1217#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1216#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1214#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1215#L17-3 [2023-11-06 22:36:31,911 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:31,911 INFO L85 PathProgramCache]: Analyzing trace with hash 203385399, now seen corresponding path program 6 times [2023-11-06 22:36:31,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:31,912 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420803907] [2023-11-06 22:36:31,912 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:31,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:31,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:32,110 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 15 proven. 33 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2023-11-06 22:36:32,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:32,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1420803907] [2023-11-06 22:36:32,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1420803907] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:32,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [667598453] [2023-11-06 22:36:32,111 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-06 22:36:32,111 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:32,111 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:32,118 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:32,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2023-11-06 22:36:32,273 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2023-11-06 22:36:32,273 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:32,275 INFO L262 TraceCheckSpWp]: Trace formula consists of 183 conjuncts, 9 conjunts are in the unsatisfiable core [2023-11-06 22:36:32,277 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:32,382 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 23 proven. 25 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2023-11-06 22:36:32,382 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:32,480 INFO L134 CoverageAnalysis]: Checked inductivity of 53 backedges. 23 proven. 25 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2023-11-06 22:36:32,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [667598453] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:32,480 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:32,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 15 [2023-11-06 22:36:32,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648121462] [2023-11-06 22:36:32,481 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:32,483 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:36:32,483 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:32,483 INFO L85 PathProgramCache]: Analyzing trace with hash -81249831, now seen corresponding path program 3 times [2023-11-06 22:36:32,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:32,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889879429] [2023-11-06 22:36:32,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:32,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:32,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:32,505 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:32,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:32,516 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:32,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:32,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2023-11-06 22:36:32,983 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=152, Unknown=0, NotChecked=0, Total=210 [2023-11-06 22:36:32,983 INFO L87 Difference]: Start difference. First operand 68 states and 76 transitions. cyclomatic complexity: 11 Second operand has 15 states, 15 states have (on average 3.066666666666667) internal successors, (46), 15 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:33,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:33,234 INFO L93 Difference]: Finished difference Result 74 states and 78 transitions. [2023-11-06 22:36:33,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74 states and 78 transitions. [2023-11-06 22:36:33,235 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 15 [2023-11-06 22:36:33,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74 states to 52 states and 54 transitions. [2023-11-06 22:36:33,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2023-11-06 22:36:33,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2023-11-06 22:36:33,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 54 transitions. [2023-11-06 22:36:33,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:36:33,237 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 54 transitions. [2023-11-06 22:36:33,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 54 transitions. [2023-11-06 22:36:33,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 45. [2023-11-06 22:36:33,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0444444444444445) internal successors, (47), 44 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:33,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 47 transitions. [2023-11-06 22:36:33,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 47 transitions. [2023-11-06 22:36:33,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-06 22:36:33,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 45 states and 47 transitions. [2023-11-06 22:36:33,242 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:36:33,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 47 transitions. [2023-11-06 22:36:33,243 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2023-11-06 22:36:33,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:33,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:33,244 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 3, 3, 3, 3, 1, 1] [2023-11-06 22:36:33,244 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 1, 1, 1, 1, 1] [2023-11-06 22:36:33,245 INFO L748 eck$LassoCheckResult]: Stem: 1532#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1533#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1534#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1566#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1565#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1564#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1563#L17-4 foo_#res#1 := foo_~i~0#1; 1525#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1526#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1530#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1536#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1523#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1524#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1535#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1567#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1537#L17-4 foo_#res#1 := foo_~i~0#1; 1538#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1562#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1561#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1560#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1559#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1558#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1557#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1556#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1555#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1554#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1553#L17-4 foo_#res#1 := foo_~i~0#1; 1552#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1551#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1550#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1540#L17-3 [2023-11-06 22:36:33,245 INFO L750 eck$LassoCheckResult]: Loop: 1540#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1549#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1548#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1547#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1546#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1545#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1544#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1543#L17-4 foo_#res#1 := foo_~i~0#1; 1542#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1541#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1539#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1540#L17-3 [2023-11-06 22:36:33,245 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:33,245 INFO L85 PathProgramCache]: Analyzing trace with hash -463974539, now seen corresponding path program 7 times [2023-11-06 22:36:33,246 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:33,246 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130773541] [2023-11-06 22:36:33,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:33,246 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:33,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:33,270 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:33,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:33,308 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:33,309 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:33,309 INFO L85 PathProgramCache]: Analyzing trace with hash -81249831, now seen corresponding path program 4 times [2023-11-06 22:36:33,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:33,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047286731] [2023-11-06 22:36:33,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:33,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:33,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:33,321 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:33,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:33,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:33,341 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:33,342 INFO L85 PathProgramCache]: Analyzing trace with hash -1101563419, now seen corresponding path program 8 times [2023-11-06 22:36:33,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:33,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169667666] [2023-11-06 22:36:33,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:33,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:33,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:33,715 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 49 proven. 79 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:33,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:33,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169667666] [2023-11-06 22:36:33,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169667666] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:33,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1349014374] [2023-11-06 22:36:33,716 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-06 22:36:33,717 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:33,717 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:33,721 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:33,759 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-06 22:36:33,851 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-06 22:36:33,851 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:33,853 INFO L262 TraceCheckSpWp]: Trace formula consists of 255 conjuncts, 11 conjunts are in the unsatisfiable core [2023-11-06 22:36:33,856 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:34,010 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 65 proven. 63 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:34,011 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:34,182 INFO L134 CoverageAnalysis]: Checked inductivity of 142 backedges. 65 proven. 63 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:34,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1349014374] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:34,182 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:34,183 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 19 [2023-11-06 22:36:34,183 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636777812] [2023-11-06 22:36:34,183 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:34,651 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:34,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2023-11-06 22:36:34,652 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=254, Unknown=0, NotChecked=0, Total=342 [2023-11-06 22:36:34,652 INFO L87 Difference]: Start difference. First operand 45 states and 47 transitions. cyclomatic complexity: 4 Second operand has 19 states, 19 states have (on average 3.1052631578947367) internal successors, (59), 19 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:35,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:35,098 INFO L93 Difference]: Finished difference Result 57 states and 59 transitions. [2023-11-06 22:36:35,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 59 transitions. [2023-11-06 22:36:35,099 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17 [2023-11-06 22:36:35,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 59 transitions. [2023-11-06 22:36:35,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57 [2023-11-06 22:36:35,100 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57 [2023-11-06 22:36:35,100 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 59 transitions. [2023-11-06 22:36:35,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:36:35,101 INFO L218 hiAutomatonCegarLoop]: Abstraction has 57 states and 59 transitions. [2023-11-06 22:36:35,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 59 transitions. [2023-11-06 22:36:35,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 47. [2023-11-06 22:36:35,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0425531914893618) internal successors, (49), 46 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:35,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 49 transitions. [2023-11-06 22:36:35,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47 states and 49 transitions. [2023-11-06 22:36:35,110 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2023-11-06 22:36:35,111 INFO L428 stractBuchiCegarLoop]: Abstraction has 47 states and 49 transitions. [2023-11-06 22:36:35,111 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:36:35,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 49 transitions. [2023-11-06 22:36:35,112 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:35,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:35,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:35,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 4, 3, 3, 3, 3, 1, 1] [2023-11-06 22:36:35,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2023-11-06 22:36:35,116 INFO L748 eck$LassoCheckResult]: Stem: 1919#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 1920#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 1921#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1922#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1923#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1953#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1951#L17-4 foo_#res#1 := foo_~i~0#1; 1950#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1916#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1917#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1955#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1909#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1910#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1954#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1952#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1924#L17-4 foo_#res#1 := foo_~i~0#1; 1911#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1912#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1949#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1948#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1947#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1946#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1945#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1944#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1943#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1942#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1941#L17-4 foo_#res#1 := foo_~i~0#1; 1940#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1939#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1938#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1926#L17-3 [2023-11-06 22:36:35,117 INFO L750 eck$LassoCheckResult]: Loop: 1926#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1937#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1936#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1935#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1934#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1933#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1932#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 1931#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 1930#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 1929#L17-4 foo_#res#1 := foo_~i~0#1; 1928#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 1927#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1925#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 1926#L17-3 [2023-11-06 22:36:35,118 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:35,118 INFO L85 PathProgramCache]: Analyzing trace with hash -463974539, now seen corresponding path program 9 times [2023-11-06 22:36:35,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:35,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [796559128] [2023-11-06 22:36:35,119 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:35,119 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:35,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,157 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:35,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,193 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:35,194 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:35,195 INFO L85 PathProgramCache]: Analyzing trace with hash 879476375, now seen corresponding path program 5 times [2023-11-06 22:36:35,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:35,195 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960176017] [2023-11-06 22:36:35,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:35,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:35,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:35,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,230 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:35,231 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:35,231 INFO L85 PathProgramCache]: Analyzing trace with hash -389338205, now seen corresponding path program 10 times [2023-11-06 22:36:35,231 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:35,231 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1141119287] [2023-11-06 22:36:35,232 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:35,232 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:35,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,273 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:35,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:35,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:38,088 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:36:38,089 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:36:38,089 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:36:38,089 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:36:38,089 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-06 22:36:38,089 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:38,089 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:36:38,089 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:36:38,089 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration10_Lasso [2023-11-06 22:36:38,090 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:36:38,090 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:36:38,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,097 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,100 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,103 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,107 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:38,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:39,325 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:36:39,329 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-06 22:36:39,330 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,330 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,334 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,348 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,362 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-06 22:36:39,363 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,363 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:39,363 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,364 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,364 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,364 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:39,365 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:39,373 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,379 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,379 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,380 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,392 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,403 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-06 22:36:39,404 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,418 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,419 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:39,419 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,419 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,419 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,421 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:39,421 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:39,443 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,454 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,454 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,455 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,456 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,462 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-06 22:36:39,463 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,478 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,479 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:39,479 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,479 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,479 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,480 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:39,480 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:39,489 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,502 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,502 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,502 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,504 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-06 22:36:39,514 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,529 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,529 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,529 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,529 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,532 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,532 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,547 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,558 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,558 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,558 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,560 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,565 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,577 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,577 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,578 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,578 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,581 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,581 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-06 22:36:39,592 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,601 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,602 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,602 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,603 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,613 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,626 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,626 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,626 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,626 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,627 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-06 22:36:39,629 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,629 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,647 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,656 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,657 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,657 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,658 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,668 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,681 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-06 22:36:39,682 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,682 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,682 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,682 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,688 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,688 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,711 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,721 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,722 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,723 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,733 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,746 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-06 22:36:39,747 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,747 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,747 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,747 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,753 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,753 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,771 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,781 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,782 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,782 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,783 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,793 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,806 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-06 22:36:39,806 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,807 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:39,807 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,807 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,807 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,807 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:39,808 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:39,823 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,833 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,833 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,833 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,834 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,844 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,858 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,858 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,858 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,858 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,858 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-06 22:36:39,860 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,861 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,891 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:39,901 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:39,901 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:39,902 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:39,903 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:39,913 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:39,928 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-06 22:36:39,929 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:39,929 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:39,929 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:39,930 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:39,956 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:39,956 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:39,996 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-06 22:36:40,133 INFO L443 ModelExtractionUtils]: Simplification made 19 calls to the SMT solver. [2023-11-06 22:36:40,133 INFO L444 ModelExtractionUtils]: 5 out of 37 variables were initially zero. Simplification set additionally 21 variables to zero. [2023-11-06 22:36:40,133 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:40,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:40,137 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:40,139 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-06 22:36:40,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-06 22:36:40,169 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 2. [2023-11-06 22:36:40,169 INFO L513 LassoAnalysis]: Proved termination. [2023-11-06 22:36:40,169 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_foo_#in~size#1, ULTIMATE.start_foo_~size#1, ULTIMATE.start_main_~i~1#1, ULTIMATE.start_foo_~i~0#1) = 2*ULTIMATE.start_foo_#in~size#1 - 2*ULTIMATE.start_foo_~size#1 - 2*ULTIMATE.start_main_~i~1#1 + 2*ULTIMATE.start_foo_~i~0#1 + 7 Supporting invariants [1*ULTIMATE.start_foo_~i~0#1 - 1*ULTIMATE.start_foo_~size#1 + 1*ULTIMATE.start_foo_#in~size#1 >= 0, 1*ULTIMATE.start_foo_#in~size#1 - 1*ULTIMATE.start_main_~i~1#1 >= 0] [2023-11-06 22:36:40,183 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:40,223 INFO L156 tatePredicateManager]: 6 out of 8 supporting invariants were superfluous and have been removed [2023-11-06 22:36:40,262 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:40,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:40,311 INFO L262 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 5 conjunts are in the unsatisfiable core [2023-11-06 22:36:40,313 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:40,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:40,386 INFO L262 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 15 conjunts are in the unsatisfiable core [2023-11-06 22:36:40,387 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:40,608 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:40,609 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 8 loop predicates [2023-11-06 22:36:40,609 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 47 states and 49 transitions. cyclomatic complexity: 4 Second operand has 9 states, 9 states have (on average 2.5555555555555554) internal successors, (23), 9 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:40,982 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 47 states and 49 transitions. cyclomatic complexity: 4. Second operand has 9 states, 9 states have (on average 2.5555555555555554) internal successors, (23), 9 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 100 states and 104 transitions. Complement of second has 25 states. [2023-11-06 22:36:40,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 13 states 1 stem states 11 non-accepting loop states 1 accepting loop states [2023-11-06 22:36:40,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 2.5555555555555554) internal successors, (23), 9 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:40,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 27 transitions. [2023-11-06 22:36:40,984 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 13 states and 27 transitions. Stem has 30 letters. Loop has 13 letters. [2023-11-06 22:36:40,984 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:40,984 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 13 states and 27 transitions. Stem has 43 letters. Loop has 13 letters. [2023-11-06 22:36:40,985 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:40,985 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 13 states and 27 transitions. Stem has 30 letters. Loop has 26 letters. [2023-11-06 22:36:40,986 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:40,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 104 transitions. [2023-11-06 22:36:40,987 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:40,988 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 74 states and 78 transitions. [2023-11-06 22:36:40,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2023-11-06 22:36:40,989 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2023-11-06 22:36:40,989 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 78 transitions. [2023-11-06 22:36:40,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:40,989 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 78 transitions. [2023-11-06 22:36:40,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 78 transitions. [2023-11-06 22:36:40,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 61. [2023-11-06 22:36:40,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.0655737704918034) internal successors, (65), 60 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:40,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 65 transitions. [2023-11-06 22:36:40,994 INFO L240 hiAutomatonCegarLoop]: Abstraction has 61 states and 65 transitions. [2023-11-06 22:36:40,994 INFO L428 stractBuchiCegarLoop]: Abstraction has 61 states and 65 transitions. [2023-11-06 22:36:40,995 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:36:40,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 65 transitions. [2023-11-06 22:36:40,995 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:40,995 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:40,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:40,997 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 4, 3, 3, 3, 3, 1, 1] [2023-11-06 22:36:40,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:36:40,997 INFO L748 eck$LassoCheckResult]: Stem: 2297#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2298#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 2302#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2299#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2300#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2333#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2306#L17-4 foo_#res#1 := foo_~i~0#1; 2307#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2326#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2327#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2338#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2337#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2335#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2336#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2330#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2331#L17-4 foo_#res#1 := foo_~i~0#1; 2340#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2339#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2303#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2285#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2301#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2342#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2341#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2334#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2332#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2329#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2328#L17-4 foo_#res#1 := foo_~i~0#1; 2288#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2289#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2295#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2325#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2282#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2283#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2318#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2319#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2314#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2315#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2323#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2308#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2310#L17-2 [2023-11-06 22:36:40,997 INFO L750 eck$LassoCheckResult]: Loop: 2310#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2312#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2310#L17-2 [2023-11-06 22:36:40,998 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:40,998 INFO L85 PathProgramCache]: Analyzing trace with hash 870362933, now seen corresponding path program 11 times [2023-11-06 22:36:40,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:40,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380284912] [2023-11-06 22:36:40,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:40,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:41,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:41,297 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-06 22:36:41,323 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 9 proven. 128 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:41,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:41,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380284912] [2023-11-06 22:36:41,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380284912] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:41,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [33225853] [2023-11-06 22:36:41,324 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:36:41,325 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:41,325 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:41,328 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:41,354 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-06 22:36:41,517 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2023-11-06 22:36:41,517 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:41,519 INFO L262 TraceCheckSpWp]: Trace formula consists of 247 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-06 22:36:41,521 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:41,699 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 16 proven. 121 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:41,699 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:41,845 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 16 proven. 121 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2023-11-06 22:36:41,845 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [33225853] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:41,845 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:41,845 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 17 [2023-11-06 22:36:41,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1586914234] [2023-11-06 22:36:41,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:41,846 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:36:41,847 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:41,847 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 3 times [2023-11-06 22:36:41,847 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:41,847 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65404275] [2023-11-06 22:36:41,848 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:41,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:41,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:41,853 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:41,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:41,857 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:41,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:41,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2023-11-06 22:36:41,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2023-11-06 22:36:41,916 INFO L87 Difference]: Start difference. First operand 61 states and 65 transitions. cyclomatic complexity: 7 Second operand has 18 states, 17 states have (on average 3.176470588235294) internal successors, (54), 18 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:42,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:42,293 INFO L93 Difference]: Finished difference Result 107 states and 112 transitions. [2023-11-06 22:36:42,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 112 transitions. [2023-11-06 22:36:42,294 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:42,295 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 112 transitions. [2023-11-06 22:36:42,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2023-11-06 22:36:42,295 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2023-11-06 22:36:42,295 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 112 transitions. [2023-11-06 22:36:42,295 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:42,295 INFO L218 hiAutomatonCegarLoop]: Abstraction has 107 states and 112 transitions. [2023-11-06 22:36:42,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 112 transitions. [2023-11-06 22:36:42,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 81. [2023-11-06 22:36:42,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.0617283950617284) internal successors, (86), 80 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:42,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 86 transitions. [2023-11-06 22:36:42,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81 states and 86 transitions. [2023-11-06 22:36:42,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2023-11-06 22:36:42,302 INFO L428 stractBuchiCegarLoop]: Abstraction has 81 states and 86 transitions. [2023-11-06 22:36:42,302 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:36:42,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 86 transitions. [2023-11-06 22:36:42,303 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:42,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:42,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:42,304 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 4, 4, 4, 4, 4, 1, 1, 1, 1] [2023-11-06 22:36:42,304 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:36:42,305 INFO L748 eck$LassoCheckResult]: Stem: 2742#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 2743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 2744#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2747#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2790#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2789#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2788#L17-4 foo_#res#1 := foo_~i~0#1; 2787#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2786#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2785#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2784#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2783#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2782#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2781#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2780#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2779#L17-4 foo_#res#1 := foo_~i~0#1; 2778#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2777#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2776#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2775#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2774#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2773#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2772#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2771#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2770#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2769#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2768#L17-4 foo_#res#1 := foo_~i~0#1; 2767#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2766#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2765#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 2764#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2763#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2762#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2761#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2760#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2759#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2758#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 2757#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 2752#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 2749#L17-4 foo_#res#1 := foo_~i~0#1; 2731#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 2732#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2751#L26-3 assume !(main_~i~1#1 % 4294967296 < 32); 2741#L26-4 main_~i~1#1 := 0; 2735#L29-3 [2023-11-06 22:36:42,305 INFO L750 eck$LassoCheckResult]: Loop: 2735#L29-3 assume !!(main_~i~1#1 % 4294967296 < 32);call main_#t~mem5#1 := read~int(main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4); 2736#L30 assume !(main_#t~mem5#1 != main_~i~1#1);havoc main_#t~mem5#1; 2737#L29-2 main_#t~post4#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2735#L29-3 [2023-11-06 22:36:42,306 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:42,306 INFO L85 PathProgramCache]: Analyzing trace with hash 815417503, now seen corresponding path program 2 times [2023-11-06 22:36:42,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:42,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879055679] [2023-11-06 22:36:42,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:42,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:42,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:42,498 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:42,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:42,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879055679] [2023-11-06 22:36:42,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879055679] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:42,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1158199710] [2023-11-06 22:36:42,499 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-06 22:36:42,499 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:42,499 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:42,504 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:42,539 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2023-11-06 22:36:42,812 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-06 22:36:42,812 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:36:42,814 INFO L262 TraceCheckSpWp]: Trace formula consists of 254 conjuncts, 11 conjunts are in the unsatisfiable core [2023-11-06 22:36:42,816 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:42,922 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:42,922 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:43,107 INFO L134 CoverageAnalysis]: Checked inductivity of 164 backedges. 0 proven. 134 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:43,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1158199710] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:43,107 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:43,107 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 13 [2023-11-06 22:36:43,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748428027] [2023-11-06 22:36:43,108 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:43,108 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:36:43,109 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:43,109 INFO L85 PathProgramCache]: Analyzing trace with hash 69737, now seen corresponding path program 2 times [2023-11-06 22:36:43,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:43,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1307857216] [2023-11-06 22:36:43,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:43,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:43,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,113 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:43,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,117 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:43,169 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:43,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-06 22:36:43,170 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=98, Unknown=0, NotChecked=0, Total=156 [2023-11-06 22:36:43,170 INFO L87 Difference]: Start difference. First operand 81 states and 86 transitions. cyclomatic complexity: 8 Second operand has 13 states, 13 states have (on average 4.923076923076923) internal successors, (64), 13 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:43,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:43,727 INFO L93 Difference]: Finished difference Result 308 states and 322 transitions. [2023-11-06 22:36:43,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 308 states and 322 transitions. [2023-11-06 22:36:43,730 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 26 [2023-11-06 22:36:43,732 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 308 states to 276 states and 290 transitions. [2023-11-06 22:36:43,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159 [2023-11-06 22:36:43,733 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159 [2023-11-06 22:36:43,733 INFO L73 IsDeterministic]: Start isDeterministic. Operand 276 states and 290 transitions. [2023-11-06 22:36:43,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:43,734 INFO L218 hiAutomatonCegarLoop]: Abstraction has 276 states and 290 transitions. [2023-11-06 22:36:43,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states and 290 transitions. [2023-11-06 22:36:43,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 208. [2023-11-06 22:36:43,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 208 states, 208 states have (on average 1.0673076923076923) internal successors, (222), 207 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:43,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 222 transitions. [2023-11-06 22:36:43,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 208 states and 222 transitions. [2023-11-06 22:36:43,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-06 22:36:43,747 INFO L428 stractBuchiCegarLoop]: Abstraction has 208 states and 222 transitions. [2023-11-06 22:36:43,747 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:36:43,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 208 states and 222 transitions. [2023-11-06 22:36:43,749 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 26 [2023-11-06 22:36:43,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:43,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:43,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 14, 5, 4, 4, 4, 4, 1, 1] [2023-11-06 22:36:43,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:36:43,750 INFO L748 eck$LassoCheckResult]: Stem: 3413#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 3414#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 3415#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3571#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3570#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3569#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3422#L17-4 foo_#res#1 := foo_~i~0#1; 3404#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3405#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3411#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3419#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3566#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3565#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3564#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3563#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3562#L17-4 foo_#res#1 := foo_~i~0#1; 3561#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3560#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3559#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3558#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3557#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3556#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3555#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3554#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3553#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3552#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3551#L17-4 foo_#res#1 := foo_~i~0#1; 3550#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3549#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3548#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3547#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3546#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3545#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3544#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3543#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3542#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3541#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3540#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3539#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 3538#L17-4 foo_#res#1 := foo_~i~0#1; 3537#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 3536#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3535#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 3533#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3534#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3602#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3601#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3600#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3599#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3598#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3597#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3592#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3587#L17-2 [2023-11-06 22:36:43,751 INFO L750 eck$LassoCheckResult]: Loop: 3587#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 3585#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 3587#L17-2 [2023-11-06 22:36:43,751 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:43,751 INFO L85 PathProgramCache]: Analyzing trace with hash 303539911, now seen corresponding path program 12 times [2023-11-06 22:36:43,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:43,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054521297] [2023-11-06 22:36:43,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:43,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:43,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:43,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,892 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:43,893 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:43,893 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 4 times [2023-11-06 22:36:43,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:43,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608024243] [2023-11-06 22:36:43,893 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:43,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:43,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,899 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:43,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:43,902 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:43,903 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:43,903 INFO L85 PathProgramCache]: Analyzing trace with hash -355921019, now seen corresponding path program 13 times [2023-11-06 22:36:43,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:43,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [315692007] [2023-11-06 22:36:43,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:43,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:43,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:44,307 INFO L134 CoverageAnalysis]: Checked inductivity of 323 backedges. 16 proven. 277 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:44,308 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:36:44,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [315692007] [2023-11-06 22:36:44,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [315692007] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:36:44,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [836712642] [2023-11-06 22:36:44,308 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:36:44,309 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:36:44,309 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:44,315 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:36:44,353 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2023-11-06 22:36:44,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:44,463 INFO L262 TraceCheckSpWp]: Trace formula consists of 330 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-06 22:36:44,465 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:44,662 INFO L134 CoverageAnalysis]: Checked inductivity of 323 backedges. 25 proven. 268 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:44,663 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:36:44,829 INFO L134 CoverageAnalysis]: Checked inductivity of 323 backedges. 25 proven. 268 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2023-11-06 22:36:44,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [836712642] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:36:44,829 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:36:44,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 20 [2023-11-06 22:36:44,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476784345] [2023-11-06 22:36:44,830 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:36:44,884 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:36:44,885 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2023-11-06 22:36:44,886 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=313, Unknown=0, NotChecked=0, Total=420 [2023-11-06 22:36:44,886 INFO L87 Difference]: Start difference. First operand 208 states and 222 transitions. cyclomatic complexity: 22 Second operand has 21 states, 20 states have (on average 3.25) internal successors, (65), 21 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:45,513 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:36:45,514 INFO L93 Difference]: Finished difference Result 223 states and 236 transitions. [2023-11-06 22:36:45,514 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 236 transitions. [2023-11-06 22:36:45,516 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 24 [2023-11-06 22:36:45,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 236 transitions. [2023-11-06 22:36:45,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2023-11-06 22:36:45,518 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2023-11-06 22:36:45,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 236 transitions. [2023-11-06 22:36:45,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:45,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 236 transitions. [2023-11-06 22:36:45,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 236 transitions. [2023-11-06 22:36:45,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 208. [2023-11-06 22:36:45,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 208 states, 208 states have (on average 1.0625) internal successors, (221), 207 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:45,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 221 transitions. [2023-11-06 22:36:45,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 208 states and 221 transitions. [2023-11-06 22:36:45,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2023-11-06 22:36:45,532 INFO L428 stractBuchiCegarLoop]: Abstraction has 208 states and 221 transitions. [2023-11-06 22:36:45,537 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:36:45,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 208 states and 221 transitions. [2023-11-06 22:36:45,539 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 24 [2023-11-06 22:36:45,544 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:45,544 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:45,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 18, 6, 5, 5, 5, 5, 1, 1] [2023-11-06 22:36:45,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:36:45,545 INFO L748 eck$LassoCheckResult]: Stem: 4230#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 4231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 4235#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4232#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4233#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4421#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4419#L17-4 foo_#res#1 := foo_~i~0#1; 4408#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4409#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4236#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4234#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4217#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4218#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4422#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4420#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4410#L17-4 foo_#res#1 := foo_~i~0#1; 4411#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4406#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4407#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4418#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4417#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4416#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4415#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4414#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4413#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4412#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4239#L17-4 foo_#res#1 := foo_~i~0#1; 4221#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4222#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4394#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4405#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4404#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4403#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4402#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4401#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4400#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4399#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4398#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4397#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4396#L17-4 foo_#res#1 := foo_~i~0#1; 4395#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4227#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4228#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4393#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4215#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4216#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4379#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4375#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4372#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4369#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4366#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4363#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4360#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4358#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 4354#L17-4 foo_#res#1 := foo_~i~0#1; 4219#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 4220#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4226#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 4381#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4378#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4374#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4371#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4368#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4365#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4362#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4357#L17-2 [2023-11-06 22:36:45,546 INFO L750 eck$LassoCheckResult]: Loop: 4357#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 4356#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 4357#L17-2 [2023-11-06 22:36:45,546 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:45,546 INFO L85 PathProgramCache]: Analyzing trace with hash -1286935495, now seen corresponding path program 14 times [2023-11-06 22:36:45,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:45,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767391573] [2023-11-06 22:36:45,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:45,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:45,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:45,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,693 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:45,694 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:45,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1599, now seen corresponding path program 5 times [2023-11-06 22:36:45,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:45,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [530866092] [2023-11-06 22:36:45,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:45,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:45,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,699 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:45,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:45,703 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:45,704 INFO L85 PathProgramCache]: Analyzing trace with hash 205571191, now seen corresponding path program 15 times [2023-11-06 22:36:45,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:45,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510372829] [2023-11-06 22:36:45,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:45,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:45,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,752 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:36:45,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:36:45,819 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:36:56,627 WARN L293 SmtUtils]: Spent 10.74s on a formula simplification. DAG size of input: 512 DAG size of output: 342 (called from [L 279] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2023-11-06 22:36:57,146 INFO L351 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 6 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 37 [2023-11-06 22:36:57,369 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:36:57,369 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:36:57,369 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:36:57,370 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:36:57,370 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-06 22:36:57,370 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:57,370 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:36:57,370 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:36:57,370 INFO L133 ssoRankerPreferences]: Filename of dumped script: ArraysWithLenghtAtDeclaration.c_Iteration14_Lasso [2023-11-06 22:36:57,370 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:36:57,370 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:36:57,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:57,380 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:57,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:57,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:57,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:57,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,028 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:36:58,512 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:36:58,513 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-06 22:36:58,513 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,513 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,517 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,520 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-06 22:36:58,522 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,538 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,538 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:58,538 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,538 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,538 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,539 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:58,539 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:58,541 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,544 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,544 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,545 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,546 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,560 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,563 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-06 22:36:58,573 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,573 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:58,573 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,573 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,574 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,574 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:58,574 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:58,576 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,578 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,579 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,580 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,581 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,583 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-06 22:36:58,585 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,597 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,597 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,597 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,597 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,600 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:58,600 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:58,605 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,608 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,609 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,609 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,610 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,613 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-06 22:36:58,613 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,626 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,626 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:36:58,626 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,626 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,626 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,627 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:36:58,627 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:36:58,629 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,632 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,632 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,634 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,638 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,638 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-06 22:36:58,650 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,650 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,650 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,651 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,652 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:58,653 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:58,672 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,676 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,676 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,677 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,679 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-06 22:36:58,680 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,693 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,693 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,693 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,693 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,695 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:58,695 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:58,708 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:36:58,719 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:58,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,721 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,729 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:36:58,743 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-06 22:36:58,744 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:36:58,745 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:36:58,745 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:36:58,745 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:36:58,761 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:36:58,761 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:36:58,777 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-06 22:36:58,827 INFO L443 ModelExtractionUtils]: Simplification made 16 calls to the SMT solver. [2023-11-06 22:36:58,827 INFO L444 ModelExtractionUtils]: 0 out of 19 variables were initially zero. Simplification set additionally 16 variables to zero. [2023-11-06 22:36:58,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:36:58,828 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:36:58,831 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:36:58,833 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-06 22:36:58,834 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-06 22:36:58,847 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-06 22:36:58,847 INFO L513 LassoAnalysis]: Proved termination. [2023-11-06 22:36:58,848 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_foo_~size#1, ULTIMATE.start_foo_~i~0#1) = 1*ULTIMATE.start_foo_~size#1 - 1*ULTIMATE.start_foo_~i~0#1 Supporting invariants [] [2023-11-06 22:36:58,852 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-06 22:36:58,885 INFO L156 tatePredicateManager]: 7 out of 7 supporting invariants were superfluous and have been removed [2023-11-06 22:36:58,904 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:59,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,020 INFO L262 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,023 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,137 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,138 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:59,150 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-06 22:36:59,150 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,177 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 211 states and 224 transitions. Complement of second has 5 states. [2023-11-06 22:36:59,178 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-06 22:36:59,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 7 transitions. [2023-11-06 22:36:59,179 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 65 letters. Loop has 2 letters. [2023-11-06 22:36:59,180 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:59,180 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-06 22:36:59,195 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:59,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,294 INFO L262 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,296 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,416 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,417 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:59,430 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and with honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-06 22:36:59,430 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,464 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 211 states and 224 transitions. Complement of second has 5 states. [2023-11-06 22:36:59,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-06 22:36:59,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 7 transitions. [2023-11-06 22:36:59,466 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 7 transitions. Stem has 65 letters. Loop has 2 letters. [2023-11-06 22:36:59,466 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:59,466 INFO L681 stractBuchiCegarLoop]: Bad chosen interpolant automaton: word not accepted [2023-11-06 22:36:59,484 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:59,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,592 INFO L262 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,595 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,742 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2023-11-06 22:36:59,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:36:59,781 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-06 22:36:59,782 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:36:59,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:36:59,795 INFO L141 lantAutomatonBouncer]: Defining Buchi interpolant automaton with scrooge nondeterminism in stemwith honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-06 22:36:59,795 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20 Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,829 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 208 states and 221 transitions. cyclomatic complexity: 20. Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 311 states and 328 transitions. Complement of second has 4 states. [2023-11-06 22:36:59,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-06 22:36:59,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 3 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 19 transitions. [2023-11-06 22:36:59,833 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 19 transitions. Stem has 65 letters. Loop has 2 letters. [2023-11-06 22:36:59,834 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:59,834 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 19 transitions. Stem has 67 letters. Loop has 2 letters. [2023-11-06 22:36:59,835 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:59,835 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 19 transitions. Stem has 65 letters. Loop has 4 letters. [2023-11-06 22:36:59,838 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:36:59,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 311 states and 328 transitions. [2023-11-06 22:36:59,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17 [2023-11-06 22:36:59,844 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 311 states to 222 states and 235 transitions. [2023-11-06 22:36:59,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 [2023-11-06 22:36:59,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2023-11-06 22:36:59,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 235 transitions. [2023-11-06 22:36:59,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:36:59,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 235 transitions. [2023-11-06 22:36:59,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 235 transitions. [2023-11-06 22:36:59,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 216. [2023-11-06 22:36:59,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 216 states, 216 states have (on average 1.0601851851851851) internal successors, (229), 215 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:36:59,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 229 transitions. [2023-11-06 22:36:59,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 216 states and 229 transitions. [2023-11-06 22:36:59,872 INFO L428 stractBuchiCegarLoop]: Abstraction has 216 states and 229 transitions. [2023-11-06 22:36:59,872 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:36:59,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 216 states and 229 transitions. [2023-11-06 22:36:59,875 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 16 [2023-11-06 22:36:59,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:36:59,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:36:59,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 31, 10, 9, 9, 9, 9, 1, 1] [2023-11-06 22:36:59,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [4, 4, 1, 1, 1, 1, 1] [2023-11-06 22:36:59,883 INFO L748 eck$LassoCheckResult]: Stem: 5830#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 5831#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 5834#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5978#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5976#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5974#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5837#L17-4 foo_#res#1 := foo_~i~0#1; 5822#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5823#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5828#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5835#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5971#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5970#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5969#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5968#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5967#L17-4 foo_#res#1 := foo_~i~0#1; 5966#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5965#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5964#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5963#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5962#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5961#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5960#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5959#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5958#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5957#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5956#L17-4 foo_#res#1 := foo_~i~0#1; 5955#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5954#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5953#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5952#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5951#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5950#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5949#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5948#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5947#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5946#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5945#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5944#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5943#L17-4 foo_#res#1 := foo_~i~0#1; 5942#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5941#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5940#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5938#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5937#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5936#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5935#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5934#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5933#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5932#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5931#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5930#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5929#L17-4 foo_#res#1 := foo_~i~0#1; 5928#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5927#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5926#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5925#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5924#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5923#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5922#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5921#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5920#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5919#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5918#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5917#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5916#L17-4 foo_#res#1 := foo_~i~0#1; 5915#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5914#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5913#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5911#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5910#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5909#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5908#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5907#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5906#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5905#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5904#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5903#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5902#L17-4 foo_#res#1 := foo_~i~0#1; 5901#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5900#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5899#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5897#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5896#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5895#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5894#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5893#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5892#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5891#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5890#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5889#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5888#L17-4 foo_#res#1 := foo_~i~0#1; 5887#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5886#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5885#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5883#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5884#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5982#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5980#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5977#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5975#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5973#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5972#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5876#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5875#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5873#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5871#L17-4 foo_#res#1 := foo_~i~0#1; 5869#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5867#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5865#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5861#L17-3 [2023-11-06 22:36:59,884 INFO L750 eck$LassoCheckResult]: Loop: 5861#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5859#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5860#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5855#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5856#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5852#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5848#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 5847#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 5849#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 5843#L17-4 foo_#res#1 := foo_~i~0#1; 5844#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 5839#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5840#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 5861#L17-3 [2023-11-06 22:36:59,885 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:36:59,885 INFO L85 PathProgramCache]: Analyzing trace with hash 493432179, now seen corresponding path program 16 times [2023-11-06 22:36:59,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:36:59,885 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1493426411] [2023-11-06 22:36:59,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:36:59,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:36:59,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:37:00,781 INFO L134 CoverageAnalysis]: Checked inductivity of 1398 backedges. 809 proven. 65 refuted. 0 times theorem prover too weak. 524 trivial. 0 not checked. [2023-11-06 22:37:00,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:37:00,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1493426411] [2023-11-06 22:37:00,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1493426411] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:37:00,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1088758871] [2023-11-06 22:37:00,783 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-06 22:37:00,783 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:37:00,783 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:37:00,784 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:37:00,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2023-11-06 22:37:01,163 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-06 22:37:01,163 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:37:01,169 INFO L262 TraceCheckSpWp]: Trace formula consists of 637 conjuncts, 15 conjunts are in the unsatisfiable core [2023-11-06 22:37:01,173 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:37:01,502 INFO L134 CoverageAnalysis]: Checked inductivity of 1398 backedges. 1025 proven. 208 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2023-11-06 22:37:01,502 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:37:01,906 INFO L134 CoverageAnalysis]: Checked inductivity of 1398 backedges. 1025 proven. 208 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2023-11-06 22:37:01,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1088758871] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:37:01,907 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:37:01,907 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 31 [2023-11-06 22:37:01,907 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [762634363] [2023-11-06 22:37:01,908 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:37:01,908 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:37:01,909 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:01,909 INFO L85 PathProgramCache]: Analyzing trace with hash 879476375, now seen corresponding path program 6 times [2023-11-06 22:37:01,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:01,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1730437215] [2023-11-06 22:37:01,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:01,910 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:01,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:01,924 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:01,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:01,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:02,648 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:37:02,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2023-11-06 22:37:02,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=180, Invalid=750, Unknown=0, NotChecked=0, Total=930 [2023-11-06 22:37:02,650 INFO L87 Difference]: Start difference. First operand 216 states and 229 transitions. cyclomatic complexity: 20 Second operand has 31 states, 31 states have (on average 3.6774193548387095) internal successors, (114), 31 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:04,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:37:04,341 INFO L93 Difference]: Finished difference Result 200 states and 206 transitions. [2023-11-06 22:37:04,341 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 200 states and 206 transitions. [2023-11-06 22:37:04,344 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 23 [2023-11-06 22:37:04,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 200 states to 178 states and 184 transitions. [2023-11-06 22:37:04,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2023-11-06 22:37:04,346 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2023-11-06 22:37:04,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 184 transitions. [2023-11-06 22:37:04,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:37:04,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 184 transitions. [2023-11-06 22:37:04,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 184 transitions. [2023-11-06 22:37:04,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 155. [2023-11-06 22:37:04,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155 states, 155 states have (on average 1.038709677419355) internal successors, (161), 154 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:04,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155 states to 155 states and 161 transitions. [2023-11-06 22:37:04,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 155 states and 161 transitions. [2023-11-06 22:37:04,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2023-11-06 22:37:04,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 155 states and 161 transitions. [2023-11-06 22:37:04,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:37:04,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155 states and 161 transitions. [2023-11-06 22:37:04,362 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 22 [2023-11-06 22:37:04,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:37:04,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:37:04,365 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [42, 42, 10, 9, 9, 9, 9, 1, 1] [2023-11-06 22:37:04,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [7, 7, 1, 1, 1, 1, 1] [2023-11-06 22:37:04,366 INFO L748 eck$LassoCheckResult]: Stem: 6999#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 7000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 7003#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7142#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7141#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7139#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7005#L17-4 foo_#res#1 := foo_~i~0#1; 7006#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7097#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7004#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7001#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6988#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6989#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7140#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7138#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7137#L17-4 foo_#res#1 := foo_~i~0#1; 7098#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7099#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7136#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7135#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7134#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7133#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7132#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7131#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7130#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7129#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7128#L17-4 foo_#res#1 := foo_~i~0#1; 7127#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7126#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7125#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7124#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7123#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7122#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7121#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7120#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7119#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7118#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7117#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7116#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7115#L17-4 foo_#res#1 := foo_~i~0#1; 7114#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7113#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7112#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7111#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7110#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7109#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7108#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7107#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7106#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7105#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7104#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7103#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7102#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7101#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7100#L17-4 foo_#res#1 := foo_~i~0#1; 6992#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 6993#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6997#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7096#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7095#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7002#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 6990#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 6991#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7094#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7093#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7092#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7091#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7090#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7089#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7088#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7087#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7086#L17-4 foo_#res#1 := foo_~i~0#1; 7085#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7084#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7083#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7082#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7081#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7080#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7079#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7078#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7077#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7076#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7075#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7074#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7073#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7072#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7071#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7070#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7069#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7068#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7067#L17-4 foo_#res#1 := foo_~i~0#1; 7066#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7065#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7064#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7063#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7062#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7061#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7060#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7059#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7058#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7057#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7056#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7055#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7054#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7053#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7052#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7051#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7050#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7049#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7048#L17-4 foo_#res#1 := foo_~i~0#1; 7047#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7046#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7045#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7044#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7043#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7042#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7041#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7040#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7039#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7038#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7037#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7036#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7035#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7034#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7033#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7032#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7031#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7030#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7029#L17-4 foo_#res#1 := foo_~i~0#1; 7028#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7027#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7026#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7008#L17-3 [2023-11-06 22:37:04,367 INFO L750 eck$LassoCheckResult]: Loop: 7008#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7025#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7024#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7023#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7022#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7021#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7020#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7019#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7018#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7017#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7016#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7015#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7014#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 7013#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 7012#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 7011#L17-4 foo_#res#1 := foo_~i~0#1; 7010#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 7009#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7007#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 7008#L17-3 [2023-11-06 22:37:04,367 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:04,367 INFO L85 PathProgramCache]: Analyzing trace with hash 59298289, now seen corresponding path program 17 times [2023-11-06 22:37:04,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:04,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163132892] [2023-11-06 22:37:04,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:04,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:04,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:37:05,843 INFO L134 CoverageAnalysis]: Checked inductivity of 2289 backedges. 1043 proven. 182 refuted. 0 times theorem prover too weak. 1064 trivial. 0 not checked. [2023-11-06 22:37:05,844 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:37:05,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163132892] [2023-11-06 22:37:05,844 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163132892] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:37:05,844 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [685672185] [2023-11-06 22:37:05,844 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:37:05,845 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:37:05,845 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:37:05,848 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:37:05,875 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2023-11-06 22:37:07,796 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2023-11-06 22:37:07,796 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:37:07,803 INFO L262 TraceCheckSpWp]: Trace formula consists of 627 conjuncts, 22 conjunts are in the unsatisfiable core [2023-11-06 22:37:07,806 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:37:08,355 INFO L134 CoverageAnalysis]: Checked inductivity of 2289 backedges. 1500 proven. 591 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2023-11-06 22:37:08,355 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:37:08,840 INFO L134 CoverageAnalysis]: Checked inductivity of 2289 backedges. 1627 proven. 464 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2023-11-06 22:37:08,841 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [685672185] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:37:08,841 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:37:08,841 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19] total 46 [2023-11-06 22:37:08,841 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893386963] [2023-11-06 22:37:08,841 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:37:08,842 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:37:08,842 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:08,843 INFO L85 PathProgramCache]: Analyzing trace with hash 1302888401, now seen corresponding path program 7 times [2023-11-06 22:37:08,843 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:08,843 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2001323217] [2023-11-06 22:37:08,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:08,843 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:08,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:08,861 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:08,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:08,875 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:10,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:37:10,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2023-11-06 22:37:10,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=369, Invalid=1701, Unknown=0, NotChecked=0, Total=2070 [2023-11-06 22:37:10,731 INFO L87 Difference]: Start difference. First operand 155 states and 161 transitions. cyclomatic complexity: 12 Second operand has 46 states, 46 states have (on average 2.717391304347826) internal successors, (125), 46 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:12,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:37:12,747 INFO L93 Difference]: Finished difference Result 202 states and 214 transitions. [2023-11-06 22:37:12,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 202 states and 214 transitions. [2023-11-06 22:37:12,749 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2023-11-06 22:37:12,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 202 states to 198 states and 210 transitions. [2023-11-06 22:37:12,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108 [2023-11-06 22:37:12,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108 [2023-11-06 22:37:12,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 210 transitions. [2023-11-06 22:37:12,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:37:12,752 INFO L218 hiAutomatonCegarLoop]: Abstraction has 198 states and 210 transitions. [2023-11-06 22:37:12,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 210 transitions. [2023-11-06 22:37:12,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 172. [2023-11-06 22:37:12,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.0406976744186047) internal successors, (179), 171 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:12,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 179 transitions. [2023-11-06 22:37:12,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 172 states and 179 transitions. [2023-11-06 22:37:12,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2023-11-06 22:37:12,759 INFO L428 stractBuchiCegarLoop]: Abstraction has 172 states and 179 transitions. [2023-11-06 22:37:12,759 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:37:12,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 179 transitions. [2023-11-06 22:37:12,761 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 24 [2023-11-06 22:37:12,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:37:12,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:37:12,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [44, 44, 10, 9, 9, 9, 9, 1, 1] [2023-11-06 22:37:12,763 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [8, 8, 1, 1, 1, 1, 1] [2023-11-06 22:37:12,763 INFO L748 eck$LassoCheckResult]: Stem: 8272#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 8273#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 8276#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8431#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8429#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8427#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8426#L17-4 foo_#res#1 := foo_~i~0#1; 8425#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8269#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8270#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8274#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8260#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8261#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8430#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8428#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8277#L17-4 foo_#res#1 := foo_~i~0#1; 8264#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8265#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8424#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8423#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8422#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8421#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8420#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8419#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8418#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8417#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8416#L17-4 foo_#res#1 := foo_~i~0#1; 8415#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8414#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8413#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8412#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8411#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8410#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8409#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8408#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8407#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8406#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8405#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8404#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8403#L17-4 foo_#res#1 := foo_~i~0#1; 8402#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8401#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8400#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8399#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8398#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8397#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8396#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8395#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8394#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8393#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8392#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8391#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8390#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8389#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8388#L17-4 foo_#res#1 := foo_~i~0#1; 8387#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8386#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8385#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8384#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8383#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8382#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8262#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8263#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8275#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8381#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8380#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8379#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8377#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8375#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8372#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8370#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8368#L17-4 foo_#res#1 := foo_~i~0#1; 8366#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8364#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8362#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8360#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8358#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8357#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8356#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8355#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8354#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8353#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8352#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8351#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8350#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8349#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8348#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8347#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8346#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8345#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8344#L17-4 foo_#res#1 := foo_~i~0#1; 8343#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8342#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8341#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8340#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8339#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8338#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8337#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8336#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8335#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8334#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8333#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8332#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8331#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8330#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8329#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8328#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8327#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8326#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8325#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8324#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8323#L17-4 foo_#res#1 := foo_~i~0#1; 8322#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8321#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8320#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8319#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8318#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8317#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8316#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8315#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8314#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8313#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8312#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8311#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8310#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8309#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8308#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8307#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8306#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8305#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8304#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8303#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8302#L17-4 foo_#res#1 := foo_~i~0#1; 8301#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8300#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8299#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8279#L17-3 [2023-11-06 22:37:12,764 INFO L750 eck$LassoCheckResult]: Loop: 8279#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8298#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8297#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8296#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8295#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8294#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8293#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8292#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8291#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8290#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8289#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8288#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8287#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8286#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8285#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 8284#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 8283#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 8282#L17-4 foo_#res#1 := foo_~i~0#1; 8281#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 8280#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8278#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 8279#L17-3 [2023-11-06 22:37:12,764 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:12,764 INFO L85 PathProgramCache]: Analyzing trace with hash -1602826063, now seen corresponding path program 18 times [2023-11-06 22:37:12,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:12,765 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754782868] [2023-11-06 22:37:12,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:12,765 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:12,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:37:13,748 INFO L134 CoverageAnalysis]: Checked inductivity of 2477 backedges. 1454 proven. 819 refuted. 0 times theorem prover too weak. 204 trivial. 0 not checked. [2023-11-06 22:37:13,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:37:13,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754782868] [2023-11-06 22:37:13,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754782868] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:37:13,749 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1659195007] [2023-11-06 22:37:13,749 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-06 22:37:13,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:37:13,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:37:13,753 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:37:13,767 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2023-11-06 22:37:14,704 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2023-11-06 22:37:14,704 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:37:14,711 INFO L262 TraceCheckSpWp]: Trace formula consists of 780 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-06 22:37:14,714 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:37:15,186 INFO L134 CoverageAnalysis]: Checked inductivity of 2477 backedges. 1419 proven. 849 refuted. 0 times theorem prover too weak. 209 trivial. 0 not checked. [2023-11-06 22:37:15,187 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:37:15,754 INFO L134 CoverageAnalysis]: Checked inductivity of 2477 backedges. 1589 proven. 679 refuted. 0 times theorem prover too weak. 209 trivial. 0 not checked. [2023-11-06 22:37:15,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1659195007] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:37:15,756 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:37:15,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 21, 21] total 44 [2023-11-06 22:37:15,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951970400] [2023-11-06 22:37:15,757 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:37:15,759 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:37:15,759 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:15,759 INFO L85 PathProgramCache]: Analyzing trace with hash -403544433, now seen corresponding path program 8 times [2023-11-06 22:37:15,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:15,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97390080] [2023-11-06 22:37:15,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:15,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:15,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:15,795 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:15,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:15,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:17,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:37:17,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-06 22:37:17,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=365, Invalid=1527, Unknown=0, NotChecked=0, Total=1892 [2023-11-06 22:37:17,617 INFO L87 Difference]: Start difference. First operand 172 states and 179 transitions. cyclomatic complexity: 13 Second operand has 44 states, 44 states have (on average 3.090909090909091) internal successors, (136), 44 states have internal predecessors, (136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:20,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:37:20,258 INFO L93 Difference]: Finished difference Result 220 states and 231 transitions. [2023-11-06 22:37:20,258 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220 states and 231 transitions. [2023-11-06 22:37:20,260 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2023-11-06 22:37:20,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220 states to 218 states and 229 transitions. [2023-11-06 22:37:20,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2023-11-06 22:37:20,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2023-11-06 22:37:20,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 229 transitions. [2023-11-06 22:37:20,263 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:37:20,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 229 transitions. [2023-11-06 22:37:20,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 229 transitions. [2023-11-06 22:37:20,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 176. [2023-11-06 22:37:20,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 176 states have (on average 1.0397727272727273) internal successors, (183), 175 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:20,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 183 transitions. [2023-11-06 22:37:20,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 183 transitions. [2023-11-06 22:37:20,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2023-11-06 22:37:20,269 INFO L428 stractBuchiCegarLoop]: Abstraction has 176 states and 183 transitions. [2023-11-06 22:37:20,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:37:20,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 183 transitions. [2023-11-06 22:37:20,270 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 26 [2023-11-06 22:37:20,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:37:20,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:37:20,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [45, 45, 10, 9, 9, 9, 9, 1, 1] [2023-11-06 22:37:20,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [9, 9, 1, 1, 1, 1, 1] [2023-11-06 22:37:20,273 INFO L748 eck$LassoCheckResult]: Stem: 9635#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 9636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 9637#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9798#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9797#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9795#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9640#L17-4 foo_#res#1 := foo_~i~0#1; 9641#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9632#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9633#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9638#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9623#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9624#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9796#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9794#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9793#L17-4 foo_#res#1 := foo_~i~0#1; 9627#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9628#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9792#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9791#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9790#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9789#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9788#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9787#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9786#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9785#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9784#L17-4 foo_#res#1 := foo_~i~0#1; 9783#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9782#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9781#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9780#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9779#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9778#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9777#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9776#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9775#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9774#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9773#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9772#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9771#L17-4 foo_#res#1 := foo_~i~0#1; 9770#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9769#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9768#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9767#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9766#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9765#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9764#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9763#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9762#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9761#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9760#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9759#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9758#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9757#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9756#L17-4 foo_#res#1 := foo_~i~0#1; 9755#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9754#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9753#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9752#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9751#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9639#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9625#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9626#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9750#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9749#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9748#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9747#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9746#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9744#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9741#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9739#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9737#L17-4 foo_#res#1 := foo_~i~0#1; 9735#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9733#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9731#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9729#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9727#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9725#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9724#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9723#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9722#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9721#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9720#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9719#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9718#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9717#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9716#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9715#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9714#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9713#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9712#L17-4 foo_#res#1 := foo_~i~0#1; 9711#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9710#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9709#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9708#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9707#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9706#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9705#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9704#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9703#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9702#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9701#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9700#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9699#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9698#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9697#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9696#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9695#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9694#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9693#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9692#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9691#L17-4 foo_#res#1 := foo_~i~0#1; 9690#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9689#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9688#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9687#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9686#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9685#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9684#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9683#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9682#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9681#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9680#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9679#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9678#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9677#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9676#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9675#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9674#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9673#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9672#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9671#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9670#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9669#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9668#L17-4 foo_#res#1 := foo_~i~0#1; 9667#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9666#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9665#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9643#L17-3 [2023-11-06 22:37:20,273 INFO L750 eck$LassoCheckResult]: Loop: 9643#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9664#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9663#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9662#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9661#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9660#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9659#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9658#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9657#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9656#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9655#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9654#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9653#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9652#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9651#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9650#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9649#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 9648#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 9647#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 9646#L17-4 foo_#res#1 := foo_~i~0#1; 9645#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 9644#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9642#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 9643#L17-3 [2023-11-06 22:37:20,274 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:20,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1066401937, now seen corresponding path program 19 times [2023-11-06 22:37:20,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:20,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876945960] [2023-11-06 22:37:20,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:20,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:20,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:20,388 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:20,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:20,503 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:20,503 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:20,504 INFO L85 PathProgramCache]: Analyzing trace with hash 392009165, now seen corresponding path program 9 times [2023-11-06 22:37:20,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:20,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [347368900] [2023-11-06 22:37:20,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:20,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:20,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:20,525 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:20,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:20,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:20,543 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:20,544 INFO L85 PathProgramCache]: Analyzing trace with hash 537533087, now seen corresponding path program 20 times [2023-11-06 22:37:20,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:20,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925833792] [2023-11-06 22:37:20,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:20,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:20,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:37:21,689 INFO L134 CoverageAnalysis]: Checked inductivity of 3637 backedges. 2241 proven. 1111 refuted. 0 times theorem prover too weak. 285 trivial. 0 not checked. [2023-11-06 22:37:21,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:37:21,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1925833792] [2023-11-06 22:37:21,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1925833792] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:37:21,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [543498843] [2023-11-06 22:37:21,690 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-06 22:37:21,691 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:37:21,691 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:37:21,698 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:37:21,701 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_31e4ee48-8e9c-47f5-b295-53ae6eb2167e/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2023-11-06 22:37:22,016 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-06 22:37:22,017 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:37:22,023 INFO L262 TraceCheckSpWp]: Trace formula consists of 918 conjuncts, 23 conjunts are in the unsatisfiable core [2023-11-06 22:37:22,028 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:37:22,552 INFO L134 CoverageAnalysis]: Checked inductivity of 3637 backedges. 2326 proven. 1026 refuted. 0 times theorem prover too weak. 285 trivial. 0 not checked. [2023-11-06 22:37:22,552 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:37:23,184 INFO L134 CoverageAnalysis]: Checked inductivity of 3637 backedges. 2326 proven. 1026 refuted. 0 times theorem prover too weak. 285 trivial. 0 not checked. [2023-11-06 22:37:23,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [543498843] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:37:23,184 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:37:23,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 43 [2023-11-06 22:37:23,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369497214] [2023-11-06 22:37:23,185 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:37:25,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:37:25,304 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2023-11-06 22:37:25,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=394, Invalid=1412, Unknown=0, NotChecked=0, Total=1806 [2023-11-06 22:37:25,305 INFO L87 Difference]: Start difference. First operand 176 states and 183 transitions. cyclomatic complexity: 13 Second operand has 43 states, 43 states have (on average 3.186046511627907) internal successors, (137), 43 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:27,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:37:27,256 INFO L93 Difference]: Finished difference Result 224 states and 235 transitions. [2023-11-06 22:37:27,256 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 224 states and 235 transitions. [2023-11-06 22:37:27,258 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 30 [2023-11-06 22:37:27,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 224 states to 223 states and 234 transitions. [2023-11-06 22:37:27,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 131 [2023-11-06 22:37:27,261 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 131 [2023-11-06 22:37:27,261 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 234 transitions. [2023-11-06 22:37:27,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:37:27,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 234 transitions. [2023-11-06 22:37:27,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 234 transitions. [2023-11-06 22:37:27,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 178. [2023-11-06 22:37:27,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.0393258426966292) internal successors, (185), 177 states have internal predecessors, (185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:37:27,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 185 transitions. [2023-11-06 22:37:27,266 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 185 transitions. [2023-11-06 22:37:27,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2023-11-06 22:37:27,269 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 185 transitions. [2023-11-06 22:37:27,269 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:37:27,269 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 185 transitions. [2023-11-06 22:37:27,270 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28 [2023-11-06 22:37:27,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:37:27,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:37:27,275 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [45, 45, 10, 9, 9, 9, 9, 1, 1] [2023-11-06 22:37:27,275 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [10, 10, 1, 1, 1, 1, 1] [2023-11-06 22:37:27,276 INFO L748 eck$LassoCheckResult]: Stem: 11161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier; 11162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~ret3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~post4#1, main_~i~1#1, main_~#b~0#1.base, main_~#b~0#1.offset, main_~#mask~0#1.base, main_~#mask~0#1.offset;havoc main_~i~1#1;call main_~#b~0#1.base, main_~#b~0#1.offset := #Ultimate.allocOnStack(128);call main_~#mask~0#1.base, main_~#mask~0#1.offset := #Ultimate.allocOnStack(32);main_~i~1#1 := 0; 11163#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11326#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11325#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11323#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11166#L17-4 foo_#res#1 := foo_~i~0#1; 11167#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11158#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11159#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11164#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11149#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11150#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11324#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11322#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11321#L17-4 foo_#res#1 := foo_~i~0#1; 11153#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11154#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11320#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11319#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11318#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11317#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11316#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11315#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11314#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11313#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11312#L17-4 foo_#res#1 := foo_~i~0#1; 11311#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11310#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11309#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11308#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11307#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11306#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11305#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11304#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11303#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11302#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11301#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11300#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11299#L17-4 foo_#res#1 := foo_~i~0#1; 11298#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11297#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11296#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11295#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11294#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11293#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11292#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11291#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11290#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11289#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11288#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11287#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11286#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11285#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11284#L17-4 foo_#res#1 := foo_~i~0#1; 11283#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11282#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11281#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11280#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11279#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11165#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11151#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11152#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11278#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11277#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11276#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11275#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11274#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11272#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11269#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11267#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11265#L17-4 foo_#res#1 := foo_~i~0#1; 11263#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11261#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11259#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11257#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11255#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11253#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11252#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11251#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11250#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11249#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11248#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11247#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11246#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11245#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11244#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11243#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11242#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11241#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11240#L17-4 foo_#res#1 := foo_~i~0#1; 11239#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11238#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11237#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11236#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11235#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11234#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11233#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11232#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11231#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11230#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11229#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11228#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11227#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11226#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11225#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11224#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11223#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11222#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11221#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11220#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11219#L17-4 foo_#res#1 := foo_~i~0#1; 11218#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11217#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11216#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11215#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11214#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11213#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11212#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11211#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11210#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11209#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11208#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11207#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11206#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11205#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11204#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11203#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11202#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11201#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11200#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11199#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11198#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11197#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11196#L17-4 foo_#res#1 := foo_~i~0#1; 11195#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11194#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11193#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11169#L17-3 [2023-11-06 22:37:27,276 INFO L750 eck$LassoCheckResult]: Loop: 11169#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11192#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11191#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11190#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11189#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11188#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11187#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11186#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11185#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11184#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11183#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11182#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11181#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11180#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11179#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11178#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11177#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11176#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11175#L17-3 assume !!(foo_~i~0#1 <= foo_~size#1);assume 0 <= foo_~i~0#1 % 4294967296 && foo_~i~0#1 % 4294967296 < 32;call foo_#t~mem1#1 := read~int(foo_~b#1.base, foo_~b#1.offset + foo_~i~0#1, 1);foo_~a~0#1 := foo_~a~0#1[foo_~i~0#1 := foo_#t~mem1#1];havoc foo_#t~mem1#1; 11174#L17-2 foo_#t~post0#1 := foo_~i~0#1;foo_~i~0#1 := 1 + foo_#t~post0#1;havoc foo_#t~post0#1; 11173#L17-3 assume !(foo_~i~0#1 <= foo_~size#1); 11172#L17-4 foo_#res#1 := foo_~i~0#1; 11171#foo_returnLabel#1 main_#t~ret3#1 := foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;havoc foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1;assume { :end_inline_foo } true;call write~int(main_#t~ret3#1, main_~#b~0#1.base, main_~#b~0#1.offset + 4 * main_~i~1#1, 4);havoc main_#t~ret3#1; 11170#L26-2 main_#t~post2#1 := main_~i~1#1;main_~i~1#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11168#L26-3 assume !!(main_~i~1#1 % 4294967296 < 32);assume { :begin_inline_foo } true;foo_#in~b#1.base, foo_#in~b#1.offset, foo_#in~size#1 := main_~#mask~0#1.base, main_~#mask~0#1.offset, main_~i~1#1;havoc foo_#res#1;havoc foo_#t~mem1#1, foo_#t~post0#1, foo_~b#1.base, foo_~b#1.offset, foo_~size#1, foo_~a~0#1, foo_~i~0#1;foo_~b#1.base, foo_~b#1.offset := foo_#in~b#1.base, foo_#in~b#1.offset;foo_~size#1 := foo_#in~size#1;havoc foo_~a~0#1;havoc foo_~i~0#1;foo_~i~0#1 := 0; 11169#L17-3 [2023-11-06 22:37:27,276 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:27,277 INFO L85 PathProgramCache]: Analyzing trace with hash -1066401937, now seen corresponding path program 21 times [2023-11-06 22:37:27,277 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:27,277 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483434781] [2023-11-06 22:37:27,277 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:27,277 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:27,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,429 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:27,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,535 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:27,536 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:27,536 INFO L85 PathProgramCache]: Analyzing trace with hash 414838155, now seen corresponding path program 10 times [2023-11-06 22:37:27,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:27,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236411899] [2023-11-06 22:37:27,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:27,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:27,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:27,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,586 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:37:27,587 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:37:27,587 INFO L85 PathProgramCache]: Analyzing trace with hash -1470593571, now seen corresponding path program 22 times [2023-11-06 22:37:27,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:37:27,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342527549] [2023-11-06 22:37:27,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:37:27,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:37:27,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,730 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:37:27,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:37:27,874 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:21,173 WARN L293 SmtUtils]: Spent 2.83m on a formula simplification. DAG size of input: 1022 DAG size of output: 665 (called from [L 279] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition)