./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/kundu2.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:40:07,654 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:40:07,740 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:40:07,746 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:40:07,746 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:40:07,780 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:40:07,781 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:40:07,781 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:40:07,782 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:40:07,783 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:40:07,784 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:40:07,784 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:40:07,785 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:40:07,785 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:40:07,786 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:40:07,786 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:40:07,792 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:40:07,797 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:40:07,797 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:40:07,798 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:40:07,800 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:40:07,800 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:40:07,801 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:40:07,801 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:40:07,802 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:40:07,802 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:40:07,802 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:40:07,803 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:40:07,803 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:40:07,804 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:40:07,805 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:40:07,805 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:40:07,806 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:40:07,806 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:40:07,806 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:40:07,807 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:40:07,807 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2023-11-06 22:40:08,161 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:40:08,203 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:40:08,206 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:40:08,207 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:40:08,208 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:40:08,209 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/kundu2.cil.c [2023-11-06 22:40:11,322 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:40:11,614 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:40:11,618 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/sv-benchmarks/c/systemc/kundu2.cil.c [2023-11-06 22:40:11,635 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/data/9759695f3/4a856f5a0055428caba147808e038399/FLAGb952cc6e2 [2023-11-06 22:40:11,655 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/data/9759695f3/4a856f5a0055428caba147808e038399 [2023-11-06 22:40:11,662 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:40:11,664 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:40:11,668 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:40:11,669 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:40:11,675 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:40:11,676 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:40:11" (1/1) ... [2023-11-06 22:40:11,677 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@52c34fe1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:11, skipping insertion in model container [2023-11-06 22:40:11,677 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:40:11" (1/1) ... [2023-11-06 22:40:11,736 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:40:12,015 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:40:12,042 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:40:12,084 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:40:12,102 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:40:12,103 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12 WrapperNode [2023-11-06 22:40:12,103 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:40:12,104 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:40:12,104 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:40:12,105 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:40:12,112 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,121 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,163 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 535 [2023-11-06 22:40:12,164 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:40:12,165 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:40:12,165 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:40:12,165 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:40:12,175 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,175 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,179 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,179 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,190 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,198 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,201 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,204 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,210 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:40:12,211 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:40:12,211 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:40:12,211 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:40:12,212 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (1/1) ... [2023-11-06 22:40:12,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:12,235 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:12,250 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:12,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:40:12,320 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:40:12,320 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:40:12,320 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:40:12,321 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:40:12,429 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:40:12,431 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:40:12,974 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:40:12,984 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:40:12,985 INFO L302 CfgBuilder]: Removed 5 assume(true) statements. [2023-11-06 22:40:12,988 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:12 BoogieIcfgContainer [2023-11-06 22:40:12,988 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:40:12,989 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:40:12,989 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:40:12,993 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:40:12,994 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:12,995 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:40:11" (1/3) ... [2023-11-06 22:40:12,996 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@635ce02d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:40:12, skipping insertion in model container [2023-11-06 22:40:12,996 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:12,996 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:12" (2/3) ... [2023-11-06 22:40:12,997 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@635ce02d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:40:12, skipping insertion in model container [2023-11-06 22:40:12,997 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:12,997 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:12" (3/3) ... [2023-11-06 22:40:12,999 INFO L332 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2023-11-06 22:40:13,066 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:40:13,067 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:40:13,067 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:40:13,067 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:40:13,067 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:40:13,067 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:40:13,067 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:40:13,067 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:40:13,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2023-11-06 22:40:13,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:13,106 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:13,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:40:13,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 157 [2023-11-06 22:40:13,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:13,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:13,144 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,158 INFO L748 eck$LassoCheckResult]: Stem: 130#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 137#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 189#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 134#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L304true assume !(1 == ~P_1_i~0);~P_1_st~0 := 2; 79#L304-2true assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 15#L309-1true assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 148#L314-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77#fire_delta_events_returnLabel#1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 4#L117true assume !(1 == ~P_1_pc~0); 19#L117-2true is_P_1_triggered_~__retres1~0#1 := 0; 147#L128true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 43#is_P_1_triggered_returnLabel#1true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 128#L477true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 166#L477-2true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 84#L185true assume 1 == ~P_2_pc~0; 53#L186true assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 54#L196true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 93#is_P_2_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 80#L485true assume !(0 != activate_threads_~tmp___0~1#1); 108#L485-2true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 123#L267true assume 1 == ~C_1_pc~0; 122#L268true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 23#L288true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 188#is_C_1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 116#L493true assume !(0 != activate_threads_~tmp___1~1#1); 149#L493-2true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184#reset_delta_events_returnLabel#1true assume { :end_inline_reset_delta_events } true; 145#L547-2true [2023-11-06 22:40:13,160 INFO L750 eck$LassoCheckResult]: Loop: 145#L547-2true assume !false; 151#L548true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 73#L396true assume false; 70#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34#fire_delta_events_returnLabel#2true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 30#L117-6true assume !(1 == ~P_1_pc~0); 35#L117-8true is_P_1_triggered_~__retres1~0#1 := 0; 194#L128-2true is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38#is_P_1_triggered_returnLabel#3true activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 21#L477-6true assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 56#L477-8true assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 36#L185-6true assume !(1 == ~P_2_pc~0); 51#L185-8true is_P_2_triggered_~__retres1~1#1 := 0; 187#L196-2true is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 191#is_P_2_triggered_returnLabel#3true activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 141#L485-6true assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 98#L485-8true assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 69#L267-6true assume 1 == ~C_1_pc~0; 179#L268-2true assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 142#L288-2true is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 99#is_C_1_triggered_returnLabel#3true activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144#L493-6true assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 27#L493-8true havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81#reset_delta_events_returnLabel#2true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 183#L327-1true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 90#L344-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 175#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 91#L566true assume !(0 == start_simulation_~tmp~3#1); 41#L566-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31#L327-2true assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 161#L344-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 32#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 78#L521true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138#L528true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 102#stop_simulation_returnLabel#1true start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 112#L579true assume !(0 != start_simulation_~tmp___0~2#1); 145#L547-2true [2023-11-06 22:40:13,168 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:13,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1332213672, now seen corresponding path program 1 times [2023-11-06 22:40:13,180 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:13,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1242829369] [2023-11-06 22:40:13,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:13,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:13,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:13,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:13,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:13,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1242829369] [2023-11-06 22:40:13,437 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1242829369] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:13,437 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:13,438 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:13,439 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130526605] [2023-11-06 22:40:13,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:13,445 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:13,446 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:13,446 INFO L85 PathProgramCache]: Analyzing trace with hash 2086830017, now seen corresponding path program 1 times [2023-11-06 22:40:13,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:13,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1484608519] [2023-11-06 22:40:13,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:13,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:13,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:13,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:13,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:13,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1484608519] [2023-11-06 22:40:13,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1484608519] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:13,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:13,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:40:13,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246648377] [2023-11-06 22:40:13,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:13,482 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:13,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:13,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:13,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:13,520 INFO L87 Difference]: Start difference. First operand has 194 states, 193 states have (on average 1.4922279792746114) internal successors, (288), 193 states have internal predecessors, (288), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:13,559 INFO L93 Difference]: Finished difference Result 186 states and 268 transitions. [2023-11-06 22:40:13,560 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 268 transitions. [2023-11-06 22:40:13,566 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2023-11-06 22:40:13,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 178 states and 260 transitions. [2023-11-06 22:40:13,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2023-11-06 22:40:13,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2023-11-06 22:40:13,577 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 260 transitions. [2023-11-06 22:40:13,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:13,579 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2023-11-06 22:40:13,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 260 transitions. [2023-11-06 22:40:13,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2023-11-06 22:40:13,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4606741573033708) internal successors, (260), 177 states have internal predecessors, (260), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 260 transitions. [2023-11-06 22:40:13,620 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 260 transitions. [2023-11-06 22:40:13,621 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:13,628 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 260 transitions. [2023-11-06 22:40:13,629 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:40:13,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 260 transitions. [2023-11-06 22:40:13,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2023-11-06 22:40:13,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:13,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:13,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,635 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,636 INFO L748 eck$LassoCheckResult]: Stem: 479#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 499#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 559#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 448#L309-1 assume !(1 == ~C_1_i~0);~C_1_st~0 := 2; 449#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 529#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 398#L117 assume !(1 == ~P_1_pc~0); 399#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 461#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 520#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 476#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 477#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 553#L185 assume 1 == ~P_2_pc~0; 535#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 512#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 536#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 560#L485 assume !(0 != activate_threads_~tmp___0~1#1); 403#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 404#L267 assume 1 == ~C_1_pc~0; 457#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 458#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 475#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 438#L493 assume !(0 != activate_threads_~tmp___1~1#1); 439#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 530#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 422#L547-2 [2023-11-06 22:40:13,636 INFO L750 eck$LassoCheckResult]: Loop: 422#L547-2 assume !false; 523#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 532#L396 assume !false; 528#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 451#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 412#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 429#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 430#L361 assume !(0 != eval_~tmp___2~0#1); 549#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 556#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 502#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 488#L117-6 assume 1 == ~P_1_pc~0; 489#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 504#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 507#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 462#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 463#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 505#L185-6 assume 1 == ~P_2_pc~0; 408#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 409#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 566#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 517#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 518#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 554#L267-6 assume 1 == ~C_1_pc~0; 555#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 391#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 519#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 521#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 482#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 483#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 558#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 472#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 562#L566 assume !(0 == start_simulation_~tmp~3#1); 513#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 491#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 485#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 493#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 494#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 509#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 510#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 421#L579 assume !(0 != start_simulation_~tmp___0~2#1); 422#L547-2 [2023-11-06 22:40:13,637 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:13,637 INFO L85 PathProgramCache]: Analyzing trace with hash 1466227178, now seen corresponding path program 1 times [2023-11-06 22:40:13,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:13,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1223853603] [2023-11-06 22:40:13,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:13,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:13,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:13,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:13,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:13,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1223853603] [2023-11-06 22:40:13,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1223853603] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:13,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:13,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:13,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005684541] [2023-11-06 22:40:13,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:13,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:13,709 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:13,709 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 1 times [2023-11-06 22:40:13,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:13,710 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718838014] [2023-11-06 22:40:13,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:13,711 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:13,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:13,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:13,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:13,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718838014] [2023-11-06 22:40:13,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718838014] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:13,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:13,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:13,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708632243] [2023-11-06 22:40:13,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:13,876 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:13,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:13,877 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:13,878 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:13,878 INFO L87 Difference]: Start difference. First operand 178 states and 260 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:13,902 INFO L93 Difference]: Finished difference Result 178 states and 259 transitions. [2023-11-06 22:40:13,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 259 transitions. [2023-11-06 22:40:13,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2023-11-06 22:40:13,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 259 transitions. [2023-11-06 22:40:13,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 178 [2023-11-06 22:40:13,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 178 [2023-11-06 22:40:13,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 259 transitions. [2023-11-06 22:40:13,921 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:13,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2023-11-06 22:40:13,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 259 transitions. [2023-11-06 22:40:13,934 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2023-11-06 22:40:13,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.4550561797752808) internal successors, (259), 177 states have internal predecessors, (259), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:13,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 259 transitions. [2023-11-06 22:40:13,936 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 259 transitions. [2023-11-06 22:40:13,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:13,937 INFO L428 stractBuchiCegarLoop]: Abstraction has 178 states and 259 transitions. [2023-11-06 22:40:13,938 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:40:13,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 259 transitions. [2023-11-06 22:40:13,940 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 145 [2023-11-06 22:40:13,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:13,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:13,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:13,942 INFO L748 eck$LassoCheckResult]: Stem: 844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 863#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 864#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 923#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 811#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 812#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 894#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 763#L117 assume !(1 == ~P_1_pc~0); 764#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 826#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 885#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 841#L477 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 842#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 918#L185 assume 1 == ~P_2_pc~0; 899#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 877#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 900#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 924#L485 assume !(0 != activate_threads_~tmp___0~1#1); 766#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 767#L267 assume 1 == ~C_1_pc~0; 822#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 823#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 835#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 803#L493 assume !(0 != activate_threads_~tmp___1~1#1); 804#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 895#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 787#L547-2 [2023-11-06 22:40:13,943 INFO L750 eck$LassoCheckResult]: Loop: 787#L547-2 assume !false; 887#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 897#L396 assume !false; 892#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 815#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 777#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 794#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 795#L361 assume !(0 != eval_~tmp___2~0#1); 913#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 921#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 867#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 853#L117-6 assume 1 == ~P_1_pc~0; 854#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 869#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 872#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 827#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 828#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 870#L185-6 assume 1 == ~P_2_pc~0; 773#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 774#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 931#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 882#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 883#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 919#L267-6 assume 1 == ~C_1_pc~0; 920#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 756#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 884#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 886#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 847#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 848#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 925#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 838#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 926#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 927#L566 assume !(0 == start_simulation_~tmp~3#1); 878#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 856#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 850#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 859#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 874#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 875#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 786#L579 assume !(0 != start_simulation_~tmp___0~2#1); 787#L547-2 [2023-11-06 22:40:13,943 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:13,944 INFO L85 PathProgramCache]: Analyzing trace with hash 1247372460, now seen corresponding path program 1 times [2023-11-06 22:40:13,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:13,944 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [128658208] [2023-11-06 22:40:13,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:13,945 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:13,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,071 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,071 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [128658208] [2023-11-06 22:40:14,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [128658208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:14,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2046131568] [2023-11-06 22:40:14,073 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,073 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:14,074 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:14,074 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 2 times [2023-11-06 22:40:14,074 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:14,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094820067] [2023-11-06 22:40:14,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:14,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:14,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094820067] [2023-11-06 22:40:14,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094820067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,222 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:14,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1674125064] [2023-11-06 22:40:14,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,223 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:14,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:14,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:40:14,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:40:14,224 INFO L87 Difference]: Start difference. First operand 178 states and 259 transitions. cyclomatic complexity: 82 Second operand has 5 states, 5 states have (on average 5.6) internal successors, (28), 5 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:14,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:14,387 INFO L93 Difference]: Finished difference Result 403 states and 584 transitions. [2023-11-06 22:40:14,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 403 states and 584 transitions. [2023-11-06 22:40:14,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 332 [2023-11-06 22:40:14,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 403 states to 403 states and 584 transitions. [2023-11-06 22:40:14,397 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 403 [2023-11-06 22:40:14,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 403 [2023-11-06 22:40:14,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 403 states and 584 transitions. [2023-11-06 22:40:14,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:14,401 INFO L218 hiAutomatonCegarLoop]: Abstraction has 403 states and 584 transitions. [2023-11-06 22:40:14,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 403 states and 584 transitions. [2023-11-06 22:40:14,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 403 to 190. [2023-11-06 22:40:14,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190 states, 190 states have (on average 1.4263157894736842) internal successors, (271), 189 states have internal predecessors, (271), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:14,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190 states to 190 states and 271 transitions. [2023-11-06 22:40:14,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190 states and 271 transitions. [2023-11-06 22:40:14,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:40:14,426 INFO L428 stractBuchiCegarLoop]: Abstraction has 190 states and 271 transitions. [2023-11-06 22:40:14,427 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:40:14,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190 states and 271 transitions. [2023-11-06 22:40:14,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 154 [2023-11-06 22:40:14,430 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:14,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:14,433 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:14,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:14,435 INFO L748 eck$LassoCheckResult]: Stem: 1440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 1441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 1464#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1459#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1460#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 1530#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 1409#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 1410#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1495#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1359#L117 assume !(1 == ~P_1_pc~0); 1360#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 1422#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1491#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1437#L477 assume !(0 != activate_threads_~tmp~1#1); 1438#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1521#L185 assume 1 == ~P_2_pc~0; 1501#L186 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1474#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1502#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1531#L485 assume !(0 != activate_threads_~tmp___0~1#1); 1364#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1365#L267 assume 1 == ~C_1_pc~0; 1418#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1419#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1436#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1399#L493 assume !(0 != activate_threads_~tmp___1~1#1); 1400#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1496#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 1383#L547-2 [2023-11-06 22:40:14,436 INFO L750 eck$LassoCheckResult]: Loop: 1383#L547-2 assume !false; 1487#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 1498#L396 assume !false; 1492#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1411#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1373#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1390#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1391#L361 assume !(0 != eval_~tmp___2~0#1); 1514#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1524#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1463#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 1449#L117-6 assume 1 == ~P_1_pc~0; 1450#L118-2 assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1; 1494#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 1468#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 1469#L477-6 assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0; 1424#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 1466#L185-6 assume 1 == ~P_2_pc~0; 1369#L186-2 assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1; 1370#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 1538#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1479#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 1480#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 1522#L267-6 assume 1 == ~C_1_pc~0; 1523#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 1352#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 1481#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1484#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 1443#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1444#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1529#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1433#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 1533#L566 assume !(0 == start_simulation_~tmp~3#1); 1475#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 1452#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 1446#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 1454#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 1455#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1471#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1472#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 1382#L579 assume !(0 != start_simulation_~tmp___0~2#1); 1383#L547-2 [2023-11-06 22:40:14,437 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:14,438 INFO L85 PathProgramCache]: Analyzing trace with hash -32491218, now seen corresponding path program 1 times [2023-11-06 22:40:14,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:14,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816383382] [2023-11-06 22:40:14,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:14,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:14,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,543 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,543 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816383382] [2023-11-06 22:40:14,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816383382] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-06 22:40:14,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018279501] [2023-11-06 22:40:14,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,547 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:14,553 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:14,554 INFO L85 PathProgramCache]: Analyzing trace with hash 1120930777, now seen corresponding path program 3 times [2023-11-06 22:40:14,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:14,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152654174] [2023-11-06 22:40:14,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:14,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:14,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152654174] [2023-11-06 22:40:14,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152654174] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:14,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [63412136] [2023-11-06 22:40:14,617 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,618 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:14,618 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:14,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:40:14,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:40:14,619 INFO L87 Difference]: Start difference. First operand 190 states and 271 transitions. cyclomatic complexity: 82 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:14,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:14,721 INFO L93 Difference]: Finished difference Result 475 states and 665 transitions. [2023-11-06 22:40:14,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 475 states and 665 transitions. [2023-11-06 22:40:14,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 412 [2023-11-06 22:40:14,730 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 475 states to 475 states and 665 transitions. [2023-11-06 22:40:14,731 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 475 [2023-11-06 22:40:14,732 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 475 [2023-11-06 22:40:14,732 INFO L73 IsDeterministic]: Start isDeterministic. Operand 475 states and 665 transitions. [2023-11-06 22:40:14,733 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:14,733 INFO L218 hiAutomatonCegarLoop]: Abstraction has 475 states and 665 transitions. [2023-11-06 22:40:14,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 475 states and 665 transitions. [2023-11-06 22:40:14,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 475 to 433. [2023-11-06 22:40:14,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 433 states, 433 states have (on average 1.4087759815242493) internal successors, (610), 432 states have internal predecessors, (610), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:14,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 610 transitions. [2023-11-06 22:40:14,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 433 states and 610 transitions. [2023-11-06 22:40:14,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:40:14,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 433 states and 610 transitions. [2023-11-06 22:40:14,767 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:40:14,767 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 433 states and 610 transitions. [2023-11-06 22:40:14,770 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 396 [2023-11-06 22:40:14,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:14,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:14,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:14,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:14,772 INFO L748 eck$LassoCheckResult]: Stem: 2118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 2119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 2141#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2136#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2137#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 2208#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 2084#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 2085#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2171#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2035#L117 assume !(1 == ~P_1_pc~0); 2036#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 2099#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2159#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2114#L477 assume !(0 != activate_threads_~tmp~1#1); 2115#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2199#L185 assume !(1 == ~P_2_pc~0); 2150#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 2151#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2180#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2209#L485 assume !(0 != activate_threads_~tmp___0~1#1); 2037#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2038#L267 assume 1 == ~C_1_pc~0; 2095#L268 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2096#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2108#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2073#L493 assume !(0 != activate_threads_~tmp___1~1#1); 2074#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2175#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 2058#L547-2 [2023-11-06 22:40:14,772 INFO L750 eck$LassoCheckResult]: Loop: 2058#L547-2 assume !false; 2161#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 2178#L396 assume !false; 2168#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2088#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2048#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2064#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2065#L361 assume !(0 != eval_~tmp___2~0#1); 2193#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2202#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2140#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 2127#L117-6 assume !(1 == ~P_1_pc~0); 2128#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 2142#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 2146#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 2100#L477-6 assume !(0 != activate_threads_~tmp~1#1); 2101#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 2143#L185-6 assume !(1 == ~P_2_pc~0); 2144#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 2177#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 2217#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2156#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 2157#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 2200#L267-6 assume 1 == ~C_1_pc~0; 2201#L268-2 assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1; 2030#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 2158#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2160#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 2121#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2122#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2210#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2111#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2211#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 2212#L566 assume !(0 == start_simulation_~tmp~3#1); 2152#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 2129#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 2124#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 2131#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 2132#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2148#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2149#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 2057#L579 assume !(0 != start_simulation_~tmp___0~2#1); 2058#L547-2 [2023-11-06 22:40:14,773 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:14,773 INFO L85 PathProgramCache]: Analyzing trace with hash -1311815953, now seen corresponding path program 1 times [2023-11-06 22:40:14,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:14,774 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395529157] [2023-11-06 22:40:14,774 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:14,774 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:14,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395529157] [2023-11-06 22:40:14,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395529157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,822 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2023-11-06 22:40:14,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927850266] [2023-11-06 22:40:14,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,822 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:14,823 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:14,823 INFO L85 PathProgramCache]: Analyzing trace with hash -784916195, now seen corresponding path program 1 times [2023-11-06 22:40:14,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:14,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533524991] [2023-11-06 22:40:14,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:14,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:14,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:14,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:14,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:14,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533524991] [2023-11-06 22:40:14,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533524991] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:14,873 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:14,873 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:14,873 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1146706811] [2023-11-06 22:40:14,873 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:14,874 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:14,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:14,874 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:40:14,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:40:14,875 INFO L87 Difference]: Start difference. First operand 433 states and 610 transitions. cyclomatic complexity: 179 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:15,008 INFO L93 Difference]: Finished difference Result 1179 states and 1624 transitions. [2023-11-06 22:40:15,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1179 states and 1624 transitions. [2023-11-06 22:40:15,019 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1099 [2023-11-06 22:40:15,031 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1179 states to 1179 states and 1624 transitions. [2023-11-06 22:40:15,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1179 [2023-11-06 22:40:15,033 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1179 [2023-11-06 22:40:15,033 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1179 states and 1624 transitions. [2023-11-06 22:40:15,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:15,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1179 states and 1624 transitions. [2023-11-06 22:40:15,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1179 states and 1624 transitions. [2023-11-06 22:40:15,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1179 to 1120. [2023-11-06 22:40:15,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1120 states, 1120 states have (on average 1.3857142857142857) internal successors, (1552), 1119 states have internal predecessors, (1552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1120 states to 1120 states and 1552 transitions. [2023-11-06 22:40:15,078 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2023-11-06 22:40:15,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:40:15,080 INFO L428 stractBuchiCegarLoop]: Abstraction has 1120 states and 1552 transitions. [2023-11-06 22:40:15,094 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:40:15,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1120 states and 1552 transitions. [2023-11-06 22:40:15,102 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1078 [2023-11-06 22:40:15,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:15,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:15,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,106 INFO L748 eck$LassoCheckResult]: Stem: 3743#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 3744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 3772#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3764#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3765#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 3864#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 3710#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 3711#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3810#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3660#L117 assume !(1 == ~P_1_pc~0); 3661#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 3722#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3794#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3739#L477 assume !(0 != activate_threads_~tmp~1#1); 3740#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 3851#L185 assume !(1 == ~P_2_pc~0); 3784#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 3785#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 3819#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3865#L485 assume !(0 != activate_threads_~tmp___0~1#1); 3662#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 3663#L267 assume !(1 == ~C_1_pc~0); 3723#L267-2 assume 2 == ~C_1_pc~0; 3856#L278 assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1; 3732#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3733#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3699#L493 assume !(0 != activate_threads_~tmp___1~1#1); 3700#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3814#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 3797#L547-2 [2023-11-06 22:40:15,106 INFO L750 eck$LassoCheckResult]: Loop: 3797#L547-2 assume !false; 3798#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 3860#L396 assume !false; 3861#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4738#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3745#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3746#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3840#L361 assume !(0 != eval_~tmp___2~0#1); 3841#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4764#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3770#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 3771#L117-6 assume !(1 == ~P_1_pc~0); 3773#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 3774#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 3778#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 3779#L477-6 assume !(0 != activate_threads_~tmp~1#1); 4670#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 4671#L185-6 assume !(1 == ~P_2_pc~0); 4682#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 4683#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 4678#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4679#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 4674#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 4675#L267-6 assume !(1 == ~C_1_pc~0); 3826#L267-8 assume !(2 == ~C_1_pc~0); 3827#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 3792#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 3793#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3795#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 3796#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3866#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 3867#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3886#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3887#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 3888#L566 assume !(0 == start_simulation_~tmp~3#1); 3889#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 4741#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 3843#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 3844#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 3862#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3863#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3896#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 3897#L579 assume !(0 != start_simulation_~tmp___0~2#1); 3797#L547-2 [2023-11-06 22:40:15,107 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,108 INFO L85 PathProgramCache]: Analyzing trace with hash -122788309, now seen corresponding path program 1 times [2023-11-06 22:40:15,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680637373] [2023-11-06 22:40:15,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:15,192 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:15,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:15,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680637373] [2023-11-06 22:40:15,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680637373] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:15,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:15,194 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:15,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [181801959] [2023-11-06 22:40:15,199 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:15,199 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:15,200 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,200 INFO L85 PathProgramCache]: Analyzing trace with hash -1417336067, now seen corresponding path program 1 times [2023-11-06 22:40:15,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581639868] [2023-11-06 22:40:15,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:15,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:15,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:15,264 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [581639868] [2023-11-06 22:40:15,264 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [581639868] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:15,264 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:15,265 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:15,265 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [308748019] [2023-11-06 22:40:15,265 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:15,266 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:15,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:15,267 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:15,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:15,268 INFO L87 Difference]: Start difference. First operand 1120 states and 1552 transitions. cyclomatic complexity: 436 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:15,329 INFO L93 Difference]: Finished difference Result 1488 states and 2031 transitions. [2023-11-06 22:40:15,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1488 states and 2031 transitions. [2023-11-06 22:40:15,343 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1441 [2023-11-06 22:40:15,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1488 states to 1488 states and 2031 transitions. [2023-11-06 22:40:15,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1488 [2023-11-06 22:40:15,361 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1488 [2023-11-06 22:40:15,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1488 states and 2031 transitions. [2023-11-06 22:40:15,363 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:15,364 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1488 states and 2031 transitions. [2023-11-06 22:40:15,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1488 states and 2031 transitions. [2023-11-06 22:40:15,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1488 to 1464. [2023-11-06 22:40:15,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.3668032786885247) internal successors, (2001), 1463 states have internal predecessors, (2001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2001 transitions. [2023-11-06 22:40:15,399 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2023-11-06 22:40:15,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:15,402 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2001 transitions. [2023-11-06 22:40:15,402 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:40:15,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2001 transitions. [2023-11-06 22:40:15,412 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1417 [2023-11-06 22:40:15,413 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:15,413 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:15,417 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,418 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,420 INFO L748 eck$LassoCheckResult]: Stem: 6358#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 6359#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 6386#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6379#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6380#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 6467#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 6327#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 6328#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6421#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6277#L117 assume !(1 == ~P_1_pc~0); 6278#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 6338#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6407#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6354#L477 assume !(0 != activate_threads_~tmp~1#1); 6355#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6461#L185 assume !(1 == ~P_2_pc~0); 6397#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 6398#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6431#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6468#L485 assume !(0 != activate_threads_~tmp___0~1#1); 6279#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6280#L267 assume !(1 == ~C_1_pc~0); 6339#L267-2 assume !(2 == ~C_1_pc~0); 6430#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 6349#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6350#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6315#L493 assume !(0 != activate_threads_~tmp___1~1#1); 6316#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6425#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 6303#L547-2 [2023-11-06 22:40:15,420 INFO L750 eck$LassoCheckResult]: Loop: 6303#L547-2 assume !false; 6410#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 6429#L396 assume !false; 6418#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6332#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6291#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6306#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6307#L361 assume !(0 != eval_~tmp___2~0#1); 6450#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6463#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6385#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 6370#L117-6 assume !(1 == ~P_1_pc~0); 6371#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 6387#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 6391#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 6340#L477-6 assume !(0 != activate_threads_~tmp~1#1); 6341#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 6433#L185-6 assume !(1 == ~P_2_pc~0); 6427#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 6428#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 6491#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 6403#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 6404#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 6462#L267-6 assume !(1 == ~C_1_pc~0); 6437#L267-8 assume !(2 == ~C_1_pc~0); 6438#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 6452#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 6492#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6408#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 6409#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6469#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 6470#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 6352#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 6490#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 7695#L566 assume !(0 == start_simulation_~tmp~3#1); 7693#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 7642#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 7639#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 7638#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 7636#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7635#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7634#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 6302#L579 assume !(0 != start_simulation_~tmp___0~2#1); 6303#L547-2 [2023-11-06 22:40:15,421 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,421 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 1 times [2023-11-06 22:40:15,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [656252211] [2023-11-06 22:40:15,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:15,440 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:15,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:15,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:15,485 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,485 INFO L85 PathProgramCache]: Analyzing trace with hash -1417336067, now seen corresponding path program 2 times [2023-11-06 22:40:15,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780627240] [2023-11-06 22:40:15,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:15,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:15,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:15,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1780627240] [2023-11-06 22:40:15,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1780627240] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:15,546 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:15,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:40:15,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1257139573] [2023-11-06 22:40:15,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:15,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:15,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:15,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:40:15,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:40:15,548 INFO L87 Difference]: Start difference. First operand 1464 states and 2001 transitions. cyclomatic complexity: 541 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:15,666 INFO L93 Difference]: Finished difference Result 2589 states and 3511 transitions. [2023-11-06 22:40:15,667 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2589 states and 3511 transitions. [2023-11-06 22:40:15,689 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2524 [2023-11-06 22:40:15,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2589 states to 2589 states and 3511 transitions. [2023-11-06 22:40:15,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2589 [2023-11-06 22:40:15,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2589 [2023-11-06 22:40:15,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2589 states and 3511 transitions. [2023-11-06 22:40:15,720 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:15,720 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2589 states and 3511 transitions. [2023-11-06 22:40:15,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2589 states and 3511 transitions. [2023-11-06 22:40:15,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2589 to 1500. [2023-11-06 22:40:15,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1500 states, 1500 states have (on average 1.358) internal successors, (2037), 1499 states have internal predecessors, (2037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1500 states to 1500 states and 2037 transitions. [2023-11-06 22:40:15,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2023-11-06 22:40:15,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:40:15,762 INFO L428 stractBuchiCegarLoop]: Abstraction has 1500 states and 2037 transitions. [2023-11-06 22:40:15,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:40:15,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1500 states and 2037 transitions. [2023-11-06 22:40:15,772 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1453 [2023-11-06 22:40:15,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:15,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:15,773 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,773 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:15,773 INFO L748 eck$LassoCheckResult]: Stem: 10428#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 10429#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 10456#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10449#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10450#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 10544#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 10397#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 10398#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10496#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10347#L117 assume !(1 == ~P_1_pc~0); 10348#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 10407#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10479#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10423#L477 assume !(0 != activate_threads_~tmp~1#1); 10424#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10533#L185 assume !(1 == ~P_2_pc~0); 10468#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 10469#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10504#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10545#L485 assume !(0 != activate_threads_~tmp___0~1#1); 10351#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10352#L267 assume !(1 == ~C_1_pc~0); 10410#L267-2 assume !(2 == ~C_1_pc~0); 10502#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 10421#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10422#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10384#L493 assume !(0 != activate_threads_~tmp___1~1#1); 10385#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10497#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 10560#L547-2 [2023-11-06 22:40:15,773 INFO L750 eck$LassoCheckResult]: Loop: 10560#L547-2 assume !false; 11780#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 11728#L396 assume !false; 11727#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 11725#L327 assume !(0 == ~P_1_st~0); 11726#L331 assume !(0 == ~P_2_st~0); 11723#L335 assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0; 11724#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11718#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11596#L361 assume !(0 != eval_~tmp___2~0#1); 11597#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10561#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10562#fire_delta_events_returnLabel#2 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 10440#L117-6 assume !(1 == ~P_1_pc~0); 10441#L117-8 is_P_1_triggered_~__retres1~0#1 := 0; 10572#L128-2 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 10573#is_P_1_triggered_returnLabel#3 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 10408#L477-6 assume !(0 != activate_threads_~tmp~1#1); 10409#L477-8 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 10459#L185-6 assume !(1 == ~P_2_pc~0); 10460#L185-8 is_P_2_triggered_~__retres1~1#1 := 0; 10565#L196-2 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 10566#is_P_2_triggered_returnLabel#3 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 10477#L485-6 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 10478#L485-8 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 10534#L267-6 assume !(1 == ~C_1_pc~0); 10535#L267-8 assume !(2 == ~C_1_pc~0); 10525#L277-5 is_C_1_triggered_~__retres1~2#1 := 0; 10526#L288-2 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 10567#is_C_1_triggered_returnLabel#3 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10568#L493-6 assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0; 10431#L493-8 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10432#reset_delta_events_returnLabel#2 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10559#L327-1 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 10418#L344-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 10546#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1; 10547#L566 assume !(0 == start_simulation_~tmp~3#1); 10470#L566-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 10471#L327-2 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 11798#L344-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 11796#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1; 11794#L521 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11792#L528 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11790#stop_simulation_returnLabel#1 start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1; 11788#L579 assume !(0 != start_simulation_~tmp___0~2#1); 10560#L547-2 [2023-11-06 22:40:15,774 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,774 INFO L85 PathProgramCache]: Analyzing trace with hash 1966545068, now seen corresponding path program 2 times [2023-11-06 22:40:15,774 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065882162] [2023-11-06 22:40:15,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:15,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:15,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:15,795 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:15,796 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:15,796 INFO L85 PathProgramCache]: Analyzing trace with hash -657003932, now seen corresponding path program 1 times [2023-11-06 22:40:15,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:15,797 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888076439] [2023-11-06 22:40:15,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:15,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:15,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:15,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:15,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:15,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888076439] [2023-11-06 22:40:15,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888076439] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:15,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:15,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:15,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530889397] [2023-11-06 22:40:15,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:15,852 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:40:15,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:15,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:15,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:15,853 INFO L87 Difference]: Start difference. First operand 1500 states and 2037 transitions. cyclomatic complexity: 541 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:15,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:15,929 INFO L93 Difference]: Finished difference Result 2325 states and 3118 transitions. [2023-11-06 22:40:15,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2325 states and 3118 transitions. [2023-11-06 22:40:15,949 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2023-11-06 22:40:15,968 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2325 states to 2325 states and 3118 transitions. [2023-11-06 22:40:15,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2325 [2023-11-06 22:40:15,971 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2325 [2023-11-06 22:40:15,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2325 states and 3118 transitions. [2023-11-06 22:40:15,976 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:15,976 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2023-11-06 22:40:15,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2325 states and 3118 transitions. [2023-11-06 22:40:16,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2325 to 2325. [2023-11-06 22:40:16,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2325 states, 2325 states have (on average 1.3410752688172043) internal successors, (3118), 2324 states have internal predecessors, (3118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:16,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2325 states to 2325 states and 3118 transitions. [2023-11-06 22:40:16,028 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2023-11-06 22:40:16,029 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:16,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 2325 states and 3118 transitions. [2023-11-06 22:40:16,035 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:40:16,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2325 states and 3118 transitions. [2023-11-06 22:40:16,049 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 2228 [2023-11-06 22:40:16,049 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:16,049 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:16,051 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,052 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,053 INFO L748 eck$LassoCheckResult]: Stem: 14261#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 14262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 14290#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14283#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14284#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 14373#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 14229#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 14230#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14328#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 14178#L117 assume !(1 == ~P_1_pc~0); 14179#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 14240#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 14310#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 14256#L477 assume !(0 != activate_threads_~tmp~1#1); 14257#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 14364#L185 assume !(1 == ~P_2_pc~0); 14300#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 14301#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 14336#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 14374#L485 assume !(0 != activate_threads_~tmp___0~1#1); 14182#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 14183#L267 assume !(1 == ~C_1_pc~0); 14243#L267-2 assume !(2 == ~C_1_pc~0); 14334#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 14254#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 14255#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 14215#L493 assume !(0 != activate_threads_~tmp___1~1#1); 14216#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14329#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 14394#L547-2 assume !false; 15621#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 15468#L396 [2023-11-06 22:40:16,054 INFO L750 eck$LassoCheckResult]: Loop: 15468#L396 assume !false; 15617#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 15615#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 15613#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 15611#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15609#L361 assume 0 != eval_~tmp___2~0#1; 15487#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 15483#L370 assume !(0 != eval_~tmp~0#1); 15480#L366 assume !(0 == ~P_2_st~0); 15475#L381 assume !(0 == ~C_1_st~0); 15468#L396 [2023-11-06 22:40:16,055 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,055 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 1 times [2023-11-06 22:40:16,056 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251512057] [2023-11-06 22:40:16,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,065 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:16,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,088 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:16,089 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,091 INFO L85 PathProgramCache]: Analyzing trace with hash -658298241, now seen corresponding path program 1 times [2023-11-06 22:40:16,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1352490237] [2023-11-06 22:40:16,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,096 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:16,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:16,108 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,108 INFO L85 PathProgramCache]: Analyzing trace with hash -1216568596, now seen corresponding path program 1 times [2023-11-06 22:40:16,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779211138] [2023-11-06 22:40:16,108 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:16,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:16,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:16,144 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [779211138] [2023-11-06 22:40:16,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [779211138] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:16,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:16,145 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:16,145 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727176685] [2023-11-06 22:40:16,145 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:16,233 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:16,233 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:16,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:16,234 INFO L87 Difference]: Start difference. First operand 2325 states and 3118 transitions. cyclomatic complexity: 800 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:16,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:16,294 INFO L93 Difference]: Finished difference Result 3877 states and 5120 transitions. [2023-11-06 22:40:16,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3877 states and 5120 transitions. [2023-11-06 22:40:16,322 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3725 [2023-11-06 22:40:16,351 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3877 states to 3877 states and 5120 transitions. [2023-11-06 22:40:16,351 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3877 [2023-11-06 22:40:16,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3877 [2023-11-06 22:40:16,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3877 states and 5120 transitions. [2023-11-06 22:40:16,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:16,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3877 states and 5120 transitions. [2023-11-06 22:40:16,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3877 states and 5120 transitions. [2023-11-06 22:40:16,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3877 to 3793. [2023-11-06 22:40:16,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3793 states, 3793 states have (on average 1.3229633535460057) internal successors, (5018), 3792 states have internal predecessors, (5018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:16,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3793 states to 3793 states and 5018 transitions. [2023-11-06 22:40:16,445 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2023-11-06 22:40:16,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:16,447 INFO L428 stractBuchiCegarLoop]: Abstraction has 3793 states and 5018 transitions. [2023-11-06 22:40:16,447 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:40:16,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3793 states and 5018 transitions. [2023-11-06 22:40:16,463 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2023-11-06 22:40:16,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:16,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:16,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,465 INFO L748 eck$LassoCheckResult]: Stem: 20471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 20472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 20500#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20494#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20495#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 20589#L304-2 assume !(1 == ~P_2_i~0);~P_2_st~0 := 2; 20436#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 20437#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20538#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 20388#L117 assume !(1 == ~P_1_pc~0); 20389#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 20448#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 20523#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 20467#L477 assume !(0 != activate_threads_~tmp~1#1); 20468#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 20579#L185 assume !(1 == ~P_2_pc~0); 20511#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 20512#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 20548#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20591#L485 assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0; 20592#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 22657#L267 assume !(1 == ~C_1_pc~0); 22656#L267-2 assume !(2 == ~C_1_pc~0); 22655#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 22654#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 20613#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20614#L493 assume !(0 != activate_threads_~tmp___1~1#1); 20542#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20543#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 20525#L547-2 assume !false; 20526#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 20546#L396 [2023-11-06 22:40:16,466 INFO L750 eck$LassoCheckResult]: Loop: 20546#L396 assume !false; 24050#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 24049#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 24047#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 24045#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 20567#L361 assume 0 != eval_~tmp___2~0#1; 20568#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 20394#L370 assume !(0 != eval_~tmp~0#1); 20396#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 21674#L385 assume !(0 != eval_~tmp___0~0#1); 21667#L381 assume !(0 == ~C_1_st~0); 20546#L396 [2023-11-06 22:40:16,467 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,467 INFO L85 PathProgramCache]: Analyzing trace with hash -131921874, now seen corresponding path program 1 times [2023-11-06 22:40:16,467 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1773208922] [2023-11-06 22:40:16,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:16,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:16,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:16,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1773208922] [2023-11-06 22:40:16,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1773208922] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:16,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:16,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:40:16,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926138751] [2023-11-06 22:40:16,490 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:16,490 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:16,490 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,491 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 1 times [2023-11-06 22:40:16,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973140774] [2023-11-06 22:40:16,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,495 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:16,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,499 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:16,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:16,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:16,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:16,598 INFO L87 Difference]: Start difference. First operand 3793 states and 5018 transitions. cyclomatic complexity: 1232 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:16,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:16,629 INFO L93 Difference]: Finished difference Result 3768 states and 4990 transitions. [2023-11-06 22:40:16,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3768 states and 4990 transitions. [2023-11-06 22:40:16,657 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2023-11-06 22:40:16,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3768 states to 3768 states and 4990 transitions. [2023-11-06 22:40:16,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3768 [2023-11-06 22:40:16,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3768 [2023-11-06 22:40:16,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3768 states and 4990 transitions. [2023-11-06 22:40:16,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:16,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2023-11-06 22:40:16,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3768 states and 4990 transitions. [2023-11-06 22:40:16,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3768 to 3768. [2023-11-06 22:40:16,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3768 states, 3768 states have (on average 1.3243099787685775) internal successors, (4990), 3767 states have internal predecessors, (4990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:16,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3768 states to 3768 states and 4990 transitions. [2023-11-06 22:40:16,792 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2023-11-06 22:40:16,792 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:16,793 INFO L428 stractBuchiCegarLoop]: Abstraction has 3768 states and 4990 transitions. [2023-11-06 22:40:16,793 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:40:16,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3768 states and 4990 transitions. [2023-11-06 22:40:16,808 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 3641 [2023-11-06 22:40:16,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:16,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:16,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:16,810 INFO L748 eck$LassoCheckResult]: Stem: 28038#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 28039#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 28066#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28059#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28060#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 28152#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 28005#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 28006#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28106#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 27955#L117 assume !(1 == ~P_1_pc~0); 27956#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 28018#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 28087#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 28034#L477 assume !(0 != activate_threads_~tmp~1#1); 28035#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 28139#L185 assume !(1 == ~P_2_pc~0); 28076#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 28077#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 28113#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 28153#L485 assume !(0 != activate_threads_~tmp___0~1#1); 27959#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 27960#L267 assume !(1 == ~C_1_pc~0); 28021#L267-2 assume !(2 == ~C_1_pc~0); 28111#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 28032#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 28033#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 27991#L493 assume !(0 != activate_threads_~tmp___1~1#1); 27992#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28107#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 28173#L547-2 assume !false; 31415#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 29643#L396 [2023-11-06 22:40:16,810 INFO L750 eck$LassoCheckResult]: Loop: 29643#L396 assume !false; 31213#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 31211#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 31209#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 31194#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31154#L361 assume 0 != eval_~tmp___2~0#1; 31151#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 27961#L370 assume !(0 != eval_~tmp~0#1); 27963#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 30862#L385 assume !(0 != eval_~tmp___0~0#1); 29647#L381 assume !(0 == ~C_1_st~0); 29643#L396 [2023-11-06 22:40:16,810 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,811 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 2 times [2023-11-06 22:40:16,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199910247] [2023-11-06 22:40:16,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,818 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:16,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,828 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:16,828 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,829 INFO L85 PathProgramCache]: Analyzing trace with hash 1067448397, now seen corresponding path program 2 times [2023-11-06 22:40:16,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083214084] [2023-11-06 22:40:16,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,833 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:16,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:16,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:16,837 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:16,838 INFO L85 PathProgramCache]: Analyzing trace with hash 940936576, now seen corresponding path program 1 times [2023-11-06 22:40:16,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:16,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007809373] [2023-11-06 22:40:16,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:16,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:16,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:16,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:16,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:16,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1007809373] [2023-11-06 22:40:16,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1007809373] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:16,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:16,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:40:16,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027066013] [2023-11-06 22:40:16,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:16,954 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:16,955 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:16,955 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:16,955 INFO L87 Difference]: Start difference. First operand 3768 states and 4990 transitions. cyclomatic complexity: 1229 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:17,018 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:17,019 INFO L93 Difference]: Finished difference Result 6578 states and 8632 transitions. [2023-11-06 22:40:17,019 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6578 states and 8632 transitions. [2023-11-06 22:40:17,055 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2023-11-06 22:40:17,100 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6578 states to 6578 states and 8632 transitions. [2023-11-06 22:40:17,100 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6578 [2023-11-06 22:40:17,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6578 [2023-11-06 22:40:17,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6578 states and 8632 transitions. [2023-11-06 22:40:17,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:40:17,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2023-11-06 22:40:17,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6578 states and 8632 transitions. [2023-11-06 22:40:17,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6578 to 6578. [2023-11-06 22:40:17,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6578 states, 6578 states have (on average 1.3122529644268774) internal successors, (8632), 6577 states have internal predecessors, (8632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:17,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6578 states to 6578 states and 8632 transitions. [2023-11-06 22:40:17,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2023-11-06 22:40:17,311 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:17,311 INFO L428 stractBuchiCegarLoop]: Abstraction has 6578 states and 8632 transitions. [2023-11-06 22:40:17,312 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:40:17,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6578 states and 8632 transitions. [2023-11-06 22:40:17,339 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 6355 [2023-11-06 22:40:17,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:17,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:17,340 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:17,340 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:17,340 INFO L748 eck$LassoCheckResult]: Stem: 38392#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0; 38393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1; 38423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38416#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38417#L304 assume 1 == ~P_1_i~0;~P_1_st~0 := 0; 38513#L304-2 assume 1 == ~P_2_i~0;~P_2_st~0 := 0; 38361#L309-1 assume 1 == ~C_1_i~0;~C_1_st~0 := 0; 38362#L314-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38463#fire_delta_events_returnLabel#1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1; 38310#L117 assume !(1 == ~P_1_pc~0); 38311#L117-2 is_P_1_triggered_~__retres1~0#1 := 0; 38373#L128 is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1; 38445#is_P_1_triggered_returnLabel#1 activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1; 38389#L477 assume !(0 != activate_threads_~tmp~1#1); 38390#L477-2 assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1; 38500#L185 assume !(1 == ~P_2_pc~0); 38434#L185-2 is_P_2_triggered_~__retres1~1#1 := 0; 38435#L196 is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1; 38471#is_P_2_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38514#L485 assume !(0 != activate_threads_~tmp___0~1#1); 38315#L485-2 assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1; 38316#L267 assume !(1 == ~C_1_pc~0); 38376#L267-2 assume !(2 == ~C_1_pc~0); 38468#L277-1 is_C_1_triggered_~__retres1~2#1 := 0; 38387#L288 is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1; 38388#is_C_1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38347#L493 assume !(0 != activate_threads_~tmp___1~1#1); 38348#L493-2 havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38464#reset_delta_events_returnLabel#1 assume { :end_inline_reset_delta_events } true; 38533#L547-2 assume !false; 39314#L548 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1; 39315#L396 [2023-11-06 22:40:17,341 INFO L750 eck$LassoCheckResult]: Loop: 39315#L396 assume !false; 40066#L357 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1; 40064#L327 assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1; 40065#L344 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1; 40148#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 40147#L361 assume 0 != eval_~tmp___2~0#1; 40057#L361-1 assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 40058#L370 assume !(0 != eval_~tmp~0#1); 40069#L366 assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 39289#L385 assume !(0 != eval_~tmp___0~0#1); 40068#L381 assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 39252#L400 assume !(0 != eval_~tmp___1~0#1); 39315#L396 [2023-11-06 22:40:17,341 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:17,341 INFO L85 PathProgramCache]: Analyzing trace with hash 64203950, now seen corresponding path program 3 times [2023-11-06 22:40:17,341 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:17,341 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111539352] [2023-11-06 22:40:17,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:17,342 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:17,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,349 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:17,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,358 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:17,359 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:17,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1268840153, now seen corresponding path program 1 times [2023-11-06 22:40:17,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:17,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136358916] [2023-11-06 22:40:17,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:17,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:17,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,363 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:17,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:17,368 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:17,368 INFO L85 PathProgramCache]: Analyzing trace with hash -895739308, now seen corresponding path program 1 times [2023-11-06 22:40:17,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:17,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1403959886] [2023-11-06 22:40:17,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:17,369 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:17,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:17,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:17,387 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:18,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:18,519 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:18,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:18,675 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:40:18 BoogieIcfgContainer [2023-11-06 22:40:18,678 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:40:18,679 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:40:18,679 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:40:18,679 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:40:18,680 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:12" (3/4) ... [2023-11-06 22:40:18,681 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:40:18,752 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:40:18,752 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:40:18,753 INFO L158 Benchmark]: Toolchain (without parser) took 7088.81ms. Allocated memory was 123.7MB in the beginning and 222.3MB in the end (delta: 98.6MB). Free memory was 78.0MB in the beginning and 84.2MB in the end (delta: -6.2MB). Peak memory consumption was 94.5MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,753 INFO L158 Benchmark]: CDTParser took 0.67ms. Allocated memory is still 123.7MB. Free memory is still 98.7MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:40:18,753 INFO L158 Benchmark]: CACSL2BoogieTranslator took 435.32ms. Allocated memory is still 123.7MB. Free memory was 78.0MB in the beginning and 63.8MB in the end (delta: 14.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,754 INFO L158 Benchmark]: Boogie Procedure Inliner took 60.12ms. Allocated memory is still 123.7MB. Free memory was 63.8MB in the beginning and 60.9MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,754 INFO L158 Benchmark]: Boogie Preprocessor took 45.20ms. Allocated memory is still 123.7MB. Free memory was 60.9MB in the beginning and 58.5MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,755 INFO L158 Benchmark]: RCFGBuilder took 777.29ms. Allocated memory was 123.7MB in the beginning and 184.5MB in the end (delta: 60.8MB). Free memory was 58.5MB in the beginning and 132.5MB in the end (delta: -74.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,755 INFO L158 Benchmark]: BuchiAutomizer took 5689.36ms. Allocated memory was 184.5MB in the beginning and 222.3MB in the end (delta: 37.7MB). Free memory was 132.5MB in the beginning and 88.4MB in the end (delta: 44.1MB). Peak memory consumption was 81.9MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,755 INFO L158 Benchmark]: Witness Printer took 72.97ms. Allocated memory is still 222.3MB. Free memory was 88.4MB in the beginning and 84.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:40:18,758 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.67ms. Allocated memory is still 123.7MB. Free memory is still 98.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 435.32ms. Allocated memory is still 123.7MB. Free memory was 78.0MB in the beginning and 63.8MB in the end (delta: 14.2MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 60.12ms. Allocated memory is still 123.7MB. Free memory was 63.8MB in the beginning and 60.9MB in the end (delta: 2.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 45.20ms. Allocated memory is still 123.7MB. Free memory was 60.9MB in the beginning and 58.5MB in the end (delta: 2.4MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 777.29ms. Allocated memory was 123.7MB in the beginning and 184.5MB in the end (delta: 60.8MB). Free memory was 58.5MB in the beginning and 132.5MB in the end (delta: -74.0MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 5689.36ms. Allocated memory was 184.5MB in the beginning and 222.3MB in the end (delta: 37.7MB). Free memory was 132.5MB in the beginning and 88.4MB in the end (delta: 44.1MB). Peak memory consumption was 81.9MB. Max. memory is 16.1GB. * Witness Printer took 72.97ms. Allocated memory is still 222.3MB. Free memory was 88.4MB in the beginning and 84.2MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 11 terminating modules (11 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.11 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 6578 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.5s and 12 iterations. TraceHistogramMax:1. Analysis of lassos took 3.1s. Construction of modules took 0.3s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 0. Minimization of det autom 11. Minimization of nondet autom 0. Automata minimization 0.6s AutomataMinimizationTime, 11 MinimizatonAttempts, 1511 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 3333 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 3333 mSDsluCounter, 6089 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3259 mSDsCounter, 115 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 306 IncrementalHoareTripleChecker+Invalid, 421 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 115 mSolverCounterUnsat, 2830 mSDtfsCounter, 306 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc2 concLT0 SILN1 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___0=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0, tmp=0, tmp___0=0, tmp___1=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, kernel_st=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:40:18,824 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_b8457f13-81cb-44b2-b6b8-911032b88ec0/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)