./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:50:18,848 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:50:18,997 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:50:19,007 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:50:19,007 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:50:19,048 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:50:19,049 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:50:19,050 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:50:19,051 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:50:19,056 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:50:19,058 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:50:19,058 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:50:19,059 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:50:19,060 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:50:19,061 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:50:19,061 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:50:19,062 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:50:19,063 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:50:19,063 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:50:19,064 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:50:19,064 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:50:19,065 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:50:19,065 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:50:19,066 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:50:19,066 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:50:19,066 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:50:19,067 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:50:19,067 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:50:19,068 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:50:19,068 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:50:19,069 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:50:19,070 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:50:19,070 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:50:19,070 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:50:19,071 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:50:19,071 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:50:19,072 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2023-11-06 22:50:19,380 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:50:19,422 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:50:19,425 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:50:19,426 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:50:19,427 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:50:19,428 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-06 22:50:22,471 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:50:22,698 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:50:22,698 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2023-11-06 22:50:22,706 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/data/3cdabb402/2336c84d30fa4d90ada311330566ad93/FLAG615f8f46f [2023-11-06 22:50:22,721 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/data/3cdabb402/2336c84d30fa4d90ada311330566ad93 [2023-11-06 22:50:22,724 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:50:22,725 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:50:22,727 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:50:22,727 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:50:22,733 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:50:22,734 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:22,735 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4b1e0e03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22, skipping insertion in model container [2023-11-06 22:50:22,736 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:22,758 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:50:22,919 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:50:22,941 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:50:22,959 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:50:22,976 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:50:22,977 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22 WrapperNode [2023-11-06 22:50:22,977 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:50:22,978 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:50:22,978 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:50:22,978 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:50:22,987 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:22,994 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,020 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 80 [2023-11-06 22:50:23,021 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:50:23,022 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:50:23,022 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:50:23,022 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:50:23,035 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,035 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,037 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,038 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,045 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,049 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,051 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,052 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,055 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:50:23,056 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:50:23,056 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:50:23,056 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:50:23,057 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (1/1) ... [2023-11-06 22:50:23,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:23,083 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:23,098 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:23,123 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:50:23,146 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:50:23,146 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:50:23,147 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2023-11-06 22:50:23,147 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2023-11-06 22:50:23,148 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:50:23,149 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:50:23,149 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2023-11-06 22:50:23,150 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2023-11-06 22:50:23,246 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:50:23,249 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:50:23,563 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:50:23,569 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:50:23,570 INFO L302 CfgBuilder]: Removed 3 assume(true) statements. [2023-11-06 22:50:23,572 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:50:23 BoogieIcfgContainer [2023-11-06 22:50:23,572 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:50:23,573 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:50:23,573 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:50:23,577 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:50:23,578 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:50:23,578 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:50:22" (1/3) ... [2023-11-06 22:50:23,579 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1dde1f74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:50:23, skipping insertion in model container [2023-11-06 22:50:23,579 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:50:23,579 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:50:22" (2/3) ... [2023-11-06 22:50:23,580 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1dde1f74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:50:23, skipping insertion in model container [2023-11-06 22:50:23,580 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:50:23,580 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:50:23" (3/3) ... [2023-11-06 22:50:23,581 INFO L332 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2023-11-06 22:50:23,631 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:50:23,631 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:50:23,632 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:50:23,632 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:50:23,632 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:50:23,632 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:50:23,632 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:50:23,632 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:50:23,636 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:23,652 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-06 22:50:23,653 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:23,653 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:23,658 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-06 22:50:23,658 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:50:23,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:50:23,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:23,662 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 20 [2023-11-06 22:50:23,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:23,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:23,662 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2023-11-06 22:50:23,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:50:23,670 INFO L748 eck$LassoCheckResult]: Stem: 27#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28#L27-3true [2023-11-06 22:50:23,671 INFO L750 eck$LassoCheckResult]: Loop: 28#L27-3true assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5#L27-2true main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28#L27-3true [2023-11-06 22:50:23,677 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:23,677 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2023-11-06 22:50:23,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:23,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269971246] [2023-11-06 22:50:23,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:23,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:23,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,777 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:23,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,818 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:23,821 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:23,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2023-11-06 22:50:23,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:23,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81311984] [2023-11-06 22:50:23,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:23,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:23,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,834 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:23,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:23,845 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:23,845 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2023-11-06 22:50:23,845 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:23,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218824734] [2023-11-06 22:50:23,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:23,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:23,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,871 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:23,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:23,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:24,301 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:50:24,302 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:50:24,302 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:50:24,302 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:50:24,302 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-06 22:50:24,303 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:24,303 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:50:24,303 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:50:24,303 INFO L133 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2023-11-06 22:50:24,303 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:50:24,304 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:50:24,323 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,342 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,349 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,356 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,625 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:50:24,903 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:50:24,908 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-06 22:50:24,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:24,910 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:24,913 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:24,921 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:24,935 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:24,935 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:24,936 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:24,936 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:24,936 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:24,938 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:24,938 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:24,940 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-06 22:50:24,957 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:24,965 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-06 22:50:24,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:24,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:24,968 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:24,973 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:24,986 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:24,987 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:24,987 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:24,987 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:24,987 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:24,989 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:24,989 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:24,991 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-06 22:50:24,992 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:24,995 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:24,995 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,000 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,001 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,009 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-06 22:50:25,010 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,023 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,023 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:25,023 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,023 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,023 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,025 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:25,025 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:25,035 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,047 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,048 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,048 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,050 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,055 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-06 22:50:25,057 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,069 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,069 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:25,070 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,070 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,070 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,072 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:25,073 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:25,086 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,100 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,100 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,100 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,102 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,147 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,153 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-06 22:50:25,193 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,194 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:25,194 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,194 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,194 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,195 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:25,195 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:25,205 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,221 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,221 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,222 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,223 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,239 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-06 22:50:25,240 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,250 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,250 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:25,250 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,251 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,251 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,251 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:25,252 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:25,263 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,268 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-06 22:50:25,269 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,269 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,270 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,271 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-06 22:50:25,273 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,285 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,285 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:50:25,285 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,285 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,286 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,286 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:50:25,286 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:50:25,308 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,316 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,317 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,317 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,318 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,329 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,342 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,342 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,342 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,342 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-06 22:50:25,347 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:50:25,347 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:50:25,360 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-06 22:50:25,368 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,369 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,370 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,382 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:50:25,388 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-06 22:50:25,394 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:50:25,395 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:50:25,395 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:50:25,395 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:50:25,410 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2023-11-06 22:50:25,410 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2023-11-06 22:50:25,432 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-06 22:50:25,495 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2023-11-06 22:50:25,495 INFO L444 ModelExtractionUtils]: 3 out of 16 variables were initially zero. Simplification set additionally 9 variables to zero. [2023-11-06 22:50:25,497 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:50:25,497 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:25,520 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:50:25,521 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-06 22:50:25,521 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-06 22:50:25,533 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2023-11-06 22:50:25,533 INFO L513 LassoAnalysis]: Proved termination. [2023-11-06 22:50:25,534 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1, ULTIMATE.start_main_~#array~0#1.offset) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 - 1*ULTIMATE.start_main_~#array~0#1.offset Supporting invariants [] [2023-11-06 22:50:25,539 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:25,558 INFO L156 tatePredicateManager]: 5 out of 5 supporting invariants were superfluous and have been removed [2023-11-06 22:50:25,565 WARN L1553 BoogieBacktranslator]: Unfinished Backtranslation: ArrayAccessExpression #length[~#array~0!base] could not be translated [2023-11-06 22:50:25,583 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:25,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:25,598 INFO L262 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:50:25,599 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:25,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:25,614 INFO L262 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-06 22:50:25,615 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:25,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:25,666 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-06 22:50:25,668 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:25,723 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 28 states, 27 states have (on average 1.4444444444444444) internal successors, (39), 27 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 55 states and 79 transitions. Complement of second has 8 states. [2023-11-06 22:50:25,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2023-11-06 22:50:25,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:25,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 39 transitions. [2023-11-06 22:50:25,732 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 2 letters. [2023-11-06 22:50:25,732 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:50:25,733 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 4 letters. Loop has 2 letters. [2023-11-06 22:50:25,733 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:50:25,733 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 39 transitions. Stem has 2 letters. Loop has 4 letters. [2023-11-06 22:50:25,733 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:50:25,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 79 transitions. [2023-11-06 22:50:25,738 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-06 22:50:25,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 25 states and 35 transitions. [2023-11-06 22:50:25,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2023-11-06 22:50:25,744 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2023-11-06 22:50:25,744 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2023-11-06 22:50:25,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:25,745 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-06 22:50:25,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2023-11-06 22:50:25,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2023-11-06 22:50:25,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.4) internal successors, (35), 24 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:25,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2023-11-06 22:50:25,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-06 22:50:25,773 INFO L428 stractBuchiCegarLoop]: Abstraction has 25 states and 35 transitions. [2023-11-06 22:50:25,773 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:50:25,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 35 transitions. [2023-11-06 22:50:25,775 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2023-11-06 22:50:25,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:25,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:25,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2023-11-06 22:50:25,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:25,776 INFO L748 eck$LassoCheckResult]: Stem: 165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 153#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 154#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 157#L27-4 main_~i~0#1 := 0; 158#L32-3 [2023-11-06 22:50:25,776 INFO L750 eck$LassoCheckResult]: Loop: 158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 152#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 158#L32-3 [2023-11-06 22:50:25,776 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:25,776 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2023-11-06 22:50:25,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:25,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [231863640] [2023-11-06 22:50:25,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:25,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:25,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:25,790 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:25,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:25,808 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:25,811 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:25,812 INFO L85 PathProgramCache]: Analyzing trace with hash 54361, now seen corresponding path program 1 times [2023-11-06 22:50:25,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:25,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332905595] [2023-11-06 22:50:25,817 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:25,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:25,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:25,828 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:25,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:25,850 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:25,851 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:25,851 INFO L85 PathProgramCache]: Analyzing trace with hash 1807958031, now seen corresponding path program 1 times [2023-11-06 22:50:25,851 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:25,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904355453] [2023-11-06 22:50:25,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:25,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:25,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:26,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:26,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:26,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1904355453] [2023-11-06 22:50:26,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1904355453] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:50:26,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:50:26,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:50:26,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306482991] [2023-11-06 22:50:26,026 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:50:26,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:26,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:50:26,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:50:26,100 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. cyclomatic complexity: 13 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:26,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:26,183 INFO L93 Difference]: Finished difference Result 44 states and 51 transitions. [2023-11-06 22:50:26,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 51 transitions. [2023-11-06 22:50:26,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:26,193 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 32 states and 38 transitions. [2023-11-06 22:50:26,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2023-11-06 22:50:26,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2023-11-06 22:50:26,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 38 transitions. [2023-11-06 22:50:26,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:26,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 38 transitions. [2023-11-06 22:50:26,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 38 transitions. [2023-11-06 22:50:26,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 20. [2023-11-06 22:50:26,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.2) internal successors, (24), 19 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:26,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2023-11-06 22:50:26,200 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-06 22:50:26,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:50:26,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 20 states and 24 transitions. [2023-11-06 22:50:26,209 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:50:26,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 24 transitions. [2023-11-06 22:50:26,210 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:26,214 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:26,214 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:26,214 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:50:26,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:26,215 INFO L748 eck$LassoCheckResult]: Stem: 239#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 227#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 228#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 232#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 233#L27-4 main_~i~0#1 := 0; 234#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 238#L34 [2023-11-06 22:50:26,215 INFO L750 eck$LassoCheckResult]: Loop: 238#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 226#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 235#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 238#L34 [2023-11-06 22:50:26,215 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:26,216 INFO L85 PathProgramCache]: Analyzing trace with hash 1809669547, now seen corresponding path program 1 times [2023-11-06 22:50:26,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:26,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92706599] [2023-11-06 22:50:26,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,216 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:26,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,242 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:26,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,253 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:26,254 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:26,254 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 2 times [2023-11-06 22:50:26,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:26,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [937776382] [2023-11-06 22:50:26,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:26,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,261 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:26,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,267 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:26,267 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:26,268 INFO L85 PathProgramCache]: Analyzing trace with hash 1436021995, now seen corresponding path program 1 times [2023-11-06 22:50:26,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:26,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691777547] [2023-11-06 22:50:26,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:26,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:26,423 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:26,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:26,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691777547] [2023-11-06 22:50:26,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691777547] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:26,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [140667446] [2023-11-06 22:50:26,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,424 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:26,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:26,425 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:26,452 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2023-11-06 22:50:26,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:26,495 INFO L262 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-06 22:50:26,496 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:26,582 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:26,582 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:26,633 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:26,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [140667446] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:26,635 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:26,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2023-11-06 22:50:26,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301111880] [2023-11-06 22:50:26,635 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:26,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:26,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2023-11-06 22:50:26,700 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2023-11-06 22:50:26,700 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. cyclomatic complexity: 7 Second operand has 11 states, 10 states have (on average 2.2) internal successors, (22), 11 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:26,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:26,874 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2023-11-06 22:50:26,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 74 transitions. [2023-11-06 22:50:26,884 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:26,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 46 states and 54 transitions. [2023-11-06 22:50:26,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2023-11-06 22:50:26,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2023-11-06 22:50:26,887 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 54 transitions. [2023-11-06 22:50:26,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:26,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 46 states and 54 transitions. [2023-11-06 22:50:26,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 54 transitions. [2023-11-06 22:50:26,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 28. [2023-11-06 22:50:26,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1785714285714286) internal successors, (33), 27 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:26,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2023-11-06 22:50:26,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-06 22:50:26,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2023-11-06 22:50:26,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 28 states and 33 transitions. [2023-11-06 22:50:26,901 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:50:26,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 33 transitions. [2023-11-06 22:50:26,903 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:26,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:26,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:26,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 1, 1, 1, 1, 1, 1] [2023-11-06 22:50:26,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:26,905 INFO L748 eck$LassoCheckResult]: Stem: 399#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 384#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 385#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 397#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 398#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 390#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 391#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 388#L27-4 main_~i~0#1 := 0; 389#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 403#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 392#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 393#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 396#L34 [2023-11-06 22:50:26,905 INFO L750 eck$LassoCheckResult]: Loop: 396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 383#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 401#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 396#L34 [2023-11-06 22:50:26,906 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:26,906 INFO L85 PathProgramCache]: Analyzing trace with hash 780824429, now seen corresponding path program 2 times [2023-11-06 22:50:26,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:26,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2096038919] [2023-11-06 22:50:26,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:26,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,946 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:26,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:26,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:26,986 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:26,986 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 3 times [2023-11-06 22:50:26,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:26,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720949367] [2023-11-06 22:50:26,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:26,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:27,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,022 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:27,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,032 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-06 22:50:27,041 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:27,041 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:27,041 INFO L85 PathProgramCache]: Analyzing trace with hash -2264087, now seen corresponding path program 3 times [2023-11-06 22:50:27,042 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:27,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [547181009] [2023-11-06 22:50:27,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:27,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:27,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:27,241 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:27,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:27,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [547181009] [2023-11-06 22:50:27,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [547181009] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:27,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1399782680] [2023-11-06 22:50:27,243 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:50:27,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:27,244 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:27,245 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:27,253 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2023-11-06 22:50:27,312 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2023-11-06 22:50:27,313 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:27,314 INFO L262 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjunts are in the unsatisfiable core [2023-11-06 22:50:27,316 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:27,426 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:27,426 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:27,507 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 5 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:27,507 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1399782680] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:27,507 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:27,508 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2023-11-06 22:50:27,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589742219] [2023-11-06 22:50:27,508 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:27,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:27,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2023-11-06 22:50:27,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2023-11-06 22:50:27,569 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. cyclomatic complexity: 8 Second operand has 14 states, 13 states have (on average 2.3076923076923075) internal successors, (30), 14 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:27,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:27,769 INFO L93 Difference]: Finished difference Result 89 states and 104 transitions. [2023-11-06 22:50:27,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 104 transitions. [2023-11-06 22:50:27,771 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:27,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 60 states and 70 transitions. [2023-11-06 22:50:27,772 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2023-11-06 22:50:27,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2023-11-06 22:50:27,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 70 transitions. [2023-11-06 22:50:27,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:27,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 70 transitions. [2023-11-06 22:50:27,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 70 transitions. [2023-11-06 22:50:27,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 36. [2023-11-06 22:50:27,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.1666666666666667) internal successors, (42), 35 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:27,776 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 42 transitions. [2023-11-06 22:50:27,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-06 22:50:27,777 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2023-11-06 22:50:27,778 INFO L428 stractBuchiCegarLoop]: Abstraction has 36 states and 42 transitions. [2023-11-06 22:50:27,778 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:50:27,778 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 42 transitions. [2023-11-06 22:50:27,779 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:27,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:27,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:27,780 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 2, 2, 1, 1, 1, 1] [2023-11-06 22:50:27,780 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:27,780 INFO L748 eck$LassoCheckResult]: Stem: 626#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 611#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 624#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 625#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 614#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 615#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 630#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 629#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 616#L27-4 main_~i~0#1 := 0; 617#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 638#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 618#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 619#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 623#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 632#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 637#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 622#L34 [2023-11-06 22:50:27,781 INFO L750 eck$LassoCheckResult]: Loop: 622#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 609#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 622#L34 [2023-11-06 22:50:27,781 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:27,781 INFO L85 PathProgramCache]: Analyzing trace with hash -79873369, now seen corresponding path program 4 times [2023-11-06 22:50:27,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:27,782 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317905827] [2023-11-06 22:50:27,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:27,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:27,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,803 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:27,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:27,827 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:27,827 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 4 times [2023-11-06 22:50:27,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:27,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668059561] [2023-11-06 22:50:27,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:27,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:27,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:27,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:27,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:27,836 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:27,836 INFO L85 PathProgramCache]: Analyzing trace with hash -95607185, now seen corresponding path program 5 times [2023-11-06 22:50:27,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:27,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582699279] [2023-11-06 22:50:27,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:27,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:27,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:27,986 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 5 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:27,987 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:27,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582699279] [2023-11-06 22:50:27,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582699279] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:27,987 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [966305756] [2023-11-06 22:50:27,988 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:50:27,988 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:27,988 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:27,992 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:28,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2023-11-06 22:50:28,095 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2023-11-06 22:50:28,095 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:28,096 INFO L262 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjunts are in the unsatisfiable core [2023-11-06 22:50:28,098 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:28,232 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:28,232 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:28,328 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 12 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:28,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [966305756] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:28,328 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:28,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2023-11-06 22:50:28,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [283641708] [2023-11-06 22:50:28,329 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:28,388 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:28,389 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2023-11-06 22:50:28,389 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=197, Unknown=0, NotChecked=0, Total=272 [2023-11-06 22:50:28,390 INFO L87 Difference]: Start difference. First operand 36 states and 42 transitions. cyclomatic complexity: 9 Second operand has 17 states, 16 states have (on average 2.375) internal successors, (38), 17 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:28,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:28,637 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2023-11-06 22:50:28,637 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 134 transitions. [2023-11-06 22:50:28,638 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:28,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 74 states and 86 transitions. [2023-11-06 22:50:28,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2023-11-06 22:50:28,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2023-11-06 22:50:28,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 86 transitions. [2023-11-06 22:50:28,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:28,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2023-11-06 22:50:28,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 86 transitions. [2023-11-06 22:50:28,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 44. [2023-11-06 22:50:28,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.1590909090909092) internal successors, (51), 43 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:28,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 51 transitions. [2023-11-06 22:50:28,644 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-06 22:50:28,648 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-06 22:50:28,651 INFO L428 stractBuchiCegarLoop]: Abstraction has 44 states and 51 transitions. [2023-11-06 22:50:28,651 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:50:28,651 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 51 transitions. [2023-11-06 22:50:28,653 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:28,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:28,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:28,655 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 3, 3, 1, 1, 1, 1] [2023-11-06 22:50:28,655 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:28,656 INFO L748 eck$LassoCheckResult]: Stem: 919#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 906#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 920#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 921#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 909#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 930#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 929#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 926#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 925#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 911#L27-4 main_~i~0#1 := 0; 912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 904#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 940#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 938#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 937#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 934#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 932#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 931#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 924#L34 [2023-11-06 22:50:28,656 INFO L750 eck$LassoCheckResult]: Loop: 924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 923#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 924#L34 [2023-11-06 22:50:28,656 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:28,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1712449137, now seen corresponding path program 6 times [2023-11-06 22:50:28,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:28,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1586958145] [2023-11-06 22:50:28,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:28,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:28,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:28,691 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:28,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:28,719 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:28,719 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:28,720 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 5 times [2023-11-06 22:50:28,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:28,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987278496] [2023-11-06 22:50:28,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:28,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:28,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:28,724 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:28,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:28,728 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:28,728 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:28,729 INFO L85 PathProgramCache]: Analyzing trace with hash -49254811, now seen corresponding path program 7 times [2023-11-06 22:50:28,729 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:28,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [574842375] [2023-11-06 22:50:28,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:28,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:28,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:28,914 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 12 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:28,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:28,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [574842375] [2023-11-06 22:50:28,915 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [574842375] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:28,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [750035263] [2023-11-06 22:50:28,915 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:50:28,915 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:28,916 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:28,919 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:28,944 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-06 22:50:28,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:29,001 INFO L262 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-06 22:50:29,003 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:29,174 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:29,175 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:29,318 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 22 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:29,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [750035263] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:29,318 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:29,319 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 19 [2023-11-06 22:50:29,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065009838] [2023-11-06 22:50:29,320 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:29,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:29,381 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2023-11-06 22:50:29,382 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=279, Unknown=0, NotChecked=0, Total=380 [2023-11-06 22:50:29,382 INFO L87 Difference]: Start difference. First operand 44 states and 51 transitions. cyclomatic complexity: 10 Second operand has 20 states, 19 states have (on average 2.4210526315789473) internal successors, (46), 20 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:29,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:29,665 INFO L93 Difference]: Finished difference Result 141 states and 164 transitions. [2023-11-06 22:50:29,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 141 states and 164 transitions. [2023-11-06 22:50:29,667 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:29,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 141 states to 88 states and 102 transitions. [2023-11-06 22:50:29,669 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2023-11-06 22:50:29,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2023-11-06 22:50:29,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 102 transitions. [2023-11-06 22:50:29,670 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:29,670 INFO L218 hiAutomatonCegarLoop]: Abstraction has 88 states and 102 transitions. [2023-11-06 22:50:29,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 102 transitions. [2023-11-06 22:50:29,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 52. [2023-11-06 22:50:29,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1538461538461537) internal successors, (60), 51 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:29,676 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 60 transitions. [2023-11-06 22:50:29,676 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-06 22:50:29,677 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2023-11-06 22:50:29,678 INFO L428 stractBuchiCegarLoop]: Abstraction has 52 states and 60 transitions. [2023-11-06 22:50:29,678 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:50:29,678 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 60 transitions. [2023-11-06 22:50:29,679 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:29,679 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:29,680 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:29,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 4, 4, 1, 1, 1, 1] [2023-11-06 22:50:29,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:29,681 INFO L748 eck$LassoCheckResult]: Stem: 1284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1270#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1285#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1286#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1273#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1274#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1297#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1296#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1295#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1294#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1291#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1290#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1275#L27-4 main_~i~0#1 := 0; 1276#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1281#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1268#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1278#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1283#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1311#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1310#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1307#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1305#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1304#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1301#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1299#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1298#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 [2023-11-06 22:50:29,682 INFO L750 eck$LassoCheckResult]: Loop: 1289#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1292#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1288#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1289#L34 [2023-11-06 22:50:29,682 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:29,682 INFO L85 PathProgramCache]: Analyzing trace with hash -240296029, now seen corresponding path program 8 times [2023-11-06 22:50:29,683 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:29,683 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264864613] [2023-11-06 22:50:29,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:29,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:29,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:29,715 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:29,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:29,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:29,769 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:29,770 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 6 times [2023-11-06 22:50:29,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:29,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035553089] [2023-11-06 22:50:29,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:29,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:29,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:29,781 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:29,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:29,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:29,787 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:29,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1051529203, now seen corresponding path program 9 times [2023-11-06 22:50:29,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:29,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [764956558] [2023-11-06 22:50:29,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:29,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:29,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:30,080 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 22 proven. 38 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:30,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:30,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [764956558] [2023-11-06 22:50:30,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [764956558] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:30,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1701266969] [2023-11-06 22:50:30,081 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:50:30,082 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:30,082 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:30,088 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:30,123 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-06 22:50:30,207 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2023-11-06 22:50:30,207 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:30,209 INFO L262 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjunts are in the unsatisfiable core [2023-11-06 22:50:30,211 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:30,430 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:30,431 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:30,584 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 35 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:30,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1701266969] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:30,585 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:30,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2023-11-06 22:50:30,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3557981] [2023-11-06 22:50:30,585 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:30,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:30,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2023-11-06 22:50:30,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=131, Invalid=375, Unknown=0, NotChecked=0, Total=506 [2023-11-06 22:50:30,643 INFO L87 Difference]: Start difference. First operand 52 states and 60 transitions. cyclomatic complexity: 11 Second operand has 23 states, 22 states have (on average 2.4545454545454546) internal successors, (54), 23 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:30,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:30,944 INFO L93 Difference]: Finished difference Result 167 states and 194 transitions. [2023-11-06 22:50:30,944 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 167 states and 194 transitions. [2023-11-06 22:50:30,946 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:30,947 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 167 states to 102 states and 118 transitions. [2023-11-06 22:50:30,947 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2023-11-06 22:50:30,947 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2023-11-06 22:50:30,948 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 118 transitions. [2023-11-06 22:50:30,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:30,949 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102 states and 118 transitions. [2023-11-06 22:50:30,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 118 transitions. [2023-11-06 22:50:30,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 60. [2023-11-06 22:50:30,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.15) internal successors, (69), 59 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:30,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 69 transitions. [2023-11-06 22:50:30,954 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-06 22:50:30,954 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2023-11-06 22:50:30,955 INFO L428 stractBuchiCegarLoop]: Abstraction has 60 states and 69 transitions. [2023-11-06 22:50:30,955 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:50:30,955 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 69 transitions. [2023-11-06 22:50:30,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:30,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:30,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:30,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 5, 5, 1, 1, 1, 1] [2023-11-06 22:50:30,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:30,958 INFO L748 eck$LassoCheckResult]: Stem: 1718#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 1702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 1703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1719#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1720#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1729#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1728#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 1725#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 1724#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 1706#L27-4 main_~i~0#1 := 0; 1707#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1715#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1701#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1712#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1747#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1723#L34 [2023-11-06 22:50:30,958 INFO L750 eck$LassoCheckResult]: Loop: 1723#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 1726#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 1722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 1723#L34 [2023-11-06 22:50:30,958 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:30,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1967863157, now seen corresponding path program 10 times [2023-11-06 22:50:30,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:30,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679896753] [2023-11-06 22:50:30,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:30,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:30,993 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:30,993 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:31,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:31,027 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:31,028 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:31,028 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 7 times [2023-11-06 22:50:31,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:31,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623107689] [2023-11-06 22:50:31,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:31,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:31,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:31,032 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:31,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:31,036 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:31,036 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:31,036 INFO L85 PathProgramCache]: Analyzing trace with hash -1692233503, now seen corresponding path program 11 times [2023-11-06 22:50:31,037 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:31,037 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2044352651] [2023-11-06 22:50:31,037 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:31,037 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:31,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:31,399 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 35 proven. 52 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:31,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:31,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2044352651] [2023-11-06 22:50:31,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2044352651] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:31,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [761176407] [2023-11-06 22:50:31,400 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:50:31,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:31,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:31,404 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:31,440 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2023-11-06 22:50:31,558 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2023-11-06 22:50:31,558 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:31,560 INFO L262 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjunts are in the unsatisfiable core [2023-11-06 22:50:31,562 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:31,792 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:31,792 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:31,964 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 51 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:31,964 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [761176407] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:31,964 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:31,964 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2023-11-06 22:50:31,965 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1932633923] [2023-11-06 22:50:31,965 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:32,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:32,016 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2023-11-06 22:50:32,017 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=485, Unknown=0, NotChecked=0, Total=650 [2023-11-06 22:50:32,017 INFO L87 Difference]: Start difference. First operand 60 states and 69 transitions. cyclomatic complexity: 12 Second operand has 26 states, 25 states have (on average 2.48) internal successors, (62), 26 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:32,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:32,436 INFO L93 Difference]: Finished difference Result 193 states and 224 transitions. [2023-11-06 22:50:32,436 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 224 transitions. [2023-11-06 22:50:32,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:32,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 116 states and 134 transitions. [2023-11-06 22:50:32,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2023-11-06 22:50:32,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2023-11-06 22:50:32,442 INFO L73 IsDeterministic]: Start isDeterministic. Operand 116 states and 134 transitions. [2023-11-06 22:50:32,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:32,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 116 states and 134 transitions. [2023-11-06 22:50:32,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 116 states and 134 transitions. [2023-11-06 22:50:32,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 116 to 68. [2023-11-06 22:50:32,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1470588235294117) internal successors, (78), 67 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:32,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 78 transitions. [2023-11-06 22:50:32,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-06 22:50:32,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2023-11-06 22:50:32,461 INFO L428 stractBuchiCegarLoop]: Abstraction has 68 states and 78 transitions. [2023-11-06 22:50:32,462 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:50:32,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 78 transitions. [2023-11-06 22:50:32,462 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:32,463 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:32,463 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:32,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 7, 6, 6, 1, 1, 1, 1] [2023-11-06 22:50:32,464 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:32,465 INFO L748 eck$LassoCheckResult]: Stem: 2220#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2221#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2222#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2208#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2237#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2236#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2235#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2234#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2233#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2232#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2231#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2230#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2227#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2226#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2210#L27-4 main_~i~0#1 := 0; 2211#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2217#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2203#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2214#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2219#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2262#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2261#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2259#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2256#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2255#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2253#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2250#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2249#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2247#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2245#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2244#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2241#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2239#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2238#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2225#L34 [2023-11-06 22:50:32,465 INFO L750 eck$LassoCheckResult]: Loop: 2225#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2228#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2224#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2225#L34 [2023-11-06 22:50:32,465 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:32,465 INFO L85 PathProgramCache]: Analyzing trace with hash -664171361, now seen corresponding path program 12 times [2023-11-06 22:50:32,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:32,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [99111114] [2023-11-06 22:50:32,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:32,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:32,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:32,498 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:32,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:32,539 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:32,540 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:32,540 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 8 times [2023-11-06 22:50:32,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:32,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430753757] [2023-11-06 22:50:32,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:32,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:32,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:32,545 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:32,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:32,548 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:32,549 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:32,549 INFO L85 PathProgramCache]: Analyzing trace with hash 585363831, now seen corresponding path program 13 times [2023-11-06 22:50:32,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:32,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [982350878] [2023-11-06 22:50:32,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:32,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:32,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:33,007 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:33,007 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:33,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [982350878] [2023-11-06 22:50:33,008 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [982350878] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:33,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1196045381] [2023-11-06 22:50:33,008 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:50:33,008 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:33,008 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:33,014 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:33,037 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2023-11-06 22:50:33,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:33,112 INFO L262 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjunts are in the unsatisfiable core [2023-11-06 22:50:33,115 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:33,416 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:33,416 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:33,656 INFO L134 CoverageAnalysis]: Checked inductivity of 119 backedges. 70 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:33,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1196045381] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:33,656 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:33,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 28 [2023-11-06 22:50:33,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1692446801] [2023-11-06 22:50:33,657 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:33,711 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:33,712 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2023-11-06 22:50:33,712 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=203, Invalid=609, Unknown=0, NotChecked=0, Total=812 [2023-11-06 22:50:33,713 INFO L87 Difference]: Start difference. First operand 68 states and 78 transitions. cyclomatic complexity: 13 Second operand has 29 states, 28 states have (on average 2.5) internal successors, (70), 29 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:34,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:34,131 INFO L93 Difference]: Finished difference Result 219 states and 254 transitions. [2023-11-06 22:50:34,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 219 states and 254 transitions. [2023-11-06 22:50:34,134 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:34,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 219 states to 130 states and 150 transitions. [2023-11-06 22:50:34,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2023-11-06 22:50:34,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2023-11-06 22:50:34,136 INFO L73 IsDeterministic]: Start isDeterministic. Operand 130 states and 150 transitions. [2023-11-06 22:50:34,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:34,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 130 states and 150 transitions. [2023-11-06 22:50:34,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states and 150 transitions. [2023-11-06 22:50:34,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 76. [2023-11-06 22:50:34,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.144736842105263) internal successors, (87), 75 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:34,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 87 transitions. [2023-11-06 22:50:34,142 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-06 22:50:34,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2023-11-06 22:50:34,143 INFO L428 stractBuchiCegarLoop]: Abstraction has 76 states and 87 transitions. [2023-11-06 22:50:34,144 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:50:34,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 87 transitions. [2023-11-06 22:50:34,144 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:34,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:34,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:34,146 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 8, 7, 7, 1, 1, 1, 1] [2023-11-06 22:50:34,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:34,147 INFO L748 eck$LassoCheckResult]: Stem: 2791#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 2775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 2776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2792#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2793#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2779#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2810#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2809#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2808#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2807#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2806#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2805#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2804#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2803#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2802#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2801#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 2798#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2797#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 2781#L27-4 main_~i~0#1 := 0; 2782#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2788#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2774#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2785#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2790#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2841#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2840#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2835#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2832#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2829#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2826#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2823#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2818#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2817#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2814#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2812#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2811#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2796#L34 [2023-11-06 22:50:34,147 INFO L750 eck$LassoCheckResult]: Loop: 2796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 2799#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 2795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 2796#L34 [2023-11-06 22:50:34,147 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:34,147 INFO L85 PathProgramCache]: Analyzing trace with hash -704996231, now seen corresponding path program 14 times [2023-11-06 22:50:34,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:34,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530951376] [2023-11-06 22:50:34,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:34,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:34,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:34,187 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:34,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:34,232 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:34,233 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:34,233 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 9 times [2023-11-06 22:50:34,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:34,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063843095] [2023-11-06 22:50:34,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:34,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:34,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:34,237 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:34,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:34,241 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:34,241 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:34,241 INFO L85 PathProgramCache]: Analyzing trace with hash -152593571, now seen corresponding path program 15 times [2023-11-06 22:50:34,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:34,242 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [459117332] [2023-11-06 22:50:34,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:34,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:34,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:34,809 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 70 proven. 86 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:34,810 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:34,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [459117332] [2023-11-06 22:50:34,810 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [459117332] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:34,810 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [125153451] [2023-11-06 22:50:34,810 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:50:34,810 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:34,810 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:34,815 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:34,836 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2023-11-06 22:50:34,973 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2023-11-06 22:50:34,973 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:34,975 INFO L262 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjunts are in the unsatisfiable core [2023-11-06 22:50:34,977 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:35,326 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:35,327 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:35,581 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 92 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:35,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [125153451] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:35,582 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:35,582 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20] total 31 [2023-11-06 22:50:35,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891036855] [2023-11-06 22:50:35,584 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:35,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:35,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2023-11-06 22:50:35,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=245, Invalid=747, Unknown=0, NotChecked=0, Total=992 [2023-11-06 22:50:35,644 INFO L87 Difference]: Start difference. First operand 76 states and 87 transitions. cyclomatic complexity: 14 Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 32 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:36,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:36,128 INFO L93 Difference]: Finished difference Result 245 states and 284 transitions. [2023-11-06 22:50:36,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245 states and 284 transitions. [2023-11-06 22:50:36,130 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:36,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245 states to 144 states and 166 transitions. [2023-11-06 22:50:36,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125 [2023-11-06 22:50:36,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125 [2023-11-06 22:50:36,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 166 transitions. [2023-11-06 22:50:36,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:36,133 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 166 transitions. [2023-11-06 22:50:36,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 166 transitions. [2023-11-06 22:50:36,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 84. [2023-11-06 22:50:36,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.1428571428571428) internal successors, (96), 83 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:36,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 96 transitions. [2023-11-06 22:50:36,141 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-06 22:50:36,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2023-11-06 22:50:36,142 INFO L428 stractBuchiCegarLoop]: Abstraction has 84 states and 96 transitions. [2023-11-06 22:50:36,142 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:50:36,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 96 transitions. [2023-11-06 22:50:36,143 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:36,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:36,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:36,148 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 9, 8, 8, 1, 1, 1, 1] [2023-11-06 22:50:36,148 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:36,151 INFO L748 eck$LassoCheckResult]: Stem: 3431#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 3415#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 3416#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3432#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3433#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3419#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3420#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3452#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3451#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3450#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3449#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3448#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3447#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3446#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3445#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3444#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3443#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3442#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3441#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 3438#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 3437#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 3421#L27-4 main_~i~0#1 := 0; 3422#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3428#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3414#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3425#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3430#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3489#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3488#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3486#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3483#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3480#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3477#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3476#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3474#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3471#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3468#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3465#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3462#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3460#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3459#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3456#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3454#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3453#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 [2023-11-06 22:50:36,151 INFO L750 eck$LassoCheckResult]: Loop: 3436#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 3439#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 3435#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 3436#L34 [2023-11-06 22:50:36,151 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:36,152 INFO L85 PathProgramCache]: Analyzing trace with hash -1850900069, now seen corresponding path program 16 times [2023-11-06 22:50:36,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:36,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000658209] [2023-11-06 22:50:36,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:36,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:36,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:36,208 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:36,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:36,288 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:36,289 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:36,289 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 10 times [2023-11-06 22:50:36,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:36,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411000611] [2023-11-06 22:50:36,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:36,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:36,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:36,294 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:36,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:36,297 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:36,298 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:36,298 INFO L85 PathProgramCache]: Analyzing trace with hash -1373762821, now seen corresponding path program 17 times [2023-11-06 22:50:36,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:36,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768258157] [2023-11-06 22:50:36,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:36,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:36,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:36,932 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 92 proven. 106 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:36,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:36,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768258157] [2023-11-06 22:50:36,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768258157] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:36,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1994939607] [2023-11-06 22:50:36,933 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:50:36,933 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:36,933 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:36,937 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:36,968 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2023-11-06 22:50:37,236 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2023-11-06 22:50:37,236 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:37,238 INFO L262 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjunts are in the unsatisfiable core [2023-11-06 22:50:37,241 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:37,645 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:37,645 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:37,975 INFO L134 CoverageAnalysis]: Checked inductivity of 198 backedges. 117 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:37,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1994939607] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:37,976 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:37,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 34 [2023-11-06 22:50:37,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1937074499] [2023-11-06 22:50:37,976 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:38,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:38,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2023-11-06 22:50:38,033 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=291, Invalid=899, Unknown=0, NotChecked=0, Total=1190 [2023-11-06 22:50:38,033 INFO L87 Difference]: Start difference. First operand 84 states and 96 transitions. cyclomatic complexity: 15 Second operand has 35 states, 34 states have (on average 2.5294117647058822) internal successors, (86), 35 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:38,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:38,593 INFO L93 Difference]: Finished difference Result 271 states and 314 transitions. [2023-11-06 22:50:38,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 314 transitions. [2023-11-06 22:50:38,596 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:38,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 158 states and 182 transitions. [2023-11-06 22:50:38,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 137 [2023-11-06 22:50:38,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 137 [2023-11-06 22:50:38,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 182 transitions. [2023-11-06 22:50:38,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:38,599 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 182 transitions. [2023-11-06 22:50:38,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 182 transitions. [2023-11-06 22:50:38,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 92. [2023-11-06 22:50:38,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.141304347826087) internal successors, (105), 91 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:38,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 105 transitions. [2023-11-06 22:50:38,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-06 22:50:38,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-06 22:50:38,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 92 states and 105 transitions. [2023-11-06 22:50:38,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:50:38,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 105 transitions. [2023-11-06 22:50:38,607 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:38,607 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:38,607 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:38,608 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 10, 9, 9, 1, 1, 1, 1] [2023-11-06 22:50:38,608 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:38,608 INFO L748 eck$LassoCheckResult]: Stem: 4142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4125#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4140#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4141#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4128#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4129#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4163#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4162#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4161#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4160#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4159#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4158#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4157#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4156#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4155#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4154#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4153#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4152#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4151#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4150#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4147#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4146#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4130#L27-4 main_~i~0#1 := 0; 4131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4137#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4139#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4206#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4205#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4203#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4200#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4199#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4197#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4194#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4193#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4191#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4188#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4187#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4185#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4182#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4181#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4179#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4176#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4175#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4173#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4171#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4167#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4165#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4145#L34 [2023-11-06 22:50:38,608 INFO L750 eck$LassoCheckResult]: Loop: 4145#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4145#L34 [2023-11-06 22:50:38,609 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:38,609 INFO L85 PathProgramCache]: Analyzing trace with hash -354133123, now seen corresponding path program 18 times [2023-11-06 22:50:38,609 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:38,609 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326081918] [2023-11-06 22:50:38,609 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:38,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:38,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:38,675 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:38,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:38,724 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:38,724 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:38,724 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 11 times [2023-11-06 22:50:38,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:38,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1951001716] [2023-11-06 22:50:38,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:38,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:38,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:38,728 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:38,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:38,731 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:38,731 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:38,732 INFO L85 PathProgramCache]: Analyzing trace with hash -1540141607, now seen corresponding path program 19 times [2023-11-06 22:50:38,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:38,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541454122] [2023-11-06 22:50:38,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:38,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:38,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:39,351 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 117 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:39,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:39,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541454122] [2023-11-06 22:50:39,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541454122] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:39,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1211252630] [2023-11-06 22:50:39,352 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:50:39,352 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:39,352 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:39,356 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:39,372 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2023-11-06 22:50:39,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:39,476 INFO L262 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-06 22:50:39,478 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:39,884 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:39,885 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:40,192 INFO L134 CoverageAnalysis]: Checked inductivity of 245 backedges. 145 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:40,192 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1211252630] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:40,193 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:40,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 37 [2023-11-06 22:50:40,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1824016867] [2023-11-06 22:50:40,193 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:40,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:40,245 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2023-11-06 22:50:40,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=341, Invalid=1065, Unknown=0, NotChecked=0, Total=1406 [2023-11-06 22:50:40,246 INFO L87 Difference]: Start difference. First operand 92 states and 105 transitions. cyclomatic complexity: 16 Second operand has 38 states, 37 states have (on average 2.5405405405405403) internal successors, (94), 38 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:40,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:40,814 INFO L93 Difference]: Finished difference Result 297 states and 344 transitions. [2023-11-06 22:50:40,814 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 344 transitions. [2023-11-06 22:50:40,818 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:40,820 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 172 states and 198 transitions. [2023-11-06 22:50:40,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 149 [2023-11-06 22:50:40,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 149 [2023-11-06 22:50:40,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 172 states and 198 transitions. [2023-11-06 22:50:40,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:40,821 INFO L218 hiAutomatonCegarLoop]: Abstraction has 172 states and 198 transitions. [2023-11-06 22:50:40,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states and 198 transitions. [2023-11-06 22:50:40,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 100. [2023-11-06 22:50:40,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.14) internal successors, (114), 99 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:40,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 114 transitions. [2023-11-06 22:50:40,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-06 22:50:40,837 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2023-11-06 22:50:40,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 100 states and 114 transitions. [2023-11-06 22:50:40,840 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:50:40,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 114 transitions. [2023-11-06 22:50:40,841 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:40,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:40,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:40,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 11, 10, 10, 1, 1, 1, 1] [2023-11-06 22:50:40,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:40,845 INFO L748 eck$LassoCheckResult]: Stem: 4918#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 4902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 4903#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4919#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4920#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4906#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4907#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4943#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4942#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4941#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4940#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4939#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4938#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4937#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4936#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4935#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4934#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4933#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4932#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4931#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4930#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4929#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4928#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 4925#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 4924#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 4908#L27-4 main_~i~0#1 := 0; 4909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4915#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4901#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4912#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4917#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4992#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4991#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4989#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4986#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4985#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4983#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4980#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4979#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4977#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4974#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4973#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4971#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4968#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4967#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4965#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4962#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4961#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4959#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4956#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4955#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4953#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4947#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4945#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4923#L34 [2023-11-06 22:50:40,846 INFO L750 eck$LassoCheckResult]: Loop: 4923#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 4926#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 4922#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 4923#L34 [2023-11-06 22:50:40,846 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:40,846 INFO L85 PathProgramCache]: Analyzing trace with hash -726335849, now seen corresponding path program 20 times [2023-11-06 22:50:40,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:40,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604802652] [2023-11-06 22:50:40,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:40,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:40,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:40,956 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:41,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:41,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:41,032 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:41,033 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 12 times [2023-11-06 22:50:41,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:41,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590271062] [2023-11-06 22:50:41,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:41,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:41,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:41,037 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:41,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:41,042 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:41,043 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:41,043 INFO L85 PathProgramCache]: Analyzing trace with hash -225993601, now seen corresponding path program 21 times [2023-11-06 22:50:41,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:41,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150912318] [2023-11-06 22:50:41,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:41,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:41,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:41,739 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 145 proven. 152 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:41,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:41,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [150912318] [2023-11-06 22:50:41,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [150912318] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:41,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [276516210] [2023-11-06 22:50:41,740 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:50:41,740 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:41,740 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:41,748 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:41,752 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2023-11-06 22:50:42,336 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2023-11-06 22:50:42,336 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:42,339 INFO L262 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjunts are in the unsatisfiable core [2023-11-06 22:50:42,341 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:42,836 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:42,836 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:43,222 INFO L134 CoverageAnalysis]: Checked inductivity of 297 backedges. 176 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:43,223 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [276516210] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:43,223 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:43,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 40 [2023-11-06 22:50:43,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430341061] [2023-11-06 22:50:43,223 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:43,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:43,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2023-11-06 22:50:43,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=395, Invalid=1245, Unknown=0, NotChecked=0, Total=1640 [2023-11-06 22:50:43,278 INFO L87 Difference]: Start difference. First operand 100 states and 114 transitions. cyclomatic complexity: 17 Second operand has 41 states, 40 states have (on average 2.55) internal successors, (102), 41 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:43,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:43,902 INFO L93 Difference]: Finished difference Result 323 states and 374 transitions. [2023-11-06 22:50:43,902 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 323 states and 374 transitions. [2023-11-06 22:50:43,905 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:43,906 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 323 states to 186 states and 214 transitions. [2023-11-06 22:50:43,906 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161 [2023-11-06 22:50:43,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161 [2023-11-06 22:50:43,907 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 214 transitions. [2023-11-06 22:50:43,907 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:43,907 INFO L218 hiAutomatonCegarLoop]: Abstraction has 186 states and 214 transitions. [2023-11-06 22:50:43,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 214 transitions. [2023-11-06 22:50:43,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 108. [2023-11-06 22:50:43,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1388888888888888) internal successors, (123), 107 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:43,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 123 transitions. [2023-11-06 22:50:43,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-06 22:50:43,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2023-11-06 22:50:43,915 INFO L428 stractBuchiCegarLoop]: Abstraction has 108 states and 123 transitions. [2023-11-06 22:50:43,916 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:50:43,916 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 123 transitions. [2023-11-06 22:50:43,917 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:43,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:43,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:43,918 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 12, 11, 11, 1, 1, 1, 1] [2023-11-06 22:50:43,918 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:43,919 INFO L748 eck$LassoCheckResult]: Stem: 5765#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 5749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 5750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5754#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5792#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5791#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5790#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5789#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5788#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5787#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5786#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5785#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5784#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5783#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 5772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5771#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 5755#L27-4 main_~i~0#1 := 0; 5756#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5748#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5759#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5764#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5847#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5846#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5844#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5841#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5840#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5838#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5835#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5832#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5829#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5828#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5826#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5823#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5822#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5820#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5817#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5816#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5814#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5811#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5810#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5808#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5805#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5802#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5800#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5796#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5770#L34 [2023-11-06 22:50:43,919 INFO L750 eck$LassoCheckResult]: Loop: 5770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 5773#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 5769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 5770#L34 [2023-11-06 22:50:43,919 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:43,919 INFO L85 PathProgramCache]: Analyzing trace with hash -2083736959, now seen corresponding path program 22 times [2023-11-06 22:50:43,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:43,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919399274] [2023-11-06 22:50:43,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:43,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:43,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:43,983 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:44,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:44,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:44,098 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:44,098 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 13 times [2023-11-06 22:50:44,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:44,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612832833] [2023-11-06 22:50:44,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:44,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:44,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:44,104 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:44,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:44,108 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:44,109 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:44,109 INFO L85 PathProgramCache]: Analyzing trace with hash -1445369771, now seen corresponding path program 23 times [2023-11-06 22:50:44,109 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:44,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808844966] [2023-11-06 22:50:44,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:44,110 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:44,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:44,909 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 176 proven. 178 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:44,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:44,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808844966] [2023-11-06 22:50:44,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808844966] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:44,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1408158727] [2023-11-06 22:50:44,910 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:50:44,910 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:44,910 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:44,916 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:44,927 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2023-11-06 22:50:45,327 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2023-11-06 22:50:45,328 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:45,330 INFO L262 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjunts are in the unsatisfiable core [2023-11-06 22:50:45,333 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:46,008 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:46,008 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:46,423 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 210 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:46,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1408158727] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:46,424 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:46,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 43 [2023-11-06 22:50:46,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127612048] [2023-11-06 22:50:46,424 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:46,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:46,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2023-11-06 22:50:46,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=453, Invalid=1439, Unknown=0, NotChecked=0, Total=1892 [2023-11-06 22:50:46,483 INFO L87 Difference]: Start difference. First operand 108 states and 123 transitions. cyclomatic complexity: 18 Second operand has 44 states, 43 states have (on average 2.558139534883721) internal successors, (110), 44 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:47,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:47,190 INFO L93 Difference]: Finished difference Result 349 states and 404 transitions. [2023-11-06 22:50:47,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 349 states and 404 transitions. [2023-11-06 22:50:47,193 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:47,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 349 states to 200 states and 230 transitions. [2023-11-06 22:50:47,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 173 [2023-11-06 22:50:47,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 173 [2023-11-06 22:50:47,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 230 transitions. [2023-11-06 22:50:47,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:47,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 230 transitions. [2023-11-06 22:50:47,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 230 transitions. [2023-11-06 22:50:47,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 116. [2023-11-06 22:50:47,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1379310344827587) internal successors, (132), 115 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:47,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 132 transitions. [2023-11-06 22:50:47,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-06 22:50:47,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2023-11-06 22:50:47,201 INFO L428 stractBuchiCegarLoop]: Abstraction has 116 states and 132 transitions. [2023-11-06 22:50:47,201 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:50:47,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 132 transitions. [2023-11-06 22:50:47,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:47,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:47,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:47,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 13, 12, 12, 1, 1, 1, 1] [2023-11-06 22:50:47,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:47,204 INFO L748 eck$LassoCheckResult]: Stem: 6681#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 6665#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 6666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6682#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6683#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6669#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6710#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6707#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6706#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6704#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6701#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6700#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6699#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6698#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6697#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6696#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6695#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6694#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6693#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6692#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6691#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 6688#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 6687#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 6671#L27-4 main_~i~0#1 := 0; 6672#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6678#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6664#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6675#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6680#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6771#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6770#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6768#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6765#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6764#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6762#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6759#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6758#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6756#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6753#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6752#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6750#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6747#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6746#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6744#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6738#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6732#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6726#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6723#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6718#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6717#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6714#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6712#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6686#L34 [2023-11-06 22:50:47,204 INFO L750 eck$LassoCheckResult]: Loop: 6686#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 6689#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 6685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 6686#L34 [2023-11-06 22:50:47,204 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:47,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1447312493, now seen corresponding path program 24 times [2023-11-06 22:50:47,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:47,205 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772172491] [2023-11-06 22:50:47,205 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:47,205 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:47,283 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:47,283 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:47,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:47,359 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:47,360 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:47,360 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 14 times [2023-11-06 22:50:47,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:47,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [61961577] [2023-11-06 22:50:47,361 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:47,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:47,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:47,365 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:47,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:47,368 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:47,369 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:47,369 INFO L85 PathProgramCache]: Analyzing trace with hash 290252291, now seen corresponding path program 25 times [2023-11-06 22:50:47,369 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:47,369 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259966041] [2023-11-06 22:50:47,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:47,370 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:47,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:48,210 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 210 proven. 206 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:48,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:48,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259966041] [2023-11-06 22:50:48,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259966041] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:48,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [747648032] [2023-11-06 22:50:48,210 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:50:48,211 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:48,211 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:48,216 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:48,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2023-11-06 22:50:48,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:48,380 INFO L262 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjunts are in the unsatisfiable core [2023-11-06 22:50:48,383 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:49,046 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:49,046 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:49,546 INFO L134 CoverageAnalysis]: Checked inductivity of 416 backedges. 247 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:49,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [747648032] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:49,547 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:49,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 46 [2023-11-06 22:50:49,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [258112833] [2023-11-06 22:50:49,548 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:49,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:49,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2023-11-06 22:50:49,607 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=515, Invalid=1647, Unknown=0, NotChecked=0, Total=2162 [2023-11-06 22:50:49,607 INFO L87 Difference]: Start difference. First operand 116 states and 132 transitions. cyclomatic complexity: 19 Second operand has 47 states, 46 states have (on average 2.5652173913043477) internal successors, (118), 47 states have internal predecessors, (118), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:50,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:50,311 INFO L93 Difference]: Finished difference Result 375 states and 434 transitions. [2023-11-06 22:50:50,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 375 states and 434 transitions. [2023-11-06 22:50:50,314 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:50,316 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 375 states to 214 states and 246 transitions. [2023-11-06 22:50:50,316 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 185 [2023-11-06 22:50:50,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 185 [2023-11-06 22:50:50,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214 states and 246 transitions. [2023-11-06 22:50:50,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:50,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 214 states and 246 transitions. [2023-11-06 22:50:50,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states and 246 transitions. [2023-11-06 22:50:50,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 124. [2023-11-06 22:50:50,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 124 states, 124 states have (on average 1.1370967741935485) internal successors, (141), 123 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:50,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 141 transitions. [2023-11-06 22:50:50,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-06 22:50:50,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2023-11-06 22:50:50,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 124 states and 141 transitions. [2023-11-06 22:50:50,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:50:50,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124 states and 141 transitions. [2023-11-06 22:50:50,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:50,324 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:50,324 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:50,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 14, 13, 13, 1, 1, 1, 1] [2023-11-06 22:50:50,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:50,325 INFO L748 eck$LassoCheckResult]: Stem: 7666#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 7650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 7651#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7654#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7655#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7697#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7696#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7695#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7694#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7693#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7692#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7691#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7688#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7687#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 7673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 7672#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 7656#L27-4 main_~i~0#1 := 0; 7657#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7663#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7649#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7660#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7665#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7764#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7761#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7671#L34 [2023-11-06 22:50:50,325 INFO L750 eck$LassoCheckResult]: Loop: 7671#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 7674#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 7670#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 7671#L34 [2023-11-06 22:50:50,326 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:50,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1635246469, now seen corresponding path program 26 times [2023-11-06 22:50:50,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:50,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76977354] [2023-11-06 22:50:50,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:50,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:50,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:50,402 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:50,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:50,479 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:50,479 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:50,479 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 15 times [2023-11-06 22:50:50,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:50,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628034427] [2023-11-06 22:50:50,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:50,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:50,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:50,484 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:50,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:50,487 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:50,488 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:50,488 INFO L85 PathProgramCache]: Analyzing trace with hash 2108533457, now seen corresponding path program 27 times [2023-11-06 22:50:50,488 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:50,488 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403253845] [2023-11-06 22:50:50,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:50,488 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:50,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:51,562 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 247 proven. 236 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:51,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:51,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [403253845] [2023-11-06 22:50:51,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [403253845] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:51,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1021853446] [2023-11-06 22:50:51,562 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:50:51,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:51,563 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:51,568 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:51,573 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2023-11-06 22:50:52,159 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2023-11-06 22:50:52,159 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:52,163 INFO L262 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjunts are in the unsatisfiable core [2023-11-06 22:50:52,166 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:52,857 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:52,857 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:53,446 INFO L134 CoverageAnalysis]: Checked inductivity of 483 backedges. 287 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:53,446 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1021853446] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:53,446 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:53,446 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32] total 49 [2023-11-06 22:50:53,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738458555] [2023-11-06 22:50:53,446 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:53,498 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:53,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2023-11-06 22:50:53,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=581, Invalid=1869, Unknown=0, NotChecked=0, Total=2450 [2023-11-06 22:50:53,500 INFO L87 Difference]: Start difference. First operand 124 states and 141 transitions. cyclomatic complexity: 20 Second operand has 50 states, 49 states have (on average 2.5714285714285716) internal successors, (126), 50 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:54,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:54,259 INFO L93 Difference]: Finished difference Result 401 states and 464 transitions. [2023-11-06 22:50:54,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 401 states and 464 transitions. [2023-11-06 22:50:54,262 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:54,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 401 states to 228 states and 262 transitions. [2023-11-06 22:50:54,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 197 [2023-11-06 22:50:54,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 197 [2023-11-06 22:50:54,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 262 transitions. [2023-11-06 22:50:54,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:54,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228 states and 262 transitions. [2023-11-06 22:50:54,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 262 transitions. [2023-11-06 22:50:54,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 132. [2023-11-06 22:50:54,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 132 states, 132 states have (on average 1.1363636363636365) internal successors, (150), 131 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:54,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 150 transitions. [2023-11-06 22:50:54,270 INFO L240 hiAutomatonCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-06 22:50:54,270 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2023-11-06 22:50:54,271 INFO L428 stractBuchiCegarLoop]: Abstraction has 132 states and 150 transitions. [2023-11-06 22:50:54,271 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:50:54,271 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 132 states and 150 transitions. [2023-11-06 22:50:54,272 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:54,272 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:54,272 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:54,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 15, 14, 14, 1, 1, 1, 1] [2023-11-06 22:50:54,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:54,273 INFO L748 eck$LassoCheckResult]: Stem: 8720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 8704#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 8705#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8721#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8722#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8709#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8753#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8750#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8749#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8748#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8747#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8746#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8745#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8744#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8743#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8742#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8741#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8740#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8739#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8738#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8737#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8736#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8735#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8734#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8733#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8732#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8731#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8730#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 8727#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 8726#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 8710#L27-4 main_~i~0#1 := 0; 8711#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8717#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8703#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8714#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8825#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8820#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8819#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8817#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8814#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8813#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8811#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8808#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8807#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8805#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8802#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8801#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8799#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8796#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8795#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8793#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8787#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8781#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8778#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8777#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8775#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8772#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8771#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8769#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8766#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8765#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8763#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8761#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8760#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8757#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8755#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8725#L34 [2023-11-06 22:50:54,274 INFO L750 eck$LassoCheckResult]: Loop: 8725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 8728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 8724#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 8725#L34 [2023-11-06 22:50:54,274 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:54,274 INFO L85 PathProgramCache]: Analyzing trace with hash -436367217, now seen corresponding path program 28 times [2023-11-06 22:50:54,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:54,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1235615167] [2023-11-06 22:50:54,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:54,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:54,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:54,356 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:54,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:54,438 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:54,438 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:54,438 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 16 times [2023-11-06 22:50:54,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:54,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681240489] [2023-11-06 22:50:54,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:54,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:54,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:54,443 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:54,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:54,446 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:54,447 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:54,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1050290055, now seen corresponding path program 29 times [2023-11-06 22:50:54,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:54,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763926709] [2023-11-06 22:50:54,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:54,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:54,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:55,505 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 287 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:55,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:55,506 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763926709] [2023-11-06 22:50:55,506 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763926709] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:55,506 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1007898500] [2023-11-06 22:50:55,506 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:50:55,506 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:55,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:55,510 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:55,513 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2023-11-06 22:50:55,936 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2023-11-06 22:50:55,936 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:50:55,944 INFO L262 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjunts are in the unsatisfiable core [2023-11-06 22:50:55,946 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:50:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:56,702 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:50:57,283 INFO L134 CoverageAnalysis]: Checked inductivity of 555 backedges. 330 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:57,284 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1007898500] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:50:57,284 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:50:57,284 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 52 [2023-11-06 22:50:57,284 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902224815] [2023-11-06 22:50:57,284 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:50:57,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:50:57,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2023-11-06 22:50:57,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=2105, Unknown=0, NotChecked=0, Total=2756 [2023-11-06 22:50:57,339 INFO L87 Difference]: Start difference. First operand 132 states and 150 transitions. cyclomatic complexity: 21 Second operand has 53 states, 52 states have (on average 2.576923076923077) internal successors, (134), 53 states have internal predecessors, (134), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:58,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:50:58,183 INFO L93 Difference]: Finished difference Result 427 states and 494 transitions. [2023-11-06 22:50:58,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427 states and 494 transitions. [2023-11-06 22:50:58,189 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:58,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427 states to 242 states and 278 transitions. [2023-11-06 22:50:58,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209 [2023-11-06 22:50:58,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209 [2023-11-06 22:50:58,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 278 transitions. [2023-11-06 22:50:58,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:50:58,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 278 transitions. [2023-11-06 22:50:58,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 278 transitions. [2023-11-06 22:50:58,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 140. [2023-11-06 22:50:58,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1357142857142857) internal successors, (159), 139 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:50:58,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 159 transitions. [2023-11-06 22:50:58,197 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-06 22:50:58,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2023-11-06 22:50:58,198 INFO L428 stractBuchiCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-06 22:50:58,198 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:50:58,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 159 transitions. [2023-11-06 22:50:58,199 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:50:58,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:50:58,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:50:58,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 16, 15, 15, 1, 1, 1, 1] [2023-11-06 22:50:58,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:50:58,201 INFO L748 eck$LassoCheckResult]: Stem: 9843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 9827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 9828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9844#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9845#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9831#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9878#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9877#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9876#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9875#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9874#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9873#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9872#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9871#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9870#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9869#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9868#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9867#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9866#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9865#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9864#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9863#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9862#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9861#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9860#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9859#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9858#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9855#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9854#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 9850#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 9849#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 9833#L27-4 main_~i~0#1 := 0; 9834#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9842#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9957#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9956#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9954#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9950#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9948#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9945#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9944#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9942#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9918#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9912#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9906#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9894#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9888#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9882#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9880#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9848#L34 [2023-11-06 22:50:58,201 INFO L750 eck$LassoCheckResult]: Loop: 9848#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 9851#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 9847#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 9848#L34 [2023-11-06 22:50:58,201 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:58,201 INFO L85 PathProgramCache]: Analyzing trace with hash -1180030839, now seen corresponding path program 30 times [2023-11-06 22:50:58,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:58,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019004046] [2023-11-06 22:50:58,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:58,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:58,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:58,315 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:58,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:58,392 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:58,393 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:58,393 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 17 times [2023-11-06 22:50:58,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:58,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [181838020] [2023-11-06 22:50:58,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:58,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:58,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:58,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:50:58,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:50:58,402 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:50:58,402 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:50:58,402 INFO L85 PathProgramCache]: Analyzing trace with hash 8639821, now seen corresponding path program 31 times [2023-11-06 22:50:58,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:50:58,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396675950] [2023-11-06 22:50:58,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:50:58,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:50:58,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:59,619 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 330 proven. 302 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:50:59,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:50:59,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1396675950] [2023-11-06 22:50:59,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1396675950] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:50:59,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [329976856] [2023-11-06 22:50:59,619 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:50:59,619 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:50:59,620 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:50:59,627 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:50:59,629 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2023-11-06 22:50:59,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:50:59,833 INFO L262 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjunts are in the unsatisfiable core [2023-11-06 22:50:59,835 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:00,603 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:00,603 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:01,234 INFO L134 CoverageAnalysis]: Checked inductivity of 632 backedges. 376 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:01,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [329976856] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:01,234 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:01,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 55 [2023-11-06 22:51:01,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521923356] [2023-11-06 22:51:01,234 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:01,282 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:01,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2023-11-06 22:51:01,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=725, Invalid=2355, Unknown=0, NotChecked=0, Total=3080 [2023-11-06 22:51:01,285 INFO L87 Difference]: Start difference. First operand 140 states and 159 transitions. cyclomatic complexity: 22 Second operand has 56 states, 55 states have (on average 2.581818181818182) internal successors, (142), 56 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:02,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:02,167 INFO L93 Difference]: Finished difference Result 453 states and 524 transitions. [2023-11-06 22:51:02,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453 states and 524 transitions. [2023-11-06 22:51:02,171 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:02,173 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453 states to 256 states and 294 transitions. [2023-11-06 22:51:02,173 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 221 [2023-11-06 22:51:02,173 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 221 [2023-11-06 22:51:02,173 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 294 transitions. [2023-11-06 22:51:02,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:02,174 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 294 transitions. [2023-11-06 22:51:02,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 294 transitions. [2023-11-06 22:51:02,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 148. [2023-11-06 22:51:02,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 148 states, 148 states have (on average 1.135135135135135) internal successors, (168), 147 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:02,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 168 transitions. [2023-11-06 22:51:02,178 INFO L240 hiAutomatonCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-06 22:51:02,179 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2023-11-06 22:51:02,179 INFO L428 stractBuchiCegarLoop]: Abstraction has 148 states and 168 transitions. [2023-11-06 22:51:02,179 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:51:02,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 148 states and 168 transitions. [2023-11-06 22:51:02,180 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:02,181 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:02,181 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:02,182 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 17, 16, 16, 1, 1, 1, 1] [2023-11-06 22:51:02,182 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:02,182 INFO L748 eck$LassoCheckResult]: Stem: 11035#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 11019#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 11020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11023#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11072#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11071#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11070#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 11042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 11041#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 11025#L27-4 main_~i~0#1 := 0; 11026#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11032#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11034#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11157#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11154#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11148#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11145#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11142#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11139#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11136#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11133#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11130#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11124#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11121#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11118#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11115#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11114#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11112#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11109#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11108#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11106#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11103#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11102#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11100#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11097#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11096#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11094#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11091#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11090#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11088#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11085#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11084#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11082#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11080#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11079#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11076#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11074#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11073#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11040#L34 [2023-11-06 22:51:02,182 INFO L750 eck$LassoCheckResult]: Loop: 11040#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 11043#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 11039#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 11040#L34 [2023-11-06 22:51:02,183 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:02,183 INFO L85 PathProgramCache]: Analyzing trace with hash -1481235061, now seen corresponding path program 32 times [2023-11-06 22:51:02,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:02,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682488424] [2023-11-06 22:51:02,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:02,184 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:02,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:02,288 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:02,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:02,377 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:02,378 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:02,378 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 18 times [2023-11-06 22:51:02,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:02,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420175523] [2023-11-06 22:51:02,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:02,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:02,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:02,382 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:02,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:02,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:02,386 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:02,387 INFO L85 PathProgramCache]: Analyzing trace with hash -979656437, now seen corresponding path program 33 times [2023-11-06 22:51:02,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:02,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755818058] [2023-11-06 22:51:02,387 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:02,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:02,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:03,665 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 376 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:03,665 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:03,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755818058] [2023-11-06 22:51:03,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755818058] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:03,665 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [870543505] [2023-11-06 22:51:03,665 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:51:03,666 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:03,666 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:03,667 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:03,668 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2023-11-06 22:51:04,368 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2023-11-06 22:51:04,368 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:04,372 INFO L262 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjunts are in the unsatisfiable core [2023-11-06 22:51:04,374 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:05,241 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:05,241 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:05,933 INFO L134 CoverageAnalysis]: Checked inductivity of 714 backedges. 425 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:05,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [870543505] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:05,934 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:05,934 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 58 [2023-11-06 22:51:05,934 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [557422338] [2023-11-06 22:51:05,934 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:05,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:05,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2023-11-06 22:51:05,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=803, Invalid=2619, Unknown=0, NotChecked=0, Total=3422 [2023-11-06 22:51:05,987 INFO L87 Difference]: Start difference. First operand 148 states and 168 transitions. cyclomatic complexity: 23 Second operand has 59 states, 58 states have (on average 2.586206896551724) internal successors, (150), 59 states have internal predecessors, (150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:07,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:07,010 INFO L93 Difference]: Finished difference Result 479 states and 554 transitions. [2023-11-06 22:51:07,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 554 transitions. [2023-11-06 22:51:07,014 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:07,017 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 270 states and 310 transitions. [2023-11-06 22:51:07,017 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 233 [2023-11-06 22:51:07,017 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 233 [2023-11-06 22:51:07,017 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 310 transitions. [2023-11-06 22:51:07,018 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:07,018 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 310 transitions. [2023-11-06 22:51:07,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 310 transitions. [2023-11-06 22:51:07,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 156. [2023-11-06 22:51:07,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 156 states, 156 states have (on average 1.1346153846153846) internal successors, (177), 155 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:07,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 177 transitions. [2023-11-06 22:51:07,023 INFO L240 hiAutomatonCegarLoop]: Abstraction has 156 states and 177 transitions. [2023-11-06 22:51:07,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2023-11-06 22:51:07,024 INFO L428 stractBuchiCegarLoop]: Abstraction has 156 states and 177 transitions. [2023-11-06 22:51:07,024 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:51:07,024 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156 states and 177 transitions. [2023-11-06 22:51:07,025 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:07,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:07,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:07,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 18, 17, 17, 1, 1, 1, 1] [2023-11-06 22:51:07,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:07,027 INFO L748 eck$LassoCheckResult]: Stem: 12298#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 12280#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 12281#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12296#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12297#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12284#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12285#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12335#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12334#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12333#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12332#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12331#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12330#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12329#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12328#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12327#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12326#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12325#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12324#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12323#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12322#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12321#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12320#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12319#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12318#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12317#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12316#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12315#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12314#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12313#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12312#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12311#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12310#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12309#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12308#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12307#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12306#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 12303#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 12302#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 12286#L27-4 main_~i~0#1 := 0; 12287#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12293#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12279#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12290#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12295#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12426#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12425#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12423#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12420#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12419#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12417#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12414#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12413#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12411#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12408#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12407#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12405#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12402#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12401#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12399#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12396#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12395#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12393#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12390#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12389#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12387#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12384#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12383#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12381#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12378#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12377#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12375#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12372#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12371#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12369#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12366#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12365#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12363#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12360#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12359#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12357#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12354#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12353#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12351#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12348#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12347#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12345#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12343#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12342#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12339#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12337#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12336#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12301#L34 [2023-11-06 22:51:07,027 INFO L750 eck$LassoCheckResult]: Loop: 12301#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 12304#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 12300#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 12301#L34 [2023-11-06 22:51:07,027 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:07,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1155020915, now seen corresponding path program 34 times [2023-11-06 22:51:07,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:07,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499016341] [2023-11-06 22:51:07,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:07,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:07,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:07,145 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:07,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:07,242 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:07,243 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:07,243 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 19 times [2023-11-06 22:51:07,243 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:07,243 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227363882] [2023-11-06 22:51:07,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:07,243 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:07,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:07,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:07,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:07,252 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:07,253 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:07,253 INFO L85 PathProgramCache]: Analyzing trace with hash 2049943497, now seen corresponding path program 35 times [2023-11-06 22:51:07,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:07,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715023362] [2023-11-06 22:51:07,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:07,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:07,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:08,721 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 425 proven. 376 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:08,721 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:08,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1715023362] [2023-11-06 22:51:08,721 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1715023362] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:08,721 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [77210588] [2023-11-06 22:51:08,722 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:51:08,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:08,722 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:08,728 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:08,730 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2023-11-06 22:51:09,581 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2023-11-06 22:51:09,581 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:09,587 INFO L262 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjunts are in the unsatisfiable core [2023-11-06 22:51:09,590 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:10,484 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:10,485 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:11,210 INFO L134 CoverageAnalysis]: Checked inductivity of 801 backedges. 477 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:11,211 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [77210588] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:11,211 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:11,211 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 61 [2023-11-06 22:51:11,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [243810896] [2023-11-06 22:51:11,211 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:11,260 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:11,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2023-11-06 22:51:11,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=885, Invalid=2897, Unknown=0, NotChecked=0, Total=3782 [2023-11-06 22:51:11,263 INFO L87 Difference]: Start difference. First operand 156 states and 177 transitions. cyclomatic complexity: 24 Second operand has 62 states, 61 states have (on average 2.5901639344262297) internal successors, (158), 62 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:12,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:12,265 INFO L93 Difference]: Finished difference Result 505 states and 584 transitions. [2023-11-06 22:51:12,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 584 transitions. [2023-11-06 22:51:12,269 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:12,271 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 284 states and 326 transitions. [2023-11-06 22:51:12,271 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245 [2023-11-06 22:51:12,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245 [2023-11-06 22:51:12,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 326 transitions. [2023-11-06 22:51:12,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:12,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 326 transitions. [2023-11-06 22:51:12,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 326 transitions. [2023-11-06 22:51:12,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 164. [2023-11-06 22:51:12,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1341463414634145) internal successors, (186), 163 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:12,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 186 transitions. [2023-11-06 22:51:12,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 186 transitions. [2023-11-06 22:51:12,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2023-11-06 22:51:12,280 INFO L428 stractBuchiCegarLoop]: Abstraction has 164 states and 186 transitions. [2023-11-06 22:51:12,280 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:51:12,280 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 186 transitions. [2023-11-06 22:51:12,281 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:12,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:12,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:12,282 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 19, 18, 18, 1, 1, 1, 1] [2023-11-06 22:51:12,283 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:12,283 INFO L748 eck$LassoCheckResult]: Stem: 13626#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 13610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 13611#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13627#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13628#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13614#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13615#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13665#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13661#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13660#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13659#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13658#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13657#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13655#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13654#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13653#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13651#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13650#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13649#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13647#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13646#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13645#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13644#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13643#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13642#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13641#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13640#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13639#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13638#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13637#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13636#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 13633#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 13632#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 13616#L27-4 main_~i~0#1 := 0; 13617#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13623#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13609#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13620#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13625#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13764#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13761#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13692#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13691#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13689#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13686#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13685#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13683#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13680#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13679#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13677#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13675#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13671#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13631#L34 [2023-11-06 22:51:12,283 INFO L750 eck$LassoCheckResult]: Loop: 13631#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 13634#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 13630#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 13631#L34 [2023-11-06 22:51:12,283 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:12,284 INFO L85 PathProgramCache]: Analyzing trace with hash -769572217, now seen corresponding path program 36 times [2023-11-06 22:51:12,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:12,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566014176] [2023-11-06 22:51:12,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:12,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:12,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:12,387 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:12,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:12,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:12,505 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:12,505 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 20 times [2023-11-06 22:51:12,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:12,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169606493] [2023-11-06 22:51:12,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:12,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:12,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:12,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:12,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:12,514 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:12,515 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:12,515 INFO L85 PathProgramCache]: Analyzing trace with hash 209556111, now seen corresponding path program 37 times [2023-11-06 22:51:12,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:12,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [338434277] [2023-11-06 22:51:12,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:12,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:12,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:13,944 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 477 proven. 416 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:13,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:13,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [338434277] [2023-11-06 22:51:13,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [338434277] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:13,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1282196190] [2023-11-06 22:51:13,945 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:51:13,945 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:13,945 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:13,952 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:13,968 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2023-11-06 22:51:14,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:14,187 INFO L262 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjunts are in the unsatisfiable core [2023-11-06 22:51:14,190 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:15,226 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:15,226 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:16,054 INFO L134 CoverageAnalysis]: Checked inductivity of 893 backedges. 532 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:16,055 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1282196190] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:16,055 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:16,055 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 64 [2023-11-06 22:51:16,055 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1816428201] [2023-11-06 22:51:16,055 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:16,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:16,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2023-11-06 22:51:16,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=971, Invalid=3189, Unknown=0, NotChecked=0, Total=4160 [2023-11-06 22:51:16,103 INFO L87 Difference]: Start difference. First operand 164 states and 186 transitions. cyclomatic complexity: 25 Second operand has 65 states, 64 states have (on average 2.59375) internal successors, (166), 65 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:17,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:17,305 INFO L93 Difference]: Finished difference Result 531 states and 614 transitions. [2023-11-06 22:51:17,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 531 states and 614 transitions. [2023-11-06 22:51:17,309 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:17,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 531 states to 298 states and 342 transitions. [2023-11-06 22:51:17,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2023-11-06 22:51:17,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2023-11-06 22:51:17,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 342 transitions. [2023-11-06 22:51:17,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:17,313 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 342 transitions. [2023-11-06 22:51:17,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 342 transitions. [2023-11-06 22:51:17,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 172. [2023-11-06 22:51:17,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 172 states have (on average 1.1337209302325582) internal successors, (195), 171 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:17,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 195 transitions. [2023-11-06 22:51:17,317 INFO L240 hiAutomatonCegarLoop]: Abstraction has 172 states and 195 transitions. [2023-11-06 22:51:17,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2023-11-06 22:51:17,321 INFO L428 stractBuchiCegarLoop]: Abstraction has 172 states and 195 transitions. [2023-11-06 22:51:17,321 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:51:17,321 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 172 states and 195 transitions. [2023-11-06 22:51:17,322 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:17,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:17,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:17,323 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 20, 19, 19, 1, 1, 1, 1] [2023-11-06 22:51:17,323 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:17,324 INFO L748 eck$LassoCheckResult]: Stem: 15025#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 15009#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 15010#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15026#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15027#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15013#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15014#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15064#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15063#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15061#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15060#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15059#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15058#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15055#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15054#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15053#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15052#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15051#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15050#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15049#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15048#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15047#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15046#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15045#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15044#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15043#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15042#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15041#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15040#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15039#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15038#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15037#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15036#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15035#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 15032#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 15031#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 15015#L27-4 main_~i~0#1 := 0; 15016#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15022#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15008#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15019#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15024#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15171#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15170#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15168#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15165#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15164#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15162#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15159#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15158#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15156#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15153#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15152#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15150#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15147#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15146#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15144#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15141#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15140#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15138#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15135#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15134#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15132#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15129#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15128#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15126#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15123#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15122#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15120#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15117#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15116#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15114#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15111#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15110#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15108#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15105#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15104#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15102#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15099#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15098#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15096#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15093#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15092#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15090#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15087#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15086#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15084#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15081#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15080#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15078#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15072#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15070#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15030#L34 [2023-11-06 22:51:17,324 INFO L750 eck$LassoCheckResult]: Loop: 15030#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 15033#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 15029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 15030#L34 [2023-11-06 22:51:17,324 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:17,324 INFO L85 PathProgramCache]: Analyzing trace with hash 297074321, now seen corresponding path program 38 times [2023-11-06 22:51:17,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:17,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972661430] [2023-11-06 22:51:17,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:17,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:17,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:17,460 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:17,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:17,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:17,602 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:17,602 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 21 times [2023-11-06 22:51:17,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:17,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [575646726] [2023-11-06 22:51:17,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:17,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:17,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:17,607 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:17,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:17,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:17,612 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:17,612 INFO L85 PathProgramCache]: Analyzing trace with hash -1786453435, now seen corresponding path program 39 times [2023-11-06 22:51:17,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:17,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801164086] [2023-11-06 22:51:17,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:17,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:17,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:19,304 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 532 proven. 458 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:19,304 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:19,304 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801164086] [2023-11-06 22:51:19,304 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [801164086] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:19,305 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2035303944] [2023-11-06 22:51:19,305 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:51:19,305 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:19,305 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:19,312 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:19,317 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2023-11-06 22:51:21,034 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2023-11-06 22:51:21,034 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:21,040 INFO L262 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjunts are in the unsatisfiable core [2023-11-06 22:51:21,042 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:22,098 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:22,098 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:22,923 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 590 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:22,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2035303944] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:22,924 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:22,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 67 [2023-11-06 22:51:22,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696399766] [2023-11-06 22:51:22,924 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:22,987 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:22,988 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2023-11-06 22:51:22,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1061, Invalid=3495, Unknown=0, NotChecked=0, Total=4556 [2023-11-06 22:51:22,990 INFO L87 Difference]: Start difference. First operand 172 states and 195 transitions. cyclomatic complexity: 26 Second operand has 68 states, 67 states have (on average 2.5970149253731343) internal successors, (174), 68 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:24,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:24,261 INFO L93 Difference]: Finished difference Result 557 states and 644 transitions. [2023-11-06 22:51:24,261 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 644 transitions. [2023-11-06 22:51:24,264 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:24,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 312 states and 358 transitions. [2023-11-06 22:51:24,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2023-11-06 22:51:24,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2023-11-06 22:51:24,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 312 states and 358 transitions. [2023-11-06 22:51:24,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:24,268 INFO L218 hiAutomatonCegarLoop]: Abstraction has 312 states and 358 transitions. [2023-11-06 22:51:24,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states and 358 transitions. [2023-11-06 22:51:24,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 180. [2023-11-06 22:51:24,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 180 states, 180 states have (on average 1.1333333333333333) internal successors, (204), 179 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:24,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 204 transitions. [2023-11-06 22:51:24,272 INFO L240 hiAutomatonCegarLoop]: Abstraction has 180 states and 204 transitions. [2023-11-06 22:51:24,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2023-11-06 22:51:24,274 INFO L428 stractBuchiCegarLoop]: Abstraction has 180 states and 204 transitions. [2023-11-06 22:51:24,274 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:51:24,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 180 states and 204 transitions. [2023-11-06 22:51:24,275 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:24,276 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:24,276 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:24,277 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 21, 20, 20, 1, 1, 1, 1] [2023-11-06 22:51:24,277 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:24,277 INFO L748 eck$LassoCheckResult]: Stem: 16493#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 16477#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 16478#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16494#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16495#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16481#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16482#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16538#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16537#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16536#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16535#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16534#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16533#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16532#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16531#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16530#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16529#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16528#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16527#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16526#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16525#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16524#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16523#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16522#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16521#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16520#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16519#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16518#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16517#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16516#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16515#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16514#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16513#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16512#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16511#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16510#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16509#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16508#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16507#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16506#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16505#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16504#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16503#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 16500#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16499#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 16483#L27-4 main_~i~0#1 := 0; 16484#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16490#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16476#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16487#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16492#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16647#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16646#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16644#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16641#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16640#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16638#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16635#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16634#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16632#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16629#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16628#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16626#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16623#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16622#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16620#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16617#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16616#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16614#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16611#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16610#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16608#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16605#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16604#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16602#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16599#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16598#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16596#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16593#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16592#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16590#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16587#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16586#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16584#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16581#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16580#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16578#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16575#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16574#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16572#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16569#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16568#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16566#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16563#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16562#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16560#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16557#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16556#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16554#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16551#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16550#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16548#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16546#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16545#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16542#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16540#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16539#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16498#L34 [2023-11-06 22:51:24,277 INFO L750 eck$LassoCheckResult]: Loop: 16498#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 16501#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 16497#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 16498#L34 [2023-11-06 22:51:24,278 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:24,278 INFO L85 PathProgramCache]: Analyzing trace with hash -1988450429, now seen corresponding path program 40 times [2023-11-06 22:51:24,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:24,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927345886] [2023-11-06 22:51:24,278 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:24,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:24,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:24,404 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:24,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:24,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:24,568 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:24,569 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 22 times [2023-11-06 22:51:24,569 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:24,569 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884126120] [2023-11-06 22:51:24,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:24,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:24,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:24,573 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:24,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:24,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:24,578 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:24,579 INFO L85 PathProgramCache]: Analyzing trace with hash -1737737197, now seen corresponding path program 41 times [2023-11-06 22:51:24,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:24,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900320021] [2023-11-06 22:51:24,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:24,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:24,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:26,218 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 590 proven. 502 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:26,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:26,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [900320021] [2023-11-06 22:51:26,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [900320021] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:26,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [164924331] [2023-11-06 22:51:26,219 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:51:26,220 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:26,220 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:26,223 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:26,226 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2023-11-06 22:51:27,346 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2023-11-06 22:51:27,346 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:27,352 INFO L262 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjunts are in the unsatisfiable core [2023-11-06 22:51:27,355 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:28,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:28,466 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:29,356 INFO L134 CoverageAnalysis]: Checked inductivity of 1092 backedges. 651 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:29,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [164924331] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:29,357 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:29,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 70 [2023-11-06 22:51:29,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [801896745] [2023-11-06 22:51:29,357 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:29,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:29,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2023-11-06 22:51:29,405 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1155, Invalid=3815, Unknown=0, NotChecked=0, Total=4970 [2023-11-06 22:51:29,405 INFO L87 Difference]: Start difference. First operand 180 states and 204 transitions. cyclomatic complexity: 27 Second operand has 71 states, 70 states have (on average 2.6) internal successors, (182), 71 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:30,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:30,647 INFO L93 Difference]: Finished difference Result 583 states and 674 transitions. [2023-11-06 22:51:30,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 583 states and 674 transitions. [2023-11-06 22:51:30,650 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:30,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 583 states to 326 states and 374 transitions. [2023-11-06 22:51:30,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281 [2023-11-06 22:51:30,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281 [2023-11-06 22:51:30,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 374 transitions. [2023-11-06 22:51:30,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:30,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 374 transitions. [2023-11-06 22:51:30,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 374 transitions. [2023-11-06 22:51:30,656 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 188. [2023-11-06 22:51:30,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 188 states have (on average 1.1329787234042554) internal successors, (213), 187 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:30,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 213 transitions. [2023-11-06 22:51:30,658 INFO L240 hiAutomatonCegarLoop]: Abstraction has 188 states and 213 transitions. [2023-11-06 22:51:30,660 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-06 22:51:30,660 INFO L428 stractBuchiCegarLoop]: Abstraction has 188 states and 213 transitions. [2023-11-06 22:51:30,660 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:51:30,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188 states and 213 transitions. [2023-11-06 22:51:30,661 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:30,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:30,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:30,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 22, 21, 21, 1, 1, 1, 1] [2023-11-06 22:51:30,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:30,663 INFO L748 eck$LassoCheckResult]: Stem: 18032#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 18014#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 18015#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18030#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18031#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18018#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18019#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18077#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18076#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18075#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18074#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18073#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18072#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18071#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18070#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18069#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18068#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18067#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18066#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18065#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18064#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18063#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18062#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18061#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18060#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18059#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18058#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18057#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18056#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18055#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18054#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18053#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18052#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18051#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18050#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18049#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18048#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18047#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18046#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18045#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18043#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18042#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18041#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18040#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 18037#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 18036#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 18020#L27-4 main_~i~0#1 := 0; 18021#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18027#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18013#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18024#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18029#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18192#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18191#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18189#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18186#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18185#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18183#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18180#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18179#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18177#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18174#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18173#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18171#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18168#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18167#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18165#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18162#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18161#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18159#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18156#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18155#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18153#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18150#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18149#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18147#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18144#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18143#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18141#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18138#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18137#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18135#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18132#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18131#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18129#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18126#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18125#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18123#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18120#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18119#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18117#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18114#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18113#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18111#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18108#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18107#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18105#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18102#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18101#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18099#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18096#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18095#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18093#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18090#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18089#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18087#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18085#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18084#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18081#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18079#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18078#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18035#L34 [2023-11-06 22:51:30,664 INFO L750 eck$LassoCheckResult]: Loop: 18035#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 18038#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 18034#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 18035#L34 [2023-11-06 22:51:30,664 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:30,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1779830165, now seen corresponding path program 42 times [2023-11-06 22:51:30,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:30,664 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289033629] [2023-11-06 22:51:30,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:30,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:30,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:30,825 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:30,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:31,007 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:31,008 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:31,008 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 23 times [2023-11-06 22:51:31,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:31,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2125087133] [2023-11-06 22:51:31,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:31,009 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:31,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:31,013 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:31,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:31,017 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:31,018 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:31,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1549223105, now seen corresponding path program 43 times [2023-11-06 22:51:31,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:31,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561632670] [2023-11-06 22:51:31,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:31,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:31,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:32,966 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 651 proven. 548 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:32,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:32,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [561632670] [2023-11-06 22:51:32,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [561632670] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:32,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1082010449] [2023-11-06 22:51:32,966 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:51:32,966 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:32,966 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:32,967 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:32,970 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2023-11-06 22:51:33,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:33,245 INFO L262 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-06 22:51:33,248 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:34,509 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:34,509 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:35,471 INFO L134 CoverageAnalysis]: Checked inductivity of 1199 backedges. 715 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:35,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1082010449] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:35,471 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:35,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 73 [2023-11-06 22:51:35,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368632444] [2023-11-06 22:51:35,472 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:35,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:35,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2023-11-06 22:51:35,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1253, Invalid=4149, Unknown=0, NotChecked=0, Total=5402 [2023-11-06 22:51:35,529 INFO L87 Difference]: Start difference. First operand 188 states and 213 transitions. cyclomatic complexity: 28 Second operand has 74 states, 73 states have (on average 2.6027397260273974) internal successors, (190), 74 states have internal predecessors, (190), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:36,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:36,907 INFO L93 Difference]: Finished difference Result 609 states and 704 transitions. [2023-11-06 22:51:36,907 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 609 states and 704 transitions. [2023-11-06 22:51:36,911 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:36,913 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 609 states to 340 states and 390 transitions. [2023-11-06 22:51:36,913 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 293 [2023-11-06 22:51:36,914 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 293 [2023-11-06 22:51:36,914 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 390 transitions. [2023-11-06 22:51:36,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:36,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 390 transitions. [2023-11-06 22:51:36,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 390 transitions. [2023-11-06 22:51:36,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 196. [2023-11-06 22:51:36,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 196 states, 196 states have (on average 1.1326530612244898) internal successors, (222), 195 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:36,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 196 states to 196 states and 222 transitions. [2023-11-06 22:51:36,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 196 states and 222 transitions. [2023-11-06 22:51:36,920 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2023-11-06 22:51:36,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 196 states and 222 transitions. [2023-11-06 22:51:36,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-06 22:51:36,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 196 states and 222 transitions. [2023-11-06 22:51:36,922 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:36,922 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:36,922 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:36,923 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 23, 22, 22, 1, 1, 1, 1] [2023-11-06 22:51:36,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:36,924 INFO L748 eck$LassoCheckResult]: Stem: 19636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 19620#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 19621#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19637#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19638#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19624#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19625#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19685#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19684#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19683#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19682#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19681#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19680#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19679#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19678#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19677#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19676#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19675#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19674#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19673#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19672#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19671#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19670#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19669#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19668#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19667#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19666#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19665#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19664#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19663#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19662#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19661#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19660#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19659#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19658#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19657#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19656#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19655#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19654#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19653#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19652#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19651#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19650#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19649#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19648#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19647#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19646#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 19643#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 19642#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 19626#L27-4 main_~i~0#1 := 0; 19627#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19633#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19619#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19630#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19635#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19806#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19805#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19803#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19800#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19799#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19797#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19794#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19793#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19791#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19788#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19787#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19785#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19782#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19781#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19779#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19776#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19775#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19773#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19770#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19769#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19767#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19764#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19763#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19761#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19757#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19752#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19751#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19746#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19745#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19743#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19740#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19739#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19737#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19734#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19733#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19731#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19728#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19727#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19725#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19722#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19721#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19719#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19716#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19713#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19710#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19709#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19707#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19703#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19701#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19698#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19697#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19695#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19693#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19689#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19687#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19641#L34 [2023-11-06 22:51:36,924 INFO L750 eck$LassoCheckResult]: Loop: 19641#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 19644#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 19640#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 19641#L34 [2023-11-06 22:51:36,924 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:36,924 INFO L85 PathProgramCache]: Analyzing trace with hash -1359080321, now seen corresponding path program 44 times [2023-11-06 22:51:36,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:36,925 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613711847] [2023-11-06 22:51:36,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:36,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:37,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:37,092 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:37,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:37,244 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:37,244 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:37,244 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 24 times [2023-11-06 22:51:37,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:37,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704105935] [2023-11-06 22:51:37,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:37,245 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:37,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:37,249 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:37,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:37,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:37,254 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:37,254 INFO L85 PathProgramCache]: Analyzing trace with hash 294903191, now seen corresponding path program 45 times [2023-11-06 22:51:37,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:37,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043464881] [2023-11-06 22:51:37,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:37,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:37,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:39,180 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 715 proven. 596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:39,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:39,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043464881] [2023-11-06 22:51:39,181 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043464881] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:39,181 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1787293523] [2023-11-06 22:51:39,181 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:51:39,181 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:39,181 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:39,188 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:39,192 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2023-11-06 22:51:41,094 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2023-11-06 22:51:41,094 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:41,102 INFO L262 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjunts are in the unsatisfiable core [2023-11-06 22:51:41,104 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:42,495 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:42,495 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:43,592 INFO L134 CoverageAnalysis]: Checked inductivity of 1311 backedges. 782 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:43,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1787293523] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:43,593 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:43,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 76 [2023-11-06 22:51:43,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [883491544] [2023-11-06 22:51:43,593 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:43,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:43,641 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2023-11-06 22:51:43,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1355, Invalid=4497, Unknown=0, NotChecked=0, Total=5852 [2023-11-06 22:51:43,644 INFO L87 Difference]: Start difference. First operand 196 states and 222 transitions. cyclomatic complexity: 29 Second operand has 77 states, 76 states have (on average 2.6052631578947367) internal successors, (198), 77 states have internal predecessors, (198), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:45,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:45,028 INFO L93 Difference]: Finished difference Result 635 states and 734 transitions. [2023-11-06 22:51:45,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 635 states and 734 transitions. [2023-11-06 22:51:45,032 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:45,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 635 states to 354 states and 406 transitions. [2023-11-06 22:51:45,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 305 [2023-11-06 22:51:45,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 305 [2023-11-06 22:51:45,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 354 states and 406 transitions. [2023-11-06 22:51:45,036 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:45,036 INFO L218 hiAutomatonCegarLoop]: Abstraction has 354 states and 406 transitions. [2023-11-06 22:51:45,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 354 states and 406 transitions. [2023-11-06 22:51:45,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 354 to 204. [2023-11-06 22:51:45,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 204 states, 204 states have (on average 1.1323529411764706) internal successors, (231), 203 states have internal predecessors, (231), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:45,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 231 transitions. [2023-11-06 22:51:45,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 204 states and 231 transitions. [2023-11-06 22:51:45,042 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2023-11-06 22:51:45,043 INFO L428 stractBuchiCegarLoop]: Abstraction has 204 states and 231 transitions. [2023-11-06 22:51:45,043 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-06 22:51:45,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 231 transitions. [2023-11-06 22:51:45,044 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:45,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:45,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:45,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 24, 23, 23, 1, 1, 1, 1] [2023-11-06 22:51:45,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:45,046 INFO L748 eck$LassoCheckResult]: Stem: 21311#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 21295#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 21296#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21312#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21313#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21299#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21300#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21362#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21361#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21360#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21359#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21358#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21357#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21356#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21355#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21354#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21353#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21352#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21351#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21350#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21349#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21348#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21347#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21346#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21345#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21344#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21343#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21342#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21341#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21340#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21339#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21338#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21337#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21336#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21335#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21334#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21333#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21332#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21331#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21330#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21329#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21328#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21327#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21326#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21325#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21324#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21323#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21322#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21321#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 21318#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 21317#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 21301#L27-4 main_~i~0#1 := 0; 21302#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21308#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21294#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21305#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21310#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21489#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21488#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21486#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21483#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21480#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21477#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21476#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21474#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21471#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21470#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21468#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21465#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21464#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21462#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21459#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21458#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21456#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21453#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21452#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21450#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21447#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21446#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21444#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21441#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21440#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21438#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21435#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21434#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21432#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21429#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21428#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21426#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21423#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21422#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21420#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21417#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21416#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21414#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21411#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21410#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21408#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21405#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21404#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21402#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21399#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21398#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21396#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21393#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21392#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21390#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21387#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21386#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21384#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21381#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21380#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21378#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21375#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21374#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21372#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21370#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21369#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21366#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21364#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21363#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21316#L34 [2023-11-06 22:51:45,046 INFO L750 eck$LassoCheckResult]: Loop: 21316#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 21319#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 21315#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 21316#L34 [2023-11-06 22:51:45,046 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:45,047 INFO L85 PathProgramCache]: Analyzing trace with hash -166775655, now seen corresponding path program 46 times [2023-11-06 22:51:45,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:45,047 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829170093] [2023-11-06 22:51:45,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:45,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:45,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:45,221 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:45,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:45,401 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:45,402 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:45,402 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 25 times [2023-11-06 22:51:45,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:45,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [247333223] [2023-11-06 22:51:45,402 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:45,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:45,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:45,407 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:45,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:45,424 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:45,424 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:45,425 INFO L85 PathProgramCache]: Analyzing trace with hash 863670077, now seen corresponding path program 47 times [2023-11-06 22:51:45,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:45,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2106492400] [2023-11-06 22:51:45,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:45,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:45,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:47,602 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 782 proven. 646 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:47,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:47,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2106492400] [2023-11-06 22:51:47,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2106492400] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:47,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1549181056] [2023-11-06 22:51:47,604 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:51:47,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:47,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:47,607 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:47,611 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2023-11-06 22:51:49,542 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2023-11-06 22:51:49,542 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:51:49,548 INFO L262 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjunts are in the unsatisfiable core [2023-11-06 22:51:49,551 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:50,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:50,994 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:52,082 INFO L134 CoverageAnalysis]: Checked inductivity of 1428 backedges. 852 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:52,083 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1549181056] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:52,083 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:52,083 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 79 [2023-11-06 22:51:52,083 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721311692] [2023-11-06 22:51:52,083 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:52,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:52,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2023-11-06 22:51:52,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1461, Invalid=4859, Unknown=0, NotChecked=0, Total=6320 [2023-11-06 22:51:52,138 INFO L87 Difference]: Start difference. First operand 204 states and 231 transitions. cyclomatic complexity: 30 Second operand has 80 states, 79 states have (on average 2.607594936708861) internal successors, (206), 80 states have internal predecessors, (206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:53,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:51:53,613 INFO L93 Difference]: Finished difference Result 661 states and 764 transitions. [2023-11-06 22:51:53,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 661 states and 764 transitions. [2023-11-06 22:51:53,616 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:53,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 661 states to 368 states and 422 transitions. [2023-11-06 22:51:53,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 317 [2023-11-06 22:51:53,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 317 [2023-11-06 22:51:53,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 368 states and 422 transitions. [2023-11-06 22:51:53,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:51:53,619 INFO L218 hiAutomatonCegarLoop]: Abstraction has 368 states and 422 transitions. [2023-11-06 22:51:53,620 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 368 states and 422 transitions. [2023-11-06 22:51:53,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 368 to 212. [2023-11-06 22:51:53,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212 states, 212 states have (on average 1.1320754716981132) internal successors, (240), 211 states have internal predecessors, (240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:51:53,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 240 transitions. [2023-11-06 22:51:53,625 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212 states and 240 transitions. [2023-11-06 22:51:53,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2023-11-06 22:51:53,628 INFO L428 stractBuchiCegarLoop]: Abstraction has 212 states and 240 transitions. [2023-11-06 22:51:53,628 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-06 22:51:53,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212 states and 240 transitions. [2023-11-06 22:51:53,629 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:51:53,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:51:53,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:51:53,631 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 25, 24, 24, 1, 1, 1, 1] [2023-11-06 22:51:53,631 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:51:53,631 INFO L748 eck$LassoCheckResult]: Stem: 23055#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 23039#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 23040#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23056#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23057#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23043#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23044#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23108#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23107#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23106#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23105#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23104#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23103#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23102#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23101#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23100#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23099#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23098#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23097#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23096#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23095#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23094#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23093#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23092#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23091#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23090#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23089#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23088#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23087#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23086#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23085#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23084#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23083#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23082#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23081#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23080#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23079#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23078#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23077#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23076#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23075#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23074#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23073#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23072#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23071#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23070#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23069#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23068#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23067#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23066#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23065#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 23062#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 23061#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 23045#L27-4 main_~i~0#1 := 0; 23046#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23052#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23038#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23049#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23054#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23241#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23240#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23238#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23235#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23234#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23232#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23229#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23228#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23226#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23223#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23222#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23220#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23217#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23216#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23214#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23211#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23210#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23208#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23205#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23204#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23202#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23199#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23198#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23196#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23193#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23192#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23190#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23187#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23186#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23184#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23181#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23180#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23178#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23175#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23174#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23172#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23169#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23168#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23166#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23163#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23162#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23160#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23157#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23156#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23154#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23151#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23150#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23148#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23145#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23144#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23142#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23139#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23138#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23136#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23133#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23132#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23130#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23127#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23126#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23124#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23121#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23120#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23118#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23116#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23115#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23112#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23110#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23109#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23060#L34 [2023-11-06 22:51:53,632 INFO L750 eck$LassoCheckResult]: Loop: 23060#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 23063#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 23059#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 23060#L34 [2023-11-06 22:51:53,632 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:53,632 INFO L85 PathProgramCache]: Analyzing trace with hash 1558661499, now seen corresponding path program 48 times [2023-11-06 22:51:53,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:53,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910426108] [2023-11-06 22:51:53,632 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:53,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:53,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:53,821 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:53,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:54,022 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:54,022 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:54,022 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 26 times [2023-11-06 22:51:54,022 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:54,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750044238] [2023-11-06 22:51:54,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:54,023 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:54,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:54,027 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:51:54,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:51:54,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:51:54,032 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:51:54,032 INFO L85 PathProgramCache]: Analyzing trace with hash 1193326363, now seen corresponding path program 49 times [2023-11-06 22:51:54,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:51:54,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087192256] [2023-11-06 22:51:54,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:51:54,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:51:54,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:56,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 852 proven. 698 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:56,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:51:56,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087192256] [2023-11-06 22:51:56,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087192256] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:51:56,100 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1455602666] [2023-11-06 22:51:56,100 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:51:56,101 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:51:56,101 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:51:56,103 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:51:56,104 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2023-11-06 22:51:56,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:51:56,409 INFO L262 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjunts are in the unsatisfiable core [2023-11-06 22:51:56,411 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:51:57,927 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:57,928 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:51:59,067 INFO L134 CoverageAnalysis]: Checked inductivity of 1550 backedges. 925 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:51:59,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1455602666] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:51:59,067 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:51:59,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 82 [2023-11-06 22:51:59,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66298674] [2023-11-06 22:51:59,067 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:51:59,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:51:59,114 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2023-11-06 22:51:59,116 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1571, Invalid=5235, Unknown=0, NotChecked=0, Total=6806 [2023-11-06 22:51:59,117 INFO L87 Difference]: Start difference. First operand 212 states and 240 transitions. cyclomatic complexity: 31 Second operand has 83 states, 82 states have (on average 2.6097560975609757) internal successors, (214), 83 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:00,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:52:00,781 INFO L93 Difference]: Finished difference Result 687 states and 794 transitions. [2023-11-06 22:52:00,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 687 states and 794 transitions. [2023-11-06 22:52:00,784 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:00,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 687 states to 382 states and 438 transitions. [2023-11-06 22:52:00,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2023-11-06 22:52:00,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2023-11-06 22:52:00,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 382 states and 438 transitions. [2023-11-06 22:52:00,787 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:52:00,788 INFO L218 hiAutomatonCegarLoop]: Abstraction has 382 states and 438 transitions. [2023-11-06 22:52:00,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 382 states and 438 transitions. [2023-11-06 22:52:00,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 382 to 220. [2023-11-06 22:52:00,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 220 states, 220 states have (on average 1.1318181818181818) internal successors, (249), 219 states have internal predecessors, (249), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:00,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 249 transitions. [2023-11-06 22:52:00,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 220 states and 249 transitions. [2023-11-06 22:52:00,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2023-11-06 22:52:00,796 INFO L428 stractBuchiCegarLoop]: Abstraction has 220 states and 249 transitions. [2023-11-06 22:52:00,796 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-06 22:52:00,796 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 220 states and 249 transitions. [2023-11-06 22:52:00,797 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:00,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:52:00,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:52:00,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 26, 25, 25, 1, 1, 1, 1] [2023-11-06 22:52:00,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:52:00,799 INFO L748 eck$LassoCheckResult]: Stem: 24868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 24852#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 24853#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24869#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24870#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24856#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24857#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24923#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24922#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24921#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24920#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24919#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24918#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24917#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24916#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24915#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24914#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24913#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24912#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24911#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24910#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24909#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24908#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24907#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24906#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24905#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24904#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24903#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24902#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24901#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24900#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24899#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24898#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24897#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24896#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24895#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24894#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24893#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24892#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24891#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24890#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24889#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24888#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24887#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24886#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24885#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24884#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24883#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24882#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24881#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24880#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24879#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24878#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 24875#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 24874#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 24858#L27-4 main_~i~0#1 := 0; 24859#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24865#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24851#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24862#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24867#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25062#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25061#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25059#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25056#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25055#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25053#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25050#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25049#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25047#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25044#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25043#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25041#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25038#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25037#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25035#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25032#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25031#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25029#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25026#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25025#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25023#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25020#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25019#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25017#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25014#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25013#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25011#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25008#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25007#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 25005#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 25002#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 25001#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24999#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24996#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24995#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24993#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24990#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24989#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24987#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24984#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24983#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24981#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24978#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24977#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24975#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24972#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24971#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24969#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24966#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24965#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24963#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24960#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24959#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24957#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24954#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24953#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24951#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24948#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24947#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24945#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24942#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24941#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24939#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24936#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24935#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24933#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24931#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24930#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24927#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24925#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24924#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24873#L34 [2023-11-06 22:52:00,799 INFO L750 eck$LassoCheckResult]: Loop: 24873#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 24876#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 24872#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 24873#L34 [2023-11-06 22:52:00,799 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:00,800 INFO L85 PathProgramCache]: Analyzing trace with hash -261835875, now seen corresponding path program 50 times [2023-11-06 22:52:00,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:00,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [735498808] [2023-11-06 22:52:00,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:00,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:00,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:00,992 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:01,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:01,196 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:01,197 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:01,197 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 27 times [2023-11-06 22:52:01,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:01,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12121349] [2023-11-06 22:52:01,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:01,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:01,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:01,202 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:01,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:01,206 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:01,207 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:01,207 INFO L85 PathProgramCache]: Analyzing trace with hash -691895879, now seen corresponding path program 51 times [2023-11-06 22:52:01,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:01,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3901882] [2023-11-06 22:52:01,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:01,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:01,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:03,597 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 925 proven. 752 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:03,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:52:03,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3901882] [2023-11-06 22:52:03,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3901882] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:52:03,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [771676356] [2023-11-06 22:52:03,597 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:52:03,597 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:52:03,597 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:52:03,599 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:52:03,601 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2023-11-06 22:52:05,807 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2023-11-06 22:52:05,807 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:52:05,813 INFO L262 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjunts are in the unsatisfiable core [2023-11-06 22:52:05,816 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:52:07,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:07,447 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:52:08,706 INFO L134 CoverageAnalysis]: Checked inductivity of 1677 backedges. 1001 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:08,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [771676356] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:52:08,707 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:52:08,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56] total 85 [2023-11-06 22:52:08,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2084345054] [2023-11-06 22:52:08,707 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:52:08,766 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:52:08,767 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2023-11-06 22:52:08,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1685, Invalid=5625, Unknown=0, NotChecked=0, Total=7310 [2023-11-06 22:52:08,769 INFO L87 Difference]: Start difference. First operand 220 states and 249 transitions. cyclomatic complexity: 32 Second operand has 86 states, 85 states have (on average 2.611764705882353) internal successors, (222), 86 states have internal predecessors, (222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:10,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:52:10,564 INFO L93 Difference]: Finished difference Result 713 states and 824 transitions. [2023-11-06 22:52:10,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 713 states and 824 transitions. [2023-11-06 22:52:10,567 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:10,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 713 states to 396 states and 454 transitions. [2023-11-06 22:52:10,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2023-11-06 22:52:10,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2023-11-06 22:52:10,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 396 states and 454 transitions. [2023-11-06 22:52:10,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:52:10,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 396 states and 454 transitions. [2023-11-06 22:52:10,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 396 states and 454 transitions. [2023-11-06 22:52:10,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 396 to 228. [2023-11-06 22:52:10,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228 states, 228 states have (on average 1.131578947368421) internal successors, (258), 227 states have internal predecessors, (258), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:10,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 258 transitions. [2023-11-06 22:52:10,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228 states and 258 transitions. [2023-11-06 22:52:10,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2023-11-06 22:52:10,578 INFO L428 stractBuchiCegarLoop]: Abstraction has 228 states and 258 transitions. [2023-11-06 22:52:10,578 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-06 22:52:10,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228 states and 258 transitions. [2023-11-06 22:52:10,579 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:10,580 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:52:10,580 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:52:10,581 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 27, 26, 26, 1, 1, 1, 1] [2023-11-06 22:52:10,581 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:52:10,581 INFO L748 eck$LassoCheckResult]: Stem: 26750#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 26734#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 26735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26751#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26752#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26738#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26739#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26807#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26806#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26805#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26804#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26803#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26802#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26801#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26800#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26799#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26798#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26797#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26796#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26795#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26794#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26793#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26792#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26791#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26790#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26789#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26788#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26787#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26786#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26785#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26784#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26783#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26782#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26781#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26780#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26779#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26778#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26777#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26776#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26775#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26774#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26773#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26772#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26771#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26770#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26769#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26768#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26767#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26766#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26765#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26764#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26763#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26762#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26761#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26760#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 26757#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 26756#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 26740#L27-4 main_~i~0#1 := 0; 26741#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26747#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26733#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26744#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26749#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26952#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26951#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26949#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26946#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26945#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26943#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26940#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26939#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26937#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26934#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26931#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26925#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26922#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26921#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26919#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26916#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26915#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26913#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26910#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26907#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26904#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26903#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26901#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26898#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26895#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26892#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26889#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26883#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26880#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26879#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26877#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26874#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26873#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26871#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26868#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26867#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26865#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26862#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26861#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26859#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26856#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26855#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26853#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26850#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26849#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26847#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26844#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26843#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26841#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26838#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26837#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26835#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26832#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26831#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26829#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26826#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26825#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26823#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26820#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26819#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26817#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26815#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26814#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26811#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26809#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26808#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26755#L34 [2023-11-06 22:52:10,582 INFO L750 eck$LassoCheckResult]: Loop: 26755#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 26758#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 26754#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 26755#L34 [2023-11-06 22:52:10,582 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:10,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1651639927, now seen corresponding path program 52 times [2023-11-06 22:52:10,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:10,582 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446303970] [2023-11-06 22:52:10,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:10,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:10,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:10,750 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:10,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:10,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:10,969 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:10,969 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 28 times [2023-11-06 22:52:10,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:10,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757027418] [2023-11-06 22:52:10,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:10,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:10,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:10,974 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:10,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:10,979 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:10,980 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:10,980 INFO L85 PathProgramCache]: Analyzing trace with hash 859768991, now seen corresponding path program 53 times [2023-11-06 22:52:10,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:10,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959182992] [2023-11-06 22:52:10,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:10,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:11,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:13,186 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1001 proven. 808 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:13,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:52:13,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959182992] [2023-11-06 22:52:13,187 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959182992] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:52:13,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [302296625] [2023-11-06 22:52:13,187 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:52:13,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:52:13,187 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:52:13,189 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:52:13,191 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2023-11-06 22:52:18,939 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2023-11-06 22:52:18,939 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:52:18,948 INFO L262 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 58 conjunts are in the unsatisfiable core [2023-11-06 22:52:18,950 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:52:20,776 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:20,776 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:52:22,080 INFO L134 CoverageAnalysis]: Checked inductivity of 1809 backedges. 1080 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:22,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [302296625] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:52:22,081 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:52:22,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58] total 88 [2023-11-06 22:52:22,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [469430804] [2023-11-06 22:52:22,081 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:52:22,126 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:52:22,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2023-11-06 22:52:22,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1803, Invalid=6029, Unknown=0, NotChecked=0, Total=7832 [2023-11-06 22:52:22,129 INFO L87 Difference]: Start difference. First operand 228 states and 258 transitions. cyclomatic complexity: 33 Second operand has 89 states, 88 states have (on average 2.6136363636363638) internal successors, (230), 89 states have internal predecessors, (230), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:24,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:52:24,009 INFO L93 Difference]: Finished difference Result 739 states and 854 transitions. [2023-11-06 22:52:24,010 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 739 states and 854 transitions. [2023-11-06 22:52:24,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:24,014 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 739 states to 410 states and 470 transitions. [2023-11-06 22:52:24,014 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 353 [2023-11-06 22:52:24,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 353 [2023-11-06 22:52:24,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 410 states and 470 transitions. [2023-11-06 22:52:24,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:52:24,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 410 states and 470 transitions. [2023-11-06 22:52:24,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states and 470 transitions. [2023-11-06 22:52:24,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 236. [2023-11-06 22:52:24,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 236 states, 236 states have (on average 1.13135593220339) internal successors, (267), 235 states have internal predecessors, (267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:24,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 267 transitions. [2023-11-06 22:52:24,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 236 states and 267 transitions. [2023-11-06 22:52:24,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2023-11-06 22:52:24,027 INFO L428 stractBuchiCegarLoop]: Abstraction has 236 states and 267 transitions. [2023-11-06 22:52:24,027 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-06 22:52:24,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236 states and 267 transitions. [2023-11-06 22:52:24,028 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:24,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:52:24,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:52:24,030 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 28, 27, 27, 1, 1, 1, 1] [2023-11-06 22:52:24,030 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:52:24,030 INFO L748 eck$LassoCheckResult]: Stem: 28701#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 28685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 28686#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28702#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28703#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28689#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28690#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28752#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28750#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28749#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28748#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28746#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28745#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28744#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28743#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28742#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28741#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28740#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28739#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28738#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28737#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28736#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28730#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28729#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28728#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28727#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28726#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28725#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28724#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28723#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28722#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28721#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28720#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28719#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28718#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28717#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28716#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28715#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28714#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28713#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28712#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28711#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 28708#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 28707#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 28691#L27-4 main_~i~0#1 := 0; 28692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28698#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28684#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28695#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28700#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28911#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28910#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28908#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28905#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28904#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28902#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28899#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28898#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28896#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28893#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28892#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28890#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28887#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28886#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28884#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28881#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28880#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28878#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28875#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28872#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28869#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28868#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28866#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28863#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28862#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28860#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28857#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28856#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28854#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28851#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28850#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28848#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28845#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28844#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28842#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28839#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28838#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28836#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28833#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28832#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28830#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28827#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28826#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28824#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28821#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28820#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28818#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28815#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28814#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28812#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28809#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28808#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28806#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28803#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28802#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28800#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28797#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28796#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28794#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28791#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28790#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28788#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28785#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28784#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28782#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28779#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28778#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28776#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28773#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28772#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28770#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28768#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28767#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28764#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28762#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28761#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28706#L34 [2023-11-06 22:52:24,030 INFO L750 eck$LassoCheckResult]: Loop: 28706#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 28709#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 28705#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 28706#L34 [2023-11-06 22:52:24,031 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:24,031 INFO L85 PathProgramCache]: Analyzing trace with hash 551209633, now seen corresponding path program 54 times [2023-11-06 22:52:24,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:24,031 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2004845500] [2023-11-06 22:52:24,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:24,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:24,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:24,323 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:24,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:24,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:24,527 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:24,528 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 29 times [2023-11-06 22:52:24,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:24,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267452461] [2023-11-06 22:52:24,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:24,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:24,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:24,534 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:24,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:24,538 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:24,539 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:24,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1426250805, now seen corresponding path program 55 times [2023-11-06 22:52:24,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:24,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833623546] [2023-11-06 22:52:24,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:24,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:24,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:26,914 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1080 proven. 866 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:26,914 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:52:26,914 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833623546] [2023-11-06 22:52:26,914 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833623546] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:52:26,915 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [804660563] [2023-11-06 22:52:26,915 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:52:26,915 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:52:26,915 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:52:26,916 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:52:26,918 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2023-11-06 22:52:27,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:27,286 INFO L262 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjunts are in the unsatisfiable core [2023-11-06 22:52:27,290 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:52:29,227 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:29,228 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:52:30,615 INFO L134 CoverageAnalysis]: Checked inductivity of 1946 backedges. 1162 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:30,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [804660563] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:52:30,615 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:52:30,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60, 60] total 91 [2023-11-06 22:52:30,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999575001] [2023-11-06 22:52:30,616 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:52:30,661 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:52:30,662 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2023-11-06 22:52:30,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1925, Invalid=6447, Unknown=0, NotChecked=0, Total=8372 [2023-11-06 22:52:30,664 INFO L87 Difference]: Start difference. First operand 236 states and 267 transitions. cyclomatic complexity: 34 Second operand has 92 states, 91 states have (on average 2.6153846153846154) internal successors, (238), 92 states have internal predecessors, (238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:32,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:52:32,601 INFO L93 Difference]: Finished difference Result 765 states and 884 transitions. [2023-11-06 22:52:32,601 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 765 states and 884 transitions. [2023-11-06 22:52:32,604 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:32,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 765 states to 424 states and 486 transitions. [2023-11-06 22:52:32,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 365 [2023-11-06 22:52:32,608 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 365 [2023-11-06 22:52:32,608 INFO L73 IsDeterministic]: Start isDeterministic. Operand 424 states and 486 transitions. [2023-11-06 22:52:32,609 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:52:32,609 INFO L218 hiAutomatonCegarLoop]: Abstraction has 424 states and 486 transitions. [2023-11-06 22:52:32,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 424 states and 486 transitions. [2023-11-06 22:52:32,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 424 to 244. [2023-11-06 22:52:32,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 244 states, 244 states have (on average 1.1311475409836065) internal successors, (276), 243 states have internal predecessors, (276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:32,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 276 transitions. [2023-11-06 22:52:32,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 244 states and 276 transitions. [2023-11-06 22:52:32,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2023-11-06 22:52:32,615 INFO L428 stractBuchiCegarLoop]: Abstraction has 244 states and 276 transitions. [2023-11-06 22:52:32,615 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-06 22:52:32,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 244 states and 276 transitions. [2023-11-06 22:52:32,617 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:32,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:52:32,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:52:32,618 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 29, 28, 28, 1, 1, 1, 1] [2023-11-06 22:52:32,619 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:52:32,619 INFO L748 eck$LassoCheckResult]: Stem: 30721#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 30705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 30706#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30722#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30723#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30709#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30710#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30782#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30781#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30780#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30779#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30778#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30777#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30776#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30775#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30774#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30773#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30772#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30771#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30770#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30769#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30768#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30767#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30766#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30765#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30764#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30763#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30762#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30761#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30760#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30759#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30758#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30757#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30756#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30755#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30754#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30753#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30752#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30751#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30750#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30749#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30748#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30747#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30746#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30745#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30744#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30743#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30742#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30741#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30740#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30739#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30738#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30737#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30736#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30735#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30734#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30733#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30732#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30731#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 30728#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 30727#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 30711#L27-4 main_~i~0#1 := 0; 30712#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30718#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30704#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30715#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30939#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30938#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30936#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30933#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30932#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30930#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30927#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30926#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30924#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30921#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30920#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30918#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30915#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30914#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30912#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30909#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30908#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30906#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30903#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30902#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30900#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30897#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30896#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30894#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30891#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30890#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30888#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30885#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30884#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30882#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30879#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30878#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30876#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30873#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30872#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30870#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30867#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30866#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30864#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30861#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30860#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30858#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30855#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30854#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30852#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30849#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30848#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30846#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30843#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30842#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30840#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30837#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30836#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30834#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30831#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30830#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30828#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30825#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30824#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30822#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30819#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30818#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30816#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30813#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30812#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30810#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30807#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30806#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30804#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30801#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30800#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30798#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30795#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30794#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30792#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30790#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30789#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30786#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30784#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30783#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30726#L34 [2023-11-06 22:52:32,619 INFO L750 eck$LassoCheckResult]: Loop: 30726#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 30729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 30725#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 30726#L34 [2023-11-06 22:52:32,620 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:32,620 INFO L85 PathProgramCache]: Analyzing trace with hash -1076229261, now seen corresponding path program 56 times [2023-11-06 22:52:32,620 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:32,620 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1047362533] [2023-11-06 22:52:32,620 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:32,620 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:32,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:32,918 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:33,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:33,114 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:33,114 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:33,114 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 30 times [2023-11-06 22:52:33,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:33,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070264786] [2023-11-06 22:52:33,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:33,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:33,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:33,120 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:33,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:33,126 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:33,126 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:33,126 INFO L85 PathProgramCache]: Analyzing trace with hash -15003101, now seen corresponding path program 57 times [2023-11-06 22:52:33,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:33,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641199173] [2023-11-06 22:52:33,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:33,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:33,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:35,573 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1162 proven. 926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:35,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:52:35,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641199173] [2023-11-06 22:52:35,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641199173] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:52:35,574 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [373348549] [2023-11-06 22:52:35,574 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:52:35,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:52:35,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:52:35,579 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:52:35,581 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2023-11-06 22:52:42,173 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2023-11-06 22:52:42,174 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:52:42,186 INFO L262 TraceCheckSpWp]: Trace formula consists of 650 conjuncts, 62 conjunts are in the unsatisfiable core [2023-11-06 22:52:42,190 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:52:44,280 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:44,280 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:52:45,873 INFO L134 CoverageAnalysis]: Checked inductivity of 2088 backedges. 1247 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:45,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [373348549] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:52:45,876 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:52:45,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62, 62] total 94 [2023-11-06 22:52:45,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241567855] [2023-11-06 22:52:45,877 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:52:45,923 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:52:45,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2023-11-06 22:52:45,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2051, Invalid=6879, Unknown=0, NotChecked=0, Total=8930 [2023-11-06 22:52:45,926 INFO L87 Difference]: Start difference. First operand 244 states and 276 transitions. cyclomatic complexity: 35 Second operand has 95 states, 94 states have (on average 2.617021276595745) internal successors, (246), 95 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:47,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:52:47,911 INFO L93 Difference]: Finished difference Result 791 states and 914 transitions. [2023-11-06 22:52:47,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 791 states and 914 transitions. [2023-11-06 22:52:47,914 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:47,916 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 791 states to 438 states and 502 transitions. [2023-11-06 22:52:47,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2023-11-06 22:52:47,917 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2023-11-06 22:52:47,917 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 502 transitions. [2023-11-06 22:52:47,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:52:47,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438 states and 502 transitions. [2023-11-06 22:52:47,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 502 transitions. [2023-11-06 22:52:47,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 252. [2023-11-06 22:52:47,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 252 states, 252 states have (on average 1.130952380952381) internal successors, (285), 251 states have internal predecessors, (285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:52:47,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 252 states to 252 states and 285 transitions. [2023-11-06 22:52:47,923 INFO L240 hiAutomatonCegarLoop]: Abstraction has 252 states and 285 transitions. [2023-11-06 22:52:47,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2023-11-06 22:52:47,926 INFO L428 stractBuchiCegarLoop]: Abstraction has 252 states and 285 transitions. [2023-11-06 22:52:47,926 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-06 22:52:47,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 252 states and 285 transitions. [2023-11-06 22:52:47,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:52:47,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:52:47,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:52:47,929 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [30, 30, 30, 29, 29, 1, 1, 1, 1] [2023-11-06 22:52:47,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:52:47,930 INFO L748 eck$LassoCheckResult]: Stem: 32810#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 32794#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 32795#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32811#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32812#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32798#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32799#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32873#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32872#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32871#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32870#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32869#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32868#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32867#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32866#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32865#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32864#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32863#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32862#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32861#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32860#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32859#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32858#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32857#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32856#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32855#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32854#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32853#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32852#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32851#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32850#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32849#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32848#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32847#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32846#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32845#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32844#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32843#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32842#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32841#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32840#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32839#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32838#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32837#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32836#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32835#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32834#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32833#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32832#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32831#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32830#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32829#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32828#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32827#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32826#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32825#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32824#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32823#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32822#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32821#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32820#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 32817#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 32816#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 32800#L27-4 main_~i~0#1 := 0; 32801#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32807#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32793#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32804#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32809#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33036#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33035#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33033#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33030#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33029#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33027#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33024#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33023#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33021#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33018#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33017#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33015#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33012#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33011#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33009#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33006#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 33005#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 33003#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 33000#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32999#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32997#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32994#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32993#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32991#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32988#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32987#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32985#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32982#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32981#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32979#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32976#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32975#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32973#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32970#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32969#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32967#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32964#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32963#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32961#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32958#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32957#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32955#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32952#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32951#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32949#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32946#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32945#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32943#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32940#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32939#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32937#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32934#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32933#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32931#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32928#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32927#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32925#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32922#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32921#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32919#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32916#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32915#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32913#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32910#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32909#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32907#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32904#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32903#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32901#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32898#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32897#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32895#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32892#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32891#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32889#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32886#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32885#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32883#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32881#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32880#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32877#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32875#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32874#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32815#L34 [2023-11-06 22:52:47,930 INFO L750 eck$LassoCheckResult]: Loop: 32815#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 32818#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 32814#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 32815#L34 [2023-11-06 22:52:47,930 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:47,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1614133669, now seen corresponding path program 58 times [2023-11-06 22:52:47,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:47,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688238851] [2023-11-06 22:52:47,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:47,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:48,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:48,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:48,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:48,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:48,409 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:48,409 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 31 times [2023-11-06 22:52:48,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:48,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1419700997] [2023-11-06 22:52:48,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:48,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:48,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:48,415 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:52:48,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:52:48,419 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:52:48,420 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:52:48,420 INFO L85 PathProgramCache]: Analyzing trace with hash 202333873, now seen corresponding path program 59 times [2023-11-06 22:52:48,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:52:48,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1365113954] [2023-11-06 22:52:48,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:52:48,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:52:48,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:52:50,986 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1247 proven. 988 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:52:50,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:52:50,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1365113954] [2023-11-06 22:52:50,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1365113954] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:52:50,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [274252186] [2023-11-06 22:52:50,986 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:52:50,986 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:52:50,986 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:52:50,989 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:52:50,990 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2023-11-06 22:53:08,104 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2023-11-06 22:53:08,105 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:53:08,123 INFO L262 TraceCheckSpWp]: Trace formula consists of 671 conjuncts, 64 conjunts are in the unsatisfiable core [2023-11-06 22:53:08,126 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:53:10,260 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:10,260 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:53:11,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2235 backedges. 1335 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:11,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [274252186] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:53:11,869 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:53:11,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64, 64] total 97 [2023-11-06 22:53:11,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73874118] [2023-11-06 22:53:11,870 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:53:11,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:53:11,923 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2023-11-06 22:53:11,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2181, Invalid=7325, Unknown=0, NotChecked=0, Total=9506 [2023-11-06 22:53:11,924 INFO L87 Difference]: Start difference. First operand 252 states and 285 transitions. cyclomatic complexity: 36 Second operand has 98 states, 97 states have (on average 2.618556701030928) internal successors, (254), 98 states have internal predecessors, (254), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:14,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:53:14,055 INFO L93 Difference]: Finished difference Result 817 states and 944 transitions. [2023-11-06 22:53:14,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 817 states and 944 transitions. [2023-11-06 22:53:14,058 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:14,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 817 states to 452 states and 518 transitions. [2023-11-06 22:53:14,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 389 [2023-11-06 22:53:14,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 389 [2023-11-06 22:53:14,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 452 states and 518 transitions. [2023-11-06 22:53:14,062 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:53:14,062 INFO L218 hiAutomatonCegarLoop]: Abstraction has 452 states and 518 transitions. [2023-11-06 22:53:14,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states and 518 transitions. [2023-11-06 22:53:14,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 260. [2023-11-06 22:53:14,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 260 states have (on average 1.1307692307692307) internal successors, (294), 259 states have internal predecessors, (294), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:14,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 294 transitions. [2023-11-06 22:53:14,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 294 transitions. [2023-11-06 22:53:14,070 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2023-11-06 22:53:14,071 INFO L428 stractBuchiCegarLoop]: Abstraction has 260 states and 294 transitions. [2023-11-06 22:53:14,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-06 22:53:14,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 294 transitions. [2023-11-06 22:53:14,073 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:14,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:53:14,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:53:14,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [31, 31, 31, 30, 30, 1, 1, 1, 1] [2023-11-06 22:53:14,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:53:14,075 INFO L748 eck$LassoCheckResult]: Stem: 34968#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 34952#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 34953#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34969#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34970#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34956#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34957#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35033#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35032#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35031#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35030#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35029#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35028#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35027#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35026#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35025#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35024#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35023#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35022#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35021#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35020#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35019#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35018#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35017#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35016#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35015#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35014#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35013#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35012#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35011#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35010#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35009#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35008#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35007#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35006#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35005#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35004#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35003#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35002#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 35001#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 35000#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34999#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34998#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34997#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34996#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34995#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34994#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34993#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34992#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34991#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34990#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34989#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34988#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34987#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34986#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34985#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34984#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34983#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34982#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34981#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34980#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34979#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34978#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 34975#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 34974#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 34958#L27-4 main_~i~0#1 := 0; 34959#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34965#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34951#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34962#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34967#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35202#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35201#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35199#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35196#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35195#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35193#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35190#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35189#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35187#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35184#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35183#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35181#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35178#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35177#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35175#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35172#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35171#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35169#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35166#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35165#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35163#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35160#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35159#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35157#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35154#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35153#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35151#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35148#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35147#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35145#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35142#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35141#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35139#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35136#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35135#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35133#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35130#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35129#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35127#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35124#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35123#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35121#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35118#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35117#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35115#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35112#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35111#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35109#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35106#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35105#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35103#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35100#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35099#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35097#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35094#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35093#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35091#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35088#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35087#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35085#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35082#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35081#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35079#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35076#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35075#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35073#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35070#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35069#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35067#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35064#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35063#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35061#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35058#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35057#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35055#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35052#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35051#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35049#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35046#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35045#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35043#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35041#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35040#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 35037#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 35035#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 35034#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34973#L34 [2023-11-06 22:53:14,075 INFO L750 eck$LassoCheckResult]: Loop: 34973#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 34976#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 34972#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 34973#L34 [2023-11-06 22:53:14,075 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:14,075 INFO L85 PathProgramCache]: Analyzing trace with hash 576395375, now seen corresponding path program 60 times [2023-11-06 22:53:14,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:14,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1588636661] [2023-11-06 22:53:14,076 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:14,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:14,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:14,315 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:14,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:14,582 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:14,582 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:14,582 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 32 times [2023-11-06 22:53:14,582 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:14,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291404563] [2023-11-06 22:53:14,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:14,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:14,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:14,589 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:14,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:14,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:14,593 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:14,594 INFO L85 PathProgramCache]: Analyzing trace with hash 115413927, now seen corresponding path program 61 times [2023-11-06 22:53:14,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:14,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635899690] [2023-11-06 22:53:14,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:14,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:14,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:53:17,183 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1335 proven. 1052 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:17,183 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:53:17,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [635899690] [2023-11-06 22:53:17,183 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [635899690] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:53:17,183 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1696624435] [2023-11-06 22:53:17,184 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2023-11-06 22:53:17,184 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:53:17,184 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:53:17,187 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:53:17,188 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2023-11-06 22:53:17,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:53:17,599 INFO L262 TraceCheckSpWp]: Trace formula consists of 692 conjuncts, 66 conjunts are in the unsatisfiable core [2023-11-06 22:53:17,602 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:53:19,836 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:19,837 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:53:21,528 INFO L134 CoverageAnalysis]: Checked inductivity of 2387 backedges. 1426 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:21,528 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1696624435] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:53:21,528 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:53:21,529 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66, 66] total 100 [2023-11-06 22:53:21,529 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1568206562] [2023-11-06 22:53:21,529 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:53:21,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:53:21,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2023-11-06 22:53:21,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2315, Invalid=7785, Unknown=0, NotChecked=0, Total=10100 [2023-11-06 22:53:21,582 INFO L87 Difference]: Start difference. First operand 260 states and 294 transitions. cyclomatic complexity: 37 Second operand has 101 states, 100 states have (on average 2.62) internal successors, (262), 101 states have internal predecessors, (262), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:23,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:53:23,780 INFO L93 Difference]: Finished difference Result 843 states and 974 transitions. [2023-11-06 22:53:23,780 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 843 states and 974 transitions. [2023-11-06 22:53:23,783 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:23,785 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 843 states to 466 states and 534 transitions. [2023-11-06 22:53:23,785 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 401 [2023-11-06 22:53:23,786 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 401 [2023-11-06 22:53:23,786 INFO L73 IsDeterministic]: Start isDeterministic. Operand 466 states and 534 transitions. [2023-11-06 22:53:23,786 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:53:23,786 INFO L218 hiAutomatonCegarLoop]: Abstraction has 466 states and 534 transitions. [2023-11-06 22:53:23,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states and 534 transitions. [2023-11-06 22:53:23,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 268. [2023-11-06 22:53:23,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 268 states, 268 states have (on average 1.1305970149253732) internal successors, (303), 267 states have internal predecessors, (303), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:23,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 268 states to 268 states and 303 transitions. [2023-11-06 22:53:23,792 INFO L240 hiAutomatonCegarLoop]: Abstraction has 268 states and 303 transitions. [2023-11-06 22:53:23,793 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2023-11-06 22:53:23,794 INFO L428 stractBuchiCegarLoop]: Abstraction has 268 states and 303 transitions. [2023-11-06 22:53:23,794 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-06 22:53:23,794 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 268 states and 303 transitions. [2023-11-06 22:53:23,795 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:23,795 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:53:23,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:53:23,797 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [32, 32, 32, 31, 31, 1, 1, 1, 1] [2023-11-06 22:53:23,797 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:53:23,797 INFO L748 eck$LassoCheckResult]: Stem: 37195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 37179#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 37180#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37196#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37197#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37183#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37184#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37262#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37261#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37260#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37259#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37258#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37257#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37256#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37255#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37254#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37253#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37252#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37251#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37250#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37249#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37248#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37247#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37246#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37245#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37244#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37243#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37242#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37241#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37240#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37239#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37238#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37237#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37236#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37235#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37234#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37233#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37232#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37231#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37230#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37229#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37228#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37227#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37226#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37225#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37224#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37223#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37222#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37221#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37220#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37219#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37218#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37217#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37216#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37215#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37214#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37213#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37212#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37211#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37210#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37209#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37208#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37207#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37206#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37205#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 37202#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 37201#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 37185#L27-4 main_~i~0#1 := 0; 37186#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37192#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37178#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37189#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37194#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37437#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37436#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37434#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37431#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37430#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37428#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37425#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37424#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37422#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37419#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37418#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37416#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37413#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37412#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37410#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37407#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37406#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37404#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37401#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37400#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37398#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37395#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37394#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37392#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37389#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37388#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37386#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37383#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37382#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37380#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37377#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37376#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37374#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37371#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37370#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37368#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37365#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37364#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37362#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37359#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37358#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37356#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37353#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37352#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37350#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37347#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37346#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37344#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37341#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37340#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37338#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37335#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37334#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37332#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37329#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37328#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37326#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37323#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37322#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37320#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37317#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37316#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37314#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37311#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37310#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37308#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37305#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37304#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37302#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37299#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37298#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37296#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37293#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37292#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37290#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37287#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37286#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37284#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37281#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37280#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37278#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37275#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37274#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37272#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37270#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37269#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37266#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37264#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37263#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37200#L34 [2023-11-06 22:53:23,797 INFO L750 eck$LassoCheckResult]: Loop: 37200#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 37203#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 37199#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 37200#L34 [2023-11-06 22:53:23,798 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:23,798 INFO L85 PathProgramCache]: Analyzing trace with hash 473546921, now seen corresponding path program 62 times [2023-11-06 22:53:23,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:23,798 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378916887] [2023-11-06 22:53:23,798 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:23,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:24,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:24,071 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:24,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:24,400 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:24,401 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:24,401 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 33 times [2023-11-06 22:53:24,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:24,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008992930] [2023-11-06 22:53:24,401 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:24,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:24,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:24,407 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:24,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:24,411 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:24,411 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:24,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1531197139, now seen corresponding path program 63 times [2023-11-06 22:53:24,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:24,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094944193] [2023-11-06 22:53:24,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:24,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:24,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:53:27,233 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1426 proven. 1118 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:27,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:53:27,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2094944193] [2023-11-06 22:53:27,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2094944193] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:53:27,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [716073560] [2023-11-06 22:53:27,233 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:53:27,234 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:53:27,234 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:53:27,236 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:53:27,237 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2023-11-06 22:53:33,532 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2023-11-06 22:53:33,532 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:53:33,545 INFO L262 TraceCheckSpWp]: Trace formula consists of 713 conjuncts, 68 conjunts are in the unsatisfiable core [2023-11-06 22:53:33,548 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:53:35,883 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:35,883 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:53:37,886 INFO L134 CoverageAnalysis]: Checked inductivity of 2544 backedges. 1520 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:37,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [716073560] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:53:37,886 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:53:37,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 68] total 103 [2023-11-06 22:53:37,887 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247877451] [2023-11-06 22:53:37,887 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:53:37,958 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:53:37,959 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2023-11-06 22:53:37,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2453, Invalid=8259, Unknown=0, NotChecked=0, Total=10712 [2023-11-06 22:53:37,961 INFO L87 Difference]: Start difference. First operand 268 states and 303 transitions. cyclomatic complexity: 38 Second operand has 104 states, 103 states have (on average 2.621359223300971) internal successors, (270), 104 states have internal predecessors, (270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:40,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:53:40,214 INFO L93 Difference]: Finished difference Result 869 states and 1004 transitions. [2023-11-06 22:53:40,214 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 869 states and 1004 transitions. [2023-11-06 22:53:40,218 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:40,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 869 states to 480 states and 550 transitions. [2023-11-06 22:53:40,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2023-11-06 22:53:40,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2023-11-06 22:53:40,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 550 transitions. [2023-11-06 22:53:40,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:53:40,227 INFO L218 hiAutomatonCegarLoop]: Abstraction has 480 states and 550 transitions. [2023-11-06 22:53:40,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 550 transitions. [2023-11-06 22:53:40,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 276. [2023-11-06 22:53:40,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 276 states have (on average 1.1304347826086956) internal successors, (312), 275 states have internal predecessors, (312), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:53:40,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 312 transitions. [2023-11-06 22:53:40,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 276 states and 312 transitions. [2023-11-06 22:53:40,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2023-11-06 22:53:40,239 INFO L428 stractBuchiCegarLoop]: Abstraction has 276 states and 312 transitions. [2023-11-06 22:53:40,239 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-06 22:53:40,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states and 312 transitions. [2023-11-06 22:53:40,240 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2023-11-06 22:53:40,240 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:53:40,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:53:40,242 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [33, 33, 33, 32, 32, 1, 1, 1, 1] [2023-11-06 22:53:40,242 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2023-11-06 22:53:40,243 INFO L748 eck$LassoCheckResult]: Stem: 39491#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(18, 2); 39475#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet3#1, main_#t~post2#1, main_#t~mem5#1, main_#t~mem6#1, main_#t~post4#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~post7#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0; 39476#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39492#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39493#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39479#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39480#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39560#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39559#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39558#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39557#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39556#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39555#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39554#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39553#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39552#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39551#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39550#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39549#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39548#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39547#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39546#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39545#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39544#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39543#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39542#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39541#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39540#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39539#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39538#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39537#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39536#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39535#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39534#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39533#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39532#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39531#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39530#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39529#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39528#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39527#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39526#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39525#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39524#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39523#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39522#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39521#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39520#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39519#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39518#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39517#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39516#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39515#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39514#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39513#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39512#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39511#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39510#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39509#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39508#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39507#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39506#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39505#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39504#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39503#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39502#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39501#L27-3 assume !!(main_~i~0#1 < main_~num~0#1);havoc main_#t~nondet3#1;call write~int(main_#t~nondet3#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet3#1; 39498#L27-2 main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 39497#L27-3 assume !(main_~i~0#1 < main_~num~0#1); 39481#L27-4 main_~i~0#1 := 0; 39482#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39488#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39474#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39485#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39490#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39741#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39740#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39738#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39735#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39734#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39732#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39729#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39728#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39726#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39723#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39722#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39720#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39717#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39716#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39714#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39711#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39710#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39708#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39705#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39704#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39702#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39699#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39698#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39696#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39693#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39692#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39690#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39687#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39686#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39684#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39681#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39680#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39678#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39675#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39674#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39672#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39669#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39668#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39666#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39663#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39662#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39660#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39657#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39656#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39654#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39651#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39650#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39648#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39645#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39644#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39642#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39639#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39638#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39636#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39633#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39632#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39630#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39627#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39626#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39624#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39621#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39620#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39618#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39615#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39614#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39612#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39609#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39608#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39606#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39603#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39602#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39600#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39597#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39596#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39594#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39591#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39590#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39588#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39585#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39584#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39582#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39579#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39578#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39576#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39573#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39572#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39570#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39568#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39567#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39564#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39562#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39561#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39496#L34 [2023-11-06 22:53:40,243 INFO L750 eck$LassoCheckResult]: Loop: 39496#L34 assume !(0 == (if main_#t~mem5#1 < 0 && 0 != main_#t~mem5#1 % 2 then main_#t~mem5#1 % 2 - 2 else main_#t~mem5#1 % 2));havoc main_#t~mem5#1; 39499#L32-2 main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1; 39495#L32-3 assume !!(main_~i~0#1 < main_~num~0#1);call main_#t~mem5#1 := read~int(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4); 39496#L34 [2023-11-06 22:53:40,244 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:40,244 INFO L85 PathProgramCache]: Analyzing trace with hash 1613819243, now seen corresponding path program 64 times [2023-11-06 22:53:40,244 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:40,244 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907080051] [2023-11-06 22:53:40,244 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:40,244 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:40,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:40,553 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:40,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:40,907 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:40,907 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:40,908 INFO L85 PathProgramCache]: Analyzing trace with hash 76501, now seen corresponding path program 34 times [2023-11-06 22:53:40,908 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:40,908 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403202908] [2023-11-06 22:53:40,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:40,908 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:40,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:40,915 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:53:40,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:53:40,919 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:53:40,920 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:53:40,920 INFO L85 PathProgramCache]: Analyzing trace with hash -574796501, now seen corresponding path program 65 times [2023-11-06 22:53:40,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:53:40,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1269267607] [2023-11-06 22:53:40,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:53:40,921 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:53:40,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:53:44,226 INFO L134 CoverageAnalysis]: Checked inductivity of 2706 backedges. 1520 proven. 1186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:53:44,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:53:44,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1269267607] [2023-11-06 22:53:44,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1269267607] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:53:44,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [451056080] [2023-11-06 22:53:44,227 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:53:44,227 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:53:44,227 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:53:44,230 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:53:44,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_576eb1a6-cead-4190-963d-ea0d61decf01/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process