./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:40:24,487 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:40:24,602 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:40:24,607 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:40:24,608 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:40:24,636 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:40:24,640 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:40:24,641 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:40:24,642 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:40:24,647 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:40:24,649 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:40:24,649 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:40:24,650 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:40:24,651 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:40:24,652 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:40:24,652 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:40:24,653 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:40:24,654 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:40:24,654 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:40:24,655 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:40:24,655 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:40:24,656 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:40:24,656 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:40:24,657 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:40:24,657 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:40:24,658 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:40:24,658 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:40:24,659 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:40:24,659 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:40:24,660 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:40:24,661 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:40:24,661 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:40:24,662 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:40:24,662 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:40:24,662 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:40:24,663 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:40:24,663 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 30a4b942034eaa47a8fcc8fdf4549d1d63a9a60d59b585da2a353c9626604750 [2023-11-06 22:40:24,926 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:40:24,947 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:40:24,949 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:40:24,951 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:40:24,951 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:40:24,953 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2023-11-06 22:40:28,230 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:40:28,434 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:40:28,435 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/sv-benchmarks/c/loop-invgen/string_concat-noarr.i [2023-11-06 22:40:28,443 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/data/9f7df4c9b/bddf7e40d70c49248ee0dbdafd49cdf6/FLAG99989cd7c [2023-11-06 22:40:28,463 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/data/9f7df4c9b/bddf7e40d70c49248ee0dbdafd49cdf6 [2023-11-06 22:40:28,470 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:40:28,472 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:40:28,476 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:40:28,478 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:40:28,483 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:40:28,487 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,488 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7ae57a2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28, skipping insertion in model container [2023-11-06 22:40:28,488 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,515 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:40:28,721 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:40:28,735 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:40:28,757 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:40:28,776 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:40:28,776 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28 WrapperNode [2023-11-06 22:40:28,776 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:40:28,778 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:40:28,778 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:40:28,779 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:40:28,787 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,798 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,816 INFO L138 Inliner]: procedures = 16, calls = 8, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 55 [2023-11-06 22:40:28,816 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:40:28,817 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:40:28,817 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:40:28,818 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:40:28,827 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,827 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,829 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,829 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,832 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,837 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,838 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,839 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,841 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:40:28,842 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:40:28,842 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:40:28,843 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:40:28,844 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (1/1) ... [2023-11-06 22:40:28,855 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:28,878 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:28,894 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:28,906 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:40:28,934 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:40:28,935 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:40:28,935 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:40:28,935 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:40:28,999 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:40:29,001 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:40:29,128 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:40:29,134 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:40:29,134 INFO L302 CfgBuilder]: Removed 2 assume(true) statements. [2023-11-06 22:40:29,136 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:29 BoogieIcfgContainer [2023-11-06 22:40:29,137 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:40:29,138 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:40:29,138 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:40:29,142 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:40:29,143 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:29,143 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:40:28" (1/3) ... [2023-11-06 22:40:29,144 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bf38e79 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:40:29, skipping insertion in model container [2023-11-06 22:40:29,144 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:29,145 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:40:28" (2/3) ... [2023-11-06 22:40:29,145 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bf38e79 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:40:29, skipping insertion in model container [2023-11-06 22:40:29,145 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:40:29,145 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:29" (3/3) ... [2023-11-06 22:40:29,147 INFO L332 chiAutomizerObserver]: Analyzing ICFG string_concat-noarr.i [2023-11-06 22:40:29,205 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:40:29,205 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:40:29,205 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:40:29,205 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:40:29,205 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:40:29,205 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:40:29,206 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:40:29,206 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:40:29,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:29,229 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2023-11-06 22:40:29,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:29,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:29,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2023-11-06 22:40:29,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:40:29,235 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:40:29,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:29,238 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 5 [2023-11-06 22:40:29,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:29,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:29,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2023-11-06 22:40:29,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2023-11-06 22:40:29,247 INFO L748 eck$LassoCheckResult]: Stem: 13#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 6#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5#L26true main_~i~0#1 := 0; 16#L29-2true [2023-11-06 22:40:29,247 INFO L750 eck$LassoCheckResult]: Loop: 16#L29-2true havoc main_#t~nondet1#1; 4#L29true assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 16#L29-2true [2023-11-06 22:40:29,253 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:29,253 INFO L85 PathProgramCache]: Analyzing trace with hash 29857, now seen corresponding path program 1 times [2023-11-06 22:40:29,262 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:29,263 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180197921] [2023-11-06 22:40:29,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:29,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:29,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,362 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:29,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:29,392 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:29,392 INFO L85 PathProgramCache]: Analyzing trace with hash 1254, now seen corresponding path program 1 times [2023-11-06 22:40:29,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:29,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206438328] [2023-11-06 22:40:29,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:29,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:29,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,403 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:29,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,409 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:29,410 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:29,411 INFO L85 PathProgramCache]: Analyzing trace with hash 28692870, now seen corresponding path program 1 times [2023-11-06 22:40:29,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:29,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306622197] [2023-11-06 22:40:29,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:29,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:29,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,425 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:29,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:29,442 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:29,542 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:40:29,542 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:40:29,542 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:40:29,543 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:40:29,543 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-06 22:40:29,543 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,543 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:40:29,543 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:40:29,543 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2023-11-06 22:40:29,543 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:40:29,544 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:40:29,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,615 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:40:29,616 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-06 22:40:29,618 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,618 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:29,623 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:29,633 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-06 22:40:29,633 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-06 22:40:29,634 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-06 22:40:29,656 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-06 22:40:29,656 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,656 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:29,666 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:29,668 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-06 22:40:29,669 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-06 22:40:29,669 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-06 22:40:29,717 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-06 22:40:29,725 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2023-11-06 22:40:29,726 INFO L210 LassoAnalysis]: Preferences: [2023-11-06 22:40:29,726 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-06 22:40:29,726 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-06 22:40:29,726 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-06 22:40:29,726 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-06 22:40:29,726 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,727 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-06 22:40:29,727 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-06 22:40:29,727 INFO L133 ssoRankerPreferences]: Filename of dumped script: string_concat-noarr.i_Iteration1_Loop [2023-11-06 22:40:29,727 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-06 22:40:29,727 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-06 22:40:29,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-06 22:40:29,793 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-06 22:40:29,798 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-06 22:40:29,799 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:29,804 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:29,811 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-06 22:40:29,825 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-06 22:40:29,826 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-06 22:40:29,826 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-06 22:40:29,826 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-06 22:40:29,827 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-06 22:40:29,829 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-06 22:40:29,830 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-06 22:40:29,830 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-06 22:40:29,834 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-06 22:40:29,839 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-06 22:40:29,839 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-06 22:40:29,841 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:40:29,841 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:29,876 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:40:29,885 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-06 22:40:29,885 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-06 22:40:29,885 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-06 22:40:29,886 INFO L513 LassoAnalysis]: Proved termination. [2023-11-06 22:40:29,887 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0#1) = -2*ULTIMATE.start_main_~i~0#1 + 1999999 Supporting invariants [] [2023-11-06 22:40:29,890 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2023-11-06 22:40:29,895 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-06 22:40:29,955 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:29,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:29,979 INFO L262 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-06 22:40:29,981 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:30,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:30,014 WARN L260 TraceCheckSpWp]: Trace formula consists of 7 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-06 22:40:30,015 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:30,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,059 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2023-11-06 22:40:30,062 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,140 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 18 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 44 states and 62 transitions. Complement of second has 6 states. [2023-11-06 22:40:30,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 4 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-06 22:40:30,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.6666666666666667) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 42 transitions. [2023-11-06 22:40:30,153 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 3 letters. Loop has 2 letters. [2023-11-06 22:40:30,154 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:40:30,155 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 5 letters. Loop has 2 letters. [2023-11-06 22:40:30,155 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:40:30,155 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 4 states and 42 transitions. Stem has 3 letters. Loop has 4 letters. [2023-11-06 22:40:30,156 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-06 22:40:30,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 62 transitions. [2023-11-06 22:40:30,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 17 states and 22 transitions. [2023-11-06 22:40:30,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:30,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2023-11-06 22:40:30,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 22 transitions. [2023-11-06 22:40:30,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:30,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17 states and 22 transitions. [2023-11-06 22:40:30,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 22 transitions. [2023-11-06 22:40:30,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2023-11-06 22:40:30,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.3125) internal successors, (21), 15 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 21 transitions. [2023-11-06 22:40:30,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16 states and 21 transitions. [2023-11-06 22:40:30,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 16 states and 21 transitions. [2023-11-06 22:40:30,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:40:30,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 21 transitions. [2023-11-06 22:40:30,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:30,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:30,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2023-11-06 22:40:30,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:30,218 INFO L748 eck$LassoCheckResult]: Stem: 105#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 112#L26 main_~i~0#1 := 0; 113#L29-2 havoc main_#t~nondet1#1; 107#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 100#L29-3 assume main_~i~0#1 >= 100; 101#L32 [2023-11-06 22:40:30,218 INFO L750 eck$LassoCheckResult]: Loop: 101#L32 assume true; 101#L32 [2023-11-06 22:40:30,225 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,226 INFO L85 PathProgramCache]: Analyzing trace with hash 889478928, now seen corresponding path program 1 times [2023-11-06 22:40:30,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321661734] [2023-11-06 22:40:30,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:30,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:30,369 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321661734] [2023-11-06 22:40:30,370 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321661734] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:30,370 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:30,370 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:40:30,370 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304681371] [2023-11-06 22:40:30,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:30,374 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:30,374 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,374 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 1 times [2023-11-06 22:40:30,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [870338107] [2023-11-06 22:40:30,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,378 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:30,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:30,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:30,392 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:30,393 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:30,395 INFO L87 Difference]: Start difference. First operand 16 states and 21 transitions. cyclomatic complexity: 8 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:30,442 INFO L93 Difference]: Finished difference Result 26 states and 32 transitions. [2023-11-06 22:40:30,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 32 transitions. [2023-11-06 22:40:30,447 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2 [2023-11-06 22:40:30,449 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 32 transitions. [2023-11-06 22:40:30,450 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2023-11-06 22:40:30,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2023-11-06 22:40:30,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 32 transitions. [2023-11-06 22:40:30,450 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:30,451 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2023-11-06 22:40:30,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 32 transitions. [2023-11-06 22:40:30,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 18. [2023-11-06 22:40:30,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 17 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2023-11-06 22:40:30,462 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 23 transitions. [2023-11-06 22:40:30,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:30,465 INFO L428 stractBuchiCegarLoop]: Abstraction has 18 states and 23 transitions. [2023-11-06 22:40:30,465 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:40:30,465 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 23 transitions. [2023-11-06 22:40:30,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:30,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:30,469 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:30,469 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:30,470 INFO L748 eck$LassoCheckResult]: Stem: 156#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 157#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 160#L26 main_~i~0#1 := 0; 161#L29-2 havoc main_#t~nondet1#1; 154#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 155#L29-2 havoc main_#t~nondet1#1; 152#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 153#L29-3 assume main_~i~0#1 >= 100; 162#L32 [2023-11-06 22:40:30,470 INFO L750 eck$LassoCheckResult]: Loop: 162#L32 assume true; 162#L32 [2023-11-06 22:40:30,470 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,470 INFO L85 PathProgramCache]: Analyzing trace with hash 90807307, now seen corresponding path program 1 times [2023-11-06 22:40:30,471 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,471 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394128251] [2023-11-06 22:40:30,471 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,471 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:30,559 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:30,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394128251] [2023-11-06 22:40:30,560 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394128251] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:30,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [425391787] [2023-11-06 22:40:30,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,561 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:30,561 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:30,562 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:30,587 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2023-11-06 22:40:30,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:30,626 INFO L262 TraceCheckSpWp]: Trace formula consists of 28 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-06 22:40:30,628 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:30,668 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,668 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:30,711 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [425391787] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:30,714 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:30,714 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-06 22:40:30,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2121561459] [2023-11-06 22:40:30,715 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:30,715 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:30,716 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,716 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 2 times [2023-11-06 22:40:30,717 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,718 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248314422] [2023-11-06 22:40:30,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,723 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:30,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,726 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:30,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:30,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-06 22:40:30,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-06 22:40:30,733 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. cyclomatic complexity: 8 Second operand has 7 states, 6 states have (on average 2.8333333333333335) internal successors, (17), 7 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:30,827 INFO L93 Difference]: Finished difference Result 60 states and 75 transitions. [2023-11-06 22:40:30,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 75 transitions. [2023-11-06 22:40:30,831 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 5 [2023-11-06 22:40:30,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 75 transitions. [2023-11-06 22:40:30,839 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2023-11-06 22:40:30,840 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2023-11-06 22:40:30,840 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 75 transitions. [2023-11-06 22:40:30,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:30,841 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60 states and 75 transitions. [2023-11-06 22:40:30,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 75 transitions. [2023-11-06 22:40:30,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 24. [2023-11-06 22:40:30,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.4583333333333333) internal successors, (35), 23 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 35 transitions. [2023-11-06 22:40:30,850 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 35 transitions. [2023-11-06 22:40:30,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-06 22:40:30,854 INFO L428 stractBuchiCegarLoop]: Abstraction has 24 states and 35 transitions. [2023-11-06 22:40:30,854 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:40:30,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 35 transitions. [2023-11-06 22:40:30,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:30,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:30,861 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:30,861 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:30,862 INFO L748 eck$LassoCheckResult]: Stem: 285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 289#L26 main_~i~0#1 := 0; 290#L29-2 havoc main_#t~nondet1#1; 282#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 278#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 279#L35-2 havoc main_#t~nondet3#1; 287#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 292#L35-3 assume main_~j~0#1 >= 100; 291#L32 [2023-11-06 22:40:30,862 INFO L750 eck$LassoCheckResult]: Loop: 291#L32 assume true; 291#L32 [2023-11-06 22:40:30,862 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,863 INFO L85 PathProgramCache]: Analyzing trace with hash -1481354991, now seen corresponding path program 1 times [2023-11-06 22:40:30,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [621544116] [2023-11-06 22:40:30,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:30,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:30,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:30,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [621544116] [2023-11-06 22:40:30,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [621544116] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:40:30,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:40:30,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:40:30,909 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445128966] [2023-11-06 22:40:30,909 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:40:30,910 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:30,910 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,910 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 3 times [2023-11-06 22:40:30,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462895090] [2023-11-06 22:40:30,911 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,914 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:30,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:30,916 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:30,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:30,919 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:40:30,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:40:30,920 INFO L87 Difference]: Start difference. First operand 24 states and 35 transitions. cyclomatic complexity: 14 Second operand has 3 states, 2 states have (on average 4.5) internal successors, (9), 3 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,926 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:30,927 INFO L93 Difference]: Finished difference Result 27 states and 37 transitions. [2023-11-06 22:40:30,927 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 37 transitions. [2023-11-06 22:40:30,928 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 22 states and 28 transitions. [2023-11-06 22:40:30,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:30,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:30,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 28 transitions. [2023-11-06 22:40:30,929 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:30,929 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22 states and 28 transitions. [2023-11-06 22:40:30,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 28 transitions. [2023-11-06 22:40:30,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2023-11-06 22:40:30,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.2857142857142858) internal successors, (27), 20 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:30,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2023-11-06 22:40:30,933 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21 states and 27 transitions. [2023-11-06 22:40:30,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:40:30,935 INFO L428 stractBuchiCegarLoop]: Abstraction has 21 states and 27 transitions. [2023-11-06 22:40:30,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:40:30,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 27 transitions. [2023-11-06 22:40:30,937 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:30,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:30,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:30,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:30,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:30,942 INFO L748 eck$LassoCheckResult]: Stem: 342#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 343#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 345#L26 main_~i~0#1 := 0; 346#L29-2 havoc main_#t~nondet1#1; 340#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 337#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 338#L35-2 havoc main_#t~nondet3#1; 344#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 349#L35-2 havoc main_#t~nondet3#1; 348#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 347#L35-3 assume main_~j~0#1 >= 100; 336#L32 [2023-11-06 22:40:30,942 INFO L750 eck$LassoCheckResult]: Loop: 336#L32 assume true; 336#L32 [2023-11-06 22:40:30,942 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:30,943 INFO L85 PathProgramCache]: Analyzing trace with hash -1947921364, now seen corresponding path program 1 times [2023-11-06 22:40:30,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:30,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474239380] [2023-11-06 22:40:30,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:30,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:30,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:31,027 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:31,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474239380] [2023-11-06 22:40:31,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474239380] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:31,029 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [939490246] [2023-11-06 22:40:31,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:31,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:31,030 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:31,033 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:31,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2023-11-06 22:40:31,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:31,088 INFO L262 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjunts are in the unsatisfiable core [2023-11-06 22:40:31,090 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:31,110 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,110 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:31,148 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [939490246] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:31,148 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:31,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3, 3] total 6 [2023-11-06 22:40:31,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1925382504] [2023-11-06 22:40:31,149 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:31,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:31,150 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:31,150 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 4 times [2023-11-06 22:40:31,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:31,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925823042] [2023-11-06 22:40:31,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:31,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:31,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:31,153 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:31,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:31,154 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:31,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:31,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2023-11-06 22:40:31,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2023-11-06 22:40:31,159 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. cyclomatic complexity: 9 Second operand has 7 states, 6 states have (on average 3.3333333333333335) internal successors, (20), 7 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:31,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:31,177 INFO L93 Difference]: Finished difference Result 34 states and 40 transitions. [2023-11-06 22:40:31,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 40 transitions. [2023-11-06 22:40:31,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:31,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 28 states and 34 transitions. [2023-11-06 22:40:31,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:31,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:31,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2023-11-06 22:40:31,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:31,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2023-11-06 22:40:31,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2023-11-06 22:40:31,181 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2023-11-06 22:40:31,181 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.2222222222222223) internal successors, (33), 26 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:31,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 33 transitions. [2023-11-06 22:40:31,182 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 33 transitions. [2023-11-06 22:40:31,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-06 22:40:31,188 INFO L428 stractBuchiCegarLoop]: Abstraction has 27 states and 33 transitions. [2023-11-06 22:40:31,188 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:40:31,188 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 33 transitions. [2023-11-06 22:40:31,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:31,189 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:31,189 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:31,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1] [2023-11-06 22:40:31,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:31,190 INFO L748 eck$LassoCheckResult]: Stem: 467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 470#L26 main_~i~0#1 := 0; 471#L29-2 havoc main_#t~nondet1#1; 465#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 466#L29-2 havoc main_#t~nondet1#1; 475#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 482#L29-2 havoc main_#t~nondet1#1; 481#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 480#L29-2 havoc main_#t~nondet1#1; 479#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 478#L29-2 havoc main_#t~nondet1#1; 464#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 460#L29-3 assume main_~i~0#1 >= 100; 461#L32 [2023-11-06 22:40:31,190 INFO L750 eck$LassoCheckResult]: Loop: 461#L32 assume true; 461#L32 [2023-11-06 22:40:31,190 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:31,190 INFO L85 PathProgramCache]: Analyzing trace with hash -957341060, now seen corresponding path program 2 times [2023-11-06 22:40:31,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:31,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688507464] [2023-11-06 22:40:31,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:31,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:31,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:31,286 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:31,286 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [688507464] [2023-11-06 22:40:31,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [688507464] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:31,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [448465203] [2023-11-06 22:40:31,287 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-06 22:40:31,287 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:31,287 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:31,291 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:31,339 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2023-11-06 22:40:31,372 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-06 22:40:31,373 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:31,373 INFO L262 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-06 22:40:31,375 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:31,407 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,408 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:31,493 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,493 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [448465203] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:31,493 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:31,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2023-11-06 22:40:31,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621736897] [2023-11-06 22:40:31,494 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:31,494 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:31,495 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:31,495 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 5 times [2023-11-06 22:40:31,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:31,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218811327] [2023-11-06 22:40:31,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:31,501 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:31,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:31,503 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:31,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:31,505 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:31,508 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:31,508 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-06 22:40:31,509 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-06 22:40:31,509 INFO L87 Difference]: Start difference. First operand 27 states and 33 transitions. cyclomatic complexity: 9 Second operand has 13 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 13 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:31,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:31,625 INFO L93 Difference]: Finished difference Result 152 states and 171 transitions. [2023-11-06 22:40:31,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152 states and 171 transitions. [2023-11-06 22:40:31,628 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2023-11-06 22:40:31,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152 states to 140 states and 159 transitions. [2023-11-06 22:40:31,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-06 22:40:31,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2023-11-06 22:40:31,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 140 states and 159 transitions. [2023-11-06 22:40:31,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:31,631 INFO L218 hiAutomatonCegarLoop]: Abstraction has 140 states and 159 transitions. [2023-11-06 22:40:31,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states and 159 transitions. [2023-11-06 22:40:31,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 39. [2023-11-06 22:40:31,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.3076923076923077) internal successors, (51), 38 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:31,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 51 transitions. [2023-11-06 22:40:31,637 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2023-11-06 22:40:31,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-06 22:40:31,638 INFO L428 stractBuchiCegarLoop]: Abstraction has 39 states and 51 transitions. [2023-11-06 22:40:31,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:40:31,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 51 transitions. [2023-11-06 22:40:31,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:31,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:31,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:31,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:31,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:31,641 INFO L748 eck$LassoCheckResult]: Stem: 737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 743#L26 main_~i~0#1 := 0; 744#L29-2 havoc main_#t~nondet1#1; 746#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 735#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 736#L35-2 havoc main_#t~nondet3#1; 742#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 749#L35-2 havoc main_#t~nondet3#1; 771#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 770#L35-2 havoc main_#t~nondet3#1; 769#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 768#L35-2 havoc main_#t~nondet3#1; 767#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 766#L35-2 havoc main_#t~nondet3#1; 748#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 745#L35-3 assume main_~j~0#1 >= 100; 734#L32 [2023-11-06 22:40:31,641 INFO L750 eck$LassoCheckResult]: Loop: 734#L32 assume true; 734#L32 [2023-11-06 22:40:31,657 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:31,658 INFO L85 PathProgramCache]: Analyzing trace with hash 606076157, now seen corresponding path program 2 times [2023-11-06 22:40:31,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:31,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2022936818] [2023-11-06 22:40:31,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:31,658 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:31,669 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-06 22:40:31,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:31,759 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:31,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2022936818] [2023-11-06 22:40:31,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2022936818] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:31,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [68275058] [2023-11-06 22:40:31,760 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2023-11-06 22:40:31,760 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:31,761 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:31,762 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:31,818 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2023-11-06 22:40:31,844 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2023-11-06 22:40:31,845 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:31,846 INFO L262 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 6 conjunts are in the unsatisfiable core [2023-11-06 22:40:31,848 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:31,900 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,900 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:31,996 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:31,996 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [68275058] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:31,996 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:31,996 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 12 [2023-11-06 22:40:31,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642432407] [2023-11-06 22:40:31,999 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:32,002 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:32,003 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:32,003 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 6 times [2023-11-06 22:40:32,003 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:32,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2009810269] [2023-11-06 22:40:32,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:32,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:32,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:32,008 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:32,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:32,010 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:32,012 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:32,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2023-11-06 22:40:32,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2023-11-06 22:40:32,016 INFO L87 Difference]: Start difference. First operand 39 states and 51 transitions. cyclomatic complexity: 15 Second operand has 13 states, 12 states have (on average 2.6666666666666665) internal successors, (32), 13 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:32,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:32,048 INFO L93 Difference]: Finished difference Result 64 states and 76 transitions. [2023-11-06 22:40:32,048 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 76 transitions. [2023-11-06 22:40:32,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:32,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 52 states and 64 transitions. [2023-11-06 22:40:32,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:32,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:32,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 64 transitions. [2023-11-06 22:40:32,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:32,054 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52 states and 64 transitions. [2023-11-06 22:40:32,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 64 transitions. [2023-11-06 22:40:32,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2023-11-06 22:40:32,063 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.2352941176470589) internal successors, (63), 50 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:32,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 63 transitions. [2023-11-06 22:40:32,068 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51 states and 63 transitions. [2023-11-06 22:40:32,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2023-11-06 22:40:32,070 INFO L428 stractBuchiCegarLoop]: Abstraction has 51 states and 63 transitions. [2023-11-06 22:40:32,071 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:40:32,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 63 transitions. [2023-11-06 22:40:32,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:32,073 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:32,073 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:32,073 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1] [2023-11-06 22:40:32,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:32,074 INFO L748 eck$LassoCheckResult]: Stem: 955#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 956#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 959#L26 main_~i~0#1 := 0; 960#L29-2 havoc main_#t~nondet1#1; 953#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 954#L29-2 havoc main_#t~nondet1#1; 964#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 983#L29-2 havoc main_#t~nondet1#1; 982#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 981#L29-2 havoc main_#t~nondet1#1; 980#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 979#L29-2 havoc main_#t~nondet1#1; 978#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 977#L29-2 havoc main_#t~nondet1#1; 976#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 975#L29-2 havoc main_#t~nondet1#1; 974#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 973#L29-2 havoc main_#t~nondet1#1; 972#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 971#L29-2 havoc main_#t~nondet1#1; 970#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 969#L29-2 havoc main_#t~nondet1#1; 968#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 967#L29-2 havoc main_#t~nondet1#1; 952#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 948#L29-3 assume main_~i~0#1 >= 100; 949#L32 [2023-11-06 22:40:32,074 INFO L750 eck$LassoCheckResult]: Loop: 949#L32 assume true; 949#L32 [2023-11-06 22:40:32,074 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:32,074 INFO L85 PathProgramCache]: Analyzing trace with hash 777893150, now seen corresponding path program 3 times [2023-11-06 22:40:32,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:32,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398574867] [2023-11-06 22:40:32,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:32,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:32,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:32,370 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:32,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:32,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [398574867] [2023-11-06 22:40:32,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [398574867] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:32,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [298528004] [2023-11-06 22:40:32,373 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:40:32,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:32,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:32,377 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:32,408 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2023-11-06 22:40:32,447 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-06 22:40:32,447 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:32,448 INFO L262 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-06 22:40:32,450 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:32,537 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:32,538 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:32,826 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:32,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [298528004] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:32,827 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:32,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2023-11-06 22:40:32,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979054802] [2023-11-06 22:40:32,827 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:32,828 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:32,828 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:32,828 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 7 times [2023-11-06 22:40:32,829 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:32,829 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772867354] [2023-11-06 22:40:32,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:32,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:32,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:32,831 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:32,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:32,833 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:32,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:32,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-06 22:40:32,836 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-06 22:40:32,837 INFO L87 Difference]: Start difference. First operand 51 states and 63 transitions. cyclomatic complexity: 15 Second operand has 25 states, 24 states have (on average 2.2083333333333335) internal successors, (53), 25 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:33,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:33,123 INFO L93 Difference]: Finished difference Result 518 states and 555 transitions. [2023-11-06 22:40:33,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 518 states and 555 transitions. [2023-11-06 22:40:33,130 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 13 [2023-11-06 22:40:33,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 518 states to 494 states and 531 transitions. [2023-11-06 22:40:33,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2023-11-06 22:40:33,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2023-11-06 22:40:33,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 494 states and 531 transitions. [2023-11-06 22:40:33,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:33,139 INFO L218 hiAutomatonCegarLoop]: Abstraction has 494 states and 531 transitions. [2023-11-06 22:40:33,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states and 531 transitions. [2023-11-06 22:40:33,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 75. [2023-11-06 22:40:33,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.32) internal successors, (99), 74 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:33,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 99 transitions. [2023-11-06 22:40:33,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 75 states and 99 transitions. [2023-11-06 22:40:33,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-06 22:40:33,165 INFO L428 stractBuchiCegarLoop]: Abstraction has 75 states and 99 transitions. [2023-11-06 22:40:33,165 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:40:33,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 99 transitions. [2023-11-06 22:40:33,166 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:33,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:33,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:33,167 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:33,167 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:33,167 INFO L748 eck$LassoCheckResult]: Stem: 1699#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 1700#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 1705#L26 main_~i~0#1 := 0; 1706#L29-2 havoc main_#t~nondet1#1; 1708#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 1697#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 1698#L35-2 havoc main_#t~nondet3#1; 1704#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1711#L35-2 havoc main_#t~nondet3#1; 1769#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1768#L35-2 havoc main_#t~nondet3#1; 1767#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1766#L35-2 havoc main_#t~nondet3#1; 1765#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1764#L35-2 havoc main_#t~nondet3#1; 1763#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1762#L35-2 havoc main_#t~nondet3#1; 1761#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1760#L35-2 havoc main_#t~nondet3#1; 1759#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1758#L35-2 havoc main_#t~nondet3#1; 1757#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1756#L35-2 havoc main_#t~nondet3#1; 1755#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1754#L35-2 havoc main_#t~nondet3#1; 1753#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 1752#L35-2 havoc main_#t~nondet3#1; 1710#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 1707#L35-3 assume main_~j~0#1 >= 100; 1696#L32 [2023-11-06 22:40:33,168 INFO L750 eck$LassoCheckResult]: Loop: 1696#L32 assume true; 1696#L32 [2023-11-06 22:40:33,168 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:33,168 INFO L85 PathProgramCache]: Analyzing trace with hash -2036695969, now seen corresponding path program 3 times [2023-11-06 22:40:33,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:33,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258929933] [2023-11-06 22:40:33,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:33,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:33,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:33,431 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:33,431 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:33,431 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [258929933] [2023-11-06 22:40:33,431 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [258929933] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:33,432 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1167659154] [2023-11-06 22:40:33,432 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2023-11-06 22:40:33,432 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:33,432 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:33,443 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:33,451 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2023-11-06 22:40:33,514 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2023-11-06 22:40:33,514 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:33,516 INFO L262 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 12 conjunts are in the unsatisfiable core [2023-11-06 22:40:33,518 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:33,587 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:33,587 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:33,847 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:33,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1167659154] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:33,847 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:33,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 24 [2023-11-06 22:40:33,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [659553695] [2023-11-06 22:40:33,848 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:33,849 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:33,850 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:33,850 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 8 times [2023-11-06 22:40:33,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:33,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887942197] [2023-11-06 22:40:33,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:33,851 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:33,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:33,853 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:33,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:33,855 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:33,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:33,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2023-11-06 22:40:33,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2023-11-06 22:40:33,862 INFO L87 Difference]: Start difference. First operand 75 states and 99 transitions. cyclomatic complexity: 27 Second operand has 25 states, 24 states have (on average 2.3333333333333335) internal successors, (56), 25 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:33,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:33,917 INFO L93 Difference]: Finished difference Result 124 states and 148 transitions. [2023-11-06 22:40:33,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 148 transitions. [2023-11-06 22:40:33,919 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:33,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 100 states and 124 transitions. [2023-11-06 22:40:33,920 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:33,920 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:33,920 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 124 transitions. [2023-11-06 22:40:33,923 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:33,923 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 124 transitions. [2023-11-06 22:40:33,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 124 transitions. [2023-11-06 22:40:33,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2023-11-06 22:40:33,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.2424242424242424) internal successors, (123), 98 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:33,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 123 transitions. [2023-11-06 22:40:33,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99 states and 123 transitions. [2023-11-06 22:40:33,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2023-11-06 22:40:33,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 99 states and 123 transitions. [2023-11-06 22:40:33,937 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:40:33,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 123 transitions. [2023-11-06 22:40:33,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:33,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:33,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:33,943 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1] [2023-11-06 22:40:33,943 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:33,945 INFO L748 eck$LassoCheckResult]: Stem: 2097#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 2098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 2101#L26 main_~i~0#1 := 0; 2102#L29-2 havoc main_#t~nondet1#1; 2095#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2096#L29-2 havoc main_#t~nondet1#1; 2106#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2149#L29-2 havoc main_#t~nondet1#1; 2148#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2147#L29-2 havoc main_#t~nondet1#1; 2146#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2145#L29-2 havoc main_#t~nondet1#1; 2144#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2143#L29-2 havoc main_#t~nondet1#1; 2142#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2141#L29-2 havoc main_#t~nondet1#1; 2140#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2139#L29-2 havoc main_#t~nondet1#1; 2138#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2137#L29-2 havoc main_#t~nondet1#1; 2136#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2135#L29-2 havoc main_#t~nondet1#1; 2134#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2133#L29-2 havoc main_#t~nondet1#1; 2132#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2131#L29-2 havoc main_#t~nondet1#1; 2130#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2129#L29-2 havoc main_#t~nondet1#1; 2128#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2127#L29-2 havoc main_#t~nondet1#1; 2126#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2125#L29-2 havoc main_#t~nondet1#1; 2124#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2123#L29-2 havoc main_#t~nondet1#1; 2122#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2121#L29-2 havoc main_#t~nondet1#1; 2120#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2119#L29-2 havoc main_#t~nondet1#1; 2118#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2117#L29-2 havoc main_#t~nondet1#1; 2116#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2115#L29-2 havoc main_#t~nondet1#1; 2114#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2113#L29-2 havoc main_#t~nondet1#1; 2112#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2111#L29-2 havoc main_#t~nondet1#1; 2110#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 2109#L29-2 havoc main_#t~nondet1#1; 2094#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 2090#L29-3 assume main_~i~0#1 >= 100; 2091#L32 [2023-11-06 22:40:33,945 INFO L750 eck$LassoCheckResult]: Loop: 2091#L32 assume true; 2091#L32 [2023-11-06 22:40:33,945 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:33,946 INFO L85 PathProgramCache]: Analyzing trace with hash -439176862, now seen corresponding path program 4 times [2023-11-06 22:40:33,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:33,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86228630] [2023-11-06 22:40:33,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:33,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:33,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:34,587 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:34,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:34,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86228630] [2023-11-06 22:40:34,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86228630] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:34,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1882729192] [2023-11-06 22:40:34,589 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-06 22:40:34,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:34,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:34,594 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:34,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2023-11-06 22:40:34,663 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-06 22:40:34,663 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:34,664 INFO L262 TraceCheckSpWp]: Trace formula consists of 133 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-06 22:40:34,670 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:34,804 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:34,804 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:35,736 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:35,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1882729192] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:35,737 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:35,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2023-11-06 22:40:35,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [846184377] [2023-11-06 22:40:35,737 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:35,738 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:35,738 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:35,738 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 9 times [2023-11-06 22:40:35,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:35,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275096595] [2023-11-06 22:40:35,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:35,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:35,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:35,740 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:35,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:35,741 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:35,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:35,745 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-06 22:40:35,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-06 22:40:35,747 INFO L87 Difference]: Start difference. First operand 99 states and 123 transitions. cyclomatic complexity: 27 Second operand has 49 states, 48 states have (on average 2.1041666666666665) internal successors, (101), 49 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:36,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:36,357 INFO L93 Difference]: Finished difference Result 1898 states and 1971 transitions. [2023-11-06 22:40:36,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1898 states and 1971 transitions. [2023-11-06 22:40:36,376 INFO L131 ngComponentsAnalysis]: Automaton has 25 accepting balls. 25 [2023-11-06 22:40:36,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1898 states to 1850 states and 1923 transitions. [2023-11-06 22:40:36,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2023-11-06 22:40:36,391 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2023-11-06 22:40:36,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1850 states and 1923 transitions. [2023-11-06 22:40:36,393 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:36,393 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1850 states and 1923 transitions. [2023-11-06 22:40:36,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1850 states and 1923 transitions. [2023-11-06 22:40:36,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1850 to 147. [2023-11-06 22:40:36,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 147 states, 147 states have (on average 1.3265306122448979) internal successors, (195), 146 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:36,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 195 transitions. [2023-11-06 22:40:36,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 147 states and 195 transitions. [2023-11-06 22:40:36,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-06 22:40:36,420 INFO L428 stractBuchiCegarLoop]: Abstraction has 147 states and 195 transitions. [2023-11-06 22:40:36,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:40:36,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 147 states and 195 transitions. [2023-11-06 22:40:36,422 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:36,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:36,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:36,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 22, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:36,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:36,424 INFO L748 eck$LassoCheckResult]: Stem: 4440#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 4441#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 4443#L26 main_~i~0#1 := 0; 4444#L29-2 havoc main_#t~nondet1#1; 4448#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 4435#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 4436#L35-2 havoc main_#t~nondet3#1; 4442#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4447#L35-2 havoc main_#t~nondet3#1; 4579#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4578#L35-2 havoc main_#t~nondet3#1; 4577#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4576#L35-2 havoc main_#t~nondet3#1; 4575#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4574#L35-2 havoc main_#t~nondet3#1; 4573#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4572#L35-2 havoc main_#t~nondet3#1; 4571#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4570#L35-2 havoc main_#t~nondet3#1; 4569#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4568#L35-2 havoc main_#t~nondet3#1; 4567#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4566#L35-2 havoc main_#t~nondet3#1; 4565#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4564#L35-2 havoc main_#t~nondet3#1; 4563#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4562#L35-2 havoc main_#t~nondet3#1; 4561#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4560#L35-2 havoc main_#t~nondet3#1; 4559#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4558#L35-2 havoc main_#t~nondet3#1; 4557#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4556#L35-2 havoc main_#t~nondet3#1; 4555#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4554#L35-2 havoc main_#t~nondet3#1; 4553#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4552#L35-2 havoc main_#t~nondet3#1; 4551#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4550#L35-2 havoc main_#t~nondet3#1; 4549#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4548#L35-2 havoc main_#t~nondet3#1; 4547#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4546#L35-2 havoc main_#t~nondet3#1; 4545#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4544#L35-2 havoc main_#t~nondet3#1; 4543#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4542#L35-2 havoc main_#t~nondet3#1; 4541#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4540#L35-2 havoc main_#t~nondet3#1; 4539#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 4538#L35-2 havoc main_#t~nondet3#1; 4446#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 4445#L35-3 assume main_~j~0#1 >= 100; 4434#L32 [2023-11-06 22:40:36,425 INFO L750 eck$LassoCheckResult]: Loop: 4434#L32 assume true; 4434#L32 [2023-11-06 22:40:36,425 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:36,425 INFO L85 PathProgramCache]: Analyzing trace with hash -173936093, now seen corresponding path program 4 times [2023-11-06 22:40:36,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:36,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563518890] [2023-11-06 22:40:36,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:36,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:36,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:37,030 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:37,031 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:37,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563518890] [2023-11-06 22:40:37,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563518890] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:37,031 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1937476350] [2023-11-06 22:40:37,031 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2023-11-06 22:40:37,031 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:37,031 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:37,035 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:37,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2023-11-06 22:40:37,115 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2023-11-06 22:40:37,115 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:37,120 INFO L262 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 24 conjunts are in the unsatisfiable core [2023-11-06 22:40:37,123 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:37,219 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:37,219 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:38,169 INFO L134 CoverageAnalysis]: Checked inductivity of 506 backedges. 0 proven. 506 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:38,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1937476350] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:38,169 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:38,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 48 [2023-11-06 22:40:38,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680567404] [2023-11-06 22:40:38,170 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:38,170 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:38,171 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:38,171 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 10 times [2023-11-06 22:40:38,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:38,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674044290] [2023-11-06 22:40:38,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:38,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:38,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:38,173 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:38,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:38,174 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:38,181 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:38,183 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2023-11-06 22:40:38,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2023-11-06 22:40:38,186 INFO L87 Difference]: Start difference. First operand 147 states and 195 transitions. cyclomatic complexity: 51 Second operand has 49 states, 48 states have (on average 2.1666666666666665) internal successors, (104), 49 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:38,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:38,276 INFO L93 Difference]: Finished difference Result 244 states and 292 transitions. [2023-11-06 22:40:38,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 244 states and 292 transitions. [2023-11-06 22:40:38,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:38,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 244 states to 196 states and 244 transitions. [2023-11-06 22:40:38,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:38,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:38,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196 states and 244 transitions. [2023-11-06 22:40:38,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:38,282 INFO L218 hiAutomatonCegarLoop]: Abstraction has 196 states and 244 transitions. [2023-11-06 22:40:38,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states and 244 transitions. [2023-11-06 22:40:38,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2023-11-06 22:40:38,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2461538461538462) internal successors, (243), 194 states have internal predecessors, (243), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:38,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 243 transitions. [2023-11-06 22:40:38,286 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 243 transitions. [2023-11-06 22:40:38,286 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2023-11-06 22:40:38,287 INFO L428 stractBuchiCegarLoop]: Abstraction has 195 states and 243 transitions. [2023-11-06 22:40:38,287 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:40:38,287 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 243 transitions. [2023-11-06 22:40:38,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:38,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:38,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:38,294 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1] [2023-11-06 22:40:38,294 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:38,296 INFO L748 eck$LassoCheckResult]: Stem: 5195#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 5196#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 5199#L26 main_~i~0#1 := 0; 5200#L29-2 havoc main_#t~nondet1#1; 5193#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5194#L29-2 havoc main_#t~nondet1#1; 5202#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5295#L29-2 havoc main_#t~nondet1#1; 5294#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5293#L29-2 havoc main_#t~nondet1#1; 5292#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5291#L29-2 havoc main_#t~nondet1#1; 5290#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5289#L29-2 havoc main_#t~nondet1#1; 5288#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5287#L29-2 havoc main_#t~nondet1#1; 5286#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5285#L29-2 havoc main_#t~nondet1#1; 5284#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5283#L29-2 havoc main_#t~nondet1#1; 5282#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5281#L29-2 havoc main_#t~nondet1#1; 5280#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5279#L29-2 havoc main_#t~nondet1#1; 5278#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5277#L29-2 havoc main_#t~nondet1#1; 5276#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5275#L29-2 havoc main_#t~nondet1#1; 5274#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5273#L29-2 havoc main_#t~nondet1#1; 5272#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5271#L29-2 havoc main_#t~nondet1#1; 5270#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5269#L29-2 havoc main_#t~nondet1#1; 5268#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5267#L29-2 havoc main_#t~nondet1#1; 5266#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5265#L29-2 havoc main_#t~nondet1#1; 5264#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5263#L29-2 havoc main_#t~nondet1#1; 5262#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5261#L29-2 havoc main_#t~nondet1#1; 5260#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5259#L29-2 havoc main_#t~nondet1#1; 5258#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5257#L29-2 havoc main_#t~nondet1#1; 5256#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5255#L29-2 havoc main_#t~nondet1#1; 5254#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5253#L29-2 havoc main_#t~nondet1#1; 5252#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5251#L29-2 havoc main_#t~nondet1#1; 5250#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5249#L29-2 havoc main_#t~nondet1#1; 5248#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5247#L29-2 havoc main_#t~nondet1#1; 5246#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5245#L29-2 havoc main_#t~nondet1#1; 5244#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5243#L29-2 havoc main_#t~nondet1#1; 5242#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5241#L29-2 havoc main_#t~nondet1#1; 5240#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5239#L29-2 havoc main_#t~nondet1#1; 5238#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5237#L29-2 havoc main_#t~nondet1#1; 5236#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5235#L29-2 havoc main_#t~nondet1#1; 5234#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5233#L29-2 havoc main_#t~nondet1#1; 5232#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5231#L29-2 havoc main_#t~nondet1#1; 5230#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5229#L29-2 havoc main_#t~nondet1#1; 5228#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5227#L29-2 havoc main_#t~nondet1#1; 5226#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5225#L29-2 havoc main_#t~nondet1#1; 5224#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5223#L29-2 havoc main_#t~nondet1#1; 5222#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5221#L29-2 havoc main_#t~nondet1#1; 5220#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5219#L29-2 havoc main_#t~nondet1#1; 5218#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5217#L29-2 havoc main_#t~nondet1#1; 5216#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5215#L29-2 havoc main_#t~nondet1#1; 5214#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5213#L29-2 havoc main_#t~nondet1#1; 5212#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5211#L29-2 havoc main_#t~nondet1#1; 5210#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5209#L29-2 havoc main_#t~nondet1#1; 5206#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 5205#L29-2 havoc main_#t~nondet1#1; 5192#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 5188#L29-3 assume main_~i~0#1 >= 100; 5189#L32 [2023-11-06 22:40:38,299 INFO L750 eck$LassoCheckResult]: Loop: 5189#L32 assume true; 5189#L32 [2023-11-06 22:40:38,302 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:38,302 INFO L85 PathProgramCache]: Analyzing trace with hash -41810454, now seen corresponding path program 5 times [2023-11-06 22:40:38,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:38,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280092234] [2023-11-06 22:40:38,303 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:38,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:38,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:40,107 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:40,107 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:40,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280092234] [2023-11-06 22:40:40,107 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280092234] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:40,107 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [252898636] [2023-11-06 22:40:40,107 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:40:40,108 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:40,108 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:40,111 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:40,131 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2023-11-06 22:40:40,253 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-06 22:40:40,254 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:40,256 INFO L262 TraceCheckSpWp]: Trace formula consists of 253 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-06 22:40:40,262 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:40,530 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:40,530 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:43,831 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:43,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [252898636] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:43,831 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:43,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2023-11-06 22:40:43,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142672852] [2023-11-06 22:40:43,832 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:43,832 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:43,833 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:43,833 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 11 times [2023-11-06 22:40:43,833 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:43,833 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991437967] [2023-11-06 22:40:43,833 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:43,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:43,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:43,836 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:43,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:43,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:43,839 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:43,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-06 22:40:43,845 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-06 22:40:43,846 INFO L87 Difference]: Start difference. First operand 195 states and 243 transitions. cyclomatic complexity: 51 Second operand has 97 states, 96 states have (on average 2.0520833333333335) internal successors, (197), 97 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:46,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:46,834 INFO L93 Difference]: Finished difference Result 7250 states and 7395 transitions. [2023-11-06 22:40:46,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7250 states and 7395 transitions. [2023-11-06 22:40:46,893 INFO L131 ngComponentsAnalysis]: Automaton has 49 accepting balls. 49 [2023-11-06 22:40:46,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7250 states to 7154 states and 7299 transitions. [2023-11-06 22:40:46,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153 [2023-11-06 22:40:46,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153 [2023-11-06 22:40:46,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7154 states and 7299 transitions. [2023-11-06 22:40:46,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:46,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7154 states and 7299 transitions. [2023-11-06 22:40:46,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7154 states and 7299 transitions. [2023-11-06 22:40:46,985 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7154 to 291. [2023-11-06 22:40:46,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 291 states have (on average 1.3298969072164948) internal successors, (387), 290 states have internal predecessors, (387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:46,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 387 transitions. [2023-11-06 22:40:46,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 387 transitions. [2023-11-06 22:40:46,989 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-06 22:40:46,989 INFO L428 stractBuchiCegarLoop]: Abstraction has 291 states and 387 transitions. [2023-11-06 22:40:46,990 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:40:46,990 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 387 transitions. [2023-11-06 22:40:46,992 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:46,992 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:46,992 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:46,994 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [47, 46, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:40:46,994 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:46,994 INFO L748 eck$LassoCheckResult]: Stem: 13319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 13320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 13325#L26 main_~i~0#1 := 0; 13326#L29-2 havoc main_#t~nondet1#1; 13328#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 13317#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 13318#L35-2 havoc main_#t~nondet3#1; 13324#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13331#L35-2 havoc main_#t~nondet3#1; 13605#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13604#L35-2 havoc main_#t~nondet3#1; 13603#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13602#L35-2 havoc main_#t~nondet3#1; 13601#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13600#L35-2 havoc main_#t~nondet3#1; 13599#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13598#L35-2 havoc main_#t~nondet3#1; 13597#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13596#L35-2 havoc main_#t~nondet3#1; 13595#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13594#L35-2 havoc main_#t~nondet3#1; 13593#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13592#L35-2 havoc main_#t~nondet3#1; 13591#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13590#L35-2 havoc main_#t~nondet3#1; 13589#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13588#L35-2 havoc main_#t~nondet3#1; 13587#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13586#L35-2 havoc main_#t~nondet3#1; 13585#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13584#L35-2 havoc main_#t~nondet3#1; 13583#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13582#L35-2 havoc main_#t~nondet3#1; 13581#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13580#L35-2 havoc main_#t~nondet3#1; 13579#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13578#L35-2 havoc main_#t~nondet3#1; 13577#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13576#L35-2 havoc main_#t~nondet3#1; 13575#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13574#L35-2 havoc main_#t~nondet3#1; 13573#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13572#L35-2 havoc main_#t~nondet3#1; 13571#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13570#L35-2 havoc main_#t~nondet3#1; 13569#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13568#L35-2 havoc main_#t~nondet3#1; 13567#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13566#L35-2 havoc main_#t~nondet3#1; 13565#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13564#L35-2 havoc main_#t~nondet3#1; 13563#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13562#L35-2 havoc main_#t~nondet3#1; 13561#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13560#L35-2 havoc main_#t~nondet3#1; 13559#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13558#L35-2 havoc main_#t~nondet3#1; 13557#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13556#L35-2 havoc main_#t~nondet3#1; 13555#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13554#L35-2 havoc main_#t~nondet3#1; 13553#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13552#L35-2 havoc main_#t~nondet3#1; 13551#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13550#L35-2 havoc main_#t~nondet3#1; 13549#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13548#L35-2 havoc main_#t~nondet3#1; 13547#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13546#L35-2 havoc main_#t~nondet3#1; 13545#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13544#L35-2 havoc main_#t~nondet3#1; 13543#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13542#L35-2 havoc main_#t~nondet3#1; 13541#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13540#L35-2 havoc main_#t~nondet3#1; 13539#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13538#L35-2 havoc main_#t~nondet3#1; 13537#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13536#L35-2 havoc main_#t~nondet3#1; 13535#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13534#L35-2 havoc main_#t~nondet3#1; 13533#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13532#L35-2 havoc main_#t~nondet3#1; 13531#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13530#L35-2 havoc main_#t~nondet3#1; 13529#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13528#L35-2 havoc main_#t~nondet3#1; 13527#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13526#L35-2 havoc main_#t~nondet3#1; 13525#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13524#L35-2 havoc main_#t~nondet3#1; 13523#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13522#L35-2 havoc main_#t~nondet3#1; 13521#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13520#L35-2 havoc main_#t~nondet3#1; 13519#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13518#L35-2 havoc main_#t~nondet3#1; 13517#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 13516#L35-2 havoc main_#t~nondet3#1; 13330#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 13327#L35-3 assume main_~j~0#1 >= 100; 13316#L32 [2023-11-06 22:40:46,994 INFO L750 eck$LassoCheckResult]: Loop: 13316#L32 assume true; 13316#L32 [2023-11-06 22:40:46,995 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:46,995 INFO L85 PathProgramCache]: Analyzing trace with hash -174540373, now seen corresponding path program 5 times [2023-11-06 22:40:46,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:46,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304519894] [2023-11-06 22:40:46,996 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:46,996 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:47,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:48,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:48,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:48,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304519894] [2023-11-06 22:40:48,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304519894] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:48,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [43231099] [2023-11-06 22:40:48,869 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2023-11-06 22:40:48,869 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:48,870 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:48,872 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:48,878 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2023-11-06 22:40:49,004 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2023-11-06 22:40:49,005 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:49,008 INFO L262 TraceCheckSpWp]: Trace formula consists of 350 conjuncts, 48 conjunts are in the unsatisfiable core [2023-11-06 22:40:49,013 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:49,209 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:49,209 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:40:52,476 INFO L134 CoverageAnalysis]: Checked inductivity of 2162 backedges. 0 proven. 2162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:52,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [43231099] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:40:52,476 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:40:52,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 96 [2023-11-06 22:40:52,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752003039] [2023-11-06 22:40:52,477 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:40:52,478 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:40:52,478 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:52,478 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 12 times [2023-11-06 22:40:52,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:52,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991574889] [2023-11-06 22:40:52,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:52,479 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:52,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:52,480 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:40:52,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:40:52,481 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:40:52,484 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:40:52,486 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2023-11-06 22:40:52,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2023-11-06 22:40:52,491 INFO L87 Difference]: Start difference. First operand 291 states and 387 transitions. cyclomatic complexity: 99 Second operand has 97 states, 96 states have (on average 2.0833333333333335) internal successors, (200), 97 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:52,789 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:40:52,789 INFO L93 Difference]: Finished difference Result 484 states and 580 transitions. [2023-11-06 22:40:52,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 484 states and 580 transitions. [2023-11-06 22:40:52,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:52,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 484 states to 388 states and 484 transitions. [2023-11-06 22:40:52,797 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:40:52,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:40:52,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 484 transitions. [2023-11-06 22:40:52,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:40:52,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 484 transitions. [2023-11-06 22:40:52,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 484 transitions. [2023-11-06 22:40:52,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 387. [2023-11-06 22:40:52,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 387 states, 387 states have (on average 1.248062015503876) internal successors, (483), 386 states have internal predecessors, (483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:40:52,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 483 transitions. [2023-11-06 22:40:52,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 387 states and 483 transitions. [2023-11-06 22:40:52,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2023-11-06 22:40:52,807 INFO L428 stractBuchiCegarLoop]: Abstraction has 387 states and 483 transitions. [2023-11-06 22:40:52,807 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:40:52,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 483 transitions. [2023-11-06 22:40:52,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:40:52,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:40:52,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:40:52,812 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1] [2023-11-06 22:40:52,812 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:40:52,813 INFO L748 eck$LassoCheckResult]: Stem: 14797#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 14798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 14801#L26 main_~i~0#1 := 0; 14802#L29-2 havoc main_#t~nondet1#1; 14795#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14796#L29-2 havoc main_#t~nondet1#1; 14804#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14993#L29-2 havoc main_#t~nondet1#1; 14992#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14991#L29-2 havoc main_#t~nondet1#1; 14990#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14989#L29-2 havoc main_#t~nondet1#1; 14988#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14987#L29-2 havoc main_#t~nondet1#1; 14986#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14985#L29-2 havoc main_#t~nondet1#1; 14984#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14983#L29-2 havoc main_#t~nondet1#1; 14982#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14981#L29-2 havoc main_#t~nondet1#1; 14980#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14979#L29-2 havoc main_#t~nondet1#1; 14978#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14977#L29-2 havoc main_#t~nondet1#1; 14976#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14975#L29-2 havoc main_#t~nondet1#1; 14974#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14973#L29-2 havoc main_#t~nondet1#1; 14972#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14971#L29-2 havoc main_#t~nondet1#1; 14970#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14969#L29-2 havoc main_#t~nondet1#1; 14968#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14967#L29-2 havoc main_#t~nondet1#1; 14966#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14965#L29-2 havoc main_#t~nondet1#1; 14964#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14963#L29-2 havoc main_#t~nondet1#1; 14962#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14961#L29-2 havoc main_#t~nondet1#1; 14960#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14959#L29-2 havoc main_#t~nondet1#1; 14958#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14957#L29-2 havoc main_#t~nondet1#1; 14956#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14955#L29-2 havoc main_#t~nondet1#1; 14954#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14953#L29-2 havoc main_#t~nondet1#1; 14952#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14951#L29-2 havoc main_#t~nondet1#1; 14950#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14949#L29-2 havoc main_#t~nondet1#1; 14948#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14947#L29-2 havoc main_#t~nondet1#1; 14946#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14945#L29-2 havoc main_#t~nondet1#1; 14944#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14943#L29-2 havoc main_#t~nondet1#1; 14942#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14941#L29-2 havoc main_#t~nondet1#1; 14940#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14939#L29-2 havoc main_#t~nondet1#1; 14938#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14937#L29-2 havoc main_#t~nondet1#1; 14936#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14935#L29-2 havoc main_#t~nondet1#1; 14934#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14933#L29-2 havoc main_#t~nondet1#1; 14932#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14931#L29-2 havoc main_#t~nondet1#1; 14930#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14929#L29-2 havoc main_#t~nondet1#1; 14928#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14927#L29-2 havoc main_#t~nondet1#1; 14926#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14925#L29-2 havoc main_#t~nondet1#1; 14924#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14923#L29-2 havoc main_#t~nondet1#1; 14922#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14921#L29-2 havoc main_#t~nondet1#1; 14920#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14919#L29-2 havoc main_#t~nondet1#1; 14918#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14917#L29-2 havoc main_#t~nondet1#1; 14916#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14915#L29-2 havoc main_#t~nondet1#1; 14914#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14913#L29-2 havoc main_#t~nondet1#1; 14912#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14911#L29-2 havoc main_#t~nondet1#1; 14910#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14909#L29-2 havoc main_#t~nondet1#1; 14908#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14907#L29-2 havoc main_#t~nondet1#1; 14906#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14905#L29-2 havoc main_#t~nondet1#1; 14904#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14903#L29-2 havoc main_#t~nondet1#1; 14902#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14901#L29-2 havoc main_#t~nondet1#1; 14900#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14899#L29-2 havoc main_#t~nondet1#1; 14898#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14897#L29-2 havoc main_#t~nondet1#1; 14896#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14895#L29-2 havoc main_#t~nondet1#1; 14894#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14893#L29-2 havoc main_#t~nondet1#1; 14892#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14891#L29-2 havoc main_#t~nondet1#1; 14890#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14889#L29-2 havoc main_#t~nondet1#1; 14888#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14887#L29-2 havoc main_#t~nondet1#1; 14886#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14885#L29-2 havoc main_#t~nondet1#1; 14884#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14883#L29-2 havoc main_#t~nondet1#1; 14882#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14881#L29-2 havoc main_#t~nondet1#1; 14880#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14879#L29-2 havoc main_#t~nondet1#1; 14878#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14877#L29-2 havoc main_#t~nondet1#1; 14876#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14875#L29-2 havoc main_#t~nondet1#1; 14874#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14873#L29-2 havoc main_#t~nondet1#1; 14872#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14871#L29-2 havoc main_#t~nondet1#1; 14870#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14869#L29-2 havoc main_#t~nondet1#1; 14868#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14867#L29-2 havoc main_#t~nondet1#1; 14866#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14865#L29-2 havoc main_#t~nondet1#1; 14864#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14863#L29-2 havoc main_#t~nondet1#1; 14862#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14861#L29-2 havoc main_#t~nondet1#1; 14860#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14859#L29-2 havoc main_#t~nondet1#1; 14858#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14857#L29-2 havoc main_#t~nondet1#1; 14856#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14855#L29-2 havoc main_#t~nondet1#1; 14854#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14853#L29-2 havoc main_#t~nondet1#1; 14852#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14851#L29-2 havoc main_#t~nondet1#1; 14850#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14849#L29-2 havoc main_#t~nondet1#1; 14848#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14847#L29-2 havoc main_#t~nondet1#1; 14846#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14845#L29-2 havoc main_#t~nondet1#1; 14844#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14843#L29-2 havoc main_#t~nondet1#1; 14842#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14841#L29-2 havoc main_#t~nondet1#1; 14840#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14839#L29-2 havoc main_#t~nondet1#1; 14838#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14837#L29-2 havoc main_#t~nondet1#1; 14836#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14835#L29-2 havoc main_#t~nondet1#1; 14834#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14833#L29-2 havoc main_#t~nondet1#1; 14832#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14831#L29-2 havoc main_#t~nondet1#1; 14830#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14829#L29-2 havoc main_#t~nondet1#1; 14828#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14827#L29-2 havoc main_#t~nondet1#1; 14826#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14825#L29-2 havoc main_#t~nondet1#1; 14824#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14823#L29-2 havoc main_#t~nondet1#1; 14822#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14821#L29-2 havoc main_#t~nondet1#1; 14820#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14819#L29-2 havoc main_#t~nondet1#1; 14818#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14817#L29-2 havoc main_#t~nondet1#1; 14816#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14815#L29-2 havoc main_#t~nondet1#1; 14814#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14813#L29-2 havoc main_#t~nondet1#1; 14812#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14811#L29-2 havoc main_#t~nondet1#1; 14808#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 14807#L29-2 havoc main_#t~nondet1#1; 14794#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 14790#L29-3 assume main_~i~0#1 >= 100; 14791#L32 [2023-11-06 22:40:52,813 INFO L750 eck$LassoCheckResult]: Loop: 14791#L32 assume true; 14791#L32 [2023-11-06 22:40:52,814 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:40:52,814 INFO L85 PathProgramCache]: Analyzing trace with hash 1558585082, now seen corresponding path program 6 times [2023-11-06 22:40:52,814 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:40:52,814 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960048912] [2023-11-06 22:40:52,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:40:52,815 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:40:52,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:40:59,033 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:59,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:40:59,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960048912] [2023-11-06 22:40:59,034 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960048912] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:40:59,034 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1872426978] [2023-11-06 22:40:59,034 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-06 22:40:59,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:40:59,034 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:40:59,037 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:40:59,040 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2023-11-06 22:40:59,226 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2023-11-06 22:40:59,226 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:40:59,230 INFO L262 TraceCheckSpWp]: Trace formula consists of 493 conjuncts, 96 conjunts are in the unsatisfiable core [2023-11-06 22:40:59,236 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:40:59,601 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:40:59,602 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:41:04,471 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:41:04,475 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1872426978] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:41:04,475 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:41:04,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2023-11-06 22:41:04,476 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447278422] [2023-11-06 22:41:04,476 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:41:04,477 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:41:04,477 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:04,477 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 13 times [2023-11-06 22:41:04,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:04,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051706169] [2023-11-06 22:41:04,478 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:04,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:04,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:04,480 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:04,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:04,481 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:41:04,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:41:04,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2023-11-06 22:41:04,488 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2023-11-06 22:41:04,489 INFO L87 Difference]: Start difference. First operand 387 states and 483 transitions. cyclomatic complexity: 99 Second operand has 103 states, 102 states have (on average 2.0588235294117645) internal successors, (210), 103 states have internal predecessors, (210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:41:07,549 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:41:07,549 INFO L93 Difference]: Finished difference Result 10592 states and 10701 transitions. [2023-11-06 22:41:07,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10592 states and 10701 transitions. [2023-11-06 22:41:07,617 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 7 [2023-11-06 22:41:07,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10592 states to 10580 states and 10689 transitions. [2023-11-06 22:41:07,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2023-11-06 22:41:07,685 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2023-11-06 22:41:07,685 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10580 states and 10689 transitions. [2023-11-06 22:41:07,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:41:07,695 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10580 states and 10689 transitions. [2023-11-06 22:41:07,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10580 states and 10689 transitions. [2023-11-06 22:41:07,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10580 to 399. [2023-11-06 22:41:07,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 399 states, 399 states have (on average 1.255639097744361) internal successors, (501), 398 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:41:07,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 399 states to 399 states and 501 transitions. [2023-11-06 22:41:07,806 INFO L240 hiAutomatonCegarLoop]: Abstraction has 399 states and 501 transitions. [2023-11-06 22:41:07,815 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2023-11-06 22:41:07,816 INFO L428 stractBuchiCegarLoop]: Abstraction has 399 states and 501 transitions. [2023-11-06 22:41:07,816 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:41:07,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states and 501 transitions. [2023-11-06 22:41:07,818 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:41:07,818 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:41:07,818 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:41:07,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [95, 94, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:41:07,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:41:07,824 INFO L748 eck$LassoCheckResult]: Stem: 27037#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 27038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 27043#L26 main_~i~0#1 := 0; 27044#L29-2 havoc main_#t~nondet1#1; 27046#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 27035#L29-3 assume !(main_~i~0#1 >= 100);main_~j~0#1 := 0; 27036#L35-2 havoc main_#t~nondet3#1; 27042#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27049#L35-2 havoc main_#t~nondet3#1; 27431#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27430#L35-2 havoc main_#t~nondet3#1; 27429#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27428#L35-2 havoc main_#t~nondet3#1; 27427#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27426#L35-2 havoc main_#t~nondet3#1; 27425#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27424#L35-2 havoc main_#t~nondet3#1; 27423#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27422#L35-2 havoc main_#t~nondet3#1; 27421#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27420#L35-2 havoc main_#t~nondet3#1; 27419#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27418#L35-2 havoc main_#t~nondet3#1; 27417#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27416#L35-2 havoc main_#t~nondet3#1; 27415#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27414#L35-2 havoc main_#t~nondet3#1; 27413#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27412#L35-2 havoc main_#t~nondet3#1; 27411#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27410#L35-2 havoc main_#t~nondet3#1; 27409#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27408#L35-2 havoc main_#t~nondet3#1; 27407#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27406#L35-2 havoc main_#t~nondet3#1; 27405#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27404#L35-2 havoc main_#t~nondet3#1; 27403#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27402#L35-2 havoc main_#t~nondet3#1; 27401#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27400#L35-2 havoc main_#t~nondet3#1; 27399#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27398#L35-2 havoc main_#t~nondet3#1; 27397#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27396#L35-2 havoc main_#t~nondet3#1; 27395#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27394#L35-2 havoc main_#t~nondet3#1; 27393#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27392#L35-2 havoc main_#t~nondet3#1; 27391#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27390#L35-2 havoc main_#t~nondet3#1; 27389#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27388#L35-2 havoc main_#t~nondet3#1; 27387#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27386#L35-2 havoc main_#t~nondet3#1; 27385#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27384#L35-2 havoc main_#t~nondet3#1; 27383#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27382#L35-2 havoc main_#t~nondet3#1; 27381#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27380#L35-2 havoc main_#t~nondet3#1; 27379#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27378#L35-2 havoc main_#t~nondet3#1; 27377#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27376#L35-2 havoc main_#t~nondet3#1; 27375#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27374#L35-2 havoc main_#t~nondet3#1; 27373#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27372#L35-2 havoc main_#t~nondet3#1; 27371#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27370#L35-2 havoc main_#t~nondet3#1; 27369#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27368#L35-2 havoc main_#t~nondet3#1; 27367#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27366#L35-2 havoc main_#t~nondet3#1; 27365#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27364#L35-2 havoc main_#t~nondet3#1; 27363#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27362#L35-2 havoc main_#t~nondet3#1; 27361#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27360#L35-2 havoc main_#t~nondet3#1; 27359#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27358#L35-2 havoc main_#t~nondet3#1; 27357#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27356#L35-2 havoc main_#t~nondet3#1; 27355#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27354#L35-2 havoc main_#t~nondet3#1; 27353#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27352#L35-2 havoc main_#t~nondet3#1; 27351#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27350#L35-2 havoc main_#t~nondet3#1; 27349#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27348#L35-2 havoc main_#t~nondet3#1; 27347#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27346#L35-2 havoc main_#t~nondet3#1; 27345#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27344#L35-2 havoc main_#t~nondet3#1; 27343#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27342#L35-2 havoc main_#t~nondet3#1; 27341#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27340#L35-2 havoc main_#t~nondet3#1; 27339#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27338#L35-2 havoc main_#t~nondet3#1; 27337#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27336#L35-2 havoc main_#t~nondet3#1; 27335#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27334#L35-2 havoc main_#t~nondet3#1; 27333#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27332#L35-2 havoc main_#t~nondet3#1; 27331#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27330#L35-2 havoc main_#t~nondet3#1; 27329#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27328#L35-2 havoc main_#t~nondet3#1; 27327#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27326#L35-2 havoc main_#t~nondet3#1; 27325#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27324#L35-2 havoc main_#t~nondet3#1; 27323#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27322#L35-2 havoc main_#t~nondet3#1; 27321#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27320#L35-2 havoc main_#t~nondet3#1; 27319#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27318#L35-2 havoc main_#t~nondet3#1; 27317#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27316#L35-2 havoc main_#t~nondet3#1; 27315#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27314#L35-2 havoc main_#t~nondet3#1; 27313#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27312#L35-2 havoc main_#t~nondet3#1; 27311#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27310#L35-2 havoc main_#t~nondet3#1; 27309#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27308#L35-2 havoc main_#t~nondet3#1; 27307#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27306#L35-2 havoc main_#t~nondet3#1; 27305#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27304#L35-2 havoc main_#t~nondet3#1; 27303#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27302#L35-2 havoc main_#t~nondet3#1; 27301#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27300#L35-2 havoc main_#t~nondet3#1; 27299#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27298#L35-2 havoc main_#t~nondet3#1; 27297#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27296#L35-2 havoc main_#t~nondet3#1; 27295#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27294#L35-2 havoc main_#t~nondet3#1; 27293#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27292#L35-2 havoc main_#t~nondet3#1; 27291#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27290#L35-2 havoc main_#t~nondet3#1; 27289#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27288#L35-2 havoc main_#t~nondet3#1; 27287#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27286#L35-2 havoc main_#t~nondet3#1; 27285#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27284#L35-2 havoc main_#t~nondet3#1; 27283#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27282#L35-2 havoc main_#t~nondet3#1; 27281#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27280#L35-2 havoc main_#t~nondet3#1; 27279#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27278#L35-2 havoc main_#t~nondet3#1; 27277#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27276#L35-2 havoc main_#t~nondet3#1; 27275#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27274#L35-2 havoc main_#t~nondet3#1; 27273#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27272#L35-2 havoc main_#t~nondet3#1; 27271#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27270#L35-2 havoc main_#t~nondet3#1; 27269#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27268#L35-2 havoc main_#t~nondet3#1; 27267#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27266#L35-2 havoc main_#t~nondet3#1; 27265#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27264#L35-2 havoc main_#t~nondet3#1; 27263#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27262#L35-2 havoc main_#t~nondet3#1; 27261#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27260#L35-2 havoc main_#t~nondet3#1; 27259#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27258#L35-2 havoc main_#t~nondet3#1; 27257#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27256#L35-2 havoc main_#t~nondet3#1; 27255#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27254#L35-2 havoc main_#t~nondet3#1; 27253#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27252#L35-2 havoc main_#t~nondet3#1; 27251#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27250#L35-2 havoc main_#t~nondet3#1; 27249#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27248#L35-2 havoc main_#t~nondet3#1; 27247#L35 assume !!(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1;main_#t~post4#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post4#1;havoc main_#t~post4#1;main_#t~post5#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post5#1;havoc main_#t~post5#1; 27246#L35-2 havoc main_#t~nondet3#1; 27048#L35 assume !(0 != main_#t~nondet3#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet3#1; 27045#L35-3 assume main_~j~0#1 >= 100; 27034#L32 [2023-11-06 22:41:07,825 INFO L750 eck$LassoCheckResult]: Loop: 27034#L32 assume true; 27034#L32 [2023-11-06 22:41:07,825 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:07,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1679145147, now seen corresponding path program 6 times [2023-11-06 22:41:07,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:07,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841492256] [2023-11-06 22:41:07,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:07,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:07,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:41:13,834 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:41:13,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:41:13,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841492256] [2023-11-06 22:41:13,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841492256] provided 0 perfect and 1 imperfect interpolant sequences [2023-11-06 22:41:13,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [208409631] [2023-11-06 22:41:13,836 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2023-11-06 22:41:13,836 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2023-11-06 22:41:13,836 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:41:13,837 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2023-11-06 22:41:13,840 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2023-11-06 22:41:14,098 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 95 check-sat command(s) [2023-11-06 22:41:14,098 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2023-11-06 22:41:14,104 INFO L262 TraceCheckSpWp]: Trace formula consists of 686 conjuncts, 96 conjunts are in the unsatisfiable core [2023-11-06 22:41:14,111 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-06 22:41:14,433 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:41:14,434 INFO L327 TraceCheckSpWp]: Computing backward predicates... [2023-11-06 22:41:18,997 INFO L134 CoverageAnalysis]: Checked inductivity of 8930 backedges. 0 proven. 8930 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:41:18,998 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [208409631] provided 0 perfect and 2 imperfect interpolant sequences [2023-11-06 22:41:18,998 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2023-11-06 22:41:18,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96, 96] total 102 [2023-11-06 22:41:18,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901829297] [2023-11-06 22:41:18,999 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2023-11-06 22:41:18,999 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:41:19,000 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:19,000 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 14 times [2023-11-06 22:41:19,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:19,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091617821] [2023-11-06 22:41:19,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:19,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:19,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,003 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:19,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,004 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:41:19,007 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:41:19,009 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2023-11-06 22:41:19,013 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2023-11-06 22:41:19,014 INFO L87 Difference]: Start difference. First operand 399 states and 501 transitions. cyclomatic complexity: 105 Second operand has 103 states, 102 states have (on average 2.088235294117647) internal successors, (213), 103 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:41:19,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:41:19,198 INFO L93 Difference]: Finished difference Result 424 states and 526 transitions. [2023-11-06 22:41:19,198 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424 states and 526 transitions. [2023-11-06 22:41:19,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:41:19,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424 states to 412 states and 514 transitions. [2023-11-06 22:41:19,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2023-11-06 22:41:19,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2023-11-06 22:41:19,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 412 states and 514 transitions. [2023-11-06 22:41:19,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-06 22:41:19,204 INFO L218 hiAutomatonCegarLoop]: Abstraction has 412 states and 514 transitions. [2023-11-06 22:41:19,205 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states and 514 transitions. [2023-11-06 22:41:19,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 411. [2023-11-06 22:41:19,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.2481751824817517) internal successors, (513), 410 states have internal predecessors, (513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:41:19,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 513 transitions. [2023-11-06 22:41:19,242 INFO L240 hiAutomatonCegarLoop]: Abstraction has 411 states and 513 transitions. [2023-11-06 22:41:19,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2023-11-06 22:41:19,242 INFO L428 stractBuchiCegarLoop]: Abstraction has 411 states and 513 transitions. [2023-11-06 22:41:19,243 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:41:19,243 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 513 transitions. [2023-11-06 22:41:19,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1 [2023-11-06 22:41:19,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:41:19,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:41:19,250 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [101, 100, 1, 1, 1, 1, 1] [2023-11-06 22:41:19,250 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2023-11-06 22:41:19,250 INFO L748 eck$LassoCheckResult]: Stem: 29142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(9, 2); 29143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~post2#1, main_#t~nondet1#1, main_#t~post4#1, main_#t~post5#1, main_#t~nondet3#1, main_~i~0#1, main_~j~0#1;havoc main_~i~0#1;havoc main_~j~0#1; 29149#L26 main_~i~0#1 := 0; 29150#L29-2 havoc main_#t~nondet1#1; 29145#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29146#L29-2 havoc main_#t~nondet1#1; 29152#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29353#L29-2 havoc main_#t~nondet1#1; 29352#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29351#L29-2 havoc main_#t~nondet1#1; 29350#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29349#L29-2 havoc main_#t~nondet1#1; 29348#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29347#L29-2 havoc main_#t~nondet1#1; 29346#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29345#L29-2 havoc main_#t~nondet1#1; 29344#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29343#L29-2 havoc main_#t~nondet1#1; 29342#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29341#L29-2 havoc main_#t~nondet1#1; 29340#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29339#L29-2 havoc main_#t~nondet1#1; 29338#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29337#L29-2 havoc main_#t~nondet1#1; 29336#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29335#L29-2 havoc main_#t~nondet1#1; 29334#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29333#L29-2 havoc main_#t~nondet1#1; 29332#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29331#L29-2 havoc main_#t~nondet1#1; 29330#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29329#L29-2 havoc main_#t~nondet1#1; 29328#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29327#L29-2 havoc main_#t~nondet1#1; 29326#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29325#L29-2 havoc main_#t~nondet1#1; 29324#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29323#L29-2 havoc main_#t~nondet1#1; 29322#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29321#L29-2 havoc main_#t~nondet1#1; 29320#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29319#L29-2 havoc main_#t~nondet1#1; 29318#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29317#L29-2 havoc main_#t~nondet1#1; 29316#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29315#L29-2 havoc main_#t~nondet1#1; 29314#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29313#L29-2 havoc main_#t~nondet1#1; 29312#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29311#L29-2 havoc main_#t~nondet1#1; 29310#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29309#L29-2 havoc main_#t~nondet1#1; 29308#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29307#L29-2 havoc main_#t~nondet1#1; 29306#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29305#L29-2 havoc main_#t~nondet1#1; 29304#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29303#L29-2 havoc main_#t~nondet1#1; 29302#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29301#L29-2 havoc main_#t~nondet1#1; 29300#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29299#L29-2 havoc main_#t~nondet1#1; 29298#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29297#L29-2 havoc main_#t~nondet1#1; 29296#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29295#L29-2 havoc main_#t~nondet1#1; 29294#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29293#L29-2 havoc main_#t~nondet1#1; 29292#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29291#L29-2 havoc main_#t~nondet1#1; 29290#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29289#L29-2 havoc main_#t~nondet1#1; 29288#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29287#L29-2 havoc main_#t~nondet1#1; 29286#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29285#L29-2 havoc main_#t~nondet1#1; 29284#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29283#L29-2 havoc main_#t~nondet1#1; 29282#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29281#L29-2 havoc main_#t~nondet1#1; 29280#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29279#L29-2 havoc main_#t~nondet1#1; 29278#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29277#L29-2 havoc main_#t~nondet1#1; 29276#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29275#L29-2 havoc main_#t~nondet1#1; 29274#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29273#L29-2 havoc main_#t~nondet1#1; 29272#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29271#L29-2 havoc main_#t~nondet1#1; 29270#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29269#L29-2 havoc main_#t~nondet1#1; 29268#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29267#L29-2 havoc main_#t~nondet1#1; 29266#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29265#L29-2 havoc main_#t~nondet1#1; 29264#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29263#L29-2 havoc main_#t~nondet1#1; 29262#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29261#L29-2 havoc main_#t~nondet1#1; 29260#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29259#L29-2 havoc main_#t~nondet1#1; 29258#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29257#L29-2 havoc main_#t~nondet1#1; 29256#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29255#L29-2 havoc main_#t~nondet1#1; 29254#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29253#L29-2 havoc main_#t~nondet1#1; 29252#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29251#L29-2 havoc main_#t~nondet1#1; 29250#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29249#L29-2 havoc main_#t~nondet1#1; 29248#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29247#L29-2 havoc main_#t~nondet1#1; 29246#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29245#L29-2 havoc main_#t~nondet1#1; 29244#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29243#L29-2 havoc main_#t~nondet1#1; 29242#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29241#L29-2 havoc main_#t~nondet1#1; 29240#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29239#L29-2 havoc main_#t~nondet1#1; 29238#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29237#L29-2 havoc main_#t~nondet1#1; 29236#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29235#L29-2 havoc main_#t~nondet1#1; 29234#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29233#L29-2 havoc main_#t~nondet1#1; 29232#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29231#L29-2 havoc main_#t~nondet1#1; 29230#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29229#L29-2 havoc main_#t~nondet1#1; 29228#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29227#L29-2 havoc main_#t~nondet1#1; 29226#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29225#L29-2 havoc main_#t~nondet1#1; 29224#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29223#L29-2 havoc main_#t~nondet1#1; 29222#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29221#L29-2 havoc main_#t~nondet1#1; 29220#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29219#L29-2 havoc main_#t~nondet1#1; 29218#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29217#L29-2 havoc main_#t~nondet1#1; 29216#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29215#L29-2 havoc main_#t~nondet1#1; 29214#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29213#L29-2 havoc main_#t~nondet1#1; 29212#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29211#L29-2 havoc main_#t~nondet1#1; 29210#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29209#L29-2 havoc main_#t~nondet1#1; 29208#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29207#L29-2 havoc main_#t~nondet1#1; 29206#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29205#L29-2 havoc main_#t~nondet1#1; 29204#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29203#L29-2 havoc main_#t~nondet1#1; 29202#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29201#L29-2 havoc main_#t~nondet1#1; 29200#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29199#L29-2 havoc main_#t~nondet1#1; 29198#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29197#L29-2 havoc main_#t~nondet1#1; 29196#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29195#L29-2 havoc main_#t~nondet1#1; 29194#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29193#L29-2 havoc main_#t~nondet1#1; 29192#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29191#L29-2 havoc main_#t~nondet1#1; 29190#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29189#L29-2 havoc main_#t~nondet1#1; 29188#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29187#L29-2 havoc main_#t~nondet1#1; 29186#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29185#L29-2 havoc main_#t~nondet1#1; 29184#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29183#L29-2 havoc main_#t~nondet1#1; 29182#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29181#L29-2 havoc main_#t~nondet1#1; 29180#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29179#L29-2 havoc main_#t~nondet1#1; 29178#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29177#L29-2 havoc main_#t~nondet1#1; 29176#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29175#L29-2 havoc main_#t~nondet1#1; 29174#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29173#L29-2 havoc main_#t~nondet1#1; 29172#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29171#L29-2 havoc main_#t~nondet1#1; 29170#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29169#L29-2 havoc main_#t~nondet1#1; 29168#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29167#L29-2 havoc main_#t~nondet1#1; 29166#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29165#L29-2 havoc main_#t~nondet1#1; 29164#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29163#L29-2 havoc main_#t~nondet1#1; 29160#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29159#L29-2 havoc main_#t~nondet1#1; 29158#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29157#L29-2 havoc main_#t~nondet1#1; 29156#L29 assume !!(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1;main_#t~post2#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post2#1;havoc main_#t~post2#1; 29155#L29-2 havoc main_#t~nondet1#1; 29144#L29 assume !(0 != main_#t~nondet1#1 && main_~i~0#1 < 1000000);havoc main_#t~nondet1#1; 29138#L29-3 assume main_~i~0#1 >= 100; 29139#L32 [2023-11-06 22:41:19,251 INFO L750 eck$LassoCheckResult]: Loop: 29139#L32 assume true; 29139#L32 [2023-11-06 22:41:19,251 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:19,251 INFO L85 PathProgramCache]: Analyzing trace with hash -608770916, now seen corresponding path program 7 times [2023-11-06 22:41:19,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:19,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006480513] [2023-11-06 22:41:19,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:19,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:19,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,335 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:19,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,468 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:41:19,468 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:19,468 INFO L85 PathProgramCache]: Analyzing trace with hash 93, now seen corresponding path program 15 times [2023-11-06 22:41:19,469 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:19,469 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061706728] [2023-11-06 22:41:19,469 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:19,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:19,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,472 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:19,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,474 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:41:19,474 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:41:19,474 INFO L85 PathProgramCache]: Analyzing trace with hash -1692029150, now seen corresponding path program 1 times [2023-11-06 22:41:19,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:41:19,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596059771] [2023-11-06 22:41:19,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:41:19,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:41:19,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,536 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:19,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:19,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:41:27,357 WARN L293 SmtUtils]: Spent 7.68s on a formula simplification. DAG size of input: 735 DAG size of output: 630 (called from [L 279] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.cfg.transitions.TransFormulaUtils.sequentialComposition) [2023-11-06 22:41:34,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:34,651 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:41:34,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:41:34,929 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:41:34 BoogieIcfgContainer [2023-11-06 22:41:34,929 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:41:34,929 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:41:34,930 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:41:34,930 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:41:34,931 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:40:29" (3/4) ... [2023-11-06 22:41:34,932 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:41:35,035 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:41:35,036 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:41:35,036 INFO L158 Benchmark]: Toolchain (without parser) took 66564.21ms. Allocated memory was 165.7MB in the beginning and 599.8MB in the end (delta: 434.1MB). Free memory was 128.5MB in the beginning and 379.1MB in the end (delta: -250.6MB). Peak memory consumption was 186.7MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,037 INFO L158 Benchmark]: CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory is still 67.9MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:41:35,037 INFO L158 Benchmark]: CACSL2BoogieTranslator took 300.70ms. Allocated memory is still 165.7MB. Free memory was 128.0MB in the beginning and 117.5MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,037 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.22ms. Allocated memory is still 165.7MB. Free memory was 117.5MB in the beginning and 115.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,038 INFO L158 Benchmark]: Boogie Preprocessor took 24.36ms. Allocated memory is still 165.7MB. Free memory was 115.9MB in the beginning and 115.4MB in the end (delta: 547.9kB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:41:35,038 INFO L158 Benchmark]: RCFGBuilder took 294.47ms. Allocated memory is still 165.7MB. Free memory was 114.9MB in the beginning and 105.5MB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,038 INFO L158 Benchmark]: BuchiAutomizer took 65791.24ms. Allocated memory was 165.7MB in the beginning and 599.8MB in the end (delta: 434.1MB). Free memory was 105.5MB in the beginning and 384.4MB in the end (delta: -278.9MB). Peak memory consumption was 157.4MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,039 INFO L158 Benchmark]: Witness Printer took 106.18ms. Allocated memory is still 599.8MB. Free memory was 384.4MB in the beginning and 379.1MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-06 22:41:35,041 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31ms. Allocated memory is still 117.4MB. Free memory is still 67.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 300.70ms. Allocated memory is still 165.7MB. Free memory was 128.0MB in the beginning and 117.5MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.22ms. Allocated memory is still 165.7MB. Free memory was 117.5MB in the beginning and 115.9MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 24.36ms. Allocated memory is still 165.7MB. Free memory was 115.9MB in the beginning and 115.4MB in the end (delta: 547.9kB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 294.47ms. Allocated memory is still 165.7MB. Free memory was 114.9MB in the beginning and 105.5MB in the end (delta: 9.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 65791.24ms. Allocated memory was 165.7MB in the beginning and 599.8MB in the end (delta: 434.1MB). Free memory was 105.5MB in the beginning and 384.4MB in the end (delta: -278.9MB). Peak memory consumption was 157.4MB. Max. memory is 16.1GB. * Witness Printer took 106.18ms. Allocated memory is still 599.8MB. Free memory was 384.4MB in the beginning and 379.1MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-2 * i) + 1999999) and consists of 4 locations. 14 modules have a trivial ranking function, the largest among these consists of 103 locations. The remainder module has 411 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 65.5s and 16 iterations. TraceHistogramMax:101. Analysis of lassos took 56.4s. Construction of modules took 2.0s. Büchi inclusion checks took 6.8s. Highest rank in rank-based complementation 3. Minimization of det autom 0. Minimization of nondet autom 15. Automata minimization 0.3s AutomataMinimizationTime, 15 MinimizatonAttempts, 19319 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 0.3s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4244 SdHoareTripleChecker+Valid, 2.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4243 mSDsluCounter, 1572 SdHoareTripleChecker+Invalid, 2.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1419 mSDsCounter, 1227 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 1672 IncrementalHoareTripleChecker+Invalid, 2899 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1227 mSolverCounterUnsat, 153 mSDtfsCounter, 1672 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT1 conc0 concLT0 SILN14 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital10 mio100 ax100 hnf100 lsp100 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq160 hnf93 smp100 dnf100 smp100 tf113 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: sat Degree: 0 Time: 87ms VariablesStem: 0 VariablesLoop: 2 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 24]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 VAL [i=100] Loop: [L32] STUCK: goto STUCK; End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 24]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int i, j; [L27] i = 0 VAL [i=0] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=1] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=2] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=3] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=4] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=5] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=6] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=7] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=8] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=9] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=10] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=11] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=12] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=13] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=14] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=15] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=16] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=17] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=18] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=19] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=20] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=21] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=22] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=23] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=24] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=25] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=26] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=27] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=28] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=29] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=30] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=31] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=32] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=33] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=34] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=35] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=36] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=37] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=38] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=39] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=40] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=41] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=42] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=43] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=44] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=45] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=46] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=47] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=48] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=49] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=50] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=51] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=52] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=53] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=54] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=55] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=56] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=57] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=58] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=59] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=60] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=61] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=62] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=63] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=64] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=65] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=66] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=67] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=68] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=69] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=70] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=71] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=72] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=73] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=74] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=75] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=76] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=77] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=78] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=79] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=80] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=81] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=82] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=83] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=84] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=85] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=86] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=87] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=88] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=89] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=90] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=91] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=92] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=93] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=94] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=95] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=96] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=97] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=98] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=99] [L29] COND TRUE __VERIFIER_nondet_int() && i < 1000000 [L30] i++ VAL [i=100] [L29] COND FALSE !(__VERIFIER_nondet_int() && i < 1000000) [L32] COND TRUE i >= 100 VAL [i=100] Loop: [L32] STUCK: goto STUCK; End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:41:35,140 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:35,339 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:35,539 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:35,739 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:35,940 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:36,141 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:36,339 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:36,539 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:36,740 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:36,939 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:37,139 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:37,340 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2023-11-06 22:41:37,542 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0d9d782-1f29-4b13-85b2-eeb9968e144f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)