./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:27:02,399 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:27:02,491 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:27:02,496 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:27:02,497 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:27:02,522 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:27:02,523 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:27:02,524 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:27:02,525 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:27:02,525 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:27:02,526 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:27:02,527 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:27:02,527 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:27:02,528 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:27:02,528 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:27:02,529 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:27:02,530 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:27:02,530 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:27:02,531 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:27:02,531 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:27:02,532 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:27:02,533 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:27:02,533 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:27:02,534 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:27:02,535 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:27:02,535 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:27:02,536 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:27:02,536 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:27:02,537 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:27:02,538 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:27:02,538 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:27:02,539 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:27:02,539 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:27:02,540 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:27:02,540 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:27:02,541 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:27:02,541 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4996a252ab084c920e1b9a19c3119ce328d4cb97d6d45029062c9dac50449e19 [2023-11-06 22:27:02,864 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:27:02,899 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:27:02,902 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:27:02,903 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:27:02,905 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:27:02,907 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2023-11-06 22:27:05,975 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:27:06,254 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:27:06,255 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/sv-benchmarks/c/systemc/token_ring.03.cil-2.c [2023-11-06 22:27:06,269 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/data/ec76e2eeb/1d181439b17045538d9c553ea15cc0e2/FLAG509719273 [2023-11-06 22:27:06,285 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/data/ec76e2eeb/1d181439b17045538d9c553ea15cc0e2 [2023-11-06 22:27:06,288 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:27:06,290 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:27:06,292 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:27:06,293 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:27:06,299 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:27:06,300 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,301 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@79b5d735 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06, skipping insertion in model container [2023-11-06 22:27:06,301 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,366 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:27:06,608 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:27:06,625 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:27:06,668 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:27:06,686 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:27:06,686 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06 WrapperNode [2023-11-06 22:27:06,687 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:27:06,687 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:27:06,688 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:27:06,688 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:27:06,695 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,704 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,766 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 63, statements flattened = 822 [2023-11-06 22:27:06,766 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:27:06,767 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:27:06,768 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:27:06,768 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:27:06,778 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,778 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,783 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,783 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,799 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,810 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,814 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,817 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,825 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:27:06,826 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:27:06,826 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:27:06,826 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:27:06,827 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (1/1) ... [2023-11-06 22:27:06,834 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:27:06,850 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:27:06,863 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:27:06,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:27:06,901 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:27:06,901 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:27:06,902 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:27:06,902 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:27:06,986 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:27:06,987 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:27:07,992 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:27:08,017 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:27:08,017 INFO L302 CfgBuilder]: Removed 6 assume(true) statements. [2023-11-06 22:27:08,020 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:27:08 BoogieIcfgContainer [2023-11-06 22:27:08,021 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:27:08,022 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:27:08,022 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:27:08,026 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:27:08,027 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:27:08,027 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:27:06" (1/3) ... [2023-11-06 22:27:08,028 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38223acd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:27:08, skipping insertion in model container [2023-11-06 22:27:08,028 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:27:08,028 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:27:06" (2/3) ... [2023-11-06 22:27:08,028 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@38223acd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:27:08, skipping insertion in model container [2023-11-06 22:27:08,029 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:27:08,029 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:27:08" (3/3) ... [2023-11-06 22:27:08,030 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.03.cil-2.c [2023-11-06 22:27:08,093 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:27:08,093 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:27:08,093 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:27:08,094 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:27:08,094 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:27:08,094 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:27:08,094 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:27:08,094 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:27:08,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:08,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2023-11-06 22:27:08,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:08,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:08,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,154 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:27:08,156 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:08,170 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 270 [2023-11-06 22:27:08,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:08,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:08,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,185 INFO L748 eck$LassoCheckResult]: Stem: 205#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 222#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 326#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 217#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L292true assume !(1 == ~m_i~0);~m_st~0 := 2; 229#L292-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 207#L297-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 190#L302-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 198#L307-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 261#L429true assume !(0 == ~M_E~0); 56#L429-2true assume !(0 == ~T1_E~0); 150#L434-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 230#L439-1true assume !(0 == ~T3_E~0); 174#L444-1true assume !(0 == ~E_M~0); 278#L449-1true assume !(0 == ~E_1~0); 58#L454-1true assume !(0 == ~E_2~0); 304#L459-1true assume !(0 == ~E_3~0); 36#L464-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 297#L208true assume 1 == ~m_pc~0; 302#L209true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 329#L219true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176#is_master_triggered_returnLabel#1true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 50#L531true assume !(0 != activate_threads_~tmp~1#1); 137#L531-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L227true assume !(1 == ~t1_pc~0); 49#L227-2true is_transmit1_triggered_~__retres1~1#1 := 0; 199#L238true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 57#L539true assume !(0 != activate_threads_~tmp___0~0#1); 145#L539-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 74#L246true assume 1 == ~t2_pc~0; 134#L247true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 156#L257true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 327#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 211#L547true assume !(0 != activate_threads_~tmp___1~0#1); 239#L547-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81#L265true assume !(1 == ~t3_pc~0); 311#L265-2true is_transmit3_triggered_~__retres1~3#1 := 0; 3#L276true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 325#L555true assume !(0 != activate_threads_~tmp___2~0#1); 63#L555-2true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 202#L477true assume !(1 == ~M_E~0); 267#L477-2true assume !(1 == ~T1_E~0); 223#L482-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 172#L487-1true assume !(1 == ~T3_E~0); 257#L492-1true assume !(1 == ~E_M~0); 40#L497-1true assume !(1 == ~E_1~0); 144#L502-1true assume !(1 == ~E_2~0); 30#L507-1true assume !(1 == ~E_3~0); 118#L512-1true assume { :end_inline_reset_delta_events } true; 194#L678-2true [2023-11-06 22:27:08,187 INFO L750 eck$LassoCheckResult]: Loop: 194#L678-2true assume !false; 286#L679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 308#L404-1true assume !true; 106#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 146#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 269#L429-3true assume 0 == ~M_E~0;~M_E~0 := 1; 330#L429-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 192#L434-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 236#L439-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 61#L444-3true assume 0 == ~E_M~0;~E_M~0 := 1; 68#L449-3true assume 0 == ~E_1~0;~E_1~0 := 1; 92#L454-3true assume !(0 == ~E_2~0); 241#L459-3true assume 0 == ~E_3~0;~E_3~0 := 1; 59#L464-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252#L208-15true assume 1 == ~m_pc~0; 281#L209-5true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 250#L219-5true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96#is_master_triggered_returnLabel#6true activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 158#L531-15true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 69#L531-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 290#L227-15true assume 1 == ~t1_pc~0; 318#L228-5true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 242#L238-5true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75#is_transmit1_triggered_returnLabel#6true activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 208#L539-15true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 189#L539-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L246-15true assume 1 == ~t2_pc~0; 9#L247-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 254#L257-5true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 279#is_transmit2_triggered_returnLabel#6true activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 313#L547-15true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55#L547-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 203#L265-15true assume !(1 == ~t3_pc~0); 271#L265-17true is_transmit3_triggered_~__retres1~3#1 := 0; 130#L276-5true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 247#is_transmit3_triggered_returnLabel#6true activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 86#L555-15true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 218#L555-17true havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 260#L477-3true assume 1 == ~M_E~0;~M_E~0 := 2; 180#L477-5true assume !(1 == ~T1_E~0); 266#L482-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 93#L487-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 54#L492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 289#L497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 142#L502-3true assume 1 == ~E_2~0;~E_2~0 := 2; 185#L507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 109#L512-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 32#L320-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13#L342-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 282#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 210#L697true assume !(0 == start_simulation_~tmp~3#1); 2#L697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 258#L320-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 79#L342-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 328#L652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 200#L659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 162#stop_simulation_returnLabel#1true start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 80#L710true assume !(0 != start_simulation_~tmp___0~1#1); 194#L678-2true [2023-11-06 22:27:08,194 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:08,194 INFO L85 PathProgramCache]: Analyzing trace with hash 1917692997, now seen corresponding path program 1 times [2023-11-06 22:27:08,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:08,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [668753282] [2023-11-06 22:27:08,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:08,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:08,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:08,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:08,509 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:08,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [668753282] [2023-11-06 22:27:08,511 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [668753282] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:08,511 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:08,511 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:08,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888617091] [2023-11-06 22:27:08,514 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:08,521 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:08,523 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:08,523 INFO L85 PathProgramCache]: Analyzing trace with hash 1122762879, now seen corresponding path program 1 times [2023-11-06 22:27:08,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:08,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776964336] [2023-11-06 22:27:08,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:08,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:08,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:08,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:08,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:08,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1776964336] [2023-11-06 22:27:08,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1776964336] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:08,599 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:08,599 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:27:08,599 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681101686] [2023-11-06 22:27:08,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:08,601 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:08,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:08,632 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:08,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:08,635 INFO L87 Difference]: Start difference. First operand has 329 states, 328 states have (on average 1.5274390243902438) internal successors, (501), 328 states have internal predecessors, (501), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:08,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:08,686 INFO L93 Difference]: Finished difference Result 327 states and 485 transitions. [2023-11-06 22:27:08,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 327 states and 485 transitions. [2023-11-06 22:27:08,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:08,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 327 states to 322 states and 480 transitions. [2023-11-06 22:27:08,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-06 22:27:08,707 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-06 22:27:08,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 480 transitions. [2023-11-06 22:27:08,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:08,710 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-06 22:27:08,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 480 transitions. [2023-11-06 22:27:08,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-06 22:27:08,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4906832298136645) internal successors, (480), 321 states have internal predecessors, (480), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:08,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 480 transitions. [2023-11-06 22:27:08,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-06 22:27:08,765 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:08,769 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 480 transitions. [2023-11-06 22:27:08,769 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:27:08,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 480 transitions. [2023-11-06 22:27:08,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:08,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:08,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:08,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,777 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:08,778 INFO L748 eck$LassoCheckResult]: Stem: 949#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 950#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 960#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 867#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 868#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 951#L297-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 937#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 938#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 945#L429 assume !(0 == ~M_E~0); 771#L429-2 assume !(0 == ~T1_E~0); 772#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 899#L439-1 assume !(0 == ~T3_E~0); 920#L444-1 assume !(0 == ~E_M~0); 921#L449-1 assume !(0 == ~E_1~0); 774#L454-1 assume !(0 == ~E_2~0); 775#L459-1 assume !(0 == ~E_3~0); 732#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 733#L208 assume 1 == ~m_pc~0; 984#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 986#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 923#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 759#L531 assume !(0 != activate_threads_~tmp~1#1); 760#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 872#L227 assume !(1 == ~t1_pc~0); 757#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 758#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 745#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 746#L539 assume !(0 != activate_threads_~tmp___0~0#1); 773#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 806#L246 assume 1 == ~t2_pc~0; 807#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 888#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 954#L547 assume !(0 != activate_threads_~tmp___1~0#1); 955#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 820#L265 assume !(1 == ~t3_pc~0); 694#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 667#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 668#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 695#L555 assume !(0 != activate_threads_~tmp___2~0#1); 788#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789#L477 assume !(1 == ~M_E~0); 948#L477-2 assume !(1 == ~T1_E~0); 963#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 916#L487-1 assume !(1 == ~T3_E~0); 917#L492-1 assume !(1 == ~E_M~0); 743#L497-1 assume !(1 == ~E_1~0); 744#L502-1 assume !(1 == ~E_2~0); 722#L507-1 assume !(1 == ~E_3~0); 723#L512-1 assume { :end_inline_reset_delta_events } true; 817#L678-2 [2023-11-06 22:27:08,778 INFO L750 eck$LassoCheckResult]: Loop: 817#L678-2 assume !false; 943#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 956#L404-1 assume !false; 871#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 852#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 707#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 696#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 697#L357 assume !(0 != eval_~tmp~0#1); 795#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 858#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 897#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 977#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 939#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 940#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 781#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 782#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 796#L454-3 assume !(0 == ~E_2~0); 835#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 776#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 777#L208-15 assume !(1 == ~m_pc~0); 925#L208-17 is_master_triggered_~__retres1~0#1 := 0; 926#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 842#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 843#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 797#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 798#L227-15 assume !(1 == ~t1_pc~0); 979#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 969#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 805#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 936#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922#L246-15 assume 1 == ~t2_pc~0; 675#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 676#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 974#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 981#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 769#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 770#L265-15 assume !(1 == ~t3_pc~0); 849#L265-17 is_transmit3_triggered_~__retres1~3#1 := 0; 848#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 880#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 825#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 826#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 959#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 927#L477-5 assume !(1 == ~T1_E~0); 928#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 834#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 765#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 766#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 893#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 894#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 860#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 726#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 686#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 687#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 952#L697 assume !(0 == start_simulation_~tmp~3#1); 665#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 666#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 815#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 738#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 739#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 946#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 905#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 816#L710 assume !(0 != start_simulation_~tmp___0~1#1); 817#L678-2 [2023-11-06 22:27:08,779 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:08,779 INFO L85 PathProgramCache]: Analyzing trace with hash -2024185917, now seen corresponding path program 1 times [2023-11-06 22:27:08,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:08,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [435148953] [2023-11-06 22:27:08,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:08,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:08,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:08,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:08,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:08,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [435148953] [2023-11-06 22:27:08,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [435148953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:08,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:08,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:08,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [935780843] [2023-11-06 22:27:08,839 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:08,840 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:08,840 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:08,841 INFO L85 PathProgramCache]: Analyzing trace with hash 1981164799, now seen corresponding path program 1 times [2023-11-06 22:27:08,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:08,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1704879131] [2023-11-06 22:27:08,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:08,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:08,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:08,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:08,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:08,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1704879131] [2023-11-06 22:27:08,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1704879131] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:08,959 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:08,959 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:08,959 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [910396697] [2023-11-06 22:27:08,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:08,961 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:08,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:08,963 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:08,963 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:08,964 INFO L87 Difference]: Start difference. First operand 322 states and 480 transitions. cyclomatic complexity: 159 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:09,034 INFO L93 Difference]: Finished difference Result 322 states and 479 transitions. [2023-11-06 22:27:09,034 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 479 transitions. [2023-11-06 22:27:09,038 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:09,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 479 transitions. [2023-11-06 22:27:09,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-06 22:27:09,048 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-06 22:27:09,049 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 479 transitions. [2023-11-06 22:27:09,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:09,057 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-06 22:27:09,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 479 transitions. [2023-11-06 22:27:09,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-06 22:27:09,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.4875776397515528) internal successors, (479), 321 states have internal predecessors, (479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 479 transitions. [2023-11-06 22:27:09,122 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-06 22:27:09,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:09,123 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 479 transitions. [2023-11-06 22:27:09,124 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:27:09,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 479 transitions. [2023-11-06 22:27:09,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:09,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:09,131 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:09,133 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,133 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,134 INFO L748 eck$LassoCheckResult]: Stem: 1600#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 1601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1611#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1520#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 1521#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1602#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1588#L302-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1589#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596#L429 assume !(0 == ~M_E~0); 1422#L429-2 assume !(0 == ~T1_E~0); 1423#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1550#L439-1 assume !(0 == ~T3_E~0); 1571#L444-1 assume !(0 == ~E_M~0); 1572#L449-1 assume !(0 == ~E_1~0); 1427#L454-1 assume !(0 == ~E_2~0); 1428#L459-1 assume !(0 == ~E_3~0); 1383#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1384#L208 assume 1 == ~m_pc~0; 1635#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1637#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1574#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1410#L531 assume !(0 != activate_threads_~tmp~1#1); 1411#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1524#L227 assume !(1 == ~t1_pc~0); 1408#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1409#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1399#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1400#L539 assume !(0 != activate_threads_~tmp___0~0#1); 1424#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1455#L246 assume 1 == ~t2_pc~0; 1456#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1539#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1554#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1605#L547 assume !(0 != activate_threads_~tmp___1~0#1); 1606#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1469#L265 assume !(1 == ~t3_pc~0); 1345#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1318#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1319#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1346#L555 assume !(0 != activate_threads_~tmp___2~0#1); 1436#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1437#L477 assume !(1 == ~M_E~0); 1599#L477-2 assume !(1 == ~T1_E~0); 1613#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1567#L487-1 assume !(1 == ~T3_E~0); 1568#L492-1 assume !(1 == ~E_M~0); 1389#L497-1 assume !(1 == ~E_1~0); 1390#L502-1 assume !(1 == ~E_2~0); 1373#L507-1 assume !(1 == ~E_3~0); 1374#L512-1 assume { :end_inline_reset_delta_events } true; 1468#L678-2 [2023-11-06 22:27:09,134 INFO L750 eck$LassoCheckResult]: Loop: 1468#L678-2 assume !false; 1592#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1607#L404-1 assume !false; 1522#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1497#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1358#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1347#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1348#L357 assume !(0 != eval_~tmp~0#1); 1444#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1546#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1628#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1590#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1591#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1432#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1433#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1447#L454-3 assume !(0 == ~E_2~0); 1485#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1425#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1426#L208-15 assume !(1 == ~m_pc~0); 1576#L208-17 is_master_triggered_~__retres1~0#1 := 0; 1577#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1493#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 1494#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1448#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1449#L227-15 assume 1 == ~t1_pc~0; 1633#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1620#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1458#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1459#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1587#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1573#L246-15 assume 1 == ~t2_pc~0; 1330#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1331#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1625#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1632#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1420#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1421#L265-15 assume 1 == ~t3_pc~0; 1499#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1500#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1534#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1477#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1478#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1610#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1578#L477-5 assume !(1 == ~T1_E~0); 1579#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1486#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1418#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1419#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1544#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1545#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1511#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1377#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1339#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 1604#L697 assume !(0 == start_simulation_~tmp~3#1); 1316#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1317#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1466#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1391#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 1392#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1597#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1556#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 1467#L710 assume !(0 != start_simulation_~tmp___0~1#1); 1468#L678-2 [2023-11-06 22:27:09,135 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,135 INFO L85 PathProgramCache]: Analyzing trace with hash 1377295041, now seen corresponding path program 1 times [2023-11-06 22:27:09,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440450991] [2023-11-06 22:27:09,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,137 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440450991] [2023-11-06 22:27:09,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440450991] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,179 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,179 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:09,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1528324620] [2023-11-06 22:27:09,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,180 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:09,180 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,181 INFO L85 PathProgramCache]: Analyzing trace with hash 315643517, now seen corresponding path program 1 times [2023-11-06 22:27:09,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1395674636] [2023-11-06 22:27:09,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1395674636] [2023-11-06 22:27:09,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1395674636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:09,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1470224683] [2023-11-06 22:27:09,234 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,234 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:09,235 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:09,235 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:09,235 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:09,236 INFO L87 Difference]: Start difference. First operand 322 states and 479 transitions. cyclomatic complexity: 158 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:09,250 INFO L93 Difference]: Finished difference Result 322 states and 478 transitions. [2023-11-06 22:27:09,250 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 478 transitions. [2023-11-06 22:27:09,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:09,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 478 transitions. [2023-11-06 22:27:09,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2023-11-06 22:27:09,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2023-11-06 22:27:09,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 478 transitions. [2023-11-06 22:27:09,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:09,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-06 22:27:09,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 478 transitions. [2023-11-06 22:27:09,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 322. [2023-11-06 22:27:09,276 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 322 states, 322 states have (on average 1.484472049689441) internal successors, (478), 321 states have internal predecessors, (478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 322 states to 322 states and 478 transitions. [2023-11-06 22:27:09,278 INFO L240 hiAutomatonCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-06 22:27:09,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:09,280 INFO L428 stractBuchiCegarLoop]: Abstraction has 322 states and 478 transitions. [2023-11-06 22:27:09,281 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:27:09,281 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 322 states and 478 transitions. [2023-11-06 22:27:09,284 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 267 [2023-11-06 22:27:09,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:09,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:09,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,288 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,288 INFO L748 eck$LassoCheckResult]: Stem: 2251#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 2252#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2264#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2261#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2167#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 2168#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2253#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2239#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2240#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2247#L429 assume !(0 == ~M_E~0); 2073#L429-2 assume !(0 == ~T1_E~0); 2074#L434-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2201#L439-1 assume !(0 == ~T3_E~0); 2222#L444-1 assume !(0 == ~E_M~0); 2223#L449-1 assume !(0 == ~E_1~0); 2076#L454-1 assume !(0 == ~E_2~0); 2077#L459-1 assume !(0 == ~E_3~0); 2034#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2035#L208 assume 1 == ~m_pc~0; 2286#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2288#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2225#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2061#L531 assume !(0 != activate_threads_~tmp~1#1); 2062#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2174#L227 assume !(1 == ~t1_pc~0); 2059#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2060#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2048#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2075#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2106#L246 assume 1 == ~t2_pc~0; 2107#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2190#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2205#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2256#L547 assume !(0 != activate_threads_~tmp___1~0#1); 2257#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2120#L265 assume !(1 == ~t3_pc~0); 1996#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1969#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1970#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1997#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2087#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2088#L477 assume !(1 == ~M_E~0); 2250#L477-2 assume !(1 == ~T1_E~0); 2265#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2218#L487-1 assume !(1 == ~T3_E~0); 2219#L492-1 assume !(1 == ~E_M~0); 2040#L497-1 assume !(1 == ~E_1~0); 2041#L502-1 assume !(1 == ~E_2~0); 2024#L507-1 assume !(1 == ~E_3~0); 2025#L512-1 assume { :end_inline_reset_delta_events } true; 2119#L678-2 [2023-11-06 22:27:09,289 INFO L750 eck$LassoCheckResult]: Loop: 2119#L678-2 assume !false; 2243#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2258#L404-1 assume !false; 2173#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2148#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2009#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1998#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1999#L357 assume !(0 != eval_~tmp~0#1); 2095#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2160#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2197#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2279#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2241#L434-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2242#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2083#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2084#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2098#L454-3 assume !(0 == ~E_2~0); 2136#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2078#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2079#L208-15 assume !(1 == ~m_pc~0); 2227#L208-17 is_master_triggered_~__retres1~0#1 := 0; 2228#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2144#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2145#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2099#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2100#L227-15 assume !(1 == ~t1_pc~0); 2281#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 2271#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2109#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2110#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2238#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2224#L246-15 assume 1 == ~t2_pc~0; 1981#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1982#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2276#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2283#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2071#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2072#L265-15 assume 1 == ~t3_pc~0; 2150#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2151#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2185#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2128#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2129#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2262#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2229#L477-5 assume !(1 == ~T1_E~0); 2230#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2137#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2069#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2070#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2195#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2196#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2163#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2028#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 1990#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 1991#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 2255#L697 assume !(0 == start_simulation_~tmp~3#1); 1967#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 1968#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2117#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2042#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2043#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2248#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2207#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 2118#L710 assume !(0 != start_simulation_~tmp___0~1#1); 2119#L678-2 [2023-11-06 22:27:09,289 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,289 INFO L85 PathProgramCache]: Analyzing trace with hash -868284413, now seen corresponding path program 1 times [2023-11-06 22:27:09,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589353477] [2023-11-06 22:27:09,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [589353477] [2023-11-06 22:27:09,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [589353477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:09,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426442664] [2023-11-06 22:27:09,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,402 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:09,402 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,403 INFO L85 PathProgramCache]: Analyzing trace with hash -641284866, now seen corresponding path program 1 times [2023-11-06 22:27:09,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085339560] [2023-11-06 22:27:09,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,486 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085339560] [2023-11-06 22:27:09,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085339560] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,487 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:09,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1142191468] [2023-11-06 22:27:09,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,489 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:09,489 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:09,489 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:27:09,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:27:09,490 INFO L87 Difference]: Start difference. First operand 322 states and 478 transitions. cyclomatic complexity: 157 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:09,603 INFO L93 Difference]: Finished difference Result 559 states and 824 transitions. [2023-11-06 22:27:09,603 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 559 states and 824 transitions. [2023-11-06 22:27:09,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2023-11-06 22:27:09,615 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 559 states to 559 states and 824 transitions. [2023-11-06 22:27:09,615 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 559 [2023-11-06 22:27:09,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 559 [2023-11-06 22:27:09,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 559 states and 824 transitions. [2023-11-06 22:27:09,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:09,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-06 22:27:09,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 559 states and 824 transitions. [2023-11-06 22:27:09,648 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 559 to 559. [2023-11-06 22:27:09,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 559 states, 559 states have (on average 1.4740608228980323) internal successors, (824), 558 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 559 states to 559 states and 824 transitions. [2023-11-06 22:27:09,653 INFO L240 hiAutomatonCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-06 22:27:09,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:27:09,657 INFO L428 stractBuchiCegarLoop]: Abstraction has 559 states and 824 transitions. [2023-11-06 22:27:09,657 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:27:09,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 559 states and 824 transitions. [2023-11-06 22:27:09,666 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 496 [2023-11-06 22:27:09,667 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:09,667 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:09,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,671 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,671 INFO L748 eck$LassoCheckResult]: Stem: 3157#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 3158#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3171#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3063#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 3064#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3159#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3141#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3142#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3151#L429 assume !(0 == ~M_E~0); 2966#L429-2 assume !(0 == ~T1_E~0); 2967#L434-1 assume !(0 == ~T2_E~0); 3102#L439-1 assume !(0 == ~T3_E~0); 3124#L444-1 assume !(0 == ~E_M~0); 3125#L449-1 assume !(0 == ~E_1~0); 2969#L454-1 assume !(0 == ~E_2~0); 2970#L459-1 assume !(0 == ~E_3~0); 2925#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2926#L208 assume 1 == ~m_pc~0; 3199#L209 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3201#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 2954#L531 assume !(0 != activate_threads_~tmp~1#1); 2955#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3071#L227 assume !(1 == ~t1_pc~0); 2952#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2953#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2939#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2940#L539 assume !(0 != activate_threads_~tmp___0~0#1); 2968#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3000#L246 assume 1 == ~t2_pc~0; 3001#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3090#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3106#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3162#L547 assume !(0 != activate_threads_~tmp___1~0#1); 3163#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3014#L265 assume !(1 == ~t3_pc~0); 2887#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2860#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2861#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2888#L555 assume !(0 != activate_threads_~tmp___2~0#1); 2980#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2981#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 3155#L477-2 assume !(1 == ~T1_E~0); 3172#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3120#L487-1 assume !(1 == ~T3_E~0); 3121#L492-1 assume !(1 == ~E_M~0); 2932#L497-1 assume !(1 == ~E_1~0); 2933#L502-1 assume !(1 == ~E_2~0); 2915#L507-1 assume !(1 == ~E_3~0); 2916#L512-1 assume { :end_inline_reset_delta_events } true; 3228#L678-2 [2023-11-06 22:27:09,672 INFO L750 eck$LassoCheckResult]: Loop: 3228#L678-2 assume !false; 3212#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3211#L404-1 assume !false; 3210#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 3208#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2929#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2889#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2890#L357 assume !(0 != eval_~tmp~0#1); 3054#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3055#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3202#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3203#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3392#L434-3 assume !(0 == ~T2_E~0); 3391#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3390#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3389#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3388#L454-3 assume !(0 == ~E_2~0); 3387#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3386#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3385#L208-15 assume !(1 == ~m_pc~0); 3383#L208-17 is_master_triggered_~__retres1~0#1 := 0; 3382#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3381#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 3380#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3379#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3378#L227-15 assume 1 == ~t1_pc~0; 3376#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3375#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3374#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3373#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3372#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3371#L246-15 assume !(1 == ~t2_pc~0); 3369#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 3368#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3367#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3366#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3365#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3364#L265-15 assume 1 == ~t3_pc~0; 3362#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3361#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3359#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3358#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3357#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3188#L477-5 assume !(1 == ~T1_E~0); 3356#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3190#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3355#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3354#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3353#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3352#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3351#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2919#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 2881#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 3161#L697 assume !(0 == start_simulation_~tmp~3#1); 2858#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 2859#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 3011#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 2934#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 2935#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3152#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3153#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 3230#L710 assume !(0 != start_simulation_~tmp___0~1#1); 3228#L678-2 [2023-11-06 22:27:09,672 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,679 INFO L85 PathProgramCache]: Analyzing trace with hash 1374817215, now seen corresponding path program 1 times [2023-11-06 22:27:09,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353429072] [2023-11-06 22:27:09,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,680 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353429072] [2023-11-06 22:27:09,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353429072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:27:09,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [965981674] [2023-11-06 22:27:09,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,780 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:09,781 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,781 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 1 times [2023-11-06 22:27:09,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373150500] [2023-11-06 22:27:09,782 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:09,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:09,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:09,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373150500] [2023-11-06 22:27:09,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373150500] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:09,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:09,822 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:09,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [239244755] [2023-11-06 22:27:09,822 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:09,822 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:09,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:09,823 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:09,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:09,824 INFO L87 Difference]: Start difference. First operand 559 states and 824 transitions. cyclomatic complexity: 267 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:09,908 INFO L93 Difference]: Finished difference Result 1037 states and 1505 transitions. [2023-11-06 22:27:09,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1037 states and 1505 transitions. [2023-11-06 22:27:09,918 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 973 [2023-11-06 22:27:09,927 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1037 states to 1037 states and 1505 transitions. [2023-11-06 22:27:09,927 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1037 [2023-11-06 22:27:09,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1037 [2023-11-06 22:27:09,928 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1037 states and 1505 transitions. [2023-11-06 22:27:09,930 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:09,930 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1037 states and 1505 transitions. [2023-11-06 22:27:09,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1037 states and 1505 transitions. [2023-11-06 22:27:09,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1037 to 983. [2023-11-06 22:27:09,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 983 states, 983 states have (on average 1.4557477110885046) internal successors, (1431), 982 states have internal predecessors, (1431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:09,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 983 states to 983 states and 1431 transitions. [2023-11-06 22:27:09,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 983 states and 1431 transitions. [2023-11-06 22:27:09,960 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:09,961 INFO L428 stractBuchiCegarLoop]: Abstraction has 983 states and 1431 transitions. [2023-11-06 22:27:09,961 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:27:09,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 983 states and 1431 transitions. [2023-11-06 22:27:09,968 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 919 [2023-11-06 22:27:09,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:09,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:09,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:09,971 INFO L748 eck$LassoCheckResult]: Stem: 4781#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 4782#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4798#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4795#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4673#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 4674#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4784#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4763#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4764#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4775#L429 assume !(0 == ~M_E~0); 4570#L429-2 assume !(0 == ~T1_E~0); 4571#L434-1 assume !(0 == ~T2_E~0); 4717#L439-1 assume !(0 == ~T3_E~0); 4741#L444-1 assume !(0 == ~E_M~0); 4742#L449-1 assume !(0 == ~E_1~0); 4575#L454-1 assume !(0 == ~E_2~0); 4576#L459-1 assume !(0 == ~E_3~0); 4529#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4530#L208 assume !(1 == ~m_pc~0); 4857#L208-2 is_master_triggered_~__retres1~0#1 := 0; 4858#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4744#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4558#L531 assume !(0 != activate_threads_~tmp~1#1); 4559#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4678#L227 assume !(1 == ~t1_pc~0); 4556#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4557#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4544#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4545#L539 assume !(0 != activate_threads_~tmp___0~0#1); 4572#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4606#L246 assume 1 == ~t2_pc~0; 4607#L247 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4700#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4721#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4788#L547 assume !(0 != activate_threads_~tmp___1~0#1); 4789#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4620#L265 assume !(1 == ~t3_pc~0); 4490#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4463#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4464#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4491#L555 assume !(0 != activate_threads_~tmp___2~0#1); 4590#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4591#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 4778#L477-2 assume !(1 == ~T1_E~0); 5424#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4737#L487-1 assume !(1 == ~T3_E~0); 4738#L492-1 assume !(1 == ~E_M~0); 4542#L497-1 assume !(1 == ~E_1~0); 4543#L502-1 assume !(1 == ~E_2~0); 4518#L507-1 assume !(1 == ~E_3~0); 4519#L512-1 assume { :end_inline_reset_delta_events } true; 5242#L678-2 [2023-11-06 22:27:09,971 INFO L750 eck$LassoCheckResult]: Loop: 5242#L678-2 assume !false; 5241#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5240#L404-1 assume !false; 4677#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4654#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4503#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4492#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4493#L357 assume !(0 != eval_~tmp~0#1); 4595#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4663#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5230#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4879#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4765#L434-3 assume !(0 == ~T2_E~0); 4766#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4580#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4581#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4596#L454-3 assume !(0 == ~E_2~0); 4635#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4573#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4574#L208-15 assume !(1 == ~m_pc~0); 4746#L208-17 is_master_triggered_~__retres1~0#1 := 0; 4747#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4641#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 4642#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4597#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4598#L227-15 assume 1 == ~t1_pc~0; 4848#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4818#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4604#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4605#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4762#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4743#L246-15 assume 1 == ~t2_pc~0; 4471#L247-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4472#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4827#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4838#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4568#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4569#L265-15 assume 1 == ~t3_pc~0; 4651#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4652#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4690#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4624#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4625#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4794#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4749#L477-5 assume !(1 == ~T1_E~0); 4750#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4636#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4637#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4977#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4976#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4975#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4974#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4973#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4484#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4485#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 4785#L697 assume !(0 == start_simulation_~tmp~3#1); 4461#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 4462#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 4615#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 4537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 4538#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5294#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5245#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 5243#L710 assume !(0 != start_simulation_~tmp___0~1#1); 5242#L678-2 [2023-11-06 22:27:09,972 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:09,972 INFO L85 PathProgramCache]: Analyzing trace with hash -201740544, now seen corresponding path program 1 times [2023-11-06 22:27:09,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:09,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78188526] [2023-11-06 22:27:09,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:09,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:09,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [78188526] [2023-11-06 22:27:10,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [78188526] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:10,029 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457220117] [2023-11-06 22:27:10,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,029 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:10,030 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,030 INFO L85 PathProgramCache]: Analyzing trace with hash 1853983547, now seen corresponding path program 1 times [2023-11-06 22:27:10,030 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,030 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245440406] [2023-11-06 22:27:10,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,031 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,070 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,070 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245440406] [2023-11-06 22:27:10,071 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245440406] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,071 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,071 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:10,071 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295676468] [2023-11-06 22:27:10,071 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,072 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:10,072 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:10,073 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:27:10,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:27:10,073 INFO L87 Difference]: Start difference. First operand 983 states and 1431 transitions. cyclomatic complexity: 452 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:10,222 INFO L93 Difference]: Finished difference Result 2227 states and 3190 transitions. [2023-11-06 22:27:10,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2227 states and 3190 transitions. [2023-11-06 22:27:10,243 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2094 [2023-11-06 22:27:10,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2227 states to 2227 states and 3190 transitions. [2023-11-06 22:27:10,263 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2227 [2023-11-06 22:27:10,266 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2227 [2023-11-06 22:27:10,266 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2227 states and 3190 transitions. [2023-11-06 22:27:10,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:10,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2227 states and 3190 transitions. [2023-11-06 22:27:10,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2227 states and 3190 transitions. [2023-11-06 22:27:10,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2227 to 1757. [2023-11-06 22:27:10,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1757 states, 1757 states have (on average 1.4450768355150825) internal successors, (2539), 1756 states have internal predecessors, (2539), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1757 states to 1757 states and 2539 transitions. [2023-11-06 22:27:10,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1757 states and 2539 transitions. [2023-11-06 22:27:10,321 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:27:10,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 1757 states and 2539 transitions. [2023-11-06 22:27:10,322 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:27:10,322 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1757 states and 2539 transitions. [2023-11-06 22:27:10,335 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1692 [2023-11-06 22:27:10,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:10,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:10,336 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,337 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,337 INFO L748 eck$LassoCheckResult]: Stem: 7988#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 7989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 8005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7884#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 7885#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7991#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7973#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7974#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7983#L429 assume !(0 == ~M_E~0); 7788#L429-2 assume !(0 == ~T1_E~0); 7789#L434-1 assume !(0 == ~T2_E~0); 7926#L439-1 assume !(0 == ~T3_E~0); 7952#L444-1 assume !(0 == ~E_M~0); 7953#L449-1 assume !(0 == ~E_1~0); 7791#L454-1 assume !(0 == ~E_2~0); 7792#L459-1 assume !(0 == ~E_3~0); 7749#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7750#L208 assume !(1 == ~m_pc~0); 8051#L208-2 is_master_triggered_~__retres1~0#1 := 0; 8052#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7955#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 7776#L531 assume !(0 != activate_threads_~tmp~1#1); 7777#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7891#L227 assume !(1 == ~t1_pc~0); 7774#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7775#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7762#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 7763#L539 assume !(0 != activate_threads_~tmp___0~0#1); 7790#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7822#L246 assume !(1 == ~t2_pc~0); 7823#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7930#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7994#L547 assume !(0 != activate_threads_~tmp___1~0#1); 7995#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7835#L265 assume !(1 == ~t3_pc~0); 7712#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7683#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7684#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7713#L555 assume !(0 != activate_threads_~tmp___2~0#1); 7802#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7803#L477 assume 1 == ~M_E~0;~M_E~0 := 2; 7986#L477-2 assume !(1 == ~T1_E~0); 8006#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8007#L487-1 assume !(1 == ~T3_E~0); 8021#L492-1 assume !(1 == ~E_M~0); 8022#L497-1 assume !(1 == ~E_1~0); 7918#L502-1 assume !(1 == ~E_2~0); 7919#L507-1 assume !(1 == ~E_3~0); 7889#L512-1 assume { :end_inline_reset_delta_events } true; 7834#L678-2 [2023-11-06 22:27:10,337 INFO L750 eck$LassoCheckResult]: Loop: 7834#L678-2 assume !false; 7979#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7997#L404-1 assume !false; 7890#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7861#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7725#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7714#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7715#L357 assume !(0 != eval_~tmp~0#1); 7810#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9437#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9436#L429-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9435#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9434#L434-3 assume !(0 == ~T2_E~0); 9433#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9432#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9431#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9430#L454-3 assume !(0 == ~E_2~0); 9429#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9428#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9427#L208-15 assume !(1 == ~m_pc~0); 9426#L208-17 is_master_triggered_~__retres1~0#1 := 0; 9425#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9424#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 9423#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9422#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9421#L227-15 assume 1 == ~t1_pc~0; 9419#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9418#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9417#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9416#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9415#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7954#L246-15 assume !(1 == ~t2_pc~0); 7706#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 7707#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8020#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8038#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7786#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7787#L265-15 assume 1 == ~t3_pc~0; 7864#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7865#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7903#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7841#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7842#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8002#L477-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8023#L477-5 assume !(1 == ~T1_E~0); 9373#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8027#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9372#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9371#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9370#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7967#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7879#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7744#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7704#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7705#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 7993#L697 assume !(0 == start_simulation_~tmp~3#1); 7681#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 7682#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 7832#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 7757#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 7758#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7984#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7937#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 7833#L710 assume !(0 != start_simulation_~tmp___0~1#1); 7834#L678-2 [2023-11-06 22:27:10,338 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1175229503, now seen corresponding path program 1 times [2023-11-06 22:27:10,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046843311] [2023-11-06 22:27:10,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046843311] [2023-11-06 22:27:10,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046843311] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:27:10,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743292518] [2023-11-06 22:27:10,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,390 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:10,391 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,391 INFO L85 PathProgramCache]: Analyzing trace with hash 277425788, now seen corresponding path program 2 times [2023-11-06 22:27:10,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781503970] [2023-11-06 22:27:10,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781503970] [2023-11-06 22:27:10,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781503970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,448 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,448 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:10,448 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286968793] [2023-11-06 22:27:10,448 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,448 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:10,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:10,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:10,449 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:10,449 INFO L87 Difference]: Start difference. First operand 1757 states and 2539 transitions. cyclomatic complexity: 786 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:10,532 INFO L93 Difference]: Finished difference Result 2561 states and 3698 transitions. [2023-11-06 22:27:10,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2561 states and 3698 transitions. [2023-11-06 22:27:10,562 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2496 [2023-11-06 22:27:10,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2561 states to 2561 states and 3698 transitions. [2023-11-06 22:27:10,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2561 [2023-11-06 22:27:10,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2561 [2023-11-06 22:27:10,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2561 states and 3698 transitions. [2023-11-06 22:27:10,599 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:10,599 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2561 states and 3698 transitions. [2023-11-06 22:27:10,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2561 states and 3698 transitions. [2023-11-06 22:27:10,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2561 to 1781. [2023-11-06 22:27:10,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.4480628860190905) internal successors, (2579), 1780 states have internal predecessors, (2579), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2579 transitions. [2023-11-06 22:27:10,657 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2579 transitions. [2023-11-06 22:27:10,657 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:10,658 INFO L428 stractBuchiCegarLoop]: Abstraction has 1781 states and 2579 transitions. [2023-11-06 22:27:10,658 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:27:10,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2579 transitions. [2023-11-06 22:27:10,671 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1724 [2023-11-06 22:27:10,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:10,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:10,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,674 INFO L748 eck$LassoCheckResult]: Stem: 12299#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 12300#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12315#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12207#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 12208#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12304#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12287#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12288#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12295#L429 assume !(0 == ~M_E~0); 12111#L429-2 assume !(0 == ~T1_E~0); 12112#L434-1 assume !(0 == ~T2_E~0); 12244#L439-1 assume !(0 == ~T3_E~0); 12267#L444-1 assume !(0 == ~E_M~0); 12268#L449-1 assume !(0 == ~E_1~0); 12114#L454-1 assume !(0 == ~E_2~0); 12115#L459-1 assume !(0 == ~E_3~0); 12072#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12073#L208 assume !(1 == ~m_pc~0); 12350#L208-2 is_master_triggered_~__retres1~0#1 := 0; 12351#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12271#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12099#L531 assume !(0 != activate_threads_~tmp~1#1); 12100#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12214#L227 assume !(1 == ~t1_pc~0); 12097#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12098#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12085#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12086#L539 assume !(0 != activate_threads_~tmp___0~0#1); 12113#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12144#L246 assume !(1 == ~t2_pc~0); 12145#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12248#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12249#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12308#L547 assume !(0 != activate_threads_~tmp___1~0#1); 12309#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12157#L265 assume !(1 == ~t3_pc~0); 12035#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12008#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12009#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12036#L555 assume !(0 != activate_threads_~tmp___2~0#1); 12125#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12126#L477 assume !(1 == ~M_E~0); 12298#L477-2 assume !(1 == ~T1_E~0); 12319#L482-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12263#L487-1 assume !(1 == ~T3_E~0); 12264#L492-1 assume !(1 == ~E_M~0); 12078#L497-1 assume !(1 == ~E_1~0); 12079#L502-1 assume !(1 == ~E_2~0); 12063#L507-1 assume !(1 == ~E_3~0); 12064#L512-1 assume { :end_inline_reset_delta_events } true; 12156#L678-2 [2023-11-06 22:27:10,674 INFO L750 eck$LassoCheckResult]: Loop: 12156#L678-2 assume !false; 12291#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12311#L404-1 assume !false; 12213#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12185#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12048#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12037#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12038#L357 assume !(0 != eval_~tmp~0#1); 12133#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13786#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13785#L429-3 assume !(0 == ~M_E~0); 13784#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13783#L434-3 assume !(0 == ~T2_E~0); 13782#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13781#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13780#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13779#L454-3 assume !(0 == ~E_2~0); 12326#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12116#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12117#L208-15 assume !(1 == ~m_pc~0); 12273#L208-17 is_master_triggered_~__retres1~0#1 := 0; 12274#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12181#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 12182#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12137#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12138#L227-15 assume !(1 == ~t1_pc~0); 12339#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 12327#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12146#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 12147#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13753#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12269#L246-15 assume !(1 == ~t2_pc~0); 12270#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 13739#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13737#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13735#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13733#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13731#L265-15 assume 1 == ~t3_pc~0; 13728#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13726#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13724#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13722#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13720#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13718#L477-3 assume !(1 == ~M_E~0); 13264#L477-5 assume !(1 == ~T1_E~0); 13715#L482-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13713#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13711#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13709#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13706#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13704#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13702#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 13700#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 13695#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 13693#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 12307#L697 assume !(0 == start_simulation_~tmp~3#1); 12006#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 12007#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 12154#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 12080#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 12081#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12296#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12251#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 12155#L710 assume !(0 != start_simulation_~tmp___0~1#1); 12156#L678-2 [2023-11-06 22:27:10,675 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,675 INFO L85 PathProgramCache]: Analyzing trace with hash -495171133, now seen corresponding path program 1 times [2023-11-06 22:27:10,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1905372478] [2023-11-06 22:27:10,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1905372478] [2023-11-06 22:27:10,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1905372478] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:10,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [486015523] [2023-11-06 22:27:10,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,735 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:10,735 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,736 INFO L85 PathProgramCache]: Analyzing trace with hash 619218237, now seen corresponding path program 1 times [2023-11-06 22:27:10,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690348741] [2023-11-06 22:27:10,736 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,737 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:10,773 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:10,773 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:10,773 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690348741] [2023-11-06 22:27:10,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690348741] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:10,774 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:10,774 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:10,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032019011] [2023-11-06 22:27:10,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:10,775 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:10,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:10,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:27:10,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:27:10,776 INFO L87 Difference]: Start difference. First operand 1781 states and 2579 transitions. cyclomatic complexity: 800 Second operand has 4 states, 4 states have (on average 12.75) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:10,838 INFO L93 Difference]: Finished difference Result 2555 states and 3666 transitions. [2023-11-06 22:27:10,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2555 states and 3666 transitions. [2023-11-06 22:27:10,858 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2496 [2023-11-06 22:27:10,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2555 states to 2555 states and 3666 transitions. [2023-11-06 22:27:10,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2555 [2023-11-06 22:27:10,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2555 [2023-11-06 22:27:10,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2555 states and 3666 transitions. [2023-11-06 22:27:10,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:10,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2555 states and 3666 transitions. [2023-11-06 22:27:10,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2555 states and 3666 transitions. [2023-11-06 22:27:10,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2555 to 1781. [2023-11-06 22:27:10,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.4385176866928693) internal successors, (2562), 1780 states have internal predecessors, (2562), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:10,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2562 transitions. [2023-11-06 22:27:10,933 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2562 transitions. [2023-11-06 22:27:10,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:27:10,934 INFO L428 stractBuchiCegarLoop]: Abstraction has 1781 states and 2562 transitions. [2023-11-06 22:27:10,935 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:27:10,935 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2562 transitions. [2023-11-06 22:27:10,946 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1724 [2023-11-06 22:27:10,946 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:10,946 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:10,947 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,948 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:10,948 INFO L748 eck$LassoCheckResult]: Stem: 16657#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 16658#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 16673#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16670#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16561#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 16562#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16660#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16645#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16646#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16653#L429 assume !(0 == ~M_E~0); 16461#L429-2 assume !(0 == ~T1_E~0); 16462#L434-1 assume !(0 == ~T2_E~0); 16602#L439-1 assume !(0 == ~T3_E~0); 16625#L444-1 assume !(0 == ~E_M~0); 16626#L449-1 assume !(0 == ~E_1~0); 16464#L454-1 assume !(0 == ~E_2~0); 16465#L459-1 assume !(0 == ~E_3~0); 16421#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16422#L208 assume !(1 == ~m_pc~0); 16709#L208-2 is_master_triggered_~__retres1~0#1 := 0; 16710#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16628#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 16449#L531 assume !(0 != activate_threads_~tmp~1#1); 16450#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16570#L227 assume !(1 == ~t1_pc~0); 16447#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16448#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16435#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 16436#L539 assume !(0 != activate_threads_~tmp___0~0#1); 16463#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16495#L246 assume !(1 == ~t2_pc~0); 16496#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16606#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16607#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16664#L547 assume !(0 != activate_threads_~tmp___1~0#1); 16665#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16508#L265 assume !(1 == ~t3_pc~0); 16384#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16354#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16355#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16385#L555 assume !(0 != activate_threads_~tmp___2~0#1); 16475#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16476#L477 assume !(1 == ~M_E~0); 16656#L477-2 assume !(1 == ~T1_E~0); 16674#L482-1 assume !(1 == ~T2_E~0); 16620#L487-1 assume !(1 == ~T3_E~0); 16621#L492-1 assume !(1 == ~E_M~0); 16428#L497-1 assume !(1 == ~E_1~0); 16429#L502-1 assume !(1 == ~E_2~0); 16412#L507-1 assume !(1 == ~E_3~0); 16413#L512-1 assume { :end_inline_reset_delta_events } true; 16567#L678-2 [2023-11-06 22:27:10,948 INFO L750 eck$LassoCheckResult]: Loop: 16567#L678-2 assume !false; 17821#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17808#L404-1 assume !false; 17798#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17795#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17790#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17789#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 17787#L357 assume !(0 != eval_~tmp~0#1); 17788#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18012#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18010#L429-3 assume !(0 == ~M_E~0); 18008#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18006#L434-3 assume !(0 == ~T2_E~0); 18004#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18002#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17999#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17997#L454-3 assume !(0 == ~E_2~0); 17995#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17993#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17991#L208-15 assume !(1 == ~m_pc~0); 17989#L208-17 is_master_triggered_~__retres1~0#1 := 0; 17987#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17986#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 17984#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17981#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17979#L227-15 assume 1 == ~t1_pc~0; 17975#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17973#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17971#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 17968#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17966#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16627#L246-15 assume !(1 == ~t2_pc~0); 16377#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 16378#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16692#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16701#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16459#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16460#L265-15 assume 1 == ~t3_pc~0; 16541#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16542#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16580#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16517#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16518#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16671#L477-3 assume !(1 == ~M_E~0); 16632#L477-5 assume !(1 == ~T1_E~0); 16633#L482-3 assume !(1 == ~T2_E~0); 16527#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16528#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16901#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16899#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16897#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16895#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 16893#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 16888#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 16702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 16662#L697 assume !(0 == start_simulation_~tmp~3#1); 16663#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 17867#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 17859#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 17847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 17843#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17838#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17834#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 17830#L710 assume !(0 != start_simulation_~tmp___0~1#1); 16567#L678-2 [2023-11-06 22:27:10,949 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 1 times [2023-11-06 22:27:10,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357857180] [2023-11-06 22:27:10,950 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,950 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:10,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:10,959 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:10,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:10,995 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:10,996 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:10,996 INFO L85 PathProgramCache]: Analyzing trace with hash -112797122, now seen corresponding path program 1 times [2023-11-06 22:27:10,996 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:10,996 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735910494] [2023-11-06 22:27:10,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:10,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:11,029 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:11,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:11,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1735910494] [2023-11-06 22:27:11,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1735910494] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:11,030 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:11,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:11,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [809993022] [2023-11-06 22:27:11,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:11,031 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:11,032 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:11,032 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:11,032 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:11,033 INFO L87 Difference]: Start difference. First operand 1781 states and 2562 transitions. cyclomatic complexity: 783 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:11,066 INFO L93 Difference]: Finished difference Result 2104 states and 3022 transitions. [2023-11-06 22:27:11,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2104 states and 3022 transitions. [2023-11-06 22:27:11,102 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2012 [2023-11-06 22:27:11,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2104 states to 2104 states and 3022 transitions. [2023-11-06 22:27:11,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2104 [2023-11-06 22:27:11,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2104 [2023-11-06 22:27:11,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2104 states and 3022 transitions. [2023-11-06 22:27:11,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:11,125 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2104 states and 3022 transitions. [2023-11-06 22:27:11,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2104 states and 3022 transitions. [2023-11-06 22:27:11,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2104 to 2104. [2023-11-06 22:27:11,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2104 states, 2104 states have (on average 1.4363117870722433) internal successors, (3022), 2103 states have internal predecessors, (3022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2104 states to 2104 states and 3022 transitions. [2023-11-06 22:27:11,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2104 states and 3022 transitions. [2023-11-06 22:27:11,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:11,175 INFO L428 stractBuchiCegarLoop]: Abstraction has 2104 states and 3022 transitions. [2023-11-06 22:27:11,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:27:11,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2104 states and 3022 transitions. [2023-11-06 22:27:11,185 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2012 [2023-11-06 22:27:11,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:11,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:11,186 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,187 INFO L748 eck$LassoCheckResult]: Stem: 20551#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 20552#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 20571#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20567#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20451#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 20452#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20556#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20539#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20540#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20547#L429 assume !(0 == ~M_E~0); 20351#L429-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20352#L434-1 assume !(0 == ~T2_E~0); 20494#L439-1 assume !(0 == ~T3_E~0); 20519#L444-1 assume !(0 == ~E_M~0); 20520#L449-1 assume !(0 == ~E_1~0); 20654#L454-1 assume !(0 == ~E_2~0); 20618#L459-1 assume !(0 == ~E_3~0); 20619#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20653#L208 assume !(1 == ~m_pc~0); 20612#L208-2 is_master_triggered_~__retres1~0#1 := 0; 20613#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20522#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 20339#L531 assume !(0 != activate_threads_~tmp~1#1); 20340#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20460#L227 assume !(1 == ~t1_pc~0); 20337#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20338#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20325#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 20326#L539 assume !(0 != activate_threads_~tmp___0~0#1); 20354#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20641#L246 assume !(1 == ~t2_pc~0); 20640#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20639#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20638#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20637#L547 assume !(0 != activate_threads_~tmp___1~0#1); 20636#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20635#L265 assume !(1 == ~t3_pc~0); 20275#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20245#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20276#L555 assume !(0 != activate_threads_~tmp___2~0#1); 20366#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20367#L477 assume !(1 == ~M_E~0); 20550#L477-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20572#L482-1 assume !(1 == ~T2_E~0); 20515#L487-1 assume !(1 == ~T3_E~0); 20516#L492-1 assume !(1 == ~E_M~0); 20318#L497-1 assume !(1 == ~E_1~0); 20319#L502-1 assume !(1 == ~E_2~0); 20303#L507-1 assume !(1 == ~E_3~0); 20304#L512-1 assume { :end_inline_reset_delta_events } true; 20457#L678-2 [2023-11-06 22:27:11,187 INFO L750 eck$LassoCheckResult]: Loop: 20457#L678-2 assume !false; 22188#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22187#L404-1 assume !false; 20458#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20459#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 21807#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 21805#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 21802#L357 assume !(0 != eval_~tmp~0#1); 21803#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22115#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22114#L429-3 assume !(0 == ~M_E~0); 22113#L429-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22112#L434-3 assume !(0 == ~T2_E~0); 22110#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22108#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22105#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22103#L454-3 assume !(0 == ~E_2~0); 22101#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22099#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22097#L208-15 assume !(1 == ~m_pc~0); 22095#L208-17 is_master_triggered_~__retres1~0#1 := 0; 22093#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22091#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 22089#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 22086#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22084#L227-15 assume 1 == ~t1_pc~0; 21984#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21982#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21980#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 21978#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21976#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21974#L246-15 assume !(1 == ~t2_pc~0); 21972#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 21970#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21968#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 21966#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21964#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21962#L265-15 assume 1 == ~t3_pc~0; 21958#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21956#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21954#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21952#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21950#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21946#L477-3 assume !(1 == ~M_E~0); 21945#L477-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22218#L482-3 assume !(1 == ~T2_E~0); 22217#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22216#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22215#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21937#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20533#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20446#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 20307#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 20266#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 20267#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 20603#L697 assume !(0 == start_simulation_~tmp~3#1); 22199#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 22198#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 22194#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 22193#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 22192#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22191#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22190#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 22189#L710 assume !(0 != start_simulation_~tmp___0~1#1); 20457#L678-2 [2023-11-06 22:27:11,188 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1665536133, now seen corresponding path program 1 times [2023-11-06 22:27:11,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1524717933] [2023-11-06 22:27:11,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:11,219 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:11,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:11,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1524717933] [2023-11-06 22:27:11,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1524717933] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:11,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:11,220 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:27:11,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421420896] [2023-11-06 22:27:11,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:11,221 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:11,222 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,222 INFO L85 PathProgramCache]: Analyzing trace with hash 704851328, now seen corresponding path program 1 times [2023-11-06 22:27:11,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663306200] [2023-11-06 22:27:11,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:11,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:11,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:11,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663306200] [2023-11-06 22:27:11,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663306200] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:11,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:11,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:27:11,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2038026258] [2023-11-06 22:27:11,274 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:11,274 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:11,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:11,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:11,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:11,275 INFO L87 Difference]: Start difference. First operand 2104 states and 3022 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 2 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:11,298 INFO L93 Difference]: Finished difference Result 1781 states and 2536 transitions. [2023-11-06 22:27:11,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1781 states and 2536 transitions. [2023-11-06 22:27:11,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1724 [2023-11-06 22:27:11,321 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1781 states to 1781 states and 2536 transitions. [2023-11-06 22:27:11,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1781 [2023-11-06 22:27:11,323 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1781 [2023-11-06 22:27:11,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1781 states and 2536 transitions. [2023-11-06 22:27:11,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:11,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2536 transitions. [2023-11-06 22:27:11,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1781 states and 2536 transitions. [2023-11-06 22:27:11,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1781 to 1781. [2023-11-06 22:27:11,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1781 states, 1781 states have (on average 1.4239191465468837) internal successors, (2536), 1780 states have internal predecessors, (2536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1781 states to 1781 states and 2536 transitions. [2023-11-06 22:27:11,368 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1781 states and 2536 transitions. [2023-11-06 22:27:11,368 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:11,369 INFO L428 stractBuchiCegarLoop]: Abstraction has 1781 states and 2536 transitions. [2023-11-06 22:27:11,369 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:27:11,369 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1781 states and 2536 transitions. [2023-11-06 22:27:11,377 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1724 [2023-11-06 22:27:11,377 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:11,377 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:11,378 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,378 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,379 INFO L748 eck$LassoCheckResult]: Stem: 24432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 24433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24450#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24447#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24339#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 24340#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24437#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24419#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24420#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24428#L429 assume !(0 == ~M_E~0); 24244#L429-2 assume !(0 == ~T1_E~0); 24245#L434-1 assume !(0 == ~T2_E~0); 24378#L439-1 assume !(0 == ~T3_E~0); 24400#L444-1 assume !(0 == ~E_M~0); 24401#L449-1 assume !(0 == ~E_1~0); 24247#L454-1 assume !(0 == ~E_2~0); 24248#L459-1 assume !(0 == ~E_3~0); 24205#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24206#L208 assume !(1 == ~m_pc~0); 24484#L208-2 is_master_triggered_~__retres1~0#1 := 0; 24485#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24403#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24232#L531 assume !(0 != activate_threads_~tmp~1#1); 24233#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24347#L227 assume !(1 == ~t1_pc~0); 24230#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 24231#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24218#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24219#L539 assume !(0 != activate_threads_~tmp___0~0#1); 24246#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24278#L246 assume !(1 == ~t2_pc~0); 24279#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 24382#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24383#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24441#L547 assume !(0 != activate_threads_~tmp___1~0#1); 24442#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24291#L265 assume !(1 == ~t3_pc~0); 24168#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 24139#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24140#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24169#L555 assume !(0 != activate_threads_~tmp___2~0#1); 24258#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24259#L477 assume !(1 == ~M_E~0); 24431#L477-2 assume !(1 == ~T1_E~0); 24451#L482-1 assume !(1 == ~T2_E~0); 24396#L487-1 assume !(1 == ~T3_E~0); 24397#L492-1 assume !(1 == ~E_M~0); 24211#L497-1 assume !(1 == ~E_1~0); 24212#L502-1 assume !(1 == ~E_2~0); 24196#L507-1 assume !(1 == ~E_3~0); 24197#L512-1 assume { :end_inline_reset_delta_events } true; 24345#L678-2 [2023-11-06 22:27:11,379 INFO L750 eck$LassoCheckResult]: Loop: 24345#L678-2 assume !false; 25720#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25719#L404-1 assume !false; 25718#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25716#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25712#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25710#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 25708#L357 assume !(0 != eval_~tmp~0#1); 24330#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24331#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 24372#L429-3 assume !(0 == ~M_E~0); 24470#L429-5 assume !(0 == ~T1_E~0); 24421#L434-3 assume !(0 == ~T2_E~0); 24422#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24254#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24255#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24269#L454-3 assume !(0 == ~E_2~0); 24305#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24249#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24250#L208-15 assume !(1 == ~m_pc~0); 24405#L208-17 is_master_triggered_~__retres1~0#1 := 0; 24406#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24313#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 24314#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 24270#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24271#L227-15 assume 1 == ~t1_pc~0; 24480#L228-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24458#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24280#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 24281#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24418#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24402#L246-15 assume !(1 == ~t2_pc~0); 24162#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 24163#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24466#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 24476#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24242#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24243#L265-15 assume 1 == ~t3_pc~0; 24320#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 24321#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24356#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24297#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24298#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24448#L477-3 assume !(1 == ~M_E~0); 24467#L477-5 assume !(1 == ~T1_E~0); 25830#L482-3 assume !(1 == ~T2_E~0); 25829#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25828#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25827#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25825#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25823#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25821#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25819#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25814#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25812#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 25811#L697 assume !(0 == start_simulation_~tmp~3#1); 25809#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 25807#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 25801#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 25799#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 25797#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25795#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25793#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 25791#L710 assume !(0 != start_simulation_~tmp___0~1#1); 24345#L678-2 [2023-11-06 22:27:11,379 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 2 times [2023-11-06 22:27:11,380 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,380 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082259839] [2023-11-06 22:27:11,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:11,389 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:11,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:11,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:11,406 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,406 INFO L85 PathProgramCache]: Analyzing trace with hash 331103552, now seen corresponding path program 1 times [2023-11-06 22:27:11,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [523597419] [2023-11-06 22:27:11,407 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:11,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:11,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:11,456 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [523597419] [2023-11-06 22:27:11,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [523597419] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:11,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:11,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:27:11,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [993243322] [2023-11-06 22:27:11,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:11,458 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:11,458 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:11,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:27:11,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:27:11,459 INFO L87 Difference]: Start difference. First operand 1781 states and 2536 transitions. cyclomatic complexity: 757 Second operand has 5 states, 5 states have (on average 12.8) internal successors, (64), 5 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:11,583 INFO L93 Difference]: Finished difference Result 3117 states and 4368 transitions. [2023-11-06 22:27:11,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3117 states and 4368 transitions. [2023-11-06 22:27:11,602 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3056 [2023-11-06 22:27:11,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3117 states to 3117 states and 4368 transitions. [2023-11-06 22:27:11,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3117 [2023-11-06 22:27:11,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3117 [2023-11-06 22:27:11,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3117 states and 4368 transitions. [2023-11-06 22:27:11,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:11,634 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3117 states and 4368 transitions. [2023-11-06 22:27:11,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3117 states and 4368 transitions. [2023-11-06 22:27:11,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3117 to 1805. [2023-11-06 22:27:11,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1805 states, 1805 states have (on average 1.4182825484764543) internal successors, (2560), 1804 states have internal predecessors, (2560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1805 states to 1805 states and 2560 transitions. [2023-11-06 22:27:11,682 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1805 states and 2560 transitions. [2023-11-06 22:27:11,683 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:27:11,683 INFO L428 stractBuchiCegarLoop]: Abstraction has 1805 states and 2560 transitions. [2023-11-06 22:27:11,683 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:27:11,683 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1805 states and 2560 transitions. [2023-11-06 22:27:11,691 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1748 [2023-11-06 22:27:11,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:11,692 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:11,693 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,693 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:11,693 INFO L748 eck$LassoCheckResult]: Stem: 29351#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 29352#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29371#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29367#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29254#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 29255#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29356#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29337#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29338#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29346#L429 assume !(0 == ~M_E~0); 29159#L429-2 assume !(0 == ~T1_E~0); 29160#L434-1 assume !(0 == ~T2_E~0); 29290#L439-1 assume !(0 == ~T3_E~0); 29315#L444-1 assume !(0 == ~E_M~0); 29316#L449-1 assume !(0 == ~E_1~0); 29162#L454-1 assume !(0 == ~E_2~0); 29163#L459-1 assume !(0 == ~E_3~0); 29118#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29119#L208 assume !(1 == ~m_pc~0); 29413#L208-2 is_master_triggered_~__retres1~0#1 := 0; 29414#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29319#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29147#L531 assume !(0 != activate_threads_~tmp~1#1); 29148#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29262#L227 assume !(1 == ~t1_pc~0); 29145#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 29146#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29134#L539 assume !(0 != activate_threads_~tmp___0~0#1); 29161#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29192#L246 assume !(1 == ~t2_pc~0); 29193#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 29294#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29295#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 29361#L547 assume !(0 != activate_threads_~tmp___1~0#1); 29362#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29205#L265 assume !(1 == ~t3_pc~0); 29081#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29054#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29055#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29082#L555 assume !(0 != activate_threads_~tmp___2~0#1); 29173#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29174#L477 assume !(1 == ~M_E~0); 29349#L477-2 assume !(1 == ~T1_E~0); 29372#L482-1 assume !(1 == ~T2_E~0); 29311#L487-1 assume !(1 == ~T3_E~0); 29312#L492-1 assume !(1 == ~E_M~0); 29126#L497-1 assume !(1 == ~E_1~0); 29127#L502-1 assume !(1 == ~E_2~0); 29109#L507-1 assume !(1 == ~E_3~0); 29110#L512-1 assume { :end_inline_reset_delta_events } true; 29260#L678-2 [2023-11-06 22:27:11,694 INFO L750 eck$LassoCheckResult]: Loop: 29260#L678-2 assume !false; 30412#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 30269#L404-1 assume !false; 30259#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30256#L320 assume !(0 == ~m_st~0); 30253#L324 assume !(0 == ~t1_st~0); 30248#L328 assume !(0 == ~t2_st~0); 30243#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 30236#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30231#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30226#L357 assume !(0 != eval_~tmp~0#1); 30224#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30222#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30220#L429-3 assume !(0 == ~M_E~0); 30210#L429-5 assume !(0 == ~T1_E~0); 30211#L434-3 assume !(0 == ~T2_E~0); 30196#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30197#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29183#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29184#L454-3 assume !(0 == ~E_2~0); 29219#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29164#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29165#L208-15 assume !(1 == ~m_pc~0); 29321#L208-17 is_master_triggered_~__retres1~0#1 := 0; 29322#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29228#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 29229#L531-15 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29297#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29406#L227-15 assume !(1 == ~t1_pc~0); 29396#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 29379#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29194#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 29195#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29336#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29317#L246-15 assume !(1 == ~t2_pc~0); 29318#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 30510#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30508#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 30506#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30504#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30502#L265-15 assume 1 == ~t3_pc~0; 30499#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30496#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30494#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30492#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30490#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30488#L477-3 assume !(1 == ~M_E~0); 30485#L477-5 assume !(1 == ~T1_E~0); 30484#L482-3 assume !(1 == ~T2_E~0); 30483#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30482#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30481#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30480#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30479#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30478#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30477#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30471#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30469#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 30467#L697 assume !(0 == start_simulation_~tmp~3#1); 30457#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 30456#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 30446#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 30442#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 30441#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30440#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30439#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 30427#L710 assume !(0 != start_simulation_~tmp___0~1#1); 29260#L678-2 [2023-11-06 22:27:11,694 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 3 times [2023-11-06 22:27:11,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205296327] [2023-11-06 22:27:11,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:11,724 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:11,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:11,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:11,741 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:11,741 INFO L85 PathProgramCache]: Analyzing trace with hash 1044594375, now seen corresponding path program 1 times [2023-11-06 22:27:11,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:11,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161283387] [2023-11-06 22:27:11,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:11,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:11,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:11,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:11,811 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:11,811 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1161283387] [2023-11-06 22:27:11,812 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1161283387] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:11,812 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:11,812 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:27:11,812 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231791490] [2023-11-06 22:27:11,812 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:11,813 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:11,813 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:11,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:27:11,813 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:27:11,813 INFO L87 Difference]: Start difference. First operand 1805 states and 2560 transitions. cyclomatic complexity: 757 Second operand has 5 states, 5 states have (on average 13.4) internal successors, (67), 5 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:11,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:11,993 INFO L93 Difference]: Finished difference Result 3129 states and 4379 transitions. [2023-11-06 22:27:11,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3129 states and 4379 transitions. [2023-11-06 22:27:12,010 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3072 [2023-11-06 22:27:12,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3129 states to 3129 states and 4379 transitions. [2023-11-06 22:27:12,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3129 [2023-11-06 22:27:12,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3129 [2023-11-06 22:27:12,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3129 states and 4379 transitions. [2023-11-06 22:27:12,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:12,040 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3129 states and 4379 transitions. [2023-11-06 22:27:12,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3129 states and 4379 transitions. [2023-11-06 22:27:12,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3129 to 1865. [2023-11-06 22:27:12,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1865 states, 1865 states have (on average 1.3957104557640752) internal successors, (2603), 1864 states have internal predecessors, (2603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1865 states to 1865 states and 2603 transitions. [2023-11-06 22:27:12,094 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1865 states and 2603 transitions. [2023-11-06 22:27:12,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:27:12,095 INFO L428 stractBuchiCegarLoop]: Abstraction has 1865 states and 2603 transitions. [2023-11-06 22:27:12,095 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:27:12,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1865 states and 2603 transitions. [2023-11-06 22:27:12,103 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1808 [2023-11-06 22:27:12,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:12,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:12,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,104 INFO L748 eck$LassoCheckResult]: Stem: 34315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 34316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 34335#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34332#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34206#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 34207#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34318#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34301#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34302#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34310#L429 assume !(0 == ~M_E~0); 34108#L429-2 assume !(0 == ~T1_E~0); 34109#L434-1 assume !(0 == ~T2_E~0); 34248#L439-1 assume !(0 == ~T3_E~0); 34282#L444-1 assume !(0 == ~E_M~0); 34283#L449-1 assume !(0 == ~E_1~0); 34113#L454-1 assume !(0 == ~E_2~0); 34114#L459-1 assume !(0 == ~E_3~0); 34068#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34069#L208 assume !(1 == ~m_pc~0); 34391#L208-2 is_master_triggered_~__retres1~0#1 := 0; 34392#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34285#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 34096#L531 assume !(0 != activate_threads_~tmp~1#1); 34097#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34215#L227 assume !(1 == ~t1_pc~0); 34094#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34095#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34084#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 34085#L539 assume !(0 != activate_threads_~tmp___0~0#1); 34110#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34144#L246 assume !(1 == ~t2_pc~0); 34145#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34253#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34254#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34323#L547 assume !(0 != activate_threads_~tmp___1~0#1); 34324#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34157#L265 assume !(1 == ~t3_pc~0); 34030#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34000#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34001#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34033#L555 assume !(0 != activate_threads_~tmp___2~0#1); 34127#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34128#L477 assume !(1 == ~M_E~0); 34314#L477-2 assume !(1 == ~T1_E~0); 34336#L482-1 assume !(1 == ~T2_E~0); 34280#L487-1 assume !(1 == ~T3_E~0); 34281#L492-1 assume !(1 == ~E_M~0); 34076#L497-1 assume !(1 == ~E_1~0); 34077#L502-1 assume !(1 == ~E_2~0); 34060#L507-1 assume !(1 == ~E_3~0); 34061#L512-1 assume { :end_inline_reset_delta_events } true; 34211#L678-2 [2023-11-06 22:27:12,105 INFO L750 eck$LassoCheckResult]: Loop: 34211#L678-2 assume !false; 35023#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35017#L404-1 assume !false; 35014#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35008#L320 assume !(0 == ~m_st~0); 35009#L324 assume !(0 == ~t1_st~0); 35005#L328 assume !(0 == ~t2_st~0); 35006#L332 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4#1 := 0; 35007#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 34974#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34975#L357 assume !(0 != eval_~tmp~0#1); 35245#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35243#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35241#L429-3 assume !(0 == ~M_E~0); 35239#L429-5 assume !(0 == ~T1_E~0); 35237#L434-3 assume !(0 == ~T2_E~0); 35235#L439-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35233#L444-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35231#L449-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35226#L454-3 assume !(0 == ~E_2~0); 35224#L459-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34111#L464-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34112#L208-15 assume !(1 == ~m_pc~0); 34360#L208-17 is_master_triggered_~__retres1~0#1 := 0; 35269#L219-5 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35268#is_master_triggered_returnLabel#6 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 35267#L531-15 assume !(0 != activate_threads_~tmp~1#1); 35266#L531-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35265#L227-15 assume !(1 == ~t1_pc~0); 35264#L227-17 is_transmit1_triggered_~__retres1~1#1 := 0; 35262#L238-5 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35261#is_transmit1_triggered_returnLabel#6 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 35260#L539-15 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35259#L539-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35258#L246-15 assume !(1 == ~t2_pc~0); 34744#L246-17 is_transmit2_triggered_~__retres1~2#1 := 0; 35257#L257-5 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35256#is_transmit2_triggered_returnLabel#6 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 35255#L547-15 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35254#L547-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35253#L265-15 assume 1 == ~t3_pc~0; 35251#L266-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 35250#L276-5 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35249#is_transmit3_triggered_returnLabel#6 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 35248#L555-15 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35247#L555-17 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35246#L477-3 assume !(1 == ~M_E~0); 35095#L477-5 assume !(1 == ~T1_E~0); 35244#L482-3 assume !(1 == ~T2_E~0); 35242#L487-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35240#L492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35238#L497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35236#L502-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35234#L507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35232#L512-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35230#L320-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35225#L342-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35223#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret15#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret15#1;havoc start_simulation_#t~ret15#1; 34320#L697 assume !(0 == start_simulation_~tmp~3#1); 34322#L697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 35065#L320-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 35058#L342-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 35053#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret14#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret14#1;havoc stop_simulation_#t~ret14#1; 35048#L652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35040#L659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35036#stop_simulation_returnLabel#1 start_simulation_#t~ret16#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret14#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret16#1;havoc start_simulation_#t~ret16#1; 35031#L710 assume !(0 != start_simulation_~tmp___0~1#1); 34211#L678-2 [2023-11-06 22:27:12,105 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1279836229, now seen corresponding path program 4 times [2023-11-06 22:27:12,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674947900] [2023-11-06 22:27:12,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:12,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:12,129 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1468241097, now seen corresponding path program 1 times [2023-11-06 22:27:12,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [244969035] [2023-11-06 22:27:12,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:12,161 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:12,161 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:12,161 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [244969035] [2023-11-06 22:27:12,162 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [244969035] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:12,162 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:12,162 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:12,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242633875] [2023-11-06 22:27:12,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:12,162 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:27:12,163 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:12,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:12,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:12,163 INFO L87 Difference]: Start difference. First operand 1865 states and 2603 transitions. cyclomatic complexity: 740 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,225 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:12,225 INFO L93 Difference]: Finished difference Result 2876 states and 3960 transitions. [2023-11-06 22:27:12,225 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2876 states and 3960 transitions. [2023-11-06 22:27:12,240 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2819 [2023-11-06 22:27:12,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2876 states to 2876 states and 3960 transitions. [2023-11-06 22:27:12,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2876 [2023-11-06 22:27:12,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2876 [2023-11-06 22:27:12,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2876 states and 3960 transitions. [2023-11-06 22:27:12,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:12,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2876 states and 3960 transitions. [2023-11-06 22:27:12,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2876 states and 3960 transitions. [2023-11-06 22:27:12,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2876 to 2786. [2023-11-06 22:27:12,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2786 states, 2786 states have (on average 1.377602297200287) internal successors, (3838), 2785 states have internal predecessors, (3838), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2786 states to 2786 states and 3838 transitions. [2023-11-06 22:27:12,322 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2786 states and 3838 transitions. [2023-11-06 22:27:12,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:12,323 INFO L428 stractBuchiCegarLoop]: Abstraction has 2786 states and 3838 transitions. [2023-11-06 22:27:12,323 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:27:12,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2786 states and 3838 transitions. [2023-11-06 22:27:12,335 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2729 [2023-11-06 22:27:12,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:12,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:12,335 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,336 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,336 INFO L748 eck$LassoCheckResult]: Stem: 39050#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 39051#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 39068#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38954#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 38955#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39053#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39037#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39038#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39045#L429 assume !(0 == ~M_E~0); 38853#L429-2 assume !(0 == ~T1_E~0); 38854#L434-1 assume !(0 == ~T2_E~0); 38994#L439-1 assume !(0 == ~T3_E~0); 39019#L444-1 assume !(0 == ~E_M~0); 39020#L449-1 assume !(0 == ~E_1~0); 38858#L454-1 assume !(0 == ~E_2~0); 38859#L459-1 assume !(0 == ~E_3~0); 38813#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38814#L208 assume !(1 == ~m_pc~0); 39108#L208-2 is_master_triggered_~__retres1~0#1 := 0; 39109#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39022#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 38841#L531 assume !(0 != activate_threads_~tmp~1#1); 38842#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38960#L227 assume !(1 == ~t1_pc~0); 38839#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38840#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38830#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 38831#L539 assume !(0 != activate_threads_~tmp___0~0#1); 38855#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38888#L246 assume !(1 == ~t2_pc~0); 38889#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38999#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39000#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39056#L547 assume !(0 != activate_threads_~tmp___1~0#1); 39057#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38901#L265 assume !(1 == ~t3_pc~0); 38776#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38747#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38748#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38779#L555 assume !(0 != activate_threads_~tmp___2~0#1); 38872#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38873#L477 assume !(1 == ~M_E~0); 39049#L477-2 assume !(1 == ~T1_E~0); 39069#L482-1 assume !(1 == ~T2_E~0); 39017#L487-1 assume !(1 == ~T3_E~0); 39018#L492-1 assume !(1 == ~E_M~0); 38825#L497-1 assume !(1 == ~E_1~0); 38826#L502-1 assume !(1 == ~E_2~0); 38806#L507-1 assume !(1 == ~E_3~0); 38807#L512-1 assume { :end_inline_reset_delta_events } true; 38956#L678-2 assume !false; 39948#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39944#L404-1 [2023-11-06 22:27:12,336 INFO L750 eck$LassoCheckResult]: Loop: 39944#L404-1 assume !false; 39939#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 39933#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 39928#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 39924#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 39919#L357 assume 0 != eval_~tmp~0#1; 39912#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 39908#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 39904#L365-2 havoc eval_~tmp_ndt_1~0#1; 39897#L362-1 assume !(0 == ~t1_st~0); 39892#L376-1 assume !(0 == ~t2_st~0); 39893#L390-1 assume !(0 == ~t3_st~0); 39944#L404-1 [2023-11-06 22:27:12,336 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,337 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 1 times [2023-11-06 22:27:12,337 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,337 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [929944178] [2023-11-06 22:27:12,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,337 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,345 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,346 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:12,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,359 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:12,359 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,359 INFO L85 PathProgramCache]: Analyzing trace with hash -616621386, now seen corresponding path program 1 times [2023-11-06 22:27:12,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,360 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1010781444] [2023-11-06 22:27:12,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,363 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:12,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:12,368 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,368 INFO L85 PathProgramCache]: Analyzing trace with hash 945603068, now seen corresponding path program 1 times [2023-11-06 22:27:12,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1455359941] [2023-11-06 22:27:12,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:12,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:12,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:12,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1455359941] [2023-11-06 22:27:12,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1455359941] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:12,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:12,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:12,435 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660901952] [2023-11-06 22:27:12,435 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:12,529 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:12,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:12,530 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:12,530 INFO L87 Difference]: Start difference. First operand 2786 states and 3838 transitions. cyclomatic complexity: 1055 Second operand has 3 states, 3 states have (on average 21.666666666666668) internal successors, (65), 3 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:12,597 INFO L93 Difference]: Finished difference Result 4996 states and 6805 transitions. [2023-11-06 22:27:12,597 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4996 states and 6805 transitions. [2023-11-06 22:27:12,623 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4888 [2023-11-06 22:27:12,660 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4996 states to 4996 states and 6805 transitions. [2023-11-06 22:27:12,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4996 [2023-11-06 22:27:12,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4996 [2023-11-06 22:27:12,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4996 states and 6805 transitions. [2023-11-06 22:27:12,673 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:12,673 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4996 states and 6805 transitions. [2023-11-06 22:27:12,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4996 states and 6805 transitions. [2023-11-06 22:27:12,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4996 to 4751. [2023-11-06 22:27:12,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4751 states, 4751 states have (on average 1.3660282045885077) internal successors, (6490), 4750 states have internal predecessors, (6490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4751 states to 4751 states and 6490 transitions. [2023-11-06 22:27:12,785 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4751 states and 6490 transitions. [2023-11-06 22:27:12,786 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:12,787 INFO L428 stractBuchiCegarLoop]: Abstraction has 4751 states and 6490 transitions. [2023-11-06 22:27:12,787 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:27:12,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4751 states and 6490 transitions. [2023-11-06 22:27:12,805 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4643 [2023-11-06 22:27:12,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:12,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:12,806 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,806 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:12,806 INFO L748 eck$LassoCheckResult]: Stem: 46879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 46880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 46897#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46749#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 46750#L292-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 46904#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46857#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46858#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46927#L429 assume !(0 == ~M_E~0); 46928#L429-2 assume !(0 == ~T1_E~0); 46801#L434-1 assume !(0 == ~T2_E~0); 46802#L439-1 assume !(0 == ~T3_E~0); 46834#L444-1 assume !(0 == ~E_M~0); 46835#L449-1 assume !(0 == ~E_1~0); 46649#L454-1 assume !(0 == ~E_2~0); 46650#L459-1 assume !(0 == ~E_3~0); 46605#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46606#L208 assume !(1 == ~m_pc~0); 46962#L208-2 is_master_triggered_~__retres1~0#1 := 0; 46963#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46837#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 46838#L531 assume !(0 != activate_threads_~tmp~1#1); 46783#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46784#L227 assume !(1 == ~t1_pc~0); 46631#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46632#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46618#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 46619#L539 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 46648#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46680#L246 assume !(1 == ~t2_pc~0); 46681#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46809#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46888#L547 assume !(0 != activate_threads_~tmp___1~0#1); 46889#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46693#L265 assume !(1 == ~t3_pc~0); 46694#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46537#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46973#L555 assume !(0 != activate_threads_~tmp___2~0#1); 46974#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46877#L477 assume !(1 == ~M_E~0); 46878#L477-2 assume !(1 == ~T1_E~0); 46898#L482-1 assume !(1 == ~T2_E~0); 46899#L487-1 assume !(1 == ~T3_E~0); 46923#L492-1 assume !(1 == ~E_M~0); 46924#L497-1 assume !(1 == ~E_1~0); 46790#L502-1 assume !(1 == ~E_2~0); 46791#L507-1 assume !(1 == ~E_3~0); 46756#L512-1 assume { :end_inline_reset_delta_events } true; 46757#L678-2 assume !false; 48456#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48455#L404-1 [2023-11-06 22:27:12,807 INFO L750 eck$LassoCheckResult]: Loop: 48455#L404-1 assume !false; 48454#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 48452#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 48451#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 48450#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 48449#L357 assume 0 != eval_~tmp~0#1; 48448#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 48446#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 48445#L365-2 havoc eval_~tmp_ndt_1~0#1; 48444#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 48097#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 48443#L379-2 havoc eval_~tmp_ndt_2~0#1; 48463#L376-1 assume !(0 == ~t2_st~0); 48458#L390-1 assume !(0 == ~t3_st~0); 48455#L404-1 [2023-11-06 22:27:12,807 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,807 INFO L85 PathProgramCache]: Analyzing trace with hash -934376957, now seen corresponding path program 1 times [2023-11-06 22:27:12,808 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,808 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422993038] [2023-11-06 22:27:12,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,808 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:12,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:12,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:12,839 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1422993038] [2023-11-06 22:27:12,839 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1422993038] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:12,839 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:12,839 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:12,840 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348355299] [2023-11-06 22:27:12,840 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:12,841 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:27:12,841 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:12,841 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 1 times [2023-11-06 22:27:12,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:12,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514068611] [2023-11-06 22:27:12,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:12,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:12,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,848 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:12,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:12,853 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:12,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:12,949 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:12,949 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:12,949 INFO L87 Difference]: Start difference. First operand 4751 states and 6490 transitions. cyclomatic complexity: 1742 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:12,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:12,991 INFO L93 Difference]: Finished difference Result 4702 states and 6423 transitions. [2023-11-06 22:27:12,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4702 states and 6423 transitions. [2023-11-06 22:27:13,014 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4643 [2023-11-06 22:27:13,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4702 states to 4702 states and 6423 transitions. [2023-11-06 22:27:13,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4702 [2023-11-06 22:27:13,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4702 [2023-11-06 22:27:13,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4702 states and 6423 transitions. [2023-11-06 22:27:13,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:13,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4702 states and 6423 transitions. [2023-11-06 22:27:13,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4702 states and 6423 transitions. [2023-11-06 22:27:13,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4702 to 4702. [2023-11-06 22:27:13,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4702 states, 4702 states have (on average 1.3660144619310932) internal successors, (6423), 4701 states have internal predecessors, (6423), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:13,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4702 states to 4702 states and 6423 transitions. [2023-11-06 22:27:13,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4702 states and 6423 transitions. [2023-11-06 22:27:13,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:13,194 INFO L428 stractBuchiCegarLoop]: Abstraction has 4702 states and 6423 transitions. [2023-11-06 22:27:13,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:27:13,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4702 states and 6423 transitions. [2023-11-06 22:27:13,218 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4643 [2023-11-06 22:27:13,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:13,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:13,219 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:13,220 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:13,220 INFO L748 eck$LassoCheckResult]: Stem: 56304#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 56305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 56324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56197#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 56198#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56307#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56289#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56290#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56298#L429 assume !(0 == ~M_E~0); 56098#L429-2 assume !(0 == ~T1_E~0); 56099#L434-1 assume !(0 == ~T2_E~0); 56239#L439-1 assume !(0 == ~T3_E~0); 56267#L444-1 assume !(0 == ~E_M~0); 56268#L449-1 assume !(0 == ~E_1~0); 56101#L454-1 assume !(0 == ~E_2~0); 56102#L459-1 assume !(0 == ~E_3~0); 56059#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56060#L208 assume !(1 == ~m_pc~0); 56363#L208-2 is_master_triggered_~__retres1~0#1 := 0; 56364#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56271#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 56086#L531 assume !(0 != activate_threads_~tmp~1#1); 56087#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56206#L227 assume !(1 == ~t1_pc~0); 56084#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56085#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56072#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56073#L539 assume !(0 != activate_threads_~tmp___0~0#1); 56100#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56131#L246 assume !(1 == ~t2_pc~0); 56132#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 56244#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56245#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56313#L547 assume !(0 != activate_threads_~tmp___1~0#1); 56314#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56145#L265 assume !(1 == ~t3_pc~0); 56023#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 55996#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55997#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56024#L555 assume !(0 != activate_threads_~tmp___2~0#1); 56112#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56113#L477 assume !(1 == ~M_E~0); 56303#L477-2 assume !(1 == ~T1_E~0); 56325#L482-1 assume !(1 == ~T2_E~0); 56262#L487-1 assume !(1 == ~T3_E~0); 56263#L492-1 assume !(1 == ~E_M~0); 56065#L497-1 assume !(1 == ~E_1~0); 56066#L502-1 assume !(1 == ~E_2~0); 56050#L507-1 assume !(1 == ~E_3~0); 56051#L512-1 assume { :end_inline_reset_delta_events } true; 56204#L678-2 assume !false; 57795#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57794#L404-1 [2023-11-06 22:27:13,220 INFO L750 eck$LassoCheckResult]: Loop: 57794#L404-1 assume !false; 57792#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 57790#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 57789#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 57787#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 57785#L357 assume 0 != eval_~tmp~0#1; 57782#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 57777#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 57772#L365-2 havoc eval_~tmp_ndt_1~0#1; 57768#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 57763#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 57760#L379-2 havoc eval_~tmp_ndt_2~0#1; 57756#L376-1 assume !(0 == ~t2_st~0); 57757#L390-1 assume !(0 == ~t3_st~0); 57794#L404-1 [2023-11-06 22:27:13,221 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 2 times [2023-11-06 22:27:13,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125782099] [2023-11-06 22:27:13,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,239 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:13,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,254 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:13,254 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,255 INFO L85 PathProgramCache]: Analyzing trace with hash 6018452, now seen corresponding path program 2 times [2023-11-06 22:27:13,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [751734536] [2023-11-06 22:27:13,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,262 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:13,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,269 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:13,270 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1934834854, now seen corresponding path program 1 times [2023-11-06 22:27:13,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069305034] [2023-11-06 22:27:13,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:13,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:13,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:13,335 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069305034] [2023-11-06 22:27:13,335 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069305034] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:13,335 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:13,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:27:13,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1841633218] [2023-11-06 22:27:13,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:13,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:13,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:13,424 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:13,424 INFO L87 Difference]: Start difference. First operand 4702 states and 6423 transitions. cyclomatic complexity: 1724 Second operand has 3 states, 3 states have (on average 22.333333333333332) internal successors, (67), 3 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:13,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:13,500 INFO L93 Difference]: Finished difference Result 8493 states and 11516 transitions. [2023-11-06 22:27:13,500 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8493 states and 11516 transitions. [2023-11-06 22:27:13,536 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8430 [2023-11-06 22:27:13,564 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8493 states to 8493 states and 11516 transitions. [2023-11-06 22:27:13,564 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8493 [2023-11-06 22:27:13,572 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8493 [2023-11-06 22:27:13,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8493 states and 11516 transitions. [2023-11-06 22:27:13,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:13,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8493 states and 11516 transitions. [2023-11-06 22:27:13,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8493 states and 11516 transitions. [2023-11-06 22:27:13,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8493 to 8339. [2023-11-06 22:27:13,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8339 states, 8339 states have (on average 1.3574769156973259) internal successors, (11320), 8338 states have internal predecessors, (11320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:13,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8339 states to 8339 states and 11320 transitions. [2023-11-06 22:27:13,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8339 states and 11320 transitions. [2023-11-06 22:27:13,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:13,725 INFO L428 stractBuchiCegarLoop]: Abstraction has 8339 states and 11320 transitions. [2023-11-06 22:27:13,725 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:27:13,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8339 states and 11320 transitions. [2023-11-06 22:27:13,797 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8276 [2023-11-06 22:27:13,797 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:13,797 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:13,798 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:13,798 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:13,798 INFO L748 eck$LassoCheckResult]: Stem: 69514#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 69515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 69530#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69528#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69408#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 69409#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69518#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69500#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69501#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69508#L429 assume !(0 == ~M_E~0); 69304#L429-2 assume !(0 == ~T1_E~0); 69305#L434-1 assume !(0 == ~T2_E~0); 69446#L439-1 assume !(0 == ~T3_E~0); 69477#L444-1 assume !(0 == ~E_M~0); 69478#L449-1 assume !(0 == ~E_1~0); 69309#L454-1 assume !(0 == ~E_2~0); 69310#L459-1 assume !(0 == ~E_3~0); 69263#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69264#L208 assume !(1 == ~m_pc~0); 69572#L208-2 is_master_triggered_~__retres1~0#1 := 0; 69573#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69481#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 69292#L531 assume !(0 != activate_threads_~tmp~1#1); 69293#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69414#L227 assume !(1 == ~t1_pc~0); 69290#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69291#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 69281#L539 assume !(0 != activate_threads_~tmp___0~0#1); 69306#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69340#L246 assume !(1 == ~t2_pc~0); 69341#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69451#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69452#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69521#L547 assume !(0 != activate_threads_~tmp___1~0#1); 69522#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69351#L265 assume !(1 == ~t3_pc~0); 69227#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69199#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69200#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69230#L555 assume !(0 != activate_threads_~tmp___2~0#1); 69323#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69324#L477 assume !(1 == ~M_E~0); 69513#L477-2 assume !(1 == ~T1_E~0); 69531#L482-1 assume !(1 == ~T2_E~0); 69475#L487-1 assume !(1 == ~T3_E~0); 69476#L492-1 assume !(1 == ~E_M~0); 69272#L497-1 assume !(1 == ~E_1~0); 69273#L502-1 assume !(1 == ~E_2~0); 69256#L507-1 assume !(1 == ~E_3~0); 69257#L512-1 assume { :end_inline_reset_delta_events } true; 69410#L678-2 assume !false; 71877#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 71871#L404-1 [2023-11-06 22:27:13,799 INFO L750 eck$LassoCheckResult]: Loop: 71871#L404-1 assume !false; 71867#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 71863#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 71857#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 71851#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 71844#L357 assume 0 != eval_~tmp~0#1; 71837#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 71830#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 71823#L365-2 havoc eval_~tmp_ndt_1~0#1; 70946#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 70947#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 70940#L379-2 havoc eval_~tmp_ndt_2~0#1; 70941#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 70697#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 70936#L393-2 havoc eval_~tmp_ndt_3~0#1; 71879#L390-1 assume !(0 == ~t3_st~0); 71871#L404-1 [2023-11-06 22:27:13,799 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,799 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 3 times [2023-11-06 22:27:13,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,800 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856747225] [2023-11-06 22:27:13,800 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,800 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,809 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:13,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:13,826 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1484720438, now seen corresponding path program 1 times [2023-11-06 22:27:13,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297429040] [2023-11-06 22:27:13,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,827 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,832 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:13,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:13,835 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:13,836 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:13,836 INFO L85 PathProgramCache]: Analyzing trace with hash 340499836, now seen corresponding path program 1 times [2023-11-06 22:27:13,836 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:13,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239497949] [2023-11-06 22:27:13,836 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:13,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:13,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:27:13,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:27:13,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:27:13,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239497949] [2023-11-06 22:27:13,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239497949] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:27:13,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:27:13,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:27:13,877 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1722920082] [2023-11-06 22:27:13,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:27:13,960 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:27:13,960 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:27:13,960 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:27:13,960 INFO L87 Difference]: Start difference. First operand 8339 states and 11320 transitions. cyclomatic complexity: 2984 Second operand has 3 states, 2 states have (on average 34.5) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:14,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:27:14,045 INFO L93 Difference]: Finished difference Result 14019 states and 18880 transitions. [2023-11-06 22:27:14,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14019 states and 18880 transitions. [2023-11-06 22:27:14,106 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13948 [2023-11-06 22:27:14,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14019 states to 14019 states and 18880 transitions. [2023-11-06 22:27:14,155 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14019 [2023-11-06 22:27:14,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14019 [2023-11-06 22:27:14,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14019 states and 18880 transitions. [2023-11-06 22:27:14,182 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:27:14,182 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14019 states and 18880 transitions. [2023-11-06 22:27:14,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14019 states and 18880 transitions. [2023-11-06 22:27:14,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14019 to 13795. [2023-11-06 22:27:14,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13795 states, 13795 states have (on average 1.3523740485683218) internal successors, (18656), 13794 states have internal predecessors, (18656), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:27:14,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13795 states to 13795 states and 18656 transitions. [2023-11-06 22:27:14,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13795 states and 18656 transitions. [2023-11-06 22:27:14,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:27:14,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 13795 states and 18656 transitions. [2023-11-06 22:27:14,491 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:27:14,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13795 states and 18656 transitions. [2023-11-06 22:27:14,535 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 13724 [2023-11-06 22:27:14,535 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:27:14,535 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:27:14,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:14,536 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:27:14,536 INFO L748 eck$LassoCheckResult]: Stem: 91883#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~token~0 := 0;~local~0 := 0; 91884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~5#1;havoc main_~__retres1~5#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 91904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret15#1, start_simulation_#t~ret16#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91900#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91772#L292 assume 1 == ~m_i~0;~m_st~0 := 0; 91773#L292-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91886#L297-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91868#L302-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91869#L307-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91878#L429 assume !(0 == ~M_E~0); 91668#L429-2 assume !(0 == ~T1_E~0); 91669#L434-1 assume !(0 == ~T2_E~0); 91817#L439-1 assume !(0 == ~T3_E~0); 91845#L444-1 assume !(0 == ~E_M~0); 91846#L449-1 assume !(0 == ~E_1~0); 91671#L454-1 assume !(0 == ~E_2~0); 91672#L459-1 assume !(0 == ~E_3~0); 91628#L464-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91629#L208 assume !(1 == ~m_pc~0); 91953#L208-2 is_master_triggered_~__retres1~0#1 := 0; 91954#L219 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91849#is_master_triggered_returnLabel#1 activate_threads_#t~ret10#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1; 91656#L531 assume !(0 != activate_threads_~tmp~1#1); 91657#L531-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91782#L227 assume !(1 == ~t1_pc~0); 91654#L227-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91655#L238 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91641#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 91642#L539 assume !(0 != activate_threads_~tmp___0~0#1); 91670#L539-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91702#L246 assume !(1 == ~t2_pc~0); 91703#L246-2 is_transmit2_triggered_~__retres1~2#1 := 0; 91823#L257 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91824#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91892#L547 assume !(0 != activate_threads_~tmp___1~0#1); 91893#L547-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91714#L265 assume !(1 == ~t3_pc~0); 91592#L265-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91565#L276 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91566#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91593#L555 assume !(0 != activate_threads_~tmp___2~0#1); 91682#L555-2 havoc activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91683#L477 assume !(1 == ~M_E~0); 91882#L477-2 assume !(1 == ~T1_E~0); 91905#L482-1 assume !(1 == ~T2_E~0); 91840#L487-1 assume !(1 == ~T3_E~0); 91841#L492-1 assume !(1 == ~E_M~0); 91634#L497-1 assume !(1 == ~E_1~0); 91635#L502-1 assume !(1 == ~E_2~0); 91619#L507-1 assume !(1 == ~E_3~0); 91620#L512-1 assume { :end_inline_reset_delta_events } true; 91779#L678-2 assume !false; 96127#L679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96125#L404-1 [2023-11-06 22:27:14,536 INFO L750 eck$LassoCheckResult]: Loop: 96125#L404-1 assume !false; 96123#L353 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;havoc exists_runnable_thread_~__retres1~4#1; 96119#L320 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4#1 := 1; 96117#L342 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~4#1; 96115#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~4#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 96113#L357 assume 0 != eval_~tmp~0#1; 96110#L357-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 96107#L365 assume !(0 != eval_~tmp_ndt_1~0#1); 96106#L365-2 havoc eval_~tmp_ndt_1~0#1; 96104#L362-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 95828#L379 assume !(0 != eval_~tmp_ndt_2~0#1); 96102#L379-2 havoc eval_~tmp_ndt_2~0#1; 96162#L376-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 94840#L393 assume !(0 != eval_~tmp_ndt_3~0#1); 96142#L393-2 havoc eval_~tmp_ndt_3~0#1; 96133#L390-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 96130#L407 assume !(0 != eval_~tmp_ndt_4~0#1); 96128#L407-2 havoc eval_~tmp_ndt_4~0#1; 96125#L404-1 [2023-11-06 22:27:14,536 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:14,537 INFO L85 PathProgramCache]: Analyzing trace with hash 1561976903, now seen corresponding path program 4 times [2023-11-06 22:27:14,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:14,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1782886722] [2023-11-06 22:27:14,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:14,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:14,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,547 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:14,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,564 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:14,565 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:14,565 INFO L85 PathProgramCache]: Analyzing trace with hash 887098260, now seen corresponding path program 1 times [2023-11-06 22:27:14,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:14,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052489635] [2023-11-06 22:27:14,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:14,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:14,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,569 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:14,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,574 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:14,574 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:27:14,574 INFO L85 PathProgramCache]: Analyzing trace with hash 802727514, now seen corresponding path program 1 times [2023-11-06 22:27:14,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:27:14,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404619228] [2023-11-06 22:27:14,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:27:14,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:27:14,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,584 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:14,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:14,604 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:27:15,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:15,983 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:27:16,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:27:16,192 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:27:16 BoogieIcfgContainer [2023-11-06 22:27:16,194 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:27:16,195 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:27:16,195 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:27:16,195 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:27:16,196 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:27:08" (3/4) ... [2023-11-06 22:27:16,197 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:27:16,300 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:27:16,300 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:27:16,301 INFO L158 Benchmark]: Toolchain (without parser) took 10011.22ms. Allocated memory was 136.3MB in the beginning and 497.0MB in the end (delta: 360.7MB). Free memory was 102.9MB in the beginning and 292.9MB in the end (delta: -189.9MB). Peak memory consumption was 173.3MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,301 INFO L158 Benchmark]: CDTParser took 0.60ms. Allocated memory is still 136.3MB. Free memory is still 80.9MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:27:16,301 INFO L158 Benchmark]: CACSL2BoogieTranslator took 395.11ms. Allocated memory is still 136.3MB. Free memory was 102.9MB in the beginning and 88.4MB in the end (delta: 14.6MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,302 INFO L158 Benchmark]: Boogie Procedure Inliner took 79.21ms. Allocated memory is still 136.3MB. Free memory was 88.4MB in the beginning and 84.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,302 INFO L158 Benchmark]: Boogie Preprocessor took 57.55ms. Allocated memory is still 136.3MB. Free memory was 84.6MB in the beginning and 81.3MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,302 INFO L158 Benchmark]: RCFGBuilder took 1195.17ms. Allocated memory was 136.3MB in the beginning and 167.8MB in the end (delta: 31.5MB). Free memory was 81.3MB in the beginning and 119.5MB in the end (delta: -38.1MB). Peak memory consumption was 31.1MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,303 INFO L158 Benchmark]: BuchiAutomizer took 8172.67ms. Allocated memory was 167.8MB in the beginning and 497.0MB in the end (delta: 329.3MB). Free memory was 118.4MB in the beginning and 299.2MB in the end (delta: -180.7MB). Peak memory consumption was 148.5MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,303 INFO L158 Benchmark]: Witness Printer took 105.17ms. Allocated memory is still 497.0MB. Free memory was 298.1MB in the beginning and 292.9MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-06 22:27:16,305 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.60ms. Allocated memory is still 136.3MB. Free memory is still 80.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 395.11ms. Allocated memory is still 136.3MB. Free memory was 102.9MB in the beginning and 88.4MB in the end (delta: 14.6MB). Peak memory consumption was 14.7MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 79.21ms. Allocated memory is still 136.3MB. Free memory was 88.4MB in the beginning and 84.6MB in the end (delta: 3.7MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 57.55ms. Allocated memory is still 136.3MB. Free memory was 84.6MB in the beginning and 81.3MB in the end (delta: 3.3MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 1195.17ms. Allocated memory was 136.3MB in the beginning and 167.8MB in the end (delta: 31.5MB). Free memory was 81.3MB in the beginning and 119.5MB in the end (delta: -38.1MB). Peak memory consumption was 31.1MB. Max. memory is 16.1GB. * BuchiAutomizer took 8172.67ms. Allocated memory was 167.8MB in the beginning and 497.0MB in the end (delta: 329.3MB). Free memory was 118.4MB in the beginning and 299.2MB in the end (delta: -180.7MB). Peak memory consumption was 148.5MB. Max. memory is 16.1GB. * Witness Printer took 105.17ms. Allocated memory is still 497.0MB. Free memory was 298.1MB in the beginning and 292.9MB in the end (delta: 5.2MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 13795 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 7.9s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.0s. Construction of modules took 0.5s. Büchi inclusion checks took 2.9s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 1.3s AutomataMinimizationTime, 17 MinimizatonAttempts, 5367 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 8849 SdHoareTripleChecker+Valid, 0.7s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 8849 mSDsluCounter, 15581 SdHoareTripleChecker+Invalid, 0.6s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 7207 mSDsCounter, 157 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 392 IncrementalHoareTripleChecker+Invalid, 549 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 157 mSolverCounterUnsat, 8374 mSDtfsCounter, 392 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc3 concLT0 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 352]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L362-L373] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L376-L387] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L390-L401] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L404-L415] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 352]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int t3_st ; [L32] int m_i ; [L33] int t1_i ; [L34] int t2_i ; [L35] int t3_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int E_M = 2; [L41] int E_1 = 2; [L42] int E_2 = 2; [L43] int E_3 = 2; [L49] int token ; [L51] int local ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, token=0] [L723] int __retres1 ; [L727] CALL init_model() [L636] m_i = 1 [L637] t1_i = 1 [L638] t2_i = 1 [L639] t3_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L727] RET init_model() [L728] CALL start_simulation() [L664] int kernel_st ; [L665] int tmp ; [L666] int tmp___0 ; [L670] kernel_st = 0 [L671] FCALL update_channels() [L672] CALL init_threads() [L292] COND TRUE m_i == 1 [L293] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L297] COND TRUE t1_i == 1 [L298] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L302] COND TRUE t2_i == 1 [L303] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L307] COND TRUE t3_i == 1 [L308] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L672] RET init_threads() [L673] CALL fire_delta_events() [L429] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L434] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L439] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L444] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L449] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L454] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L459] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L464] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L673] RET fire_delta_events() [L674] CALL activate_threads() [L522] int tmp ; [L523] int tmp___0 ; [L524] int tmp___1 ; [L525] int tmp___2 ; [L529] CALL, EXPR is_master_triggered() [L205] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L208] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L218] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L220] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L529] RET, EXPR is_master_triggered() [L529] tmp = is_master_triggered() [L531] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, token=0] [L537] CALL, EXPR is_transmit1_triggered() [L224] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L227] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L237] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L239] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L537] RET, EXPR is_transmit1_triggered() [L537] tmp___0 = is_transmit1_triggered() [L539] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, token=0] [L545] CALL, EXPR is_transmit2_triggered() [L243] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L246] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L256] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L258] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L545] RET, EXPR is_transmit2_triggered() [L545] tmp___1 = is_transmit2_triggered() [L547] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L553] CALL, EXPR is_transmit3_triggered() [L262] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L265] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L275] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L277] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L553] RET, EXPR is_transmit3_triggered() [L553] tmp___2 = is_transmit3_triggered() [L555] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L674] RET activate_threads() [L675] CALL reset_delta_events() [L477] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L482] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L487] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L492] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L497] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L502] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L507] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L512] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L675] RET reset_delta_events() [L678] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] [L681] kernel_st = 1 [L682] CALL eval() [L348] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, token=0] Loop: [L352] COND TRUE 1 [L355] CALL, EXPR exists_runnable_thread() [L317] int __retres1 ; [L320] COND TRUE m_st == 0 [L321] __retres1 = 1 [L343] return (__retres1); [L355] RET, EXPR exists_runnable_thread() [L355] tmp = exists_runnable_thread() [L357] COND TRUE \read(tmp) [L362] COND TRUE m_st == 0 [L363] int tmp_ndt_1; [L364] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L365] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L362-L373] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L376] COND TRUE t1_st == 0 [L377] int tmp_ndt_2; [L378] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L379] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L376-L387] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L390] COND TRUE t2_st == 0 [L391] int tmp_ndt_3; [L392] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L393] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L390-L401] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L404] COND TRUE t3_st == 0 [L405] int tmp_ndt_4; [L406] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L407] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L404-L415] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:27:16,400 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_e04da1b8-42f9-463b-8fbc-cc60055a705f/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)