./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:16:36,084 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:16:36,167 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:16:36,173 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:16:36,174 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:16:36,206 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:16:36,207 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:16:36,208 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:16:36,210 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:16:36,211 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:16:36,211 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:16:36,212 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:16:36,213 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:16:36,214 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:16:36,214 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:16:36,215 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:16:36,216 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:16:36,217 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:16:36,217 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:16:36,218 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:16:36,219 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:16:36,220 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:16:36,221 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:16:36,221 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:16:36,222 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:16:36,223 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:16:36,223 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:16:36,224 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:16:36,225 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:16:36,226 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:16:36,226 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:16:36,227 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:16:36,228 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:16:36,229 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:16:36,229 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:16:36,230 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:16:36,231 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 05d3b7d21cc48825b4a0189c75f03d768acc6241312029d3e223c1b9b2a509ea [2023-11-06 22:16:36,527 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:16:36,552 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:16:36,555 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:16:36,557 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:16:36,558 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:16:36,559 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2023-11-06 22:16:39,915 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:16:40,249 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:16:40,250 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/sv-benchmarks/c/systemc/token_ring.04.cil-2.c [2023-11-06 22:16:40,262 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/data/b82309cdc/87b7237e46b84040a890c3d0d894dfb2/FLAG98f69e048 [2023-11-06 22:16:40,279 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/data/b82309cdc/87b7237e46b84040a890c3d0d894dfb2 [2023-11-06 22:16:40,282 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:16:40,284 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:16:40,286 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:16:40,286 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:16:40,294 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:16:40,295 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,296 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@62327083 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40, skipping insertion in model container [2023-11-06 22:16:40,296 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,362 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:16:40,625 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:16:40,641 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:16:40,713 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:16:40,747 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:16:40,747 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40 WrapperNode [2023-11-06 22:16:40,747 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:16:40,749 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:16:40,749 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:16:40,749 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:16:40,758 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,783 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,855 INFO L138 Inliner]: procedures = 36, calls = 45, calls flagged for inlining = 40, calls inlined = 80, statements flattened = 1087 [2023-11-06 22:16:40,875 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:16:40,876 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:16:40,876 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:16:40,876 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:16:40,886 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,887 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,894 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,894 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,939 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,955 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,972 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,978 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:40,995 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:16:41,006 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:16:41,006 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:16:41,006 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:16:41,007 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (1/1) ... [2023-11-06 22:16:41,027 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:16:41,043 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:16:41,059 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:16:41,084 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:16:41,115 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:16:41,115 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:16:41,115 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:16:41,116 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:16:41,283 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:16:41,286 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:16:42,592 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:16:42,610 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:16:42,611 INFO L302 CfgBuilder]: Removed 7 assume(true) statements. [2023-11-06 22:16:42,615 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:16:42 BoogieIcfgContainer [2023-11-06 22:16:42,615 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:16:42,617 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:16:42,617 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:16:42,622 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:16:42,624 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:16:42,624 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:16:40" (1/3) ... [2023-11-06 22:16:42,625 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@73c94f78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:16:42, skipping insertion in model container [2023-11-06 22:16:42,625 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:16:42,626 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:16:40" (2/3) ... [2023-11-06 22:16:42,626 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@73c94f78 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:16:42, skipping insertion in model container [2023-11-06 22:16:42,626 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:16:42,627 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:16:42" (3/3) ... [2023-11-06 22:16:42,628 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.04.cil-2.c [2023-11-06 22:16:42,714 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:16:42,715 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:16:42,715 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:16:42,715 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:16:42,715 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:16:42,716 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:16:42,716 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:16:42,716 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:16:42,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:42,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2023-11-06 22:16:42,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:42,795 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:42,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:42,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:42,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:16:42,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:42,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 374 [2023-11-06 22:16:42,832 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:42,832 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:42,836 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:42,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:42,848 INFO L748 eck$LassoCheckResult]: Stem: 142#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 364#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 220#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 359#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49#L365true assume !(1 == ~m_i~0);~m_st~0 := 2; 334#L365-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 233#L370-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 187#L375-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 341#L380-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 213#L385-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 195#L526true assume !(0 == ~M_E~0); 421#L526-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 236#L531-1true assume !(0 == ~T2_E~0); 185#L536-1true assume !(0 == ~T3_E~0); 296#L541-1true assume !(0 == ~T4_E~0); 183#L546-1true assume !(0 == ~E_M~0); 248#L551-1true assume !(0 == ~E_1~0); 165#L556-1true assume !(0 == ~E_2~0); 192#L561-1true assume !(0 == ~E_3~0); 172#L566-1true assume 0 == ~E_4~0;~E_4~0 := 1; 376#L571-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168#L262true assume 1 == ~m_pc~0; 443#L263true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 380#L273true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 377#L649true assume !(0 != activate_threads_~tmp~1#1); 438#L649-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129#L281true assume !(1 == ~t1_pc~0); 394#L281-2true is_transmit1_triggered_~__retres1~1#1 := 0; 79#L292true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L657true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 361#L657-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 175#L300true assume 1 == ~t2_pc~0; 308#L301true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 274#L311true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 222#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190#L665true assume !(0 != activate_threads_~tmp___1~0#1); 38#L665-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 445#L319true assume !(1 == ~t3_pc~0); 17#L319-2true is_transmit3_triggered_~__retres1~3#1 := 0; 277#L330true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 141#L673true assume !(0 != activate_threads_~tmp___2~0#1); 27#L673-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 278#L338true assume 1 == ~t4_pc~0; 112#L339true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73#L349true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 66#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 384#L681true assume !(0 != activate_threads_~tmp___3~0#1); 2#L681-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 374#L584true assume !(1 == ~M_E~0); 113#L584-2true assume !(1 == ~T1_E~0); 88#L589-1true assume !(1 == ~T2_E~0); 262#L594-1true assume !(1 == ~T3_E~0); 144#L599-1true assume !(1 == ~T4_E~0); 16#L604-1true assume !(1 == ~E_M~0); 9#L609-1true assume 1 == ~E_1~0;~E_1~0 := 2; 72#L614-1true assume !(1 == ~E_2~0); 125#L619-1true assume !(1 == ~E_3~0); 188#L624-1true assume !(1 == ~E_4~0); 401#L629-1true assume { :end_inline_reset_delta_events } true; 207#L815-2true [2023-11-06 22:16:42,851 INFO L750 eck$LassoCheckResult]: Loop: 207#L815-2true assume !false; 388#L816true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 420#L501-1true assume false; 74#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 325#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 145#L526-3true assume 0 == ~M_E~0;~M_E~0 := 1; 268#L526-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 75#L531-3true assume !(0 == ~T2_E~0); 395#L536-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 13#L541-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 189#L546-3true assume 0 == ~E_M~0;~E_M~0 := 1; 439#L551-3true assume 0 == ~E_1~0;~E_1~0 := 1; 154#L556-3true assume 0 == ~E_2~0;~E_2~0 := 1; 243#L561-3true assume 0 == ~E_3~0;~E_3~0 := 1; 318#L566-3true assume 0 == ~E_4~0;~E_4~0 := 1; 81#L571-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 267#L262-18true assume !(1 == ~m_pc~0); 137#L262-20true is_master_triggered_~__retres1~0#1 := 0; 292#L273-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149#is_master_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 373#L649-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20#L649-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 163#L281-18true assume !(1 == ~t1_pc~0); 271#L281-20true is_transmit1_triggered_~__retres1~1#1 := 0; 178#L292-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 418#L657-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 293#L657-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 333#L300-18true assume !(1 == ~t2_pc~0); 14#L300-20true is_transmit2_triggered_~__retres1~2#1 := 0; 47#L311-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 217#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 255#L665-18true assume !(0 != activate_threads_~tmp___1~0#1); 319#L665-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80#L319-18true assume !(1 == ~t3_pc~0); 247#L319-20true is_transmit3_triggered_~__retres1~3#1 := 0; 96#L330-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 241#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 219#L673-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 204#L673-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128#L338-18true assume !(1 == ~t4_pc~0); 161#L338-20true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L349-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29#L681-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179#L681-20true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 140#L584-3true assume 1 == ~M_E~0;~M_E~0 := 2; 290#L584-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 28#L589-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 135#L594-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 216#L599-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 156#L604-3true assume 1 == ~E_M~0;~E_M~0 := 2; 406#L609-3true assume 1 == ~E_1~0;~E_1~0 := 2; 203#L614-3true assume !(1 == ~E_2~0); 24#L619-3true assume 1 == ~E_3~0;~E_3~0 := 2; 214#L624-3true assume 1 == ~E_4~0;~E_4~0 := 2; 249#L629-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 257#L398-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 68#L425-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 199#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 101#L834true assume !(0 == start_simulation_~tmp~3#1); 223#L834-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 355#L398-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 218#L425-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 295#L789true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 305#L796true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 336#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 205#L847true assume !(0 != start_simulation_~tmp___0~1#1); 207#L815-2true [2023-11-06 22:16:42,858 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:42,859 INFO L85 PathProgramCache]: Analyzing trace with hash 1553035642, now seen corresponding path program 1 times [2023-11-06 22:16:42,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:42,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302542434] [2023-11-06 22:16:42,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:42,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:43,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:43,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:43,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:43,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302542434] [2023-11-06 22:16:43,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302542434] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:43,204 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:43,204 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:43,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999476228] [2023-11-06 22:16:43,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:43,212 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:43,215 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:43,216 INFO L85 PathProgramCache]: Analyzing trace with hash 315649613, now seen corresponding path program 1 times [2023-11-06 22:16:43,216 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:43,216 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123779738] [2023-11-06 22:16:43,217 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:43,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:43,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:43,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:43,279 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:43,280 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123779738] [2023-11-06 22:16:43,280 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123779738] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:43,280 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:43,280 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:43,281 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718364982] [2023-11-06 22:16:43,281 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:43,283 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:43,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:43,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:43,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:43,328 INFO L87 Difference]: Start difference. First operand has 445 states, 444 states have (on average 1.527027027027027) internal successors, (678), 444 states have internal predecessors, (678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:43,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:43,401 INFO L93 Difference]: Finished difference Result 441 states and 657 transitions. [2023-11-06 22:16:43,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 657 transitions. [2023-11-06 22:16:43,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:43,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 435 states and 651 transitions. [2023-11-06 22:16:43,431 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-06 22:16:43,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-06 22:16:43,433 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 651 transitions. [2023-11-06 22:16:43,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:43,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-06 22:16:43,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 651 transitions. [2023-11-06 22:16:43,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-06 22:16:43,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4965517241379311) internal successors, (651), 434 states have internal predecessors, (651), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:43,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 651 transitions. [2023-11-06 22:16:43,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-06 22:16:43,508 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:43,512 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 651 transitions. [2023-11-06 22:16:43,512 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:16:43,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 651 transitions. [2023-11-06 22:16:43,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:43,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:43,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:43,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:43,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:43,522 INFO L748 eck$LassoCheckResult]: Stem: 1142#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 1143#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1235#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1236#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 992#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 993#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1244#L370-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1205#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1206#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1230#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1215#L526 assume !(0 == ~M_E~0); 1216#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1246#L531-1 assume !(0 == ~T2_E~0); 1201#L536-1 assume !(0 == ~T3_E~0); 1202#L541-1 assume !(0 == ~T4_E~0); 1197#L546-1 assume !(0 == ~E_M~0); 1198#L551-1 assume !(0 == ~E_1~0); 1173#L556-1 assume !(0 == ~E_2~0); 1174#L561-1 assume !(0 == ~E_3~0); 1184#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1185#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1178#L262 assume 1 == ~m_pc~0; 1179#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1324#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1112#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1113#L649 assume !(0 != activate_threads_~tmp~1#1); 1323#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1122#L281 assume !(1 == ~t1_pc~0); 1123#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1043#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 959#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 960#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1099#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1187#L300 assume 1 == ~t2_pc~0; 1188#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1277#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1238#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1209#L665 assume !(0 != activate_threads_~tmp___1~0#1); 972#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 973#L319 assume !(1 == ~t3_pc~0); 928#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 929#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916#L673 assume !(0 != activate_threads_~tmp___2~0#1); 949#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 950#L338 assume 1 == ~t4_pc~0; 1095#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1018#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024#L681 assume !(0 != activate_threads_~tmp___3~0#1); 895#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 896#L584 assume !(1 == ~M_E~0); 1096#L584-2 assume !(1 == ~T1_E~0); 1057#L589-1 assume !(1 == ~T2_E~0); 1058#L594-1 assume !(1 == ~T3_E~0); 1146#L599-1 assume !(1 == ~T4_E~0); 927#L604-1 assume !(1 == ~E_M~0); 913#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 914#L614-1 assume !(1 == ~E_2~0); 1032#L619-1 assume !(1 == ~E_3~0); 1114#L624-1 assume !(1 == ~E_4~0); 1207#L629-1 assume { :end_inline_reset_delta_events } true; 1226#L815-2 [2023-11-06 22:16:43,523 INFO L750 eck$LassoCheckResult]: Loop: 1226#L815-2 assume !false; 1227#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1104#L501-1 assume !false; 1320#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1321#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1038#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1251#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1252#L440 assume !(0 != eval_~tmp~0#1); 1033#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1034#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1147#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1148#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1035#L531-3 assume !(0 == ~T2_E~0); 1036#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 921#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 922#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1208#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1159#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1160#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1256#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1047#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1048#L262-18 assume 1 == ~m_pc~0; 1271#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1136#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1153#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1154#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 934#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 935#L281-18 assume 1 == ~t1_pc~0; 1170#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1190#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1322#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1293#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1294#L300-18 assume 1 == ~t2_pc~0; 1168#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 924#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 991#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1233#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 1262#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1044#L319-18 assume 1 == ~t3_pc~0; 1045#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1050#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1071#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1234#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1224#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1119#L338-18 assume !(1 == ~t4_pc~0); 1120#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1088#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1089#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 953#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 954#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1140#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1141#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 951#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 952#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1133#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1162#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1163#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1223#L614-3 assume !(1 == ~E_2~0); 943#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 944#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1231#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1260#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1026#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1027#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1078#L834 assume !(0 == start_simulation_~tmp~3#1); 1079#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 1239#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1200#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 957#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 958#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1295#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1300#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1225#L847 assume !(0 != start_simulation_~tmp___0~1#1); 1226#L815-2 [2023-11-06 22:16:43,524 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:43,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1119306556, now seen corresponding path program 1 times [2023-11-06 22:16:43,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:43,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800228593] [2023-11-06 22:16:43,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:43,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:43,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:43,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:43,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:43,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800228593] [2023-11-06 22:16:43,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800228593] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:43,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:43,687 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:43,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1430171969] [2023-11-06 22:16:43,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:43,688 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:43,688 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:43,689 INFO L85 PathProgramCache]: Analyzing trace with hash -1098449818, now seen corresponding path program 1 times [2023-11-06 22:16:43,689 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:43,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1431006553] [2023-11-06 22:16:43,689 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:43,690 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:43,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:43,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:43,858 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:43,858 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1431006553] [2023-11-06 22:16:43,858 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1431006553] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:43,858 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:43,859 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:43,859 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453147021] [2023-11-06 22:16:43,859 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:43,860 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:43,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:43,860 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:43,861 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:43,861 INFO L87 Difference]: Start difference. First operand 435 states and 651 transitions. cyclomatic complexity: 217 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:43,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:43,897 INFO L93 Difference]: Finished difference Result 435 states and 650 transitions. [2023-11-06 22:16:43,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 650 transitions. [2023-11-06 22:16:43,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:43,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 650 transitions. [2023-11-06 22:16:43,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-06 22:16:43,908 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-06 22:16:43,909 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 650 transitions. [2023-11-06 22:16:43,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:43,918 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-06 22:16:43,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 650 transitions. [2023-11-06 22:16:43,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-06 22:16:43,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4942528735632183) internal successors, (650), 434 states have internal predecessors, (650), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:43,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 650 transitions. [2023-11-06 22:16:43,946 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-06 22:16:43,953 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:43,956 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 650 transitions. [2023-11-06 22:16:43,957 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:16:43,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 650 transitions. [2023-11-06 22:16:43,965 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:43,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:43,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:43,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:43,984 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:43,984 INFO L748 eck$LassoCheckResult]: Stem: 2019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2112#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2113#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1869#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 1870#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2121#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2082#L375-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2083#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2107#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2092#L526 assume !(0 == ~M_E~0); 2093#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2123#L531-1 assume !(0 == ~T2_E~0); 2078#L536-1 assume !(0 == ~T3_E~0); 2079#L541-1 assume !(0 == ~T4_E~0); 2074#L546-1 assume !(0 == ~E_M~0); 2075#L551-1 assume !(0 == ~E_1~0); 2050#L556-1 assume !(0 == ~E_2~0); 2051#L561-1 assume !(0 == ~E_3~0); 2061#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2062#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2055#L262 assume 1 == ~m_pc~0; 2056#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2201#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1989#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1990#L649 assume !(0 != activate_threads_~tmp~1#1); 2200#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1999#L281 assume !(1 == ~t1_pc~0); 2000#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1920#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1836#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1837#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1976#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2064#L300 assume 1 == ~t2_pc~0; 2065#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2154#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2115#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2086#L665 assume !(0 != activate_threads_~tmp___1~0#1); 1849#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1850#L319 assume !(1 == ~t3_pc~0); 1805#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1806#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1793#L673 assume !(0 != activate_threads_~tmp___2~0#1); 1826#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1827#L338 assume 1 == ~t4_pc~0; 1972#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1895#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1900#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1901#L681 assume !(0 != activate_threads_~tmp___3~0#1); 1772#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1773#L584 assume !(1 == ~M_E~0); 1973#L584-2 assume !(1 == ~T1_E~0); 1934#L589-1 assume !(1 == ~T2_E~0); 1935#L594-1 assume !(1 == ~T3_E~0); 2023#L599-1 assume !(1 == ~T4_E~0); 1804#L604-1 assume !(1 == ~E_M~0); 1790#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1791#L614-1 assume !(1 == ~E_2~0); 1909#L619-1 assume !(1 == ~E_3~0); 1991#L624-1 assume !(1 == ~E_4~0); 2084#L629-1 assume { :end_inline_reset_delta_events } true; 2103#L815-2 [2023-11-06 22:16:43,985 INFO L750 eck$LassoCheckResult]: Loop: 2103#L815-2 assume !false; 2104#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1981#L501-1 assume !false; 2197#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2198#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1915#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2128#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 2129#L440 assume !(0 != eval_~tmp~0#1); 1910#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1911#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2024#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2025#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1912#L531-3 assume !(0 == ~T2_E~0); 1913#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1798#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1799#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2085#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2036#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2037#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2133#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1924#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1925#L262-18 assume 1 == ~m_pc~0; 2148#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2013#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2030#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2031#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1811#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1812#L281-18 assume !(1 == ~t1_pc~0); 2048#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 2067#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2068#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2199#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2170#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2171#L300-18 assume !(1 == ~t2_pc~0); 1800#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 1801#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1868#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2110#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 2139#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1921#L319-18 assume 1 == ~t3_pc~0; 1922#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1927#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2111#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2101#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1996#L338-18 assume !(1 == ~t4_pc~0); 1997#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1965#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1966#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1830#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1831#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2017#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2018#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1828#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2010#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2039#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2040#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2100#L614-3 assume !(1 == ~E_2~0); 1820#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1821#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2108#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2137#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 1903#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1904#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1955#L834 assume !(0 == start_simulation_~tmp~3#1); 1956#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2116#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2077#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 1834#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1835#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2172#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2177#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2102#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2103#L815-2 [2023-11-06 22:16:43,985 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:43,986 INFO L85 PathProgramCache]: Analyzing trace with hash 1078631806, now seen corresponding path program 1 times [2023-11-06 22:16:43,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:43,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454614257] [2023-11-06 22:16:43,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:43,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454614257] [2023-11-06 22:16:44,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454614257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775929801] [2023-11-06 22:16:44,094 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,094 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:44,095 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,095 INFO L85 PathProgramCache]: Analyzing trace with hash 817900584, now seen corresponding path program 1 times [2023-11-06 22:16:44,095 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,097 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184205514] [2023-11-06 22:16:44,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184205514] [2023-11-06 22:16:44,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184205514] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941684928] [2023-11-06 22:16:44,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,228 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:44,228 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:44,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:44,229 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:44,229 INFO L87 Difference]: Start difference. First operand 435 states and 650 transitions. cyclomatic complexity: 216 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:44,254 INFO L93 Difference]: Finished difference Result 435 states and 649 transitions. [2023-11-06 22:16:44,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 649 transitions. [2023-11-06 22:16:44,261 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 649 transitions. [2023-11-06 22:16:44,267 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-06 22:16:44,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-06 22:16:44,268 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 649 transitions. [2023-11-06 22:16:44,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:44,269 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-06 22:16:44,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 649 transitions. [2023-11-06 22:16:44,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-06 22:16:44,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4919540229885058) internal successors, (649), 434 states have internal predecessors, (649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 649 transitions. [2023-11-06 22:16:44,302 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-06 22:16:44,302 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:44,304 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 649 transitions. [2023-11-06 22:16:44,306 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:16:44,306 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 649 transitions. [2023-11-06 22:16:44,312 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:44,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:44,317 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,318 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,318 INFO L748 eck$LassoCheckResult]: Stem: 2896#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 2897#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2989#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2990#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2746#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 2747#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2998#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2959#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2960#L380-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2984#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2969#L526 assume !(0 == ~M_E~0); 2970#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3000#L531-1 assume !(0 == ~T2_E~0); 2955#L536-1 assume !(0 == ~T3_E~0); 2956#L541-1 assume !(0 == ~T4_E~0); 2951#L546-1 assume !(0 == ~E_M~0); 2952#L551-1 assume !(0 == ~E_1~0); 2927#L556-1 assume !(0 == ~E_2~0); 2928#L561-1 assume !(0 == ~E_3~0); 2938#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 2939#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2932#L262 assume 1 == ~m_pc~0; 2933#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3078#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2867#L649 assume !(0 != activate_threads_~tmp~1#1); 3077#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2876#L281 assume !(1 == ~t1_pc~0); 2877#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2797#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2714#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2853#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2941#L300 assume 1 == ~t2_pc~0; 2942#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3031#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2963#L665 assume !(0 != activate_threads_~tmp___1~0#1); 2726#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2727#L319 assume !(1 == ~t3_pc~0); 2682#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2683#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2669#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2670#L673 assume !(0 != activate_threads_~tmp___2~0#1); 2703#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2704#L338 assume 1 == ~t4_pc~0; 2849#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2772#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2778#L681 assume !(0 != activate_threads_~tmp___3~0#1); 2649#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2650#L584 assume !(1 == ~M_E~0); 2850#L584-2 assume !(1 == ~T1_E~0); 2811#L589-1 assume !(1 == ~T2_E~0); 2812#L594-1 assume !(1 == ~T3_E~0); 2900#L599-1 assume !(1 == ~T4_E~0); 2681#L604-1 assume !(1 == ~E_M~0); 2667#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2668#L614-1 assume !(1 == ~E_2~0); 2786#L619-1 assume !(1 == ~E_3~0); 2868#L624-1 assume !(1 == ~E_4~0); 2961#L629-1 assume { :end_inline_reset_delta_events } true; 2980#L815-2 [2023-11-06 22:16:44,323 INFO L750 eck$LassoCheckResult]: Loop: 2980#L815-2 assume !false; 2981#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2858#L501-1 assume !false; 3074#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3075#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2792#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3005#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3006#L440 assume !(0 != eval_~tmp~0#1); 2787#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2901#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2902#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2789#L531-3 assume !(0 == ~T2_E~0); 2790#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2675#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2676#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2962#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2913#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2914#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3010#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2801#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2802#L262-18 assume 1 == ~m_pc~0; 3025#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 2890#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2907#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2908#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2689#L281-18 assume 1 == ~t1_pc~0; 2924#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2944#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2945#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3076#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3047#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3048#L300-18 assume !(1 == ~t2_pc~0); 2677#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 2678#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2745#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2987#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3016#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2798#L319-18 assume !(1 == ~t3_pc~0); 2800#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 2804#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2825#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2988#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2978#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2873#L338-18 assume !(1 == ~t4_pc~0); 2874#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 2842#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2843#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2707#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2708#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2894#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2895#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2705#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2706#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2887#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2916#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2917#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2977#L614-3 assume !(1 == ~E_2~0); 2697#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2698#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2985#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3014#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2780#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2781#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2832#L834 assume !(0 == start_simulation_~tmp~3#1); 2833#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 2993#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 2954#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 2711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2712#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3049#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3054#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2979#L847 assume !(0 != start_simulation_~tmp___0~1#1); 2980#L815-2 [2023-11-06 22:16:44,324 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,324 INFO L85 PathProgramCache]: Analyzing trace with hash -308153604, now seen corresponding path program 1 times [2023-11-06 22:16:44,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1880611125] [2023-11-06 22:16:44,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1880611125] [2023-11-06 22:16:44,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1880611125] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342239398] [2023-11-06 22:16:44,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,419 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:44,419 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,419 INFO L85 PathProgramCache]: Analyzing trace with hash -532175448, now seen corresponding path program 1 times [2023-11-06 22:16:44,420 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,420 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1002575359] [2023-11-06 22:16:44,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,519 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,520 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1002575359] [2023-11-06 22:16:44,520 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1002575359] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,520 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,520 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,521 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1501074338] [2023-11-06 22:16:44,521 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,521 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:44,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:44,522 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:44,522 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:44,522 INFO L87 Difference]: Start difference. First operand 435 states and 649 transitions. cyclomatic complexity: 215 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:44,545 INFO L93 Difference]: Finished difference Result 435 states and 648 transitions. [2023-11-06 22:16:44,545 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 648 transitions. [2023-11-06 22:16:44,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,556 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 648 transitions. [2023-11-06 22:16:44,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-06 22:16:44,558 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-06 22:16:44,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 648 transitions. [2023-11-06 22:16:44,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:44,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-06 22:16:44,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 648 transitions. [2023-11-06 22:16:44,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-06 22:16:44,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4896551724137932) internal successors, (648), 434 states have internal predecessors, (648), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 648 transitions. [2023-11-06 22:16:44,573 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-06 22:16:44,573 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:44,576 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 648 transitions. [2023-11-06 22:16:44,576 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:16:44,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 648 transitions. [2023-11-06 22:16:44,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:44,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:44,587 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,587 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,588 INFO L748 eck$LassoCheckResult]: Stem: 3773#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 3774#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3623#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 3624#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3875#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3836#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3837#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3861#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3846#L526 assume !(0 == ~M_E~0); 3847#L526-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3877#L531-1 assume !(0 == ~T2_E~0); 3832#L536-1 assume !(0 == ~T3_E~0); 3833#L541-1 assume !(0 == ~T4_E~0); 3828#L546-1 assume !(0 == ~E_M~0); 3829#L551-1 assume !(0 == ~E_1~0); 3804#L556-1 assume !(0 == ~E_2~0); 3805#L561-1 assume !(0 == ~E_3~0); 3815#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3816#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3809#L262 assume 1 == ~m_pc~0; 3810#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3955#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3743#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3744#L649 assume !(0 != activate_threads_~tmp~1#1); 3954#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3753#L281 assume !(1 == ~t1_pc~0); 3754#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3674#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3590#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3591#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3730#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3818#L300 assume 1 == ~t2_pc~0; 3819#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3908#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3869#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3840#L665 assume !(0 != activate_threads_~tmp___1~0#1); 3603#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3604#L319 assume !(1 == ~t3_pc~0); 3559#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3560#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3546#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3547#L673 assume !(0 != activate_threads_~tmp___2~0#1); 3580#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3581#L338 assume 1 == ~t4_pc~0; 3726#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3649#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3654#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3655#L681 assume !(0 != activate_threads_~tmp___3~0#1); 3526#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3527#L584 assume !(1 == ~M_E~0); 3727#L584-2 assume !(1 == ~T1_E~0); 3688#L589-1 assume !(1 == ~T2_E~0); 3689#L594-1 assume !(1 == ~T3_E~0); 3777#L599-1 assume !(1 == ~T4_E~0); 3558#L604-1 assume !(1 == ~E_M~0); 3544#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3545#L614-1 assume !(1 == ~E_2~0); 3663#L619-1 assume !(1 == ~E_3~0); 3745#L624-1 assume !(1 == ~E_4~0); 3838#L629-1 assume { :end_inline_reset_delta_events } true; 3857#L815-2 [2023-11-06 22:16:44,588 INFO L750 eck$LassoCheckResult]: Loop: 3857#L815-2 assume !false; 3858#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3735#L501-1 assume !false; 3951#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3952#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3669#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3882#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3883#L440 assume !(0 != eval_~tmp~0#1); 3664#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3665#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3778#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3779#L526-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3666#L531-3 assume !(0 == ~T2_E~0); 3667#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3552#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3553#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3839#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3790#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3791#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3887#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3678#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3679#L262-18 assume !(1 == ~m_pc~0); 3766#L262-20 is_master_triggered_~__retres1~0#1 := 0; 3767#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3784#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3785#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3565#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3566#L281-18 assume 1 == ~t1_pc~0; 3801#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3821#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3822#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3953#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3924#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3925#L300-18 assume !(1 == ~t2_pc~0); 3554#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 3555#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3622#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3864#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 3893#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3675#L319-18 assume 1 == ~t3_pc~0; 3676#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3681#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3702#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3865#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3855#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3750#L338-18 assume !(1 == ~t4_pc~0); 3751#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 3719#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3720#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3584#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3585#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3771#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3772#L584-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3582#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3583#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3764#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3793#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3794#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3854#L614-3 assume !(1 == ~E_2~0); 3574#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3575#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3862#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3891#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3657#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3658#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3709#L834 assume !(0 == start_simulation_~tmp~3#1); 3710#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 3870#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 3831#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 3588#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3589#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3926#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3931#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3856#L847 assume !(0 != start_simulation_~tmp___0~1#1); 3857#L815-2 [2023-11-06 22:16:44,589 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,592 INFO L85 PathProgramCache]: Analyzing trace with hash -1184172610, now seen corresponding path program 1 times [2023-11-06 22:16:44,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746948376] [2023-11-06 22:16:44,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746948376] [2023-11-06 22:16:44,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746948376] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:44,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1232953084] [2023-11-06 22:16:44,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,676 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:44,678 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,678 INFO L85 PathProgramCache]: Analyzing trace with hash -1857403032, now seen corresponding path program 1 times [2023-11-06 22:16:44,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1409414810] [2023-11-06 22:16:44,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,748 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1409414810] [2023-11-06 22:16:44,749 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1409414810] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,749 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,749 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,749 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992233757] [2023-11-06 22:16:44,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,750 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:44,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:44,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:44,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:44,751 INFO L87 Difference]: Start difference. First operand 435 states and 648 transitions. cyclomatic complexity: 214 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:44,777 INFO L93 Difference]: Finished difference Result 435 states and 643 transitions. [2023-11-06 22:16:44,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 643 transitions. [2023-11-06 22:16:44,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 643 transitions. [2023-11-06 22:16:44,787 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2023-11-06 22:16:44,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2023-11-06 22:16:44,788 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 643 transitions. [2023-11-06 22:16:44,788 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:44,789 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-06 22:16:44,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 643 transitions. [2023-11-06 22:16:44,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2023-11-06 22:16:44,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 435 states have (on average 1.4781609195402299) internal successors, (643), 434 states have internal predecessors, (643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:44,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 643 transitions. [2023-11-06 22:16:44,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-06 22:16:44,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:44,805 INFO L428 stractBuchiCegarLoop]: Abstraction has 435 states and 643 transitions. [2023-11-06 22:16:44,805 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:16:44,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 643 transitions. [2023-11-06 22:16:44,823 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 368 [2023-11-06 22:16:44,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:44,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:44,831 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,831 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:44,838 INFO L748 eck$LassoCheckResult]: Stem: 4650#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 4651#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4500#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 4501#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4753#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4713#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4714#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4739#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4723#L526 assume !(0 == ~M_E~0); 4724#L526-2 assume !(0 == ~T1_E~0); 4755#L531-1 assume !(0 == ~T2_E~0); 4709#L536-1 assume !(0 == ~T3_E~0); 4710#L541-1 assume !(0 == ~T4_E~0); 4705#L546-1 assume !(0 == ~E_M~0); 4706#L551-1 assume !(0 == ~E_1~0); 4681#L556-1 assume !(0 == ~E_2~0); 4682#L561-1 assume !(0 == ~E_3~0); 4692#L566-1 assume 0 == ~E_4~0;~E_4~0 := 1; 4693#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4686#L262 assume 1 == ~m_pc~0; 4687#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4832#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4620#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4621#L649 assume !(0 != activate_threads_~tmp~1#1); 4831#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4630#L281 assume !(1 == ~t1_pc~0); 4631#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4551#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4467#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4468#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4607#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4695#L300 assume 1 == ~t2_pc~0; 4696#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4785#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4746#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4717#L665 assume !(0 != activate_threads_~tmp___1~0#1); 4480#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4481#L319 assume !(1 == ~t3_pc~0); 4436#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4437#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4423#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4424#L673 assume !(0 != activate_threads_~tmp___2~0#1); 4457#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4458#L338 assume 1 == ~t4_pc~0; 4603#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4526#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4532#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4533#L681 assume !(0 != activate_threads_~tmp___3~0#1); 4403#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4404#L584 assume !(1 == ~M_E~0); 4604#L584-2 assume !(1 == ~T1_E~0); 4565#L589-1 assume !(1 == ~T2_E~0); 4566#L594-1 assume !(1 == ~T3_E~0); 4654#L599-1 assume !(1 == ~T4_E~0); 4435#L604-1 assume !(1 == ~E_M~0); 4421#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4422#L614-1 assume !(1 == ~E_2~0); 4540#L619-1 assume !(1 == ~E_3~0); 4622#L624-1 assume !(1 == ~E_4~0); 4715#L629-1 assume { :end_inline_reset_delta_events } true; 4734#L815-2 [2023-11-06 22:16:44,839 INFO L750 eck$LassoCheckResult]: Loop: 4734#L815-2 assume !false; 4735#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4612#L501-1 assume !false; 4828#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4829#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4546#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4759#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4760#L440 assume !(0 != eval_~tmp~0#1); 4541#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4542#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4655#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4656#L526-5 assume !(0 == ~T1_E~0); 4543#L531-3 assume !(0 == ~T2_E~0); 4544#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4431#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4432#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4716#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4667#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4668#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4763#L566-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4555#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4556#L262-18 assume !(1 == ~m_pc~0); 4642#L262-20 is_master_triggered_~__retres1~0#1 := 0; 4643#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4661#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4662#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4442#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4443#L281-18 assume 1 == ~t1_pc~0; 4678#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4698#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4699#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4830#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4801#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4802#L300-18 assume 1 == ~t2_pc~0; 4676#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4430#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4499#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4741#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 4770#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4552#L319-18 assume 1 == ~t3_pc~0; 4553#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4558#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4579#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4742#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4732#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4627#L338-18 assume !(1 == ~t4_pc~0); 4628#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 4596#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4597#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4461#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4462#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4648#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4649#L584-5 assume !(1 == ~T1_E~0); 4459#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4460#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4641#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4670#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4671#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4731#L614-3 assume !(1 == ~E_2~0); 4451#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4452#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4738#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4768#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4534#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4535#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4586#L834 assume !(0 == start_simulation_~tmp~3#1); 4587#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 4747#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 4708#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 4465#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4466#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4803#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4808#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4733#L847 assume !(0 != start_simulation_~tmp___0~1#1); 4734#L815-2 [2023-11-06 22:16:44,840 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1082208576, now seen corresponding path program 1 times [2023-11-06 22:16:44,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157087638] [2023-11-06 22:16:44,842 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:44,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:44,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:44,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157087638] [2023-11-06 22:16:44,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157087638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:44,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:44,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:44,941 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922560700] [2023-11-06 22:16:44,941 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:44,941 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:44,942 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:44,942 INFO L85 PathProgramCache]: Analyzing trace with hash -1570770201, now seen corresponding path program 1 times [2023-11-06 22:16:44,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:44,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [89043348] [2023-11-06 22:16:44,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:44,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:44,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:45,005 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:45,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:45,007 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [89043348] [2023-11-06 22:16:45,007 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [89043348] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:45,007 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:45,008 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:45,008 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [89958956] [2023-11-06 22:16:45,008 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:45,009 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:45,009 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:45,010 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:16:45,010 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:16:45,010 INFO L87 Difference]: Start difference. First operand 435 states and 643 transitions. cyclomatic complexity: 209 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:45,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:45,194 INFO L93 Difference]: Finished difference Result 730 states and 1076 transitions. [2023-11-06 22:16:45,194 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 1076 transitions. [2023-11-06 22:16:45,202 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2023-11-06 22:16:45,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 730 states and 1076 transitions. [2023-11-06 22:16:45,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 730 [2023-11-06 22:16:45,211 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 730 [2023-11-06 22:16:45,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 730 states and 1076 transitions. [2023-11-06 22:16:45,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:45,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 730 states and 1076 transitions. [2023-11-06 22:16:45,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 730 states and 1076 transitions. [2023-11-06 22:16:45,233 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 730 to 729. [2023-11-06 22:16:45,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.4746227709190671) internal successors, (1075), 728 states have internal predecessors, (1075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:45,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1075 transitions. [2023-11-06 22:16:45,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1075 transitions. [2023-11-06 22:16:45,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:16:45,243 INFO L428 stractBuchiCegarLoop]: Abstraction has 729 states and 1075 transitions. [2023-11-06 22:16:45,243 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:16:45,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 729 states and 1075 transitions. [2023-11-06 22:16:45,249 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 652 [2023-11-06 22:16:45,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:45,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:45,254 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:45,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:45,255 INFO L748 eck$LassoCheckResult]: Stem: 5825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 5826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5920#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5921#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5675#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 5676#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5930#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5888#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5889#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5915#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5899#L526 assume !(0 == ~M_E~0); 5900#L526-2 assume !(0 == ~T1_E~0); 5932#L531-1 assume !(0 == ~T2_E~0); 5884#L536-1 assume !(0 == ~T3_E~0); 5885#L541-1 assume !(0 == ~T4_E~0); 5880#L546-1 assume !(0 == ~E_M~0); 5881#L551-1 assume !(0 == ~E_1~0); 5856#L556-1 assume !(0 == ~E_2~0); 5857#L561-1 assume !(0 == ~E_3~0); 5867#L566-1 assume !(0 == ~E_4~0); 5868#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5861#L262 assume 1 == ~m_pc~0; 5862#L263 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6011#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5795#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5796#L649 assume !(0 != activate_threads_~tmp~1#1); 6010#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5805#L281 assume !(1 == ~t1_pc~0); 5806#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5726#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5643#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5782#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5870#L300 assume 1 == ~t2_pc~0; 5871#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5963#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5892#L665 assume !(0 != activate_threads_~tmp___1~0#1); 5655#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5656#L319 assume !(1 == ~t3_pc~0); 5611#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5612#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5599#L673 assume !(0 != activate_threads_~tmp___2~0#1); 5632#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5633#L338 assume 1 == ~t4_pc~0; 5778#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5701#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5707#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5708#L681 assume !(0 != activate_threads_~tmp___3~0#1); 5578#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5579#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 6009#L584-2 assume !(1 == ~T1_E~0); 6279#L589-1 assume !(1 == ~T2_E~0); 6278#L594-1 assume !(1 == ~T3_E~0); 5829#L599-1 assume !(1 == ~T4_E~0); 5610#L604-1 assume !(1 == ~E_M~0); 5596#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5597#L614-1 assume !(1 == ~E_2~0); 5715#L619-1 assume !(1 == ~E_3~0); 5797#L624-1 assume !(1 == ~E_4~0); 5890#L629-1 assume { :end_inline_reset_delta_events } true; 5910#L815-2 [2023-11-06 22:16:45,256 INFO L750 eck$LassoCheckResult]: Loop: 5910#L815-2 assume !false; 5911#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5787#L501-1 assume !false; 6006#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 6007#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5721#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5936#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 5937#L440 assume !(0 != eval_~tmp~0#1); 6015#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6021#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6019#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6020#L526-5 assume !(0 == ~T1_E~0); 6306#L531-3 assume !(0 == ~T2_E~0); 6305#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6304#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6303#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6302#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6301#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6300#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6299#L566-3 assume !(0 == ~E_4~0); 6298#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6297#L262-18 assume 1 == ~m_pc~0; 6295#L263-6 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6294#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6293#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6292#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6291#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6290#L281-18 assume !(1 == ~t1_pc~0); 6288#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6287#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6286#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6285#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6284#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6283#L300-18 assume 1 == ~t2_pc~0; 6281#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6280#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5917#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5918#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 5947#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5727#L319-18 assume 1 == ~t3_pc~0; 5728#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5733#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5754#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5919#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5908#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5802#L338-18 assume !(1 == ~t4_pc~0); 5803#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 5771#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5772#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5636#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5637#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5821#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5822#L584-5 assume !(1 == ~T1_E~0); 5634#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5816#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5844#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5845#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5907#L614-3 assume !(1 == ~E_2~0); 5626#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5627#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5914#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5945#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5709#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5710#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5761#L834 assume !(0 == start_simulation_~tmp~3#1); 5762#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 5924#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 5883#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5641#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5981#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5986#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5909#L847 assume !(0 != start_simulation_~tmp___0~1#1); 5910#L815-2 [2023-11-06 22:16:45,256 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:45,256 INFO L85 PathProgramCache]: Analyzing trace with hash -516249280, now seen corresponding path program 1 times [2023-11-06 22:16:45,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:45,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603365335] [2023-11-06 22:16:45,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:45,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:45,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:45,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:45,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:45,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [603365335] [2023-11-06 22:16:45,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [603365335] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:45,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:45,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:45,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431672193] [2023-11-06 22:16:45,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:45,323 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:45,323 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:45,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1803648471, now seen corresponding path program 1 times [2023-11-06 22:16:45,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:45,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1514079613] [2023-11-06 22:16:45,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:45,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:45,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:45,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:45,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:45,372 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1514079613] [2023-11-06 22:16:45,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1514079613] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:45,372 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:45,372 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:45,372 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927970319] [2023-11-06 22:16:45,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:45,373 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:45,373 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:45,374 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:45,374 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:45,374 INFO L87 Difference]: Start difference. First operand 729 states and 1075 transitions. cyclomatic complexity: 348 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:45,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:45,452 INFO L93 Difference]: Finished difference Result 1352 states and 1966 transitions. [2023-11-06 22:16:45,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1352 states and 1966 transitions. [2023-11-06 22:16:45,465 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1274 [2023-11-06 22:16:45,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1352 states to 1352 states and 1966 transitions. [2023-11-06 22:16:45,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1352 [2023-11-06 22:16:45,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1352 [2023-11-06 22:16:45,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1352 states and 1966 transitions. [2023-11-06 22:16:45,484 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:45,484 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1352 states and 1966 transitions. [2023-11-06 22:16:45,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1352 states and 1966 transitions. [2023-11-06 22:16:45,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1352 to 1284. [2023-11-06 22:16:45,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1284 states, 1284 states have (on average 1.4579439252336448) internal successors, (1872), 1283 states have internal predecessors, (1872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:45,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1284 states to 1284 states and 1872 transitions. [2023-11-06 22:16:45,527 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1284 states and 1872 transitions. [2023-11-06 22:16:45,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:45,530 INFO L428 stractBuchiCegarLoop]: Abstraction has 1284 states and 1872 transitions. [2023-11-06 22:16:45,531 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:16:45,531 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1284 states and 1872 transitions. [2023-11-06 22:16:45,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1206 [2023-11-06 22:16:45,541 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:45,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:45,542 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:45,542 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:45,543 INFO L748 eck$LassoCheckResult]: Stem: 7922#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 7923#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 8022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7765#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 7766#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8038#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7989#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7990#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8017#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8000#L526 assume !(0 == ~M_E~0); 8001#L526-2 assume !(0 == ~T1_E~0); 8040#L531-1 assume !(0 == ~T2_E~0); 7985#L536-1 assume !(0 == ~T3_E~0); 7986#L541-1 assume !(0 == ~T4_E~0); 7981#L546-1 assume !(0 == ~E_M~0); 7982#L551-1 assume !(0 == ~E_1~0); 7957#L556-1 assume !(0 == ~E_2~0); 7958#L561-1 assume !(0 == ~E_3~0); 7967#L566-1 assume !(0 == ~E_4~0); 7968#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7962#L262 assume !(1 == ~m_pc~0); 7963#L262-2 is_master_triggered_~__retres1~0#1 := 0; 8160#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7891#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7892#L649 assume !(0 != activate_threads_~tmp~1#1); 8157#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7902#L281 assume !(1 == ~t1_pc~0); 7903#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7818#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7732#L657 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7878#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7970#L300 assume 1 == ~t2_pc~0; 7971#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8079#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8026#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7993#L665 assume !(0 != activate_threads_~tmp___1~0#1); 7744#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7745#L319 assume !(1 == ~t3_pc~0); 7699#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7700#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7686#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7687#L673 assume !(0 != activate_threads_~tmp___2~0#1); 7721#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7722#L338 assume 1 == ~t4_pc~0; 7874#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7792#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7797#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7798#L681 assume !(0 != activate_threads_~tmp___3~0#1); 7666#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7667#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 7875#L584-2 assume !(1 == ~T1_E~0); 7834#L589-1 assume !(1 == ~T2_E~0); 7835#L594-1 assume !(1 == ~T3_E~0); 7926#L599-1 assume !(1 == ~T4_E~0); 7698#L604-1 assume !(1 == ~E_M~0); 7684#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7685#L614-1 assume !(1 == ~E_2~0); 7806#L619-1 assume !(1 == ~E_3~0); 7893#L624-1 assume !(1 == ~E_4~0); 7991#L629-1 assume { :end_inline_reset_delta_events } true; 8012#L815-2 [2023-11-06 22:16:45,543 INFO L750 eck$LassoCheckResult]: Loop: 8012#L815-2 assume !false; 8014#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7883#L501-1 assume !false; 8178#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8187#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7812#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 8420#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8418#L440 assume !(0 != eval_~tmp~0#1); 8417#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8415#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8412#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8413#L526-5 assume !(0 == ~T1_E~0); 8911#L531-3 assume !(0 == ~T2_E~0); 8910#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8909#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8908#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8907#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8906#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8905#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8904#L566-3 assume !(0 == ~E_4~0); 8903#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8902#L262-18 assume !(1 == ~m_pc~0); 8901#L262-20 is_master_triggered_~__retres1~0#1 := 0; 8900#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8899#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 8898#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8896#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8893#L281-18 assume !(1 == ~t1_pc~0); 8888#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 8886#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8884#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8881#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8879#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8877#L300-18 assume 1 == ~t2_pc~0; 8869#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7763#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7764#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8020#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 8058#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7819#L319-18 assume 1 == ~t3_pc~0; 7820#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7826#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7849#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8021#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8010#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7899#L338-18 assume !(1 == ~t4_pc~0); 7900#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 7866#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7867#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7725#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7726#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7920#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7921#L584-5 assume !(1 == ~T1_E~0); 7723#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7724#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7913#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7945#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7946#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8009#L614-3 assume !(1 == ~E_2~0); 7714#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7715#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8018#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8054#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7800#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7801#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 7856#L834 assume !(0 == start_simulation_~tmp~3#1); 7857#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 8027#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 7984#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 7729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 7730#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8102#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8107#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 8011#L847 assume !(0 != start_simulation_~tmp___0~1#1); 8012#L815-2 [2023-11-06 22:16:45,544 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:45,544 INFO L85 PathProgramCache]: Analyzing trace with hash -1001423999, now seen corresponding path program 1 times [2023-11-06 22:16:45,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:45,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037156610] [2023-11-06 22:16:45,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:45,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:45,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:45,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:45,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:45,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037156610] [2023-11-06 22:16:45,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037156610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:45,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:45,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:16:45,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106460456] [2023-11-06 22:16:45,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:45,639 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:45,640 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:45,640 INFO L85 PathProgramCache]: Analyzing trace with hash -2077426966, now seen corresponding path program 1 times [2023-11-06 22:16:45,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:45,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909214522] [2023-11-06 22:16:45,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:45,644 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:45,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:45,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:45,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:45,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909214522] [2023-11-06 22:16:45,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909214522] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:45,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:45,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:45,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [309556125] [2023-11-06 22:16:45,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:45,714 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:45,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:45,714 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:16:45,714 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:16:45,715 INFO L87 Difference]: Start difference. First operand 1284 states and 1872 transitions. cyclomatic complexity: 592 Second operand has 5 states, 5 states have (on average 12.4) internal successors, (62), 5 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:45,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:45,972 INFO L93 Difference]: Finished difference Result 2978 states and 4283 transitions. [2023-11-06 22:16:45,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2978 states and 4283 transitions. [2023-11-06 22:16:46,003 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2830 [2023-11-06 22:16:46,033 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2978 states to 2978 states and 4283 transitions. [2023-11-06 22:16:46,033 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2978 [2023-11-06 22:16:46,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2978 [2023-11-06 22:16:46,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2978 states and 4283 transitions. [2023-11-06 22:16:46,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:46,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2978 states and 4283 transitions. [2023-11-06 22:16:46,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2978 states and 4283 transitions. [2023-11-06 22:16:46,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2978 to 1353. [2023-11-06 22:16:46,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1353 states, 1353 states have (on average 1.434589800443459) internal successors, (1941), 1352 states have internal predecessors, (1941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:46,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1353 states to 1353 states and 1941 transitions. [2023-11-06 22:16:46,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1353 states and 1941 transitions. [2023-11-06 22:16:46,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:16:46,100 INFO L428 stractBuchiCegarLoop]: Abstraction has 1353 states and 1941 transitions. [2023-11-06 22:16:46,100 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:16:46,101 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1353 states and 1941 transitions. [2023-11-06 22:16:46,111 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1272 [2023-11-06 22:16:46,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:46,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:46,113 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:46,113 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:46,113 INFO L748 eck$LassoCheckResult]: Stem: 12204#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 12205#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 12319#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12320#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12041#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 12042#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12330#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12274#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12275#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12310#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12286#L526 assume !(0 == ~M_E~0); 12287#L526-2 assume !(0 == ~T1_E~0); 12332#L531-1 assume !(0 == ~T2_E~0); 12270#L536-1 assume !(0 == ~T3_E~0); 12271#L541-1 assume !(0 == ~T4_E~0); 12266#L546-1 assume !(0 == ~E_M~0); 12267#L551-1 assume !(0 == ~E_1~0); 12241#L556-1 assume !(0 == ~E_2~0); 12242#L561-1 assume !(0 == ~E_3~0); 12252#L566-1 assume !(0 == ~E_4~0); 12253#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12246#L262 assume !(1 == ~m_pc~0); 12247#L262-2 is_master_triggered_~__retres1~0#1 := 0; 12469#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12172#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12173#L649 assume !(0 != activate_threads_~tmp~1#1); 12466#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12183#L281 assume !(1 == ~t1_pc~0); 12184#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12094#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12095#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12155#L657 assume !(0 != activate_threads_~tmp___0~0#1); 12156#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12256#L300 assume 1 == ~t2_pc~0; 12257#L301 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12379#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12322#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12279#L665 assume !(0 != activate_threads_~tmp___1~0#1); 12019#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12020#L319 assume !(1 == ~t3_pc~0); 11974#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11975#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11962#L673 assume !(0 != activate_threads_~tmp___2~0#1); 11996#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11997#L338 assume 1 == ~t4_pc~0; 12151#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12067#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12072#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12073#L681 assume !(0 != activate_threads_~tmp___3~0#1); 11941#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11942#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 12465#L584-2 assume !(1 == ~T1_E~0); 12779#L589-1 assume !(1 == ~T2_E~0); 12778#L594-1 assume !(1 == ~T3_E~0); 12777#L599-1 assume !(1 == ~T4_E~0); 12776#L604-1 assume !(1 == ~E_M~0); 12775#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12774#L614-1 assume !(1 == ~E_2~0); 12174#L619-1 assume !(1 == ~E_3~0); 12175#L624-1 assume !(1 == ~E_4~0); 12276#L629-1 assume { :end_inline_reset_delta_events } true; 12304#L815-2 [2023-11-06 22:16:46,114 INFO L750 eck$LassoCheckResult]: Loop: 12304#L815-2 assume !false; 12305#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12506#L501-1 assume !false; 12507#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12518#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12088#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12338#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 12339#L440 assume !(0 != eval_~tmp~0#1); 12501#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12729#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12730#L526-5 assume !(0 == ~T1_E~0); 12727#L531-3 assume !(0 == ~T2_E~0); 12728#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12723#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12724#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13007#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13006#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12343#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12344#L566-3 assume !(0 == ~E_4~0); 12099#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12100#L262-18 assume !(1 == ~m_pc~0); 13005#L262-20 is_master_triggered_~__retres1~0#1 := 0; 13004#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13003#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13002#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13001#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13000#L281-18 assume 1 == ~t1_pc~0; 12998#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12996#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12994#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12992#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12991#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12990#L300-18 assume 1 == ~t2_pc~0; 12912#L301-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12910#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12907#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12905#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 12903#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12901#L319-18 assume 1 == ~t3_pc~0; 12898#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12896#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12895#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12892#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12890#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12888#L338-18 assume !(1 == ~t4_pc~0); 12885#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 12883#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12881#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12880#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12708#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12709#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12704#L584-5 assume !(1 == ~T1_E~0); 12705#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12700#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12701#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12227#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12228#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12298#L614-3 assume !(1 == ~E_2~0); 11989#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11990#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12311#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12860#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12076#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12077#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 12133#L834 assume !(0 == start_simulation_~tmp~3#1); 12134#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 12452#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 12269#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 12004#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 12005#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12411#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12412#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 12436#L847 assume !(0 != start_simulation_~tmp___0~1#1); 12304#L815-2 [2023-11-06 22:16:46,114 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:46,115 INFO L85 PathProgramCache]: Analyzing trace with hash -299824125, now seen corresponding path program 1 times [2023-11-06 22:16:46,115 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:46,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050402963] [2023-11-06 22:16:46,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:46,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:46,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:46,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:46,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:46,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050402963] [2023-11-06 22:16:46,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050402963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:46,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:46,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:46,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [607608901] [2023-11-06 22:16:46,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:46,181 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:46,181 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:46,182 INFO L85 PathProgramCache]: Analyzing trace with hash -183984791, now seen corresponding path program 1 times [2023-11-06 22:16:46,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:46,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284627484] [2023-11-06 22:16:46,182 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:46,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:46,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:46,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:46,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:46,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284627484] [2023-11-06 22:16:46,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284627484] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:46,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:46,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:46,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278239687] [2023-11-06 22:16:46,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:46,243 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:46,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:46,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:16:46,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:16:46,244 INFO L87 Difference]: Start difference. First operand 1353 states and 1941 transitions. cyclomatic complexity: 592 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:46,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:46,425 INFO L93 Difference]: Finished difference Result 3096 states and 4386 transitions. [2023-11-06 22:16:46,425 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3096 states and 4386 transitions. [2023-11-06 22:16:46,455 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2926 [2023-11-06 22:16:46,486 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3096 states to 3096 states and 4386 transitions. [2023-11-06 22:16:46,486 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3096 [2023-11-06 22:16:46,491 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3096 [2023-11-06 22:16:46,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3096 states and 4386 transitions. [2023-11-06 22:16:46,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:46,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3096 states and 4386 transitions. [2023-11-06 22:16:46,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3096 states and 4386 transitions. [2023-11-06 22:16:46,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3096 to 2438. [2023-11-06 22:16:46,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2438 states, 2438 states have (on average 1.4265791632485645) internal successors, (3478), 2437 states have internal predecessors, (3478), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:46,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2438 states to 2438 states and 3478 transitions. [2023-11-06 22:16:46,621 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2438 states and 3478 transitions. [2023-11-06 22:16:46,622 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:16:46,623 INFO L428 stractBuchiCegarLoop]: Abstraction has 2438 states and 3478 transitions. [2023-11-06 22:16:46,623 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:16:46,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2438 states and 3478 transitions. [2023-11-06 22:16:46,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2356 [2023-11-06 22:16:46,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:46,642 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:46,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:46,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:46,644 INFO L748 eck$LassoCheckResult]: Stem: 16659#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 16660#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 16762#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16763#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16495#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 16496#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16773#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16726#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16727#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16757#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16738#L526 assume !(0 == ~M_E~0); 16739#L526-2 assume !(0 == ~T1_E~0); 16775#L531-1 assume !(0 == ~T2_E~0); 16722#L536-1 assume !(0 == ~T3_E~0); 16723#L541-1 assume !(0 == ~T4_E~0); 16718#L546-1 assume !(0 == ~E_M~0); 16719#L551-1 assume !(0 == ~E_1~0); 16696#L556-1 assume !(0 == ~E_2~0); 16697#L561-1 assume !(0 == ~E_3~0); 16706#L566-1 assume !(0 == ~E_4~0); 16707#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16701#L262 assume !(1 == ~m_pc~0); 16702#L262-2 is_master_triggered_~__retres1~0#1 := 0; 16891#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16627#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 16628#L649 assume !(0 != activate_threads_~tmp~1#1); 16887#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16639#L281 assume !(1 == ~t1_pc~0); 16640#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16550#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16463#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16464#L657 assume !(0 != activate_threads_~tmp___0~0#1); 16609#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16709#L300 assume !(1 == ~t2_pc~0); 16710#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 16816#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16765#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16731#L665 assume !(0 != activate_threads_~tmp___1~0#1); 16476#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16477#L319 assume !(1 == ~t3_pc~0); 16432#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16433#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16418#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16419#L673 assume !(0 != activate_threads_~tmp___2~0#1); 16453#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16454#L338 assume 1 == ~t4_pc~0; 16604#L339 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16522#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16528#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16529#L681 assume !(0 != activate_threads_~tmp___3~0#1); 16400#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16401#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 16605#L584-2 assume !(1 == ~T1_E~0); 16606#L589-1 assume !(1 == ~T2_E~0); 16803#L594-1 assume !(1 == ~T3_E~0); 16804#L599-1 assume !(1 == ~T4_E~0); 16430#L604-1 assume !(1 == ~E_M~0); 16431#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16537#L614-1 assume !(1 == ~E_2~0); 16538#L619-1 assume !(1 == ~E_3~0); 16728#L624-1 assume !(1 == ~E_4~0); 16729#L629-1 assume { :end_inline_reset_delta_events } true; 18617#L815-2 [2023-11-06 22:16:46,645 INFO L750 eck$LassoCheckResult]: Loop: 18617#L815-2 assume !false; 18590#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18588#L501-1 assume !false; 18578#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18570#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18565#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18564#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 18562#L440 assume !(0 != eval_~tmp~0#1); 18563#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18828#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18827#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18826#L526-5 assume !(0 == ~T1_E~0); 18825#L531-3 assume !(0 == ~T2_E~0); 18824#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18822#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18821#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 18820#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18819#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18818#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18817#L566-3 assume !(0 == ~E_4~0); 18816#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18815#L262-18 assume !(1 == ~m_pc~0); 18814#L262-20 is_master_triggered_~__retres1~0#1 := 0; 18812#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18811#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 18810#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18809#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18808#L281-18 assume !(1 == ~t1_pc~0); 18805#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 18804#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18802#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 18800#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 18797#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18795#L300-18 assume !(1 == ~t2_pc~0); 17858#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 18793#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18792#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 18791#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 18787#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18786#L319-18 assume 1 == ~t3_pc~0; 18784#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18783#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18782#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18780#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18778#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18775#L338-18 assume !(1 == ~t4_pc~0); 16691#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 16596#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16597#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16457#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16458#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16657#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16658#L584-5 assume !(1 == ~T1_E~0); 16455#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16456#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16650#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16682#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16683#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16749#L614-3 assume !(1 == ~E_2~0); 16447#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16448#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16758#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 16792#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 16531#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 16532#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 18663#L834 assume !(0 == start_simulation_~tmp~3#1); 16642#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 18656#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 18649#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 18647#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 18642#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18623#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18621#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 18619#L847 assume !(0 != start_simulation_~tmp___0~1#1); 18617#L815-2 [2023-11-06 22:16:46,646 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:46,646 INFO L85 PathProgramCache]: Analyzing trace with hash -1271498812, now seen corresponding path program 1 times [2023-11-06 22:16:46,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:46,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162149149] [2023-11-06 22:16:46,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:46,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:46,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:46,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:46,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:46,707 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162149149] [2023-11-06 22:16:46,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162149149] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:46,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:46,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:46,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1691946535] [2023-11-06 22:16:46,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:46,708 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:46,709 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:46,709 INFO L85 PathProgramCache]: Analyzing trace with hash 834972333, now seen corresponding path program 1 times [2023-11-06 22:16:46,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:46,709 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214497897] [2023-11-06 22:16:46,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:46,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:46,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:46,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:46,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:46,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [214497897] [2023-11-06 22:16:46,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [214497897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:46,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:46,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:46,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96662566] [2023-11-06 22:16:46,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:46,759 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:46,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:46,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:46,760 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:46,760 INFO L87 Difference]: Start difference. First operand 2438 states and 3478 transitions. cyclomatic complexity: 1044 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:46,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:46,850 INFO L93 Difference]: Finished difference Result 4445 states and 6311 transitions. [2023-11-06 22:16:46,850 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4445 states and 6311 transitions. [2023-11-06 22:16:46,883 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4344 [2023-11-06 22:16:46,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4445 states to 4445 states and 6311 transitions. [2023-11-06 22:16:46,925 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4445 [2023-11-06 22:16:46,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4445 [2023-11-06 22:16:46,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4445 states and 6311 transitions. [2023-11-06 22:16:46,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:46,940 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4445 states and 6311 transitions. [2023-11-06 22:16:46,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4445 states and 6311 transitions. [2023-11-06 22:16:47,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4445 to 4429. [2023-11-06 22:16:47,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4429 states, 4429 states have (on average 1.421314066380673) internal successors, (6295), 4428 states have internal predecessors, (6295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:47,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4429 states to 4429 states and 6295 transitions. [2023-11-06 22:16:47,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4429 states and 6295 transitions. [2023-11-06 22:16:47,071 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:47,072 INFO L428 stractBuchiCegarLoop]: Abstraction has 4429 states and 6295 transitions. [2023-11-06 22:16:47,072 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:16:47,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4429 states and 6295 transitions. [2023-11-06 22:16:47,094 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4328 [2023-11-06 22:16:47,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:47,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:47,096 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:47,097 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:47,097 INFO L748 eck$LassoCheckResult]: Stem: 23545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 23546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 23649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23386#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 23387#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23663#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23609#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23610#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23644#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23621#L526 assume !(0 == ~M_E~0); 23622#L526-2 assume !(0 == ~T1_E~0); 23665#L531-1 assume !(0 == ~T2_E~0); 23605#L536-1 assume !(0 == ~T3_E~0); 23606#L541-1 assume !(0 == ~T4_E~0); 23601#L546-1 assume !(0 == ~E_M~0); 23602#L551-1 assume !(0 == ~E_1~0); 23579#L556-1 assume !(0 == ~E_2~0); 23580#L561-1 assume !(0 == ~E_3~0); 23589#L566-1 assume !(0 == ~E_4~0); 23590#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23584#L262 assume !(1 == ~m_pc~0); 23585#L262-2 is_master_triggered_~__retres1~0#1 := 0; 23780#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23513#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23514#L649 assume !(0 != activate_threads_~tmp~1#1); 23778#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23523#L281 assume !(1 == ~t1_pc~0); 23524#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 23439#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 23354#L657 assume !(0 != activate_threads_~tmp___0~0#1); 23497#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23592#L300 assume !(1 == ~t2_pc~0); 23593#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23704#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23653#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 23615#L665 assume !(0 != activate_threads_~tmp___1~0#1); 23366#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23367#L319 assume !(1 == ~t3_pc~0); 23321#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 23322#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23308#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23309#L673 assume !(0 != activate_threads_~tmp___2~0#1); 23343#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23344#L338 assume !(1 == ~t4_pc~0); 23412#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23413#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23419#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23420#L681 assume !(0 != activate_threads_~tmp___3~0#1); 23290#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23291#L584 assume 1 == ~M_E~0;~M_E~0 := 2; 23494#L584-2 assume !(1 == ~T1_E~0); 23455#L589-1 assume !(1 == ~T2_E~0); 23456#L594-1 assume !(1 == ~T3_E~0); 23691#L599-1 assume !(1 == ~T4_E~0); 25835#L604-1 assume !(1 == ~E_M~0); 25833#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25831#L614-1 assume !(1 == ~E_2~0); 23515#L619-1 assume !(1 == ~E_3~0); 23516#L624-1 assume !(1 == ~E_4~0); 23612#L629-1 assume { :end_inline_reset_delta_events } true; 25687#L815-2 [2023-11-06 22:16:47,097 INFO L750 eck$LassoCheckResult]: Loop: 25687#L815-2 assume !false; 25673#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25671#L501-1 assume !false; 25669#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25667#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25652#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25651#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 25649#L440 assume !(0 != eval_~tmp~0#1); 25650#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 27185#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 27183#L526-3 assume 0 == ~M_E~0;~M_E~0 := 1; 27181#L526-5 assume !(0 == ~T1_E~0); 27179#L531-3 assume !(0 == ~T2_E~0); 27087#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27086#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27085#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27084#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27083#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27082#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27081#L566-3 assume !(0 == ~E_4~0); 27079#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27077#L262-18 assume !(1 == ~m_pc~0); 27076#L262-20 is_master_triggered_~__retres1~0#1 := 0; 27075#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27074#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 27073#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27072#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27071#L281-18 assume 1 == ~t1_pc~0; 26736#L282-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26737#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27032#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27031#L657-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23724#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23725#L300-18 assume !(1 == ~t2_pc~0); 23760#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 27107#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27106#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27103#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 23746#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 23747#L319-18 assume 1 == ~t3_pc~0; 23446#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23447#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23469#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23648#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23634#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23521#L338-18 assume !(1 == ~t4_pc~0); 23522#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 27105#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27104#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27034#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27033#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25933#L584-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25925#L584-5 assume !(1 == ~T1_E~0); 25923#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25921#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25918#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25914#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25910#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25906#L614-3 assume !(1 == ~E_2~0); 25903#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25900#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25896#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25825#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25821#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25819#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 25816#L834 assume !(0 == start_simulation_~tmp~3#1); 25813#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 25811#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 25807#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 25805#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 25803#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25801#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25799#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 25689#L847 assume !(0 != start_simulation_~tmp___0~1#1); 25687#L815-2 [2023-11-06 22:16:47,098 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:47,098 INFO L85 PathProgramCache]: Analyzing trace with hash 843496709, now seen corresponding path program 1 times [2023-11-06 22:16:47,098 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:47,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289051468] [2023-11-06 22:16:47,099 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:47,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:47,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:47,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:47,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:47,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289051468] [2023-11-06 22:16:47,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289051468] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:47,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:47,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:47,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [43039062] [2023-11-06 22:16:47,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:47,159 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:47,160 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:47,160 INFO L85 PathProgramCache]: Analyzing trace with hash -669159510, now seen corresponding path program 1 times [2023-11-06 22:16:47,160 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:47,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646657423] [2023-11-06 22:16:47,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:47,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:47,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:47,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:47,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:47,245 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646657423] [2023-11-06 22:16:47,245 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646657423] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:47,245 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:47,245 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:47,245 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561271749] [2023-11-06 22:16:47,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:47,246 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:47,246 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:47,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:47,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:47,248 INFO L87 Difference]: Start difference. First operand 4429 states and 6295 transitions. cyclomatic complexity: 1874 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:47,325 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:47,325 INFO L93 Difference]: Finished difference Result 6636 states and 9417 transitions. [2023-11-06 22:16:47,325 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6636 states and 9417 transitions. [2023-11-06 22:16:47,370 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6532 [2023-11-06 22:16:47,434 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6636 states to 6636 states and 9417 transitions. [2023-11-06 22:16:47,434 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6636 [2023-11-06 22:16:47,443 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6636 [2023-11-06 22:16:47,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6636 states and 9417 transitions. [2023-11-06 22:16:47,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:47,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6636 states and 9417 transitions. [2023-11-06 22:16:47,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6636 states and 9417 transitions. [2023-11-06 22:16:47,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6636 to 4807. [2023-11-06 22:16:47,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4807 states, 4807 states have (on average 1.4179321822342417) internal successors, (6816), 4806 states have internal predecessors, (6816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:47,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4807 states to 4807 states and 6816 transitions. [2023-11-06 22:16:47,602 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4807 states and 6816 transitions. [2023-11-06 22:16:47,603 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:47,604 INFO L428 stractBuchiCegarLoop]: Abstraction has 4807 states and 6816 transitions. [2023-11-06 22:16:47,604 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:16:47,604 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4807 states and 6816 transitions. [2023-11-06 22:16:47,626 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4716 [2023-11-06 22:16:47,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:47,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:47,628 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:47,628 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:47,629 INFO L748 eck$LassoCheckResult]: Stem: 34616#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 34617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 34715#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34716#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34458#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 34459#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34727#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34682#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34683#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34711#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34695#L526 assume !(0 == ~M_E~0); 34696#L526-2 assume !(0 == ~T1_E~0); 34729#L531-1 assume !(0 == ~T2_E~0); 34678#L536-1 assume !(0 == ~T3_E~0); 34679#L541-1 assume !(0 == ~T4_E~0); 34674#L546-1 assume !(0 == ~E_M~0); 34675#L551-1 assume !(0 == ~E_1~0); 34651#L556-1 assume !(0 == ~E_2~0); 34652#L561-1 assume !(0 == ~E_3~0); 34661#L566-1 assume !(0 == ~E_4~0); 34662#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34656#L262 assume !(1 == ~m_pc~0); 34657#L262-2 is_master_triggered_~__retres1~0#1 := 0; 34839#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34586#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 34587#L649 assume !(0 != activate_threads_~tmp~1#1); 34838#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34596#L281 assume !(1 == ~t1_pc~0); 34597#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34511#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 34425#L657 assume !(0 != activate_threads_~tmp___0~0#1); 34569#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34664#L300 assume !(1 == ~t2_pc~0); 34665#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34766#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34686#L665 assume !(0 != activate_threads_~tmp___1~0#1); 34437#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34438#L319 assume !(1 == ~t3_pc~0); 34393#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34394#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 34381#L673 assume !(0 != activate_threads_~tmp___2~0#1); 34414#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34415#L338 assume !(1 == ~t4_pc~0); 34484#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34485#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34491#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 34492#L681 assume !(0 != activate_threads_~tmp___3~0#1); 34362#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34363#L584 assume !(1 == ~M_E~0); 34566#L584-2 assume !(1 == ~T1_E~0); 34528#L589-1 assume !(1 == ~T2_E~0); 34529#L594-1 assume !(1 == ~T3_E~0); 34622#L599-1 assume !(1 == ~T4_E~0); 34392#L604-1 assume !(1 == ~E_M~0); 34378#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34379#L614-1 assume !(1 == ~E_2~0); 34499#L619-1 assume !(1 == ~E_3~0); 34588#L624-1 assume !(1 == ~E_4~0); 34684#L629-1 assume { :end_inline_reset_delta_events } true; 34851#L815-2 [2023-11-06 22:16:47,629 INFO L750 eck$LassoCheckResult]: Loop: 34851#L815-2 assume !false; 37990#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37989#L501-1 assume !false; 37988#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 37985#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 37975#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 37973#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 37970#L440 assume !(0 != eval_~tmp~0#1); 37968#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37967#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37965#L526-3 assume !(0 == ~M_E~0); 37962#L526-5 assume !(0 == ~T1_E~0); 37960#L531-3 assume !(0 == ~T2_E~0); 37958#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37956#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37954#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 37950#L551-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37948#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37946#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37944#L566-3 assume !(0 == ~E_4~0); 37855#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 37853#L262-18 assume !(1 == ~m_pc~0); 37851#L262-20 is_master_triggered_~__retres1~0#1 := 0; 37849#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37847#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 37845#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37843#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37841#L281-18 assume !(1 == ~t1_pc~0); 37836#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 37834#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37832#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 37830#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 37827#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37825#L300-18 assume !(1 == ~t2_pc~0); 35984#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 37821#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37819#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37817#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 37815#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37813#L319-18 assume 1 == ~t3_pc~0; 36536#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36533#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36531#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 36529#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36527#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36525#L338-18 assume !(1 == ~t4_pc~0); 36523#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 36520#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36518#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36516#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36514#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36512#L584-3 assume !(1 == ~M_E~0); 35814#L584-5 assume !(1 == ~T1_E~0); 36466#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36465#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36459#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36457#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 36455#L609-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36453#L614-3 assume !(1 == ~E_2~0); 36451#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36449#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36447#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 36404#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 36398#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 34997#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 34930#L834 assume !(0 == start_simulation_~tmp~3#1); 34931#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 38108#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 38104#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 38103#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 38101#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38100#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38099#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 38098#L847 assume !(0 != start_simulation_~tmp___0~1#1); 34851#L815-2 [2023-11-06 22:16:47,630 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:47,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1544561287, now seen corresponding path program 1 times [2023-11-06 22:16:47,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:47,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077633102] [2023-11-06 22:16:47,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:47,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:47,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:47,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:47,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:47,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077633102] [2023-11-06 22:16:47,706 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077633102] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:47,706 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:47,706 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:47,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899151320] [2023-11-06 22:16:47,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:47,707 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:47,707 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:47,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1024858899, now seen corresponding path program 1 times [2023-11-06 22:16:47,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:47,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983750057] [2023-11-06 22:16:47,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:47,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:47,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:47,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:47,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:47,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983750057] [2023-11-06 22:16:47,752 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983750057] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:47,752 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:47,752 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:47,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938809763] [2023-11-06 22:16:47,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:47,753 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:47,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:47,753 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:16:47,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:16:47,754 INFO L87 Difference]: Start difference. First operand 4807 states and 6816 transitions. cyclomatic complexity: 2013 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:47,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:47,912 INFO L93 Difference]: Finished difference Result 6555 states and 9125 transitions. [2023-11-06 22:16:47,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6555 states and 9125 transitions. [2023-11-06 22:16:47,997 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6370 [2023-11-06 22:16:48,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6555 states to 6555 states and 9125 transitions. [2023-11-06 22:16:48,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6555 [2023-11-06 22:16:48,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6555 [2023-11-06 22:16:48,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6555 states and 9125 transitions. [2023-11-06 22:16:48,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:48,062 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6555 states and 9125 transitions. [2023-11-06 22:16:48,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6555 states and 9125 transitions. [2023-11-06 22:16:48,179 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6555 to 5394. [2023-11-06 22:16:48,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5394 states, 5394 states have (on average 1.400074156470152) internal successors, (7552), 5393 states have internal predecessors, (7552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:48,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5394 states to 5394 states and 7552 transitions. [2023-11-06 22:16:48,212 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5394 states and 7552 transitions. [2023-11-06 22:16:48,212 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:16:48,213 INFO L428 stractBuchiCegarLoop]: Abstraction has 5394 states and 7552 transitions. [2023-11-06 22:16:48,213 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:16:48,214 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5394 states and 7552 transitions. [2023-11-06 22:16:48,237 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5260 [2023-11-06 22:16:48,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:48,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:48,239 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:48,239 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:48,240 INFO L748 eck$LassoCheckResult]: Stem: 45987#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 45988#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 46093#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46094#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45831#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 45832#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46103#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46056#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46057#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46088#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46067#L526 assume !(0 == ~M_E~0); 46068#L526-2 assume !(0 == ~T1_E~0); 46105#L531-1 assume !(0 == ~T2_E~0); 46052#L536-1 assume !(0 == ~T3_E~0); 46053#L541-1 assume !(0 == ~T4_E~0); 46048#L546-1 assume !(0 == ~E_M~0); 46049#L551-1 assume 0 == ~E_1~0;~E_1~0 := 1; 46121#L556-1 assume !(0 == ~E_2~0); 46289#L561-1 assume !(0 == ~E_3~0); 46288#L566-1 assume !(0 == ~E_4~0); 46217#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46029#L262 assume !(1 == ~m_pc~0); 46030#L262-2 is_master_triggered_~__retres1~0#1 := 0; 46222#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45956#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 45957#L649 assume !(0 != activate_threads_~tmp~1#1); 46218#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46282#L281 assume !(1 == ~t1_pc~0); 46281#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 46280#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46279#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46274#L657 assume !(0 != activate_threads_~tmp___0~0#1); 46273#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46272#L300 assume !(1 == ~t2_pc~0); 46271#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 46270#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46269#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 46268#L665 assume !(0 != activate_threads_~tmp___1~0#1); 46267#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46266#L319 assume !(1 == ~t3_pc~0); 46264#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46263#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46262#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 46261#L673 assume !(0 != activate_threads_~tmp___2~0#1); 46260#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46259#L338 assume !(1 == ~t4_pc~0); 46258#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 46257#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46256#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46255#L681 assume !(0 != activate_threads_~tmp___3~0#1); 46254#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46253#L584 assume !(1 == ~M_E~0); 46252#L584-2 assume !(1 == ~T1_E~0); 46251#L589-1 assume !(1 == ~T2_E~0); 46250#L594-1 assume !(1 == ~T3_E~0); 46249#L599-1 assume !(1 == ~T4_E~0); 46248#L604-1 assume !(1 == ~E_M~0); 46247#L609-1 assume 1 == ~E_1~0;~E_1~0 := 2; 45751#L614-1 assume !(1 == ~E_2~0); 45870#L619-1 assume !(1 == ~E_3~0); 45958#L624-1 assume !(1 == ~E_4~0); 46058#L629-1 assume { :end_inline_reset_delta_events } true; 46079#L815-2 [2023-11-06 22:16:48,240 INFO L750 eck$LassoCheckResult]: Loop: 46079#L815-2 assume !false; 46082#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45945#L501-1 assume !false; 46209#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46210#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 45876#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 46110#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 46111#L440 assume !(0 != eval_~tmp~0#1); 46238#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46189#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45992#L526-3 assume !(0 == ~M_E~0); 45993#L526-5 assume !(0 == ~T1_E~0); 46137#L531-3 assume !(0 == ~T2_E~0); 50927#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 50925#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50923#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50921#L551-3 assume !(0 == ~E_1~0); 46007#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46008#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46115#L566-3 assume !(0 == ~E_4~0); 45886#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45887#L262-18 assume !(1 == ~m_pc~0); 45979#L262-20 is_master_triggered_~__retres1~0#1 := 0; 45980#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46000#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 46001#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45771#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45772#L281-18 assume !(1 == ~t1_pc~0); 46022#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 46041#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46042#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 46212#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 46163#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46164#L300-18 assume !(1 == ~t2_pc~0); 50968#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 50967#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50966#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 50965#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 50964#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50962#L319-18 assume !(1 == ~t3_pc~0); 50960#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 50957#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50955#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 50952#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50950#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50948#L338-18 assume !(1 == ~t4_pc~0); 50946#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 50944#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 50942#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 50940#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50939#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50938#L584-3 assume !(1 == ~M_E~0); 49930#L584-5 assume !(1 == ~T1_E~0); 50936#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50934#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50932#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50930#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 50877#L609-3 assume !(1 == ~E_1~0); 50874#L614-3 assume !(1 == ~E_2~0); 50872#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50870#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 50869#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 50860#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 50856#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 50854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 48774#L834 assume !(0 == start_simulation_~tmp~3#1); 45974#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 46097#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 46051#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 45794#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 45795#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46165#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46171#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 46078#L847 assume !(0 != start_simulation_~tmp___0~1#1); 46079#L815-2 [2023-11-06 22:16:48,241 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:48,241 INFO L85 PathProgramCache]: Analyzing trace with hash -383711415, now seen corresponding path program 1 times [2023-11-06 22:16:48,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:48,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2060577798] [2023-11-06 22:16:48,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:48,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:48,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:48,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:48,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:48,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2060577798] [2023-11-06 22:16:48,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2060577798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:48,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:48,314 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:48,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408557263] [2023-11-06 22:16:48,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:48,315 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:48,316 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:48,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1128028626, now seen corresponding path program 1 times [2023-11-06 22:16:48,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:48,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715092769] [2023-11-06 22:16:48,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:48,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:48,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:48,358 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:48,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:48,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715092769] [2023-11-06 22:16:48,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715092769] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:48,359 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:48,359 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:48,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205897666] [2023-11-06 22:16:48,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:48,360 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:48,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:48,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:16:48,362 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:16:48,362 INFO L87 Difference]: Start difference. First operand 5394 states and 7552 transitions. cyclomatic complexity: 2162 Second operand has 4 states, 4 states have (on average 15.5) internal successors, (62), 3 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:48,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:48,466 INFO L93 Difference]: Finished difference Result 5506 states and 7659 transitions. [2023-11-06 22:16:48,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5506 states and 7659 transitions. [2023-11-06 22:16:48,496 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5402 [2023-11-06 22:16:48,527 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5506 states to 5506 states and 7659 transitions. [2023-11-06 22:16:48,527 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5506 [2023-11-06 22:16:48,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5506 [2023-11-06 22:16:48,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5506 states and 7659 transitions. [2023-11-06 22:16:48,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:48,544 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5506 states and 7659 transitions. [2023-11-06 22:16:48,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5506 states and 7659 transitions. [2023-11-06 22:16:48,693 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5506 to 4588. [2023-11-06 22:16:48,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4588 states, 4588 states have (on average 1.3951612903225807) internal successors, (6401), 4587 states have internal predecessors, (6401), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:48,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4588 states to 4588 states and 6401 transitions. [2023-11-06 22:16:48,737 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4588 states and 6401 transitions. [2023-11-06 22:16:48,737 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:16:48,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 4588 states and 6401 transitions. [2023-11-06 22:16:48,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:16:48,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4588 states and 6401 transitions. [2023-11-06 22:16:48,761 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4500 [2023-11-06 22:16:48,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:48,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:48,763 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:48,764 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:48,764 INFO L748 eck$LassoCheckResult]: Stem: 56897#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 56898#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 56996#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56997#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56740#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 56741#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57005#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56961#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56962#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 56991#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56972#L526 assume !(0 == ~M_E~0); 56973#L526-2 assume !(0 == ~T1_E~0); 57007#L531-1 assume !(0 == ~T2_E~0); 56957#L536-1 assume !(0 == ~T3_E~0); 56958#L541-1 assume !(0 == ~T4_E~0); 56953#L546-1 assume !(0 == ~E_M~0); 56954#L551-1 assume !(0 == ~E_1~0); 56931#L556-1 assume !(0 == ~E_2~0); 56932#L561-1 assume !(0 == ~E_3~0); 56941#L566-1 assume !(0 == ~E_4~0); 56942#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56936#L262 assume !(1 == ~m_pc~0); 56937#L262-2 is_master_triggered_~__retres1~0#1 := 0; 57125#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56868#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56869#L649 assume !(0 != activate_threads_~tmp~1#1); 57121#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56877#L281 assume !(1 == ~t1_pc~0); 56878#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56793#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56706#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56707#L657 assume !(0 != activate_threads_~tmp___0~0#1); 56849#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56944#L300 assume !(1 == ~t2_pc~0); 56945#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 57044#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56999#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56965#L665 assume !(0 != activate_threads_~tmp___1~0#1); 56719#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56720#L319 assume !(1 == ~t3_pc~0); 56675#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 56676#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56662#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56663#L673 assume !(0 != activate_threads_~tmp___2~0#1); 56696#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56697#L338 assume !(1 == ~t4_pc~0); 56764#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56765#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56770#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56771#L681 assume !(0 != activate_threads_~tmp___3~0#1); 56644#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56645#L584 assume !(1 == ~M_E~0); 56846#L584-2 assume !(1 == ~T1_E~0); 56807#L589-1 assume !(1 == ~T2_E~0); 56808#L594-1 assume !(1 == ~T3_E~0); 56901#L599-1 assume !(1 == ~T4_E~0); 56674#L604-1 assume !(1 == ~E_M~0); 56660#L609-1 assume !(1 == ~E_1~0); 56661#L614-1 assume !(1 == ~E_2~0); 56781#L619-1 assume !(1 == ~E_3~0); 56870#L624-1 assume !(1 == ~E_4~0); 56963#L629-1 assume { :end_inline_reset_delta_events } true; 57131#L815-2 [2023-11-06 22:16:48,765 INFO L750 eck$LassoCheckResult]: Loop: 57131#L815-2 assume !false; 60982#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60980#L501-1 assume !false; 60979#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 60977#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 57143#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 57012#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 57013#L440 assume !(0 != eval_~tmp~0#1); 57141#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61228#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61227#L526-3 assume !(0 == ~M_E~0); 61225#L526-5 assume !(0 == ~T1_E~0); 61224#L531-3 assume !(0 == ~T2_E~0); 61223#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61222#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61221#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 61220#L551-3 assume !(0 == ~E_1~0); 56915#L556-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56916#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57017#L566-3 assume !(0 == ~E_4~0); 56797#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56798#L262-18 assume !(1 == ~m_pc~0); 56890#L262-20 is_master_triggered_~__retres1~0#1 := 0; 56891#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61184#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 61183#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61182#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61181#L281-18 assume !(1 == ~t1_pc~0); 61179#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 61178#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61177#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 61176#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 61175#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57103#L300-18 assume !(1 == ~t2_pc~0); 56670#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 56671#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56739#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56994#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 57025#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 56794#L319-18 assume 1 == ~t3_pc~0; 56795#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 56800#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56821#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56995#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 56983#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 56875#L338-18 assume !(1 == ~t4_pc~0); 56876#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 56839#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56840#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56700#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56701#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56895#L584-3 assume !(1 == ~M_E~0); 56896#L584-5 assume !(1 == ~T1_E~0); 56698#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56699#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56888#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56918#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56919#L609-3 assume !(1 == ~E_1~0); 61117#L614-3 assume !(1 == ~E_2~0); 61114#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61112#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61110#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 61104#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 61099#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 61097#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 59242#L834 assume !(0 == start_simulation_~tmp~3#1); 59243#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 61010#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 61005#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 61003#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 61001#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60999#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60997#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 60993#L847 assume !(0 != start_simulation_~tmp___0~1#1); 57131#L815-2 [2023-11-06 22:16:48,765 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:48,765 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 1 times [2023-11-06 22:16:48,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:48,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069995021] [2023-11-06 22:16:48,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:48,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:48,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:48,783 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:48,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:48,842 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:48,845 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:48,846 INFO L85 PathProgramCache]: Analyzing trace with hash 2115489581, now seen corresponding path program 1 times [2023-11-06 22:16:48,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:48,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006301115] [2023-11-06 22:16:48,846 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:48,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:48,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:48,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:48,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:48,895 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006301115] [2023-11-06 22:16:48,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006301115] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:48,896 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:48,896 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:48,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880944830] [2023-11-06 22:16:48,897 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:48,897 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:48,897 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:48,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:48,898 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:48,899 INFO L87 Difference]: Start difference. First operand 4588 states and 6401 transitions. cyclomatic complexity: 1817 Second operand has 3 states, 3 states have (on average 24.666666666666668) internal successors, (74), 3 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:49,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:49,007 INFO L93 Difference]: Finished difference Result 7857 states and 10878 transitions. [2023-11-06 22:16:49,007 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7857 states and 10878 transitions. [2023-11-06 22:16:49,050 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7702 [2023-11-06 22:16:49,084 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7857 states to 7857 states and 10878 transitions. [2023-11-06 22:16:49,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7857 [2023-11-06 22:16:49,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7857 [2023-11-06 22:16:49,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7857 states and 10878 transitions. [2023-11-06 22:16:49,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:49,216 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7857 states and 10878 transitions. [2023-11-06 22:16:49,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7857 states and 10878 transitions. [2023-11-06 22:16:49,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7857 to 7841. [2023-11-06 22:16:49,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7841 states, 7841 states have (on average 1.3852824894783828) internal successors, (10862), 7840 states have internal predecessors, (10862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:49,407 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7841 states to 7841 states and 10862 transitions. [2023-11-06 22:16:49,407 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7841 states and 10862 transitions. [2023-11-06 22:16:49,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:49,409 INFO L428 stractBuchiCegarLoop]: Abstraction has 7841 states and 10862 transitions. [2023-11-06 22:16:49,409 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:16:49,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7841 states and 10862 transitions. [2023-11-06 22:16:49,446 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7686 [2023-11-06 22:16:49,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:49,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:49,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:49,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:49,450 INFO L748 eck$LassoCheckResult]: Stem: 69350#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 69351#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 69456#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69457#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 69191#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 69192#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69469#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69419#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69420#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69451#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 69434#L526 assume !(0 == ~M_E~0); 69435#L526-2 assume !(0 == ~T1_E~0); 69471#L531-1 assume !(0 == ~T2_E~0); 69415#L536-1 assume !(0 == ~T3_E~0); 69416#L541-1 assume !(0 == ~T4_E~0); 69411#L546-1 assume !(0 == ~E_M~0); 69412#L551-1 assume !(0 == ~E_1~0); 69386#L556-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69387#L561-1 assume !(0 == ~E_3~0); 69431#L566-1 assume !(0 == ~E_4~0); 69594#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69595#L262 assume !(1 == ~m_pc~0); 69604#L262-2 is_master_triggered_~__retres1~0#1 := 0; 69605#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69650#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 69599#L649 assume !(0 != activate_threads_~tmp~1#1); 69600#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69649#L281 assume !(1 == ~t1_pc~0); 69609#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 69610#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69647#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 69646#L657 assume !(0 != activate_threads_~tmp___0~0#1); 69586#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 69587#L300 assume !(1 == ~t2_pc~0); 69558#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 69559#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69645#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 69424#L665 assume !(0 != activate_threads_~tmp___1~0#1); 69425#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69644#L319 assume !(1 == ~t3_pc~0); 69126#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69127#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69113#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 69114#L673 assume !(0 != activate_threads_~tmp___2~0#1); 69643#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 69515#L338 assume !(1 == ~t4_pc~0); 69215#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 69216#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69641#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 69602#L681 assume !(0 != activate_threads_~tmp___3~0#1); 69095#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69096#L584 assume !(1 == ~M_E~0); 69639#L584-2 assume !(1 == ~T1_E~0); 69638#L589-1 assume !(1 == ~T2_E~0); 69637#L594-1 assume !(1 == ~T3_E~0); 69636#L599-1 assume !(1 == ~T4_E~0); 69125#L604-1 assume !(1 == ~E_M~0); 69111#L609-1 assume !(1 == ~E_1~0); 69112#L614-1 assume 1 == ~E_2~0;~E_2~0 := 2; 69232#L619-1 assume !(1 == ~E_3~0); 69320#L624-1 assume !(1 == ~E_4~0); 69421#L629-1 assume { :end_inline_reset_delta_events } true; 69611#L815-2 [2023-11-06 22:16:49,450 INFO L750 eck$LassoCheckResult]: Loop: 69611#L815-2 assume !false; 74934#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 74927#L501-1 assume !false; 74921#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 74913#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 74907#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 74905#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 74902#L440 assume !(0 != eval_~tmp~0#1); 74903#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76808#L526-3 assume !(0 == ~M_E~0); 76806#L526-5 assume !(0 == ~T1_E~0); 76804#L531-3 assume !(0 == ~T2_E~0); 76802#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76800#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76798#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 76796#L551-3 assume !(0 == ~E_1~0); 76794#L556-3 assume !(0 == ~E_2~0); 76792#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76790#L566-3 assume !(0 == ~E_4~0); 76788#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76786#L262-18 assume !(1 == ~m_pc~0); 76784#L262-20 is_master_triggered_~__retres1~0#1 := 0; 76782#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76780#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 76778#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76775#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76557#L281-18 assume !(1 == ~t1_pc~0); 76554#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 76552#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76551#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 76549#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 76547#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76545#L300-18 assume !(1 == ~t2_pc~0); 76354#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 76541#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76526#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76525#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 76524#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76523#L319-18 assume 1 == ~t3_pc~0; 76521#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76520#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76518#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76516#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76514#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76512#L338-18 assume !(1 == ~t4_pc~0); 76510#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 76508#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76506#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76504#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76501#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76499#L584-3 assume !(1 == ~M_E~0); 74570#L584-5 assume !(1 == ~T1_E~0); 76496#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76494#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76492#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76491#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 76490#L609-3 assume !(1 == ~E_1~0); 76489#L614-3 assume !(1 == ~E_2~0); 69140#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69141#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69450#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 69487#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 69224#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 69225#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 69281#L834 assume !(0 == start_simulation_~tmp~3#1); 69282#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 74990#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 74985#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 74983#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 74981#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 74979#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 74976#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 74959#L847 assume !(0 != start_simulation_~tmp___0~1#1); 69611#L815-2 [2023-11-06 22:16:49,451 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:49,451 INFO L85 PathProgramCache]: Analyzing trace with hash 652862409, now seen corresponding path program 1 times [2023-11-06 22:16:49,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:49,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685773191] [2023-11-06 22:16:49,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:49,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:49,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:49,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:49,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:49,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1685773191] [2023-11-06 22:16:49,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1685773191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:49,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:49,504 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:49,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [194794841] [2023-11-06 22:16:49,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:49,504 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:49,505 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:49,505 INFO L85 PathProgramCache]: Analyzing trace with hash -918560465, now seen corresponding path program 1 times [2023-11-06 22:16:49,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:49,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806601433] [2023-11-06 22:16:49,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:49,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:49,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:49,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:49,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:49,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806601433] [2023-11-06 22:16:49,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806601433] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:49,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:49,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:16:49,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1895408913] [2023-11-06 22:16:49,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:49,603 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:49,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:49,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:49,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:49,604 INFO L87 Difference]: Start difference. First operand 7841 states and 10862 transitions. cyclomatic complexity: 3025 Second operand has 3 states, 3 states have (on average 20.666666666666668) internal successors, (62), 2 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:49,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:49,669 INFO L93 Difference]: Finished difference Result 4580 states and 6299 transitions. [2023-11-06 22:16:49,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4580 states and 6299 transitions. [2023-11-06 22:16:49,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4492 [2023-11-06 22:16:49,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4580 states to 4580 states and 6299 transitions. [2023-11-06 22:16:49,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4580 [2023-11-06 22:16:49,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4580 [2023-11-06 22:16:49,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4580 states and 6299 transitions. [2023-11-06 22:16:49,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:49,731 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4580 states and 6299 transitions. [2023-11-06 22:16:49,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4580 states and 6299 transitions. [2023-11-06 22:16:49,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4580 to 4580. [2023-11-06 22:16:49,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4580 states, 4580 states have (on average 1.3753275109170306) internal successors, (6299), 4579 states have internal predecessors, (6299), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:49,912 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4580 states to 4580 states and 6299 transitions. [2023-11-06 22:16:49,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4580 states and 6299 transitions. [2023-11-06 22:16:49,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:49,916 INFO L428 stractBuchiCegarLoop]: Abstraction has 4580 states and 6299 transitions. [2023-11-06 22:16:49,917 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:16:49,917 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4580 states and 6299 transitions. [2023-11-06 22:16:49,933 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4492 [2023-11-06 22:16:49,934 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:49,934 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:49,937 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:49,937 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:49,938 INFO L748 eck$LassoCheckResult]: Stem: 81771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 81772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 81866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81618#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 81619#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81876#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 81834#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 81835#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 81861#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 81844#L526 assume !(0 == ~M_E~0); 81845#L526-2 assume !(0 == ~T1_E~0); 81879#L531-1 assume !(0 == ~T2_E~0); 81830#L536-1 assume !(0 == ~T3_E~0); 81831#L541-1 assume !(0 == ~T4_E~0); 81826#L546-1 assume !(0 == ~E_M~0); 81827#L551-1 assume !(0 == ~E_1~0); 81803#L556-1 assume !(0 == ~E_2~0); 81804#L561-1 assume !(0 == ~E_3~0); 81813#L566-1 assume !(0 == ~E_4~0); 81814#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 81808#L262 assume !(1 == ~m_pc~0); 81809#L262-2 is_master_triggered_~__retres1~0#1 := 0; 81978#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81741#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 81742#L649 assume !(0 != activate_threads_~tmp~1#1); 81976#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 81751#L281 assume !(1 == ~t1_pc~0); 81752#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81669#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 81586#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81587#L657 assume !(0 != activate_threads_~tmp___0~0#1); 81726#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81816#L300 assume !(1 == ~t2_pc~0); 81817#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 81914#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 81870#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 81838#L665 assume !(0 != activate_threads_~tmp___1~0#1); 81599#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 81600#L319 assume !(1 == ~t3_pc~0); 81556#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 81557#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 81543#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 81544#L673 assume !(0 != activate_threads_~tmp___2~0#1); 81576#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81577#L338 assume !(1 == ~t4_pc~0); 81643#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81644#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 81649#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 81650#L681 assume !(0 != activate_threads_~tmp___3~0#1); 81525#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81526#L584 assume !(1 == ~M_E~0); 81723#L584-2 assume !(1 == ~T1_E~0); 81683#L589-1 assume !(1 == ~T2_E~0); 81684#L594-1 assume !(1 == ~T3_E~0); 81775#L599-1 assume !(1 == ~T4_E~0); 81555#L604-1 assume !(1 == ~E_M~0); 81541#L609-1 assume !(1 == ~E_1~0); 81542#L614-1 assume !(1 == ~E_2~0); 81658#L619-1 assume !(1 == ~E_3~0); 81743#L624-1 assume !(1 == ~E_4~0); 81836#L629-1 assume { :end_inline_reset_delta_events } true; 81984#L815-2 [2023-11-06 22:16:49,938 INFO L750 eck$LassoCheckResult]: Loop: 81984#L815-2 assume !false; 83808#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 83666#L501-1 assume !false; 83791#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83697#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83673#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83658#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 83653#L440 assume !(0 != eval_~tmp~0#1); 83654#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 84238#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 84237#L526-3 assume !(0 == ~M_E~0); 84236#L526-5 assume !(0 == ~T1_E~0); 84235#L531-3 assume !(0 == ~T2_E~0); 84234#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84233#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 84232#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 84231#L551-3 assume !(0 == ~E_1~0); 84230#L556-3 assume !(0 == ~E_2~0); 84229#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84228#L566-3 assume !(0 == ~E_4~0); 84227#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 84226#L262-18 assume !(1 == ~m_pc~0); 84225#L262-20 is_master_triggered_~__retres1~0#1 := 0; 84224#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 84223#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 84222#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 84221#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 84220#L281-18 assume !(1 == ~t1_pc~0); 84218#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 84217#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 84216#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 84215#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 84214#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 84213#L300-18 assume !(1 == ~t2_pc~0); 83429#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 84212#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 84211#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 84210#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 84209#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84208#L319-18 assume !(1 == ~t3_pc~0); 84207#L319-20 is_transmit3_triggered_~__retres1~3#1 := 0; 84205#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 84204#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 84203#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 84202#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 84201#L338-18 assume !(1 == ~t4_pc~0); 84200#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 84199#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 84198#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 84197#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 84196#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84195#L584-3 assume !(1 == ~M_E~0); 83884#L584-5 assume !(1 == ~T1_E~0); 84194#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 84193#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 84192#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84191#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84190#L609-3 assume !(1 == ~E_1~0); 84189#L614-3 assume !(1 == ~E_2~0); 84188#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 84187#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 84186#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 84183#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 82275#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 82276#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 83835#L834 assume !(0 == start_simulation_~tmp~3#1); 83833#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 83826#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 83821#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 83819#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 83817#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 83815#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 83813#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 83811#L847 assume !(0 != start_simulation_~tmp___0~1#1); 81984#L815-2 [2023-11-06 22:16:49,939 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:49,939 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 2 times [2023-11-06 22:16:49,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:49,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006505802] [2023-11-06 22:16:49,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:49,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:49,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:49,954 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:49,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:49,993 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:49,994 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:49,994 INFO L85 PathProgramCache]: Analyzing trace with hash 132888624, now seen corresponding path program 1 times [2023-11-06 22:16:49,994 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:49,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1024092632] [2023-11-06 22:16:49,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:49,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:50,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:50,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:50,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:50,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1024092632] [2023-11-06 22:16:50,067 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1024092632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:50,067 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:50,067 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:16:50,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505377354] [2023-11-06 22:16:50,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:50,068 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:50,068 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:50,068 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:16:50,069 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:16:50,069 INFO L87 Difference]: Start difference. First operand 4580 states and 6299 transitions. cyclomatic complexity: 1723 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:50,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:50,238 INFO L93 Difference]: Finished difference Result 8112 states and 11011 transitions. [2023-11-06 22:16:50,239 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8112 states and 11011 transitions. [2023-11-06 22:16:50,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8000 [2023-11-06 22:16:50,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8112 states to 8112 states and 11011 transitions. [2023-11-06 22:16:50,318 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8112 [2023-11-06 22:16:50,328 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8112 [2023-11-06 22:16:50,328 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8112 states and 11011 transitions. [2023-11-06 22:16:50,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:50,339 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8112 states and 11011 transitions. [2023-11-06 22:16:50,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8112 states and 11011 transitions. [2023-11-06 22:16:50,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8112 to 4628. [2023-11-06 22:16:50,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4628 states, 4628 states have (on average 1.3714347450302506) internal successors, (6347), 4627 states have internal predecessors, (6347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:50,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4628 states to 4628 states and 6347 transitions. [2023-11-06 22:16:50,539 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4628 states and 6347 transitions. [2023-11-06 22:16:50,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:16:50,541 INFO L428 stractBuchiCegarLoop]: Abstraction has 4628 states and 6347 transitions. [2023-11-06 22:16:50,541 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:16:50,541 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4628 states and 6347 transitions. [2023-11-06 22:16:50,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4540 [2023-11-06 22:16:50,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:50,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:50,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:50,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:50,559 INFO L748 eck$LassoCheckResult]: Stem: 94492#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 94493#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 94592#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94593#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94330#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 94331#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94604#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94557#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94558#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94585#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94567#L526 assume !(0 == ~M_E~0); 94568#L526-2 assume !(0 == ~T1_E~0); 94606#L531-1 assume !(0 == ~T2_E~0); 94553#L536-1 assume !(0 == ~T3_E~0); 94554#L541-1 assume !(0 == ~T4_E~0); 94549#L546-1 assume !(0 == ~E_M~0); 94550#L551-1 assume !(0 == ~E_1~0); 94525#L556-1 assume !(0 == ~E_2~0); 94526#L561-1 assume !(0 == ~E_3~0); 94535#L566-1 assume !(0 == ~E_4~0); 94536#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94530#L262 assume !(1 == ~m_pc~0); 94531#L262-2 is_master_triggered_~__retres1~0#1 := 0; 94722#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94462#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94463#L649 assume !(0 != activate_threads_~tmp~1#1); 94718#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94471#L281 assume !(1 == ~t1_pc~0); 94472#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 94383#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94296#L657 assume !(0 != activate_threads_~tmp___0~0#1); 94444#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94540#L300 assume !(1 == ~t2_pc~0); 94541#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94643#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 94561#L665 assume !(0 != activate_threads_~tmp___1~0#1); 94308#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94309#L319 assume !(1 == ~t3_pc~0); 94265#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94266#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94252#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94253#L673 assume !(0 != activate_threads_~tmp___2~0#1); 94285#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94286#L338 assume !(1 == ~t4_pc~0); 94354#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94355#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94360#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94361#L681 assume !(0 != activate_threads_~tmp___3~0#1); 94234#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94235#L584 assume !(1 == ~M_E~0); 94441#L584-2 assume !(1 == ~T1_E~0); 94399#L589-1 assume !(1 == ~T2_E~0); 94400#L594-1 assume !(1 == ~T3_E~0); 94496#L599-1 assume !(1 == ~T4_E~0); 94264#L604-1 assume !(1 == ~E_M~0); 94250#L609-1 assume !(1 == ~E_1~0); 94251#L614-1 assume !(1 == ~E_2~0); 94371#L619-1 assume !(1 == ~E_3~0); 94464#L624-1 assume !(1 == ~E_4~0); 94559#L629-1 assume { :end_inline_reset_delta_events } true; 94579#L815-2 [2023-11-06 22:16:50,560 INFO L750 eck$LassoCheckResult]: Loop: 94579#L815-2 assume !false; 94580#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 94450#L501-1 assume !false; 94712#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 94713#L398 assume !(0 == ~m_st~0); 94376#L402 assume !(0 == ~t1_st~0); 94378#L406 assume !(0 == ~t2_st~0); 94499#L410 assume !(0 == ~t3_st~0); 94684#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 94742#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 96407#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 96408#L440 assume !(0 != eval_~tmp~0#1); 94372#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 94373#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 94692#L526-3 assume !(0 == ~M_E~0); 98523#L526-5 assume !(0 == ~T1_E~0); 98522#L531-3 assume !(0 == ~T2_E~0); 98521#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 98520#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 98519#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94743#L551-3 assume !(0 == ~E_1~0); 94509#L556-3 assume !(0 == ~E_2~0); 94510#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94618#L566-3 assume !(0 == ~E_4~0); 94688#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 98515#L262-18 assume !(1 == ~m_pc~0); 98514#L262-20 is_master_triggered_~__retres1~0#1 := 0; 98513#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98512#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94717#L649-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 94271#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94272#L281-18 assume !(1 == ~t1_pc~0); 94523#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 94542#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94543#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94734#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 94735#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 98506#L300-18 assume !(1 == ~t2_pc~0); 98136#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 94328#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94329#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98505#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 98504#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 98503#L319-18 assume 1 == ~t3_pc~0; 94390#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 94391#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 94615#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94616#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 94577#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94469#L338-18 assume !(1 == ~t4_pc~0); 94470#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 94433#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94434#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94289#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 94290#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94490#L584-3 assume !(1 == ~M_E~0); 94491#L584-5 assume !(1 == ~T1_E~0); 94287#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94288#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 94481#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 94512#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 94513#L609-3 assume !(1 == ~E_1~0); 94576#L614-3 assume !(1 == ~E_2~0); 94279#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 94280#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 94586#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 94623#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98844#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98842#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 98840#L834 assume !(0 == start_simulation_~tmp~3#1); 98778#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 98779#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 98834#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 98833#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 94667#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 94668#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 94675#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 94578#L847 assume !(0 != start_simulation_~tmp___0~1#1); 94579#L815-2 [2023-11-06 22:16:50,560 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:50,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 3 times [2023-11-06 22:16:50,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:50,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [589249962] [2023-11-06 22:16:50,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:50,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:50,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:50,578 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:50,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:50,609 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:50,610 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:50,610 INFO L85 PathProgramCache]: Analyzing trace with hash -2030396125, now seen corresponding path program 1 times [2023-11-06 22:16:50,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:50,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077501353] [2023-11-06 22:16:50,611 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:50,611 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:50,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:50,712 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:50,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:50,713 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077501353] [2023-11-06 22:16:50,713 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077501353] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:50,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:50,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:16:50,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465921968] [2023-11-06 22:16:50,714 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:50,714 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:50,714 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:50,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:16:50,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:16:50,715 INFO L87 Difference]: Start difference. First operand 4628 states and 6347 transitions. cyclomatic complexity: 1723 Second operand has 5 states, 5 states have (on average 15.6) internal successors, (78), 5 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:50,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:50,951 INFO L93 Difference]: Finished difference Result 8248 states and 11110 transitions. [2023-11-06 22:16:50,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8248 states and 11110 transitions. [2023-11-06 22:16:50,993 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8152 [2023-11-06 22:16:51,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8248 states to 8248 states and 11110 transitions. [2023-11-06 22:16:51,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8248 [2023-11-06 22:16:51,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8248 [2023-11-06 22:16:51,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8248 states and 11110 transitions. [2023-11-06 22:16:51,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:51,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8248 states and 11110 transitions. [2023-11-06 22:16:51,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8248 states and 11110 transitions. [2023-11-06 22:16:51,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8248 to 4760. [2023-11-06 22:16:51,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4760 states, 4760 states have (on average 1.3533613445378152) internal successors, (6442), 4759 states have internal predecessors, (6442), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:51,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4760 states to 4760 states and 6442 transitions. [2023-11-06 22:16:51,249 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4760 states and 6442 transitions. [2023-11-06 22:16:51,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:16:51,250 INFO L428 stractBuchiCegarLoop]: Abstraction has 4760 states and 6442 transitions. [2023-11-06 22:16:51,250 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:16:51,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4760 states and 6442 transitions. [2023-11-06 22:16:51,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4672 [2023-11-06 22:16:51,267 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:51,267 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:51,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:51,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:51,269 INFO L748 eck$LassoCheckResult]: Stem: 107370#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 107371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 107473#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 107474#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 107218#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 107219#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 107484#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 107436#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 107437#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 107467#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 107446#L526 assume !(0 == ~M_E~0); 107447#L526-2 assume !(0 == ~T1_E~0); 107486#L531-1 assume !(0 == ~T2_E~0); 107432#L536-1 assume !(0 == ~T3_E~0); 107433#L541-1 assume !(0 == ~T4_E~0); 107428#L546-1 assume !(0 == ~E_M~0); 107429#L551-1 assume !(0 == ~E_1~0); 107405#L556-1 assume !(0 == ~E_2~0); 107406#L561-1 assume !(0 == ~E_3~0); 107415#L566-1 assume !(0 == ~E_4~0); 107416#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 107410#L262 assume !(1 == ~m_pc~0); 107411#L262-2 is_master_triggered_~__retres1~0#1 := 0; 107600#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 107342#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 107343#L649 assume !(0 != activate_threads_~tmp~1#1); 107597#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 107351#L281 assume !(1 == ~t1_pc~0); 107352#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 107269#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 107183#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 107184#L657 assume !(0 != activate_threads_~tmp___0~0#1); 107328#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 107418#L300 assume !(1 == ~t2_pc~0); 107419#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 107523#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 107477#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 107440#L665 assume !(0 != activate_threads_~tmp___1~0#1); 107196#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 107197#L319 assume !(1 == ~t3_pc~0); 107153#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 107154#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 107140#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 107141#L673 assume !(0 != activate_threads_~tmp___2~0#1); 107173#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 107174#L338 assume !(1 == ~t4_pc~0); 107243#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 107244#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 107249#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 107250#L681 assume !(0 != activate_threads_~tmp___3~0#1); 107122#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107123#L584 assume !(1 == ~M_E~0); 107325#L584-2 assume !(1 == ~T1_E~0); 107284#L589-1 assume !(1 == ~T2_E~0); 107285#L594-1 assume !(1 == ~T3_E~0); 107374#L599-1 assume !(1 == ~T4_E~0); 107152#L604-1 assume !(1 == ~E_M~0); 107138#L609-1 assume !(1 == ~E_1~0); 107139#L614-1 assume !(1 == ~E_2~0); 107258#L619-1 assume !(1 == ~E_3~0); 107344#L624-1 assume !(1 == ~E_4~0); 107438#L629-1 assume { :end_inline_reset_delta_events } true; 107606#L815-2 [2023-11-06 22:16:51,269 INFO L750 eck$LassoCheckResult]: Loop: 107606#L815-2 assume !false; 109623#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 108647#L501-1 assume !false; 109622#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109621#L398 assume !(0 == ~m_st~0); 109618#L402 assume !(0 == ~t1_st~0); 109619#L406 assume !(0 == ~t2_st~0); 109620#L410 assume !(0 == ~t3_st~0); 109616#L414 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5#1 := 0; 109617#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109276#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 109277#L440 assume !(0 != eval_~tmp~0#1); 109706#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 109705#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 109704#L526-3 assume !(0 == ~M_E~0); 109703#L526-5 assume !(0 == ~T1_E~0); 109702#L531-3 assume !(0 == ~T2_E~0); 109701#L536-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 109700#L541-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 109699#L546-3 assume 0 == ~E_M~0;~E_M~0 := 1; 109698#L551-3 assume !(0 == ~E_1~0); 109697#L556-3 assume !(0 == ~E_2~0); 109696#L561-3 assume 0 == ~E_3~0;~E_3~0 := 1; 109695#L566-3 assume !(0 == ~E_4~0); 109694#L571-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109693#L262-18 assume !(1 == ~m_pc~0); 109692#L262-20 is_master_triggered_~__retres1~0#1 := 0; 109691#L273-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109690#is_master_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 109689#L649-18 assume !(0 != activate_threads_~tmp~1#1); 109688#L649-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109687#L281-18 assume !(1 == ~t1_pc~0); 109685#L281-20 is_transmit1_triggered_~__retres1~1#1 := 0; 109684#L292-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109683#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 109682#L657-18 assume !(0 != activate_threads_~tmp___0~0#1); 109681#L657-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109680#L300-18 assume !(1 == ~t2_pc~0); 109430#L300-20 is_transmit2_triggered_~__retres1~2#1 := 0; 109679#L311-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109678#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109677#L665-18 assume !(0 != activate_threads_~tmp___1~0#1); 109676#L665-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109675#L319-18 assume 1 == ~t3_pc~0; 109673#L320-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 109672#L330-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109671#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109670#L673-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 109669#L673-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109668#L338-18 assume !(1 == ~t4_pc~0); 109667#L338-20 is_transmit4_triggered_~__retres1~4#1 := 0; 109666#L349-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109665#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109664#L681-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 109663#L681-20 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109662#L584-3 assume !(1 == ~M_E~0); 109546#L584-5 assume !(1 == ~T1_E~0); 109661#L589-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 109660#L594-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109659#L599-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109658#L604-3 assume 1 == ~E_M~0;~E_M~0 := 2; 109657#L609-3 assume !(1 == ~E_1~0); 109655#L614-3 assume !(1 == ~E_2~0); 109653#L619-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109651#L624-3 assume 1 == ~E_4~0;~E_4~0 := 2; 109649#L629-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109645#L398-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 109641#L425-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109639#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 109637#L834 assume !(0 == start_simulation_~tmp~3#1); 109635#L834-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 109633#L398-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 109629#L425-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 109628#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 109627#L789 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 109626#L796 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 109625#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 109624#L847 assume !(0 != start_simulation_~tmp___0~1#1); 107606#L815-2 [2023-11-06 22:16:51,270 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:51,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1546408329, now seen corresponding path program 4 times [2023-11-06 22:16:51,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:51,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308884879] [2023-11-06 22:16:51,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:51,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:51,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,293 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:51,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,321 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:51,323 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:51,323 INFO L85 PathProgramCache]: Analyzing trace with hash -2045914843, now seen corresponding path program 1 times [2023-11-06 22:16:51,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:51,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144267514] [2023-11-06 22:16:51,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:51,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:51,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:51,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:51,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:51,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144267514] [2023-11-06 22:16:51,368 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144267514] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:51,368 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:51,368 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:51,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300169274] [2023-11-06 22:16:51,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:51,369 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:16:51,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:51,370 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:51,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:51,370 INFO L87 Difference]: Start difference. First operand 4760 states and 6442 transitions. cyclomatic complexity: 1686 Second operand has 3 states, 3 states have (on average 26.0) internal successors, (78), 3 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:51,451 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:51,451 INFO L93 Difference]: Finished difference Result 7462 states and 9945 transitions. [2023-11-06 22:16:51,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7462 states and 9945 transitions. [2023-11-06 22:16:51,622 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7364 [2023-11-06 22:16:51,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7462 states to 7462 states and 9945 transitions. [2023-11-06 22:16:51,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7462 [2023-11-06 22:16:51,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7462 [2023-11-06 22:16:51,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7462 states and 9945 transitions. [2023-11-06 22:16:51,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:51,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7462 states and 9945 transitions. [2023-11-06 22:16:51,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7462 states and 9945 transitions. [2023-11-06 22:16:51,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7462 to 7206. [2023-11-06 22:16:51,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7206 states, 7206 states have (on average 1.3340271995559256) internal successors, (9613), 7205 states have internal predecessors, (9613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:51,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7206 states to 7206 states and 9613 transitions. [2023-11-06 22:16:51,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7206 states and 9613 transitions. [2023-11-06 22:16:51,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:51,838 INFO L428 stractBuchiCegarLoop]: Abstraction has 7206 states and 9613 transitions. [2023-11-06 22:16:51,838 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:16:51,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7206 states and 9613 transitions. [2023-11-06 22:16:51,870 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7108 [2023-11-06 22:16:51,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:51,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:51,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:51,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:51,872 INFO L748 eck$LassoCheckResult]: Stem: 119605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 119606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 119708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 119709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 119447#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 119448#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 119721#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 119670#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 119671#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 119704#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 119683#L526 assume !(0 == ~M_E~0); 119684#L526-2 assume !(0 == ~T1_E~0); 119723#L531-1 assume !(0 == ~T2_E~0); 119666#L536-1 assume !(0 == ~T3_E~0); 119667#L541-1 assume !(0 == ~T4_E~0); 119662#L546-1 assume !(0 == ~E_M~0); 119663#L551-1 assume !(0 == ~E_1~0); 119638#L556-1 assume !(0 == ~E_2~0); 119639#L561-1 assume !(0 == ~E_3~0); 119648#L566-1 assume !(0 == ~E_4~0); 119649#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119643#L262 assume !(1 == ~m_pc~0); 119644#L262-2 is_master_triggered_~__retres1~0#1 := 0; 119837#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119575#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119576#L649 assume !(0 != activate_threads_~tmp~1#1); 119836#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119584#L281 assume !(1 == ~t1_pc~0); 119585#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 119500#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119411#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119412#L657 assume !(0 != activate_threads_~tmp___0~0#1); 119558#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119651#L300 assume !(1 == ~t2_pc~0); 119652#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 119760#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119674#L665 assume !(0 != activate_threads_~tmp___1~0#1); 119424#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119425#L319 assume !(1 == ~t3_pc~0); 119381#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 119382#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119368#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119369#L673 assume !(0 != activate_threads_~tmp___2~0#1); 119401#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119402#L338 assume !(1 == ~t4_pc~0); 119471#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 119472#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119478#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119479#L681 assume !(0 != activate_threads_~tmp___3~0#1); 119350#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119351#L584 assume !(1 == ~M_E~0); 119555#L584-2 assume !(1 == ~T1_E~0); 119515#L589-1 assume !(1 == ~T2_E~0); 119516#L594-1 assume !(1 == ~T3_E~0); 119611#L599-1 assume !(1 == ~T4_E~0); 119380#L604-1 assume !(1 == ~E_M~0); 119366#L609-1 assume !(1 == ~E_1~0); 119367#L614-1 assume !(1 == ~E_2~0); 119488#L619-1 assume !(1 == ~E_3~0); 119577#L624-1 assume !(1 == ~E_4~0); 119672#L629-1 assume { :end_inline_reset_delta_events } true; 119842#L815-2 assume !false; 120663#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 120664#L501-1 [2023-11-06 22:16:51,873 INFO L750 eck$LassoCheckResult]: Loop: 120664#L501-1 assume !false; 120657#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 120658#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 120968#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 120967#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 120965#L440 assume 0 != eval_~tmp~0#1; 120953#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 120951#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 120949#L448-2 havoc eval_~tmp_ndt_1~0#1; 120950#L445-1 assume !(0 == ~t1_st~0); 120920#L459-1 assume !(0 == ~t2_st~0); 120919#L473-1 assume !(0 == ~t3_st~0); 120666#L487-1 assume !(0 == ~t4_st~0); 120664#L501-1 [2023-11-06 22:16:51,876 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:51,877 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 1 times [2023-11-06 22:16:51,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:51,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1715041951] [2023-11-06 22:16:51,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:51,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:51,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,892 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:51,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,921 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:51,922 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:51,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 1 times [2023-11-06 22:16:51,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:51,923 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466899663] [2023-11-06 22:16:51,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:51,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:51,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,930 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:51,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:51,935 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:51,937 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:51,937 INFO L85 PathProgramCache]: Analyzing trace with hash -1780226006, now seen corresponding path program 1 times [2023-11-06 22:16:51,937 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:51,938 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1942912026] [2023-11-06 22:16:51,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:51,938 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:51,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:51,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:51,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:51,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1942912026] [2023-11-06 22:16:52,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1942912026] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:52,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:52,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:52,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318414672] [2023-11-06 22:16:52,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:52,137 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:52,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:52,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:52,138 INFO L87 Difference]: Start difference. First operand 7206 states and 9613 transitions. cyclomatic complexity: 2413 Second operand has 3 states, 3 states have (on average 25.666666666666668) internal successors, (77), 3 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:52,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:52,254 INFO L93 Difference]: Finished difference Result 11656 states and 15415 transitions. [2023-11-06 22:16:52,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11656 states and 15415 transitions. [2023-11-06 22:16:52,461 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11466 [2023-11-06 22:16:52,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11656 states to 11656 states and 15415 transitions. [2023-11-06 22:16:52,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11656 [2023-11-06 22:16:52,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11656 [2023-11-06 22:16:52,516 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11656 states and 15415 transitions. [2023-11-06 22:16:52,525 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:52,525 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11656 states and 15415 transitions. [2023-11-06 22:16:52,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11656 states and 15415 transitions. [2023-11-06 22:16:52,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11656 to 11656. [2023-11-06 22:16:52,683 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11656 states, 11656 states have (on average 1.3224948524365134) internal successors, (15415), 11655 states have internal predecessors, (15415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:52,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11656 states to 11656 states and 15415 transitions. [2023-11-06 22:16:52,717 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11656 states and 15415 transitions. [2023-11-06 22:16:52,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:52,718 INFO L428 stractBuchiCegarLoop]: Abstraction has 11656 states and 15415 transitions. [2023-11-06 22:16:52,719 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:16:52,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11656 states and 15415 transitions. [2023-11-06 22:16:52,862 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11466 [2023-11-06 22:16:52,863 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:52,863 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:52,864 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:52,864 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:52,864 INFO L748 eck$LassoCheckResult]: Stem: 138475#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 138476#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 138583#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 138584#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 138317#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 138318#L365-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 138701#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 138541#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 138542#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 138577#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 138578#L526 assume !(0 == ~M_E~0); 138759#L526-2 assume !(0 == ~T1_E~0); 138760#L531-1 assume !(0 == ~T2_E~0); 138537#L536-1 assume !(0 == ~T3_E~0); 138538#L541-1 assume !(0 == ~T4_E~0); 138533#L546-1 assume !(0 == ~E_M~0); 138534#L551-1 assume !(0 == ~E_1~0); 138510#L556-1 assume !(0 == ~E_2~0); 138511#L561-1 assume !(0 == ~E_3~0); 138521#L566-1 assume !(0 == ~E_4~0); 138522#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138515#L262 assume !(1 == ~m_pc~0); 138516#L262-2 is_master_triggered_~__retres1~0#1 := 0; 138732#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138733#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 138730#L649 assume !(0 != activate_threads_~tmp~1#1); 138731#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138455#L281 assume !(1 == ~t1_pc~0); 138456#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 138368#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138369#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138427#L657 assume !(0 != activate_threads_~tmp___0~0#1); 138428#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138524#L300 assume !(1 == ~t2_pc~0); 138525#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 138636#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138637#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138545#L665 assume !(0 != activate_threads_~tmp___1~0#1); 138546#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138772#L319 assume !(1 == ~t3_pc~0); 138251#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 138252#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138238#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138239#L673 assume !(0 != activate_threads_~tmp___2~0#1); 138271#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138272#L338 assume !(1 == ~t4_pc~0); 138341#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 138342#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138350#L681 assume !(0 != activate_threads_~tmp___3~0#1); 138220#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138221#L584 assume !(1 == ~M_E~0); 138424#L584-2 assume !(1 == ~T1_E~0); 138385#L589-1 assume !(1 == ~T2_E~0); 138386#L594-1 assume !(1 == ~T3_E~0); 138481#L599-1 assume !(1 == ~T4_E~0); 138250#L604-1 assume !(1 == ~E_M~0); 138236#L609-1 assume !(1 == ~E_1~0); 138237#L614-1 assume !(1 == ~E_2~0); 138357#L619-1 assume !(1 == ~E_3~0); 138447#L624-1 assume !(1 == ~E_4~0); 138543#L629-1 assume { :end_inline_reset_delta_events } true; 138967#L815-2 assume !false; 138968#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 138960#L501-1 [2023-11-06 22:16:52,864 INFO L750 eck$LassoCheckResult]: Loop: 138960#L501-1 assume !false; 138961#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 138955#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 138957#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 138951#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 138952#L440 assume 0 != eval_~tmp~0#1; 138946#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 138947#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 138993#L448-2 havoc eval_~tmp_ndt_1~0#1; 138991#L445-1 assume !(0 == ~t1_st~0); 138990#L459-1 assume !(0 == ~t2_st~0); 138974#L473-1 assume !(0 == ~t3_st~0); 138973#L487-1 assume !(0 == ~t4_st~0); 138960#L501-1 [2023-11-06 22:16:52,865 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:52,865 INFO L85 PathProgramCache]: Analyzing trace with hash 600428717, now seen corresponding path program 1 times [2023-11-06 22:16:52,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:52,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1261712521] [2023-11-06 22:16:52,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:52,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:52,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:52,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:52,920 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:52,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1261712521] [2023-11-06 22:16:52,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1261712521] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:52,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:52,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:52,921 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [96667424] [2023-11-06 22:16:52,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:52,921 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:16:52,922 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:52,922 INFO L85 PathProgramCache]: Analyzing trace with hash -1697797356, now seen corresponding path program 2 times [2023-11-06 22:16:52,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:52,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377713151] [2023-11-06 22:16:52,923 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:52,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:52,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:52,940 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:52,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:52,944 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:53,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:53,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:53,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:53,050 INFO L87 Difference]: Start difference. First operand 11656 states and 15415 transitions. cyclomatic complexity: 3765 Second operand has 3 states, 3 states have (on average 21.333333333333332) internal successors, (64), 3 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:53,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:53,106 INFO L93 Difference]: Finished difference Result 11596 states and 15337 transitions. [2023-11-06 22:16:53,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11596 states and 15337 transitions. [2023-11-06 22:16:53,164 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11466 [2023-11-06 22:16:53,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11596 states to 11596 states and 15337 transitions. [2023-11-06 22:16:53,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11596 [2023-11-06 22:16:53,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11596 [2023-11-06 22:16:53,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11596 states and 15337 transitions. [2023-11-06 22:16:53,232 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:53,232 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11596 states and 15337 transitions. [2023-11-06 22:16:53,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11596 states and 15337 transitions. [2023-11-06 22:16:53,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11596 to 11596. [2023-11-06 22:16:53,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11596 states, 11596 states have (on average 1.3226112452569851) internal successors, (15337), 11595 states have internal predecessors, (15337), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:53,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11596 states to 11596 states and 15337 transitions. [2023-11-06 22:16:53,566 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11596 states and 15337 transitions. [2023-11-06 22:16:53,567 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:53,568 INFO L428 stractBuchiCegarLoop]: Abstraction has 11596 states and 15337 transitions. [2023-11-06 22:16:53,568 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:16:53,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11596 states and 15337 transitions. [2023-11-06 22:16:53,600 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 11466 [2023-11-06 22:16:53,600 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:53,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:53,601 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:53,601 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:53,602 INFO L748 eck$LassoCheckResult]: Stem: 161737#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 161738#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 161838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 161839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 161573#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 161574#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 161850#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 161801#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161802#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 161830#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161811#L526 assume !(0 == ~M_E~0); 161812#L526-2 assume !(0 == ~T1_E~0); 161853#L531-1 assume !(0 == ~T2_E~0); 161797#L536-1 assume !(0 == ~T3_E~0); 161798#L541-1 assume !(0 == ~T4_E~0); 161793#L546-1 assume !(0 == ~E_M~0); 161794#L551-1 assume !(0 == ~E_1~0); 161770#L556-1 assume !(0 == ~E_2~0); 161771#L561-1 assume !(0 == ~E_3~0); 161781#L566-1 assume !(0 == ~E_4~0); 161782#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 161775#L262 assume !(1 == ~m_pc~0); 161776#L262-2 is_master_triggered_~__retres1~0#1 := 0; 161974#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161706#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 161707#L649 assume !(0 != activate_threads_~tmp~1#1); 161969#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 161715#L281 assume !(1 == ~t1_pc~0); 161716#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 161624#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 161539#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161540#L657 assume !(0 != activate_threads_~tmp___0~0#1); 161685#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 161784#L300 assume !(1 == ~t2_pc~0); 161785#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 161893#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 161842#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 161805#L665 assume !(0 != activate_threads_~tmp___1~0#1); 161552#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 161553#L319 assume !(1 == ~t3_pc~0); 161509#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 161510#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 161496#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 161497#L673 assume !(0 != activate_threads_~tmp___2~0#1); 161529#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 161530#L338 assume !(1 == ~t4_pc~0); 161597#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 161598#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 161603#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 161604#L681 assume !(0 != activate_threads_~tmp___3~0#1); 161478#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161479#L584 assume !(1 == ~M_E~0); 161682#L584-2 assume !(1 == ~T1_E~0); 161640#L589-1 assume !(1 == ~T2_E~0); 161641#L594-1 assume !(1 == ~T3_E~0); 161741#L599-1 assume !(1 == ~T4_E~0); 161508#L604-1 assume !(1 == ~E_M~0); 161494#L609-1 assume !(1 == ~E_1~0); 161495#L614-1 assume !(1 == ~E_2~0); 161614#L619-1 assume !(1 == ~E_3~0); 161708#L624-1 assume !(1 == ~E_4~0); 161803#L629-1 assume { :end_inline_reset_delta_events } true; 161983#L815-2 assume !false; 167842#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 167840#L501-1 [2023-11-06 22:16:53,602 INFO L750 eck$LassoCheckResult]: Loop: 167840#L501-1 assume !false; 167838#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 167836#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 167834#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 167832#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 167830#L440 assume 0 != eval_~tmp~0#1; 167827#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 167824#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 167821#L448-2 havoc eval_~tmp_ndt_1~0#1; 167819#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 167791#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 167673#L462-2 havoc eval_~tmp_ndt_2~0#1; 167671#L459-1 assume !(0 == ~t2_st~0); 167672#L473-1 assume !(0 == ~t3_st~0); 167844#L487-1 assume !(0 == ~t4_st~0); 167840#L501-1 [2023-11-06 22:16:53,602 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:53,603 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 2 times [2023-11-06 22:16:53,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:53,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447387261] [2023-11-06 22:16:53,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:53,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:53,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:53,620 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:53,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:53,638 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:53,639 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:53,639 INFO L85 PathProgramCache]: Analyzing trace with hash 201422285, now seen corresponding path program 1 times [2023-11-06 22:16:53,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:53,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873017516] [2023-11-06 22:16:53,639 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:53,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:53,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:53,644 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:53,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:53,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:53,651 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:53,651 INFO L85 PathProgramCache]: Analyzing trace with hash -1703099037, now seen corresponding path program 1 times [2023-11-06 22:16:53,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:53,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039651464] [2023-11-06 22:16:53,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:53,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:53,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:53,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:53,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:53,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1039651464] [2023-11-06 22:16:53,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1039651464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:53,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:53,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:53,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2043570144] [2023-11-06 22:16:53,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:53,790 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:53,791 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:53,791 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:53,791 INFO L87 Difference]: Start difference. First operand 11596 states and 15337 transitions. cyclomatic complexity: 3747 Second operand has 3 states, 3 states have (on average 26.333333333333332) internal successors, (79), 3 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:54,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:54,042 INFO L93 Difference]: Finished difference Result 21490 states and 28295 transitions. [2023-11-06 22:16:54,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21490 states and 28295 transitions. [2023-11-06 22:16:54,175 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 21296 [2023-11-06 22:16:54,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21490 states to 21490 states and 28295 transitions. [2023-11-06 22:16:54,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21490 [2023-11-06 22:16:54,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21490 [2023-11-06 22:16:54,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21490 states and 28295 transitions. [2023-11-06 22:16:54,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:54,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21490 states and 28295 transitions. [2023-11-06 22:16:54,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21490 states and 28295 transitions. [2023-11-06 22:16:54,699 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21490 to 21000. [2023-11-06 22:16:54,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21000 states, 21000 states have (on average 1.3173809523809523) internal successors, (27665), 20999 states have internal predecessors, (27665), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:54,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21000 states to 21000 states and 27665 transitions. [2023-11-06 22:16:54,779 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21000 states and 27665 transitions. [2023-11-06 22:16:54,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:54,781 INFO L428 stractBuchiCegarLoop]: Abstraction has 21000 states and 27665 transitions. [2023-11-06 22:16:54,781 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:16:54,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21000 states and 27665 transitions. [2023-11-06 22:16:55,007 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20806 [2023-11-06 22:16:55,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:55,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:55,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:55,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:55,020 INFO L748 eck$LassoCheckResult]: Stem: 194826#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 194827#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 194932#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 194933#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 194668#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 194669#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 194946#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194893#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194894#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 194924#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 194903#L526 assume !(0 == ~M_E~0); 194904#L526-2 assume !(0 == ~T1_E~0); 194948#L531-1 assume !(0 == ~T2_E~0); 194889#L536-1 assume !(0 == ~T3_E~0); 194890#L541-1 assume !(0 == ~T4_E~0); 194885#L546-1 assume !(0 == ~E_M~0); 194886#L551-1 assume !(0 == ~E_1~0); 194861#L556-1 assume !(0 == ~E_2~0); 194862#L561-1 assume !(0 == ~E_3~0); 194872#L566-1 assume !(0 == ~E_4~0); 194873#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 194866#L262 assume !(1 == ~m_pc~0); 194867#L262-2 is_master_triggered_~__retres1~0#1 := 0; 195085#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 194795#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 194796#L649 assume !(0 != activate_threads_~tmp~1#1); 195080#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 194804#L281 assume !(1 == ~t1_pc~0); 194805#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 194719#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 194633#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 194634#L657 assume !(0 != activate_threads_~tmp___0~0#1); 194777#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 194876#L300 assume !(1 == ~t2_pc~0); 194877#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 194988#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 194936#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 194897#L665 assume !(0 != activate_threads_~tmp___1~0#1); 194646#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 194647#L319 assume !(1 == ~t3_pc~0); 194603#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 194604#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 194590#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 194591#L673 assume !(0 != activate_threads_~tmp___2~0#1); 194623#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 194624#L338 assume !(1 == ~t4_pc~0); 194692#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 194693#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 194698#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 194699#L681 assume !(0 != activate_threads_~tmp___3~0#1); 194572#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194573#L584 assume !(1 == ~M_E~0); 194774#L584-2 assume !(1 == ~T1_E~0); 194733#L589-1 assume !(1 == ~T2_E~0); 194734#L594-1 assume !(1 == ~T3_E~0); 194830#L599-1 assume !(1 == ~T4_E~0); 194602#L604-1 assume !(1 == ~E_M~0); 194588#L609-1 assume !(1 == ~E_1~0); 194589#L614-1 assume !(1 == ~E_2~0); 194709#L619-1 assume !(1 == ~E_3~0); 194797#L624-1 assume !(1 == ~E_4~0); 194895#L629-1 assume { :end_inline_reset_delta_events } true; 195092#L815-2 assume !false; 203760#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 203758#L501-1 [2023-11-06 22:16:55,020 INFO L750 eck$LassoCheckResult]: Loop: 203758#L501-1 assume !false; 203756#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 203753#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 203751#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 203749#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 203746#L440 assume 0 != eval_~tmp~0#1; 203743#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 203740#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 203738#L448-2 havoc eval_~tmp_ndt_1~0#1; 203736#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 203733#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 203731#L462-2 havoc eval_~tmp_ndt_2~0#1; 203729#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 202221#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 203727#L476-2 havoc eval_~tmp_ndt_3~0#1; 203815#L473-1 assume !(0 == ~t3_st~0); 203814#L487-1 assume !(0 == ~t4_st~0); 203758#L501-1 [2023-11-06 22:16:55,021 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:55,021 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 3 times [2023-11-06 22:16:55,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:55,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560878274] [2023-11-06 22:16:55,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:55,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:55,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:55,035 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:55,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:55,058 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:55,058 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:55,059 INFO L85 PathProgramCache]: Analyzing trace with hash 145011028, now seen corresponding path program 1 times [2023-11-06 22:16:55,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:55,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876641318] [2023-11-06 22:16:55,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:55,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:55,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:55,064 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:55,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:55,069 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:55,070 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:55,070 INFO L85 PathProgramCache]: Analyzing trace with hash -443911318, now seen corresponding path program 1 times [2023-11-06 22:16:55,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:55,070 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65367228] [2023-11-06 22:16:55,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:55,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:55,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:55,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:55,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:55,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65367228] [2023-11-06 22:16:55,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65367228] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:55,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:55,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:16:55,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858163585] [2023-11-06 22:16:55,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:55,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:55,234 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:55,234 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:55,235 INFO L87 Difference]: Start difference. First operand 21000 states and 27665 transitions. cyclomatic complexity: 6671 Second operand has 3 states, 3 states have (on average 27.0) internal successors, (81), 3 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:55,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:55,428 INFO L93 Difference]: Finished difference Result 37186 states and 48815 transitions. [2023-11-06 22:16:55,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37186 states and 48815 transitions. [2023-11-06 22:16:55,885 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 36864 [2023-11-06 22:16:56,015 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37186 states to 37186 states and 48815 transitions. [2023-11-06 22:16:56,015 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37186 [2023-11-06 22:16:56,040 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37186 [2023-11-06 22:16:56,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37186 states and 48815 transitions. [2023-11-06 22:16:56,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:56,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37186 states and 48815 transitions. [2023-11-06 22:16:56,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37186 states and 48815 transitions. [2023-11-06 22:16:56,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37186 to 36010. [2023-11-06 22:16:56,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36010 states, 36010 states have (on average 1.3167175784504304) internal successors, (47415), 36009 states have internal predecessors, (47415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:56,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36010 states to 36010 states and 47415 transitions. [2023-11-06 22:16:56,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36010 states and 47415 transitions. [2023-11-06 22:16:56,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:56,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 36010 states and 47415 transitions. [2023-11-06 22:16:56,901 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:16:56,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36010 states and 47415 transitions. [2023-11-06 22:16:57,253 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 35688 [2023-11-06 22:16:57,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:57,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:57,255 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:57,255 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:57,255 INFO L748 eck$LassoCheckResult]: Stem: 253027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 253028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 253134#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253135#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252862#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 252863#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253147#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253095#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253096#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253126#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253106#L526 assume !(0 == ~M_E~0); 253107#L526-2 assume !(0 == ~T1_E~0); 253149#L531-1 assume !(0 == ~T2_E~0); 253091#L536-1 assume !(0 == ~T3_E~0); 253092#L541-1 assume !(0 == ~T4_E~0); 253087#L546-1 assume !(0 == ~E_M~0); 253088#L551-1 assume !(0 == ~E_1~0); 253062#L556-1 assume !(0 == ~E_2~0); 253063#L561-1 assume !(0 == ~E_3~0); 253073#L566-1 assume !(0 == ~E_4~0); 253074#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253067#L262 assume !(1 == ~m_pc~0); 253068#L262-2 is_master_triggered_~__retres1~0#1 := 0; 253287#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252994#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 252995#L649 assume !(0 != activate_threads_~tmp~1#1); 253283#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253004#L281 assume !(1 == ~t1_pc~0); 253005#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252916#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252828#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252829#L657 assume !(0 != activate_threads_~tmp___0~0#1); 252973#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253077#L300 assume !(1 == ~t2_pc~0); 253078#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 253191#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253100#L665 assume !(0 != activate_threads_~tmp___1~0#1); 252841#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252842#L319 assume !(1 == ~t3_pc~0); 252797#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 252798#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 252785#L673 assume !(0 != activate_threads_~tmp___2~0#1); 252818#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252819#L338 assume !(1 == ~t4_pc~0); 252887#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 252888#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252893#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252894#L681 assume !(0 != activate_threads_~tmp___3~0#1); 252766#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252767#L584 assume !(1 == ~M_E~0); 252970#L584-2 assume !(1 == ~T1_E~0); 252930#L589-1 assume !(1 == ~T2_E~0); 252931#L594-1 assume !(1 == ~T3_E~0); 253031#L599-1 assume !(1 == ~T4_E~0); 252796#L604-1 assume !(1 == ~E_M~0); 252782#L609-1 assume !(1 == ~E_1~0); 252783#L614-1 assume !(1 == ~E_2~0); 252905#L619-1 assume !(1 == ~E_3~0); 252996#L624-1 assume !(1 == ~E_4~0); 253097#L629-1 assume { :end_inline_reset_delta_events } true; 253300#L815-2 assume !false; 260969#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 260966#L501-1 [2023-11-06 22:16:57,256 INFO L750 eck$LassoCheckResult]: Loop: 260966#L501-1 assume !false; 260964#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 260960#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 260957#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 260954#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 260949#L440 assume 0 != eval_~tmp~0#1; 260945#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 260941#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 260937#L448-2 havoc eval_~tmp_ndt_1~0#1; 260934#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 260920#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 260931#L462-2 havoc eval_~tmp_ndt_2~0#1; 260061#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 260056#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 260057#L476-2 havoc eval_~tmp_ndt_3~0#1; 260981#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 260864#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 260975#L490-2 havoc eval_~tmp_ndt_4~0#1; 260971#L487-1 assume !(0 == ~t4_st~0); 260966#L501-1 [2023-11-06 22:16:57,256 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:57,256 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 4 times [2023-11-06 22:16:57,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:57,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543362605] [2023-11-06 22:16:57,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:57,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:57,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:57,270 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:57,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:57,298 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:57,298 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:57,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1911902797, now seen corresponding path program 1 times [2023-11-06 22:16:57,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:57,301 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293167384] [2023-11-06 22:16:57,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:57,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:57,305 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:57,306 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:57,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:57,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:57,312 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:57,312 INFO L85 PathProgramCache]: Analyzing trace with hash -1401755933, now seen corresponding path program 1 times [2023-11-06 22:16:57,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:57,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898428665] [2023-11-06 22:16:57,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:57,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:57,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:16:57,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:16:57,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:16:57,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1898428665] [2023-11-06 22:16:57,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1898428665] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:16:57,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:16:57,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:16:57,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320800781] [2023-11-06 22:16:57,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:16:57,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:16:57,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:16:57,474 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:16:57,474 INFO L87 Difference]: Start difference. First operand 36010 states and 47415 transitions. cyclomatic complexity: 11411 Second operand has 3 states, 2 states have (on average 41.5) internal successors, (83), 3 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:57,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:16:57,691 INFO L93 Difference]: Finished difference Result 41120 states and 53939 transitions. [2023-11-06 22:16:57,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41120 states and 53939 transitions. [2023-11-06 22:16:57,891 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40878 [2023-11-06 22:16:58,294 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41120 states to 41120 states and 53939 transitions. [2023-11-06 22:16:58,295 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41120 [2023-11-06 22:16:58,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41120 [2023-11-06 22:16:58,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41120 states and 53939 transitions. [2023-11-06 22:16:58,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:16:58,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41120 states and 53939 transitions. [2023-11-06 22:16:58,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41120 states and 53939 transitions. [2023-11-06 22:16:58,922 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41120 to 40672. [2023-11-06 22:16:58,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40672 states, 40672 states have (on average 1.3151799763965382) internal successors, (53491), 40671 states have internal predecessors, (53491), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:16:59,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40672 states to 40672 states and 53491 transitions. [2023-11-06 22:16:59,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40672 states and 53491 transitions. [2023-11-06 22:16:59,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:16:59,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 40672 states and 53491 transitions. [2023-11-06 22:16:59,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:16:59,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40672 states and 53491 transitions. [2023-11-06 22:16:59,229 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40430 [2023-11-06 22:16:59,229 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:16:59,229 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:16:59,230 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:59,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:16:59,232 INFO L748 eck$LassoCheckResult]: Stem: 330162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~token~0 := 0;~local~0 := 0; 330163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~6#1;havoc main_~__retres1~6#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 330269#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 330270#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 330002#L365 assume 1 == ~m_i~0;~m_st~0 := 0; 330003#L365-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 330285#L370-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 330231#L375-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 330232#L380-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 330262#L385-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 330242#L526 assume !(0 == ~M_E~0); 330243#L526-2 assume !(0 == ~T1_E~0); 330288#L531-1 assume !(0 == ~T2_E~0); 330227#L536-1 assume !(0 == ~T3_E~0); 330228#L541-1 assume !(0 == ~T4_E~0); 330223#L546-1 assume !(0 == ~E_M~0); 330224#L551-1 assume !(0 == ~E_1~0); 330197#L556-1 assume !(0 == ~E_2~0); 330198#L561-1 assume !(0 == ~E_3~0); 330207#L566-1 assume !(0 == ~E_4~0); 330208#L571-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 330202#L262 assume !(1 == ~m_pc~0); 330203#L262-2 is_master_triggered_~__retres1~0#1 := 0; 330431#L273 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 330132#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 330133#L649 assume !(0 != activate_threads_~tmp~1#1); 330429#L649-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 330142#L281 assume !(1 == ~t1_pc~0); 330143#L281-2 is_transmit1_triggered_~__retres1~1#1 := 0; 330054#L292 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 329968#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 329969#L657 assume !(0 != activate_threads_~tmp___0~0#1); 330114#L657-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 330211#L300 assume !(1 == ~t2_pc~0); 330212#L300-2 is_transmit2_triggered_~__retres1~2#1 := 0; 330335#L311 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 330274#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 330236#L665 assume !(0 != activate_threads_~tmp___1~0#1); 329981#L665-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 329982#L319 assume !(1 == ~t3_pc~0); 329935#L319-2 is_transmit3_triggered_~__retres1~3#1 := 0; 329936#L330 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 329922#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 329923#L673 assume !(0 != activate_threads_~tmp___2~0#1); 329957#L673-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 329958#L338 assume !(1 == ~t4_pc~0); 330028#L338-2 is_transmit4_triggered_~__retres1~4#1 := 0; 330029#L349 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 330036#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330037#L681 assume !(0 != activate_threads_~tmp___3~0#1); 329904#L681-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 329905#L584 assume !(1 == ~M_E~0); 330111#L584-2 assume !(1 == ~T1_E~0); 330068#L589-1 assume !(1 == ~T2_E~0); 330069#L594-1 assume !(1 == ~T3_E~0); 330166#L599-1 assume !(1 == ~T4_E~0); 329934#L604-1 assume !(1 == ~E_M~0); 329920#L609-1 assume !(1 == ~E_1~0); 329921#L614-1 assume !(1 == ~E_2~0); 330044#L619-1 assume !(1 == ~E_3~0); 330134#L624-1 assume !(1 == ~E_4~0); 330233#L629-1 assume { :end_inline_reset_delta_events } true; 330440#L815-2 assume !false; 341570#L816 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 341568#L501-1 [2023-11-06 22:16:59,232 INFO L750 eck$LassoCheckResult]: Loop: 341568#L501-1 assume !false; 341566#L436 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;havoc exists_runnable_thread_~__retres1~5#1; 341563#L398 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5#1 := 1; 341561#L425 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~5#1; 341560#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~5#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 341558#L440 assume 0 != eval_~tmp~0#1; 341554#L440-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 341551#L448 assume !(0 != eval_~tmp_ndt_1~0#1); 341549#L448-2 havoc eval_~tmp_ndt_1~0#1; 341547#L445-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 340328#L462 assume !(0 != eval_~tmp_ndt_2~0#1); 341544#L462-2 havoc eval_~tmp_ndt_2~0#1; 341542#L459-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 340655#L476 assume !(0 != eval_~tmp_ndt_3~0#1); 341538#L476-2 havoc eval_~tmp_ndt_3~0#1; 341536#L473-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 341522#L490 assume !(0 != eval_~tmp_ndt_4~0#1); 341534#L490-2 havoc eval_~tmp_ndt_4~0#1; 341575#L487-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 341573#L504 assume !(0 != eval_~tmp_ndt_5~0#1); 341571#L504-2 havoc eval_~tmp_ndt_5~0#1; 341568#L501-1 [2023-11-06 22:16:59,233 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:59,233 INFO L85 PathProgramCache]: Analyzing trace with hash 39728939, now seen corresponding path program 5 times [2023-11-06 22:16:59,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:59,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199734070] [2023-11-06 22:16:59,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:59,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:59,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,248 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:59,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:59,273 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:59,273 INFO L85 PathProgramCache]: Analyzing trace with hash -907526252, now seen corresponding path program 1 times [2023-11-06 22:16:59,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:59,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891864413] [2023-11-06 22:16:59,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:59,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:59,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,280 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:59,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,286 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:16:59,286 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:16:59,287 INFO L85 PathProgramCache]: Analyzing trace with hash 1532167850, now seen corresponding path program 1 times [2023-11-06 22:16:59,287 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:16:59,287 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513343140] [2023-11-06 22:16:59,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:16:59,287 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:16:59,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,300 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:16:59,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:16:59,326 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:17:01,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:17:01,525 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:17:01,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:17:01,806 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:17:01 BoogieIcfgContainer [2023-11-06 22:17:01,806 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:17:01,807 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:17:01,807 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:17:01,807 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:17:01,808 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:16:42" (3/4) ... [2023-11-06 22:17:01,810 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:17:01,932 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:17:01,932 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:17:01,933 INFO L158 Benchmark]: Toolchain (without parser) took 21648.73ms. Allocated memory was 136.3MB in the beginning and 8.9GB in the end (delta: 8.7GB). Free memory was 97.1MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 729.9MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,933 INFO L158 Benchmark]: CDTParser took 0.26ms. Allocated memory is still 113.2MB. Free memory was 66.8MB in the beginning and 66.7MB in the end (delta: 158.8kB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:17:01,934 INFO L158 Benchmark]: CACSL2BoogieTranslator took 461.97ms. Allocated memory is still 136.3MB. Free memory was 96.9MB in the beginning and 81.3MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,934 INFO L158 Benchmark]: Boogie Procedure Inliner took 126.83ms. Allocated memory is still 136.3MB. Free memory was 81.3MB in the beginning and 77.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,935 INFO L158 Benchmark]: Boogie Preprocessor took 128.05ms. Allocated memory is still 136.3MB. Free memory was 77.1MB in the beginning and 72.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,936 INFO L158 Benchmark]: RCFGBuilder took 1610.08ms. Allocated memory was 136.3MB in the beginning and 186.6MB in the end (delta: 50.3MB). Free memory was 72.9MB in the beginning and 124.5MB in the end (delta: -51.6MB). Peak memory consumption was 29.0MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,936 INFO L158 Benchmark]: BuchiAutomizer took 19189.25ms. Allocated memory was 186.6MB in the beginning and 8.9GB in the end (delta: 8.7GB). Free memory was 124.5MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 696.7MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,937 INFO L158 Benchmark]: Witness Printer took 125.37ms. Allocated memory is still 8.9GB. Free memory was 8.1GB in the beginning and 8.1GB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-06 22:17:01,939 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.26ms. Allocated memory is still 113.2MB. Free memory was 66.8MB in the beginning and 66.7MB in the end (delta: 158.8kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 461.97ms. Allocated memory is still 136.3MB. Free memory was 96.9MB in the beginning and 81.3MB in the end (delta: 15.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 126.83ms. Allocated memory is still 136.3MB. Free memory was 81.3MB in the beginning and 77.1MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 128.05ms. Allocated memory is still 136.3MB. Free memory was 77.1MB in the beginning and 72.9MB in the end (delta: 4.2MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1610.08ms. Allocated memory was 136.3MB in the beginning and 186.6MB in the end (delta: 50.3MB). Free memory was 72.9MB in the beginning and 124.5MB in the end (delta: -51.6MB). Peak memory consumption was 29.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 19189.25ms. Allocated memory was 186.6MB in the beginning and 8.9GB in the end (delta: 8.7GB). Free memory was 124.5MB in the beginning and 8.1GB in the end (delta: -8.0GB). Peak memory consumption was 696.7MB. Max. memory is 16.1GB. * Witness Printer took 125.37ms. Allocated memory is still 8.9GB. Free memory was 8.1GB in the beginning and 8.1GB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (23 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.23 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 40672 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 18.9s and 24 iterations. TraceHistogramMax:1. Analysis of lassos took 6.6s. Construction of modules took 1.0s. Büchi inclusion checks took 9.7s. Highest rank in rank-based complementation 0. Minimization of det autom 23. Minimization of nondet autom 0. Automata minimization 4.2s AutomataMinimizationTime, 23 MinimizatonAttempts, 15634 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 2.9s Buchi closure took 0.1s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 16176 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 16176 mSDsluCounter, 30421 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 14109 mSDsCounter, 276 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 773 IncrementalHoareTripleChecker+Invalid, 1049 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 276 mSolverCounterUnsat, 16312 mSDtfsCounter, 773 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI14 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 435]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L445-L456] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L459-L470] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L473-L484] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L487-L498] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L501-L512] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 435]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int m_st ; [L30] int t1_st ; [L31] int t2_st ; [L32] int t3_st ; [L33] int t4_st ; [L34] int m_i ; [L35] int t1_i ; [L36] int t2_i ; [L37] int t3_i ; [L38] int t4_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int E_M = 2; [L45] int E_1 = 2; [L46] int E_2 = 2; [L47] int E_3 = 2; [L48] int E_4 = 2; [L55] int token ; [L57] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, token=0] [L860] int __retres1 ; [L864] CALL init_model() [L772] m_i = 1 [L773] t1_i = 1 [L774] t2_i = 1 [L775] t3_i = 1 [L776] t4_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L864] RET init_model() [L865] CALL start_simulation() [L801] int kernel_st ; [L802] int tmp ; [L803] int tmp___0 ; [L807] kernel_st = 0 [L808] FCALL update_channels() [L809] CALL init_threads() [L365] COND TRUE m_i == 1 [L366] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L370] COND TRUE t1_i == 1 [L371] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L375] COND TRUE t2_i == 1 [L376] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L380] COND TRUE t3_i == 1 [L381] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L385] COND TRUE t4_i == 1 [L386] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L809] RET init_threads() [L810] CALL fire_delta_events() [L526] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L531] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L536] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L541] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L546] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L551] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L556] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L561] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L566] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L571] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L810] RET fire_delta_events() [L811] CALL activate_threads() [L639] int tmp ; [L640] int tmp___0 ; [L641] int tmp___1 ; [L642] int tmp___2 ; [L643] int tmp___3 ; [L647] CALL, EXPR is_master_triggered() [L259] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L262] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L272] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L274] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L647] RET, EXPR is_master_triggered() [L647] tmp = is_master_triggered() [L649] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, token=0] [L655] CALL, EXPR is_transmit1_triggered() [L278] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L281] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L291] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L293] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L655] RET, EXPR is_transmit1_triggered() [L655] tmp___0 = is_transmit1_triggered() [L657] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, token=0] [L663] CALL, EXPR is_transmit2_triggered() [L297] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L300] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L310] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L312] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L663] RET, EXPR is_transmit2_triggered() [L663] tmp___1 = is_transmit2_triggered() [L665] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L671] CALL, EXPR is_transmit3_triggered() [L316] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L319] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L329] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L331] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L671] RET, EXPR is_transmit3_triggered() [L671] tmp___2 = is_transmit3_triggered() [L673] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L679] CALL, EXPR is_transmit4_triggered() [L335] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L338] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L348] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L350] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L679] RET, EXPR is_transmit4_triggered() [L679] tmp___3 = is_transmit4_triggered() [L681] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L811] RET activate_threads() [L812] CALL reset_delta_events() [L584] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L589] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L594] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L599] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L604] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L609] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L614] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L619] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L624] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L629] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L812] RET reset_delta_events() [L815] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] [L818] kernel_st = 1 [L819] CALL eval() [L431] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, token=0] Loop: [L435] COND TRUE 1 [L438] CALL, EXPR exists_runnable_thread() [L395] int __retres1 ; [L398] COND TRUE m_st == 0 [L399] __retres1 = 1 [L426] return (__retres1); [L438] RET, EXPR exists_runnable_thread() [L438] tmp = exists_runnable_thread() [L440] COND TRUE \read(tmp) [L445] COND TRUE m_st == 0 [L446] int tmp_ndt_1; [L447] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L448] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L445-L456] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L459] COND TRUE t1_st == 0 [L460] int tmp_ndt_2; [L461] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L462] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L459-L470] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L473] COND TRUE t2_st == 0 [L474] int tmp_ndt_3; [L475] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L476] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L473-L484] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L487] COND TRUE t3_st == 0 [L488] int tmp_ndt_4; [L489] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L490] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L487-L498] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L501] COND TRUE t4_st == 0 [L502] int tmp_ndt_5; [L503] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L504] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L501-L512] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:17:02,076 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9a65ea1d-d069-4781-b05e-4c2672ba3c9a/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)