./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:25:11,830 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:25:11,902 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:25:11,907 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:25:11,907 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:25:11,933 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:25:11,937 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:25:11,938 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:25:11,939 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:25:11,940 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:25:11,941 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:25:11,942 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:25:11,942 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:25:11,945 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:25:11,945 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:25:11,946 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:25:11,947 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:25:11,952 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:25:11,952 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:25:11,953 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:25:11,953 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:25:11,955 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:25:11,956 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:25:11,956 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:25:11,957 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:25:11,957 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:25:11,958 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:25:11,958 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:25:11,958 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:25:11,959 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:25:11,960 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:25:11,961 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:25:11,961 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:25:11,961 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:25:11,962 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:25:11,962 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:25:11,963 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a75784c0f203c4a6f14019aef9d9a89ba63a0efbe594dc5cdecfb5d06e7619f2 [2023-11-06 22:25:12,295 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:25:12,339 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:25:12,342 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:25:12,344 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:25:12,345 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:25:12,346 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2023-11-06 22:25:15,511 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:25:15,722 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:25:15,722 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/sv-benchmarks/c/systemc/token_ring.05.cil-1.c [2023-11-06 22:25:15,750 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/data/5e89339d1/8fab82e2b8c04951aff8b599b2d93db5/FLAG1edd709a2 [2023-11-06 22:25:15,771 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/data/5e89339d1/8fab82e2b8c04951aff8b599b2d93db5 [2023-11-06 22:25:15,779 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:25:15,782 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:25:15,787 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:25:15,788 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:25:15,794 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:25:15,795 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:25:15" (1/1) ... [2023-11-06 22:25:15,796 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@406f4411 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:15, skipping insertion in model container [2023-11-06 22:25:15,796 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:25:15" (1/1) ... [2023-11-06 22:25:15,860 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:25:16,154 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:25:16,170 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:25:16,221 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:25:16,239 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:25:16,240 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16 WrapperNode [2023-11-06 22:25:16,240 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:25:16,241 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:25:16,241 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:25:16,241 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:25:16,248 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,258 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,331 INFO L138 Inliner]: procedures = 38, calls = 47, calls flagged for inlining = 42, calls inlined = 95, statements flattened = 1354 [2023-11-06 22:25:16,339 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:25:16,340 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:25:16,340 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:25:16,340 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:25:16,350 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,355 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,375 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,375 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,424 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,442 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,446 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,451 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,461 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:25:16,462 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:25:16,463 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:25:16,463 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:25:16,464 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (1/1) ... [2023-11-06 22:25:16,470 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:25:16,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:25:16,519 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:25:16,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:25:16,568 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:25:16,568 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:25:16,568 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:25:16,569 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:25:16,698 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:25:16,701 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:25:17,961 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:25:17,985 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:25:17,986 INFO L302 CfgBuilder]: Removed 8 assume(true) statements. [2023-11-06 22:25:17,989 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:17 BoogieIcfgContainer [2023-11-06 22:25:17,989 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:25:17,990 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:25:17,990 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:25:17,995 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:25:17,995 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:17,996 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:25:15" (1/3) ... [2023-11-06 22:25:17,997 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e708716 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:25:17, skipping insertion in model container [2023-11-06 22:25:17,997 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:17,997 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:25:16" (2/3) ... [2023-11-06 22:25:17,997 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e708716 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:25:17, skipping insertion in model container [2023-11-06 22:25:17,998 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:25:17,998 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:17" (3/3) ... [2023-11-06 22:25:18,005 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-1.c [2023-11-06 22:25:18,113 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:25:18,113 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:25:18,113 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:25:18,114 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:25:18,114 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:25:18,114 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:25:18,114 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:25:18,115 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:25:18,125 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:18,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2023-11-06 22:25:18,209 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:18,209 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:18,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:18,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:18,234 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:25:18,236 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:18,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 476 [2023-11-06 22:25:18,254 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:18,254 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:18,264 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:18,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:18,281 INFO L748 eck$LassoCheckResult]: Stem: 172#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 464#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 267#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 460#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 551#L414true assume !(1 == ~m_i~0);~m_st~0 := 2; 222#L414-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 415#L419-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 414#L424-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 203#L429-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 406#L434-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L439-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 201#L599true assume 0 == ~M_E~0;~M_E~0 := 1; 360#L599-2true assume !(0 == ~T1_E~0); 10#L604-1true assume !(0 == ~T2_E~0); 5#L609-1true assume !(0 == ~T3_E~0); 83#L614-1true assume !(0 == ~T4_E~0); 155#L619-1true assume !(0 == ~T5_E~0); 226#L624-1true assume !(0 == ~E_M~0); 506#L629-1true assume !(0 == ~E_1~0); 47#L634-1true assume 0 == ~E_2~0;~E_2~0 := 1; 327#L639-1true assume !(0 == ~E_3~0); 400#L644-1true assume !(0 == ~E_4~0); 351#L649-1true assume !(0 == ~E_5~0); 31#L654-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 90#L292true assume !(1 == ~m_pc~0); 184#L292-2true is_master_triggered_~__retres1~0#1 := 0; 260#L303true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 153#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L743true assume !(0 != activate_threads_~tmp~1#1); 62#L743-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326#L311true assume 1 == ~t1_pc~0; 140#L312true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231#L322true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19#L751true assume !(0 != activate_threads_~tmp___0~0#1); 427#L751-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L330true assume 1 == ~t2_pc~0; 157#L331true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 91#L341true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 270#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 454#L759true assume !(0 != activate_threads_~tmp___1~0#1); 468#L759-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 84#L349true assume !(1 == ~t3_pc~0); 510#L349-2true is_transmit3_triggered_~__retres1~3#1 := 0; 298#L360true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537#L767true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 444#L767-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 538#L368true assume 1 == ~t4_pc~0; 456#L369true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 388#L379true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 435#L775true assume !(0 != activate_threads_~tmp___3~0#1); 12#L775-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475#L387true assume !(1 == ~t5_pc~0); 242#L387-2true is_transmit5_triggered_~__retres1~5#1 := 0; 546#L398true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 159#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70#L783true assume !(0 != activate_threads_~tmp___4~0#1); 123#L783-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 178#L667true assume !(1 == ~M_E~0); 335#L667-2true assume !(1 == ~T1_E~0); 342#L672-1true assume !(1 == ~T2_E~0); 147#L677-1true assume !(1 == ~T3_E~0); 309#L682-1true assume !(1 == ~T4_E~0); 402#L687-1true assume !(1 == ~T5_E~0); 469#L692-1true assume !(1 == ~E_M~0); 297#L697-1true assume 1 == ~E_1~0;~E_1~0 := 2; 527#L702-1true assume !(1 == ~E_2~0); 350#L707-1true assume !(1 == ~E_3~0); 215#L712-1true assume !(1 == ~E_4~0); 334#L717-1true assume !(1 == ~E_5~0); 316#L722-1true assume { :end_inline_reset_delta_events } true; 16#L928-2true [2023-11-06 22:25:18,294 INFO L750 eck$LassoCheckResult]: Loop: 16#L928-2true assume !false; 218#L929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 141#L574-1true assume !true; 85#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 398#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257#L599-3true assume 0 == ~M_E~0;~M_E~0 := 1; 308#L599-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 190#L604-3true assume !(0 == ~T2_E~0); 515#L609-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 246#L614-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 20#L619-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 255#L624-3true assume 0 == ~E_M~0;~E_M~0 := 1; 305#L629-3true assume 0 == ~E_1~0;~E_1~0 := 1; 397#L634-3true assume 0 == ~E_2~0;~E_2~0 := 1; 317#L639-3true assume 0 == ~E_3~0;~E_3~0 := 1; 447#L644-3true assume !(0 == ~E_4~0); 517#L649-3true assume 0 == ~E_5~0;~E_5~0 := 1; 196#L654-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295#L292-21true assume 1 == ~m_pc~0; 262#L293-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53#L303-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 428#L743-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187#L743-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 399#L311-21true assume !(1 == ~t1_pc~0); 136#L311-23true is_transmit1_triggered_~__retres1~1#1 := 0; 35#L322-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 66#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 465#L751-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89#L751-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282#L330-21true assume 1 == ~t2_pc~0; 480#L331-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 252#L341-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 183#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 272#L759-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 58#L759-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L349-21true assume !(1 == ~t3_pc~0); 369#L349-23true is_transmit3_triggered_~__retres1~3#1 := 0; 385#L360-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 477#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 321#L767-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 452#L767-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 101#L368-21true assume 1 == ~t4_pc~0; 42#L369-7true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 383#L379-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 438#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 362#L775-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8#L775-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37#L387-21true assume 1 == ~t5_pc~0; 241#L388-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 338#L398-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 248#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 393#L783-21true assume !(0 != activate_threads_~tmp___4~0#1); 55#L783-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186#L667-3true assume 1 == ~M_E~0;~M_E~0 := 2; 49#L667-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 331#L672-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 88#L677-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 556#L682-3true assume !(1 == ~T4_E~0); 380#L687-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 114#L692-3true assume 1 == ~E_M~0;~E_M~0 := 2; 497#L697-3true assume 1 == ~E_1~0;~E_1~0 := 2; 165#L702-3true assume 1 == ~E_2~0;~E_2~0 := 2; 261#L707-3true assume 1 == ~E_3~0;~E_3~0 := 2; 294#L712-3true assume 1 == ~E_4~0;~E_4~0 := 2; 52#L717-3true assume 1 == ~E_5~0;~E_5~0 := 2; 287#L722-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 451#L452-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 387#L484-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 238#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 192#L947true assume !(0 == start_simulation_~tmp~3#1); 528#L947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 195#L452-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 323#L484-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 27#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 378#L902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 333#L909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 419#stop_simulation_returnLabel#1true start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 278#L960true assume !(0 != start_simulation_~tmp___0~1#1); 16#L928-2true [2023-11-06 22:25:18,305 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:18,305 INFO L85 PathProgramCache]: Analyzing trace with hash 907431560, now seen corresponding path program 1 times [2023-11-06 22:25:18,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:18,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [60011632] [2023-11-06 22:25:18,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:18,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:18,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:18,687 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:18,687 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:18,688 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [60011632] [2023-11-06 22:25:18,689 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [60011632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:18,689 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:18,689 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:18,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941402548] [2023-11-06 22:25:18,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:18,697 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:18,699 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:18,700 INFO L85 PathProgramCache]: Analyzing trace with hash 1012277568, now seen corresponding path program 1 times [2023-11-06 22:25:18,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:18,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87298357] [2023-11-06 22:25:18,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:18,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:18,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:18,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:18,784 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:18,789 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87298357] [2023-11-06 22:25:18,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87298357] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:18,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:18,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:18,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184511876] [2023-11-06 22:25:18,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:18,792 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:18,794 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:18,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:18,834 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:18,837 INFO L87 Difference]: Start difference. First operand has 559 states, 558 states have (on average 1.521505376344086) internal successors, (849), 558 states have internal predecessors, (849), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:18,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:18,904 INFO L93 Difference]: Finished difference Result 557 states and 829 transitions. [2023-11-06 22:25:18,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 557 states and 829 transitions. [2023-11-06 22:25:18,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:18,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 557 states to 552 states and 824 transitions. [2023-11-06 22:25:18,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-06 22:25:18,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-06 22:25:18,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 824 transitions. [2023-11-06 22:25:18,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:18,933 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-06 22:25:18,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 824 transitions. [2023-11-06 22:25:19,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-06 22:25:19,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4927536231884058) internal successors, (824), 551 states have internal predecessors, (824), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 824 transitions. [2023-11-06 22:25:19,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-06 22:25:19,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:19,026 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 824 transitions. [2023-11-06 22:25:19,027 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:25:19,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 824 transitions. [2023-11-06 22:25:19,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:19,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:19,037 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,038 INFO L748 eck$LassoCheckResult]: Stem: 1434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1666#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 1504#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1505#L419-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1650#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1479#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1480#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1646#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1477#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 1478#L599-2 assume !(0 == ~T1_E~0); 1142#L604-1 assume !(0 == ~T2_E~0); 1131#L609-1 assume !(0 == ~T3_E~0); 1132#L614-1 assume !(0 == ~T4_E~0); 1299#L619-1 assume !(0 == ~T5_E~0); 1413#L624-1 assume !(0 == ~E_M~0); 1508#L629-1 assume !(0 == ~E_1~0); 1221#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 1222#L639-1 assume !(0 == ~E_3~0); 1609#L644-1 assume !(0 == ~E_4~0); 1624#L649-1 assume !(0 == ~E_5~0); 1185#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1186#L292 assume !(1 == ~m_pc~0); 1312#L292-2 is_master_triggered_~__retres1~0#1 := 0; 1450#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1409#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1410#L743 assume !(0 != activate_threads_~tmp~1#1); 1254#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1255#L311 assume 1 == ~t1_pc~0; 1386#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1387#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1158#L751 assume !(0 != activate_threads_~tmp___0~0#1); 1159#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1610#L330 assume 1 == ~t2_pc~0; 1415#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1314#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1315#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 1664#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1300#L349 assume !(1 == ~t3_pc~0); 1301#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1350#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1134#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1659#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1660#L368 assume 1 == ~t4_pc~0; 1665#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1377#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1285#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1286#L775 assume !(0 != activate_threads_~tmp___3~0#1); 1145#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1146#L387 assume !(1 == ~t5_pc~0); 1525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1271#L783 assume !(0 != activate_threads_~tmp___4~0#1); 1272#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1365#L667 assume !(1 == ~M_E~0); 1442#L667-2 assume !(1 == ~T1_E~0); 1616#L672-1 assume !(1 == ~T2_E~0); 1400#L677-1 assume !(1 == ~T3_E~0); 1401#L682-1 assume !(1 == ~T4_E~0); 1593#L687-1 assume !(1 == ~T5_E~0); 1643#L692-1 assume !(1 == ~E_M~0); 1583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 1584#L702-1 assume !(1 == ~E_2~0); 1623#L707-1 assume !(1 == ~E_3~0); 1496#L712-1 assume !(1 == ~E_4~0); 1497#L717-1 assume !(1 == ~E_5~0); 1600#L722-1 assume { :end_inline_reset_delta_events } true; 1153#L928-2 [2023-11-06 22:25:19,039 INFO L750 eck$LassoCheckResult]: Loop: 1153#L928-2 assume !false; 1154#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1389#L574-1 assume !false; 1390#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1658#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1353#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1576#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1189#L499 assume !(0 != eval_~tmp~0#1); 1190#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1303#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1548#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1549#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1459#L604-3 assume !(0 == ~T2_E~0); 1460#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1534#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1160#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1161#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1590#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1601#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1602#L644-3 assume !(0 == ~E_4~0); 1662#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1469#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1470#L292-21 assume !(1 == ~m_pc~0); 1369#L292-23 is_master_triggered_~__retres1~0#1 := 0; 1236#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1237#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1339#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1453#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1454#L311-21 assume !(1 == ~t1_pc~0); 1381#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 1193#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1194#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1262#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1310#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1311#L330-21 assume !(1 == ~t2_pc~0); 1571#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1448#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1449#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1246#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1247#L349-21 assume 1 == ~t3_pc~0; 1493#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1633#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1638#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1604#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1605#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1329#L368-21 assume 1 == ~t4_pc~0; 1210#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1211#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1637#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1627#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1138#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1139#L387-21 assume !(1 == ~t5_pc~0); 1198#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 1524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1532#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1533#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 1238#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1239#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1223#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1224#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1306#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1307#L682-3 assume !(1 == ~T4_E~0); 1636#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1348#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1349#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1423#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1424#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1550#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1230#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1231#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1575#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1168#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1521#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1462#L947 assume !(0 == start_simulation_~tmp~3#1); 1463#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1466#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1427#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 1178#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1614#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1615#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1563#L960 assume !(0 != start_simulation_~tmp___0~1#1); 1153#L928-2 [2023-11-06 22:25:19,040 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,041 INFO L85 PathProgramCache]: Analyzing trace with hash 1400057734, now seen corresponding path program 1 times [2023-11-06 22:25:19,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,042 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801351563] [2023-11-06 22:25:19,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,042 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [801351563] [2023-11-06 22:25:19,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [801351563] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [679170099] [2023-11-06 22:25:19,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,170 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:19,171 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 1 times [2023-11-06 22:25:19,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,173 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130856251] [2023-11-06 22:25:19,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130856251] [2023-11-06 22:25:19,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130856251] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81291275] [2023-11-06 22:25:19,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,328 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:19,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:19,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:19,329 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:19,329 INFO L87 Difference]: Start difference. First operand 552 states and 824 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:19,354 INFO L93 Difference]: Finished difference Result 552 states and 823 transitions. [2023-11-06 22:25:19,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 823 transitions. [2023-11-06 22:25:19,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 823 transitions. [2023-11-06 22:25:19,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-06 22:25:19,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-06 22:25:19,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 823 transitions. [2023-11-06 22:25:19,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:19,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-06 22:25:19,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 823 transitions. [2023-11-06 22:25:19,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-06 22:25:19,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4909420289855073) internal successors, (823), 551 states have internal predecessors, (823), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 823 transitions. [2023-11-06 22:25:19,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-06 22:25:19,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:19,386 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 823 transitions. [2023-11-06 22:25:19,386 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:25:19,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 823 transitions. [2023-11-06 22:25:19,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:19,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:19,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,394 INFO L748 eck$LassoCheckResult]: Stem: 2545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2665#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2666#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2777#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 2615#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2616#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2761#L424-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2590#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2591#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2757#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2588#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 2589#L599-2 assume !(0 == ~T1_E~0); 2255#L604-1 assume !(0 == ~T2_E~0); 2242#L609-1 assume !(0 == ~T3_E~0); 2243#L614-1 assume !(0 == ~T4_E~0); 2410#L619-1 assume !(0 == ~T5_E~0); 2524#L624-1 assume !(0 == ~E_M~0); 2619#L629-1 assume !(0 == ~E_1~0); 2332#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 2333#L639-1 assume !(0 == ~E_3~0); 2720#L644-1 assume !(0 == ~E_4~0); 2735#L649-1 assume !(0 == ~E_5~0); 2296#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2297#L292 assume !(1 == ~m_pc~0); 2423#L292-2 is_master_triggered_~__retres1~0#1 := 0; 2561#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2520#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2521#L743 assume !(0 != activate_threads_~tmp~1#1); 2365#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2366#L311 assume 1 == ~t1_pc~0; 2497#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2498#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2269#L751 assume !(0 != activate_threads_~tmp___0~0#1); 2270#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2721#L330 assume 1 == ~t2_pc~0; 2526#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2425#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2426#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2670#L759 assume !(0 != activate_threads_~tmp___1~0#1); 2775#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2411#L349 assume !(1 == ~t3_pc~0); 2412#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2461#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2246#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2247#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2770#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2771#L368 assume 1 == ~t4_pc~0; 2776#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2488#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2397#L775 assume !(0 != activate_threads_~tmp___3~0#1); 2256#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257#L387 assume !(1 == ~t5_pc~0); 2636#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2637#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2529#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2382#L783 assume !(0 != activate_threads_~tmp___4~0#1); 2383#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2478#L667 assume !(1 == ~M_E~0); 2553#L667-2 assume !(1 == ~T1_E~0); 2727#L672-1 assume !(1 == ~T2_E~0); 2511#L677-1 assume !(1 == ~T3_E~0); 2512#L682-1 assume !(1 == ~T4_E~0); 2704#L687-1 assume !(1 == ~T5_E~0); 2754#L692-1 assume !(1 == ~E_M~0); 2694#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2695#L702-1 assume !(1 == ~E_2~0); 2734#L707-1 assume !(1 == ~E_3~0); 2607#L712-1 assume !(1 == ~E_4~0); 2608#L717-1 assume !(1 == ~E_5~0); 2711#L722-1 assume { :end_inline_reset_delta_events } true; 2264#L928-2 [2023-11-06 22:25:19,395 INFO L750 eck$LassoCheckResult]: Loop: 2264#L928-2 assume !false; 2265#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2500#L574-1 assume !false; 2501#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2769#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2464#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2687#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2300#L499 assume !(0 != eval_~tmp~0#1); 2301#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2659#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2660#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2570#L604-3 assume !(0 == ~T2_E~0); 2571#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2645#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2271#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2272#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2654#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2701#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2712#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2713#L644-3 assume !(0 == ~E_4~0); 2773#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2580#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2581#L292-21 assume !(1 == ~m_pc~0); 2480#L292-23 is_master_triggered_~__retres1~0#1 := 0; 2347#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2348#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2450#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2564#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2565#L311-21 assume 1 == ~t1_pc~0; 2753#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2304#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2305#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2373#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2421#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2422#L330-21 assume !(1 == ~t2_pc~0); 2682#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 2651#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2559#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2560#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2359#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2360#L349-21 assume 1 == ~t3_pc~0; 2604#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2743#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2749#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2715#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2716#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2440#L368-21 assume 1 == ~t4_pc~0; 2321#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2322#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2748#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2244#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2245#L387-21 assume !(1 == ~t5_pc~0); 2309#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 2635#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2643#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2644#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 2349#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2350#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2334#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2335#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2417#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2418#L682-3 assume !(1 == ~T4_E~0); 2747#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2459#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2460#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2534#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2535#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2661#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2343#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2344#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2686#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2279#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2632#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2573#L947 assume !(0 == start_simulation_~tmp~3#1); 2574#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2577#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2538#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 2289#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2725#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2726#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 2674#L960 assume !(0 != start_simulation_~tmp___0~1#1); 2264#L928-2 [2023-11-06 22:25:19,396 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,396 INFO L85 PathProgramCache]: Analyzing trace with hash -1678755836, now seen corresponding path program 1 times [2023-11-06 22:25:19,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116972808] [2023-11-06 22:25:19,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [116972808] [2023-11-06 22:25:19,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [116972808] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1685973307] [2023-11-06 22:25:19,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,441 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:19,441 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,441 INFO L85 PathProgramCache]: Analyzing trace with hash -815672335, now seen corresponding path program 1 times [2023-11-06 22:25:19,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [463715013] [2023-11-06 22:25:19,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,496 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,497 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [463715013] [2023-11-06 22:25:19,497 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [463715013] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,497 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,497 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139312249] [2023-11-06 22:25:19,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,498 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:19,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:19,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:19,499 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:19,500 INFO L87 Difference]: Start difference. First operand 552 states and 823 transitions. cyclomatic complexity: 272 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:19,519 INFO L93 Difference]: Finished difference Result 552 states and 822 transitions. [2023-11-06 22:25:19,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 822 transitions. [2023-11-06 22:25:19,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 822 transitions. [2023-11-06 22:25:19,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-06 22:25:19,531 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-06 22:25:19,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 822 transitions. [2023-11-06 22:25:19,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:19,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-06 22:25:19,534 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 822 transitions. [2023-11-06 22:25:19,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-06 22:25:19,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4891304347826086) internal successors, (822), 551 states have internal predecessors, (822), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 822 transitions. [2023-11-06 22:25:19,547 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-06 22:25:19,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:19,548 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 822 transitions. [2023-11-06 22:25:19,548 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:25:19,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 822 transitions. [2023-11-06 22:25:19,553 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:19,554 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:19,555 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,555 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,557 INFO L748 eck$LassoCheckResult]: Stem: 3656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3776#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3777#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3888#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 3726#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3727#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3872#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3703#L429-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3704#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3868#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3699#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 3700#L599-2 assume !(0 == ~T1_E~0); 3366#L604-1 assume !(0 == ~T2_E~0); 3353#L609-1 assume !(0 == ~T3_E~0); 3354#L614-1 assume !(0 == ~T4_E~0); 3521#L619-1 assume !(0 == ~T5_E~0); 3635#L624-1 assume !(0 == ~E_M~0); 3730#L629-1 assume !(0 == ~E_1~0); 3443#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3444#L639-1 assume !(0 == ~E_3~0); 3831#L644-1 assume !(0 == ~E_4~0); 3846#L649-1 assume !(0 == ~E_5~0); 3407#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3408#L292 assume !(1 == ~m_pc~0); 3534#L292-2 is_master_triggered_~__retres1~0#1 := 0; 3672#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3631#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3632#L743 assume !(0 != activate_threads_~tmp~1#1); 3476#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3477#L311 assume 1 == ~t1_pc~0; 3608#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3609#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3401#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3380#L751 assume !(0 != activate_threads_~tmp___0~0#1); 3381#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3832#L330 assume 1 == ~t2_pc~0; 3637#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3536#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3781#L759 assume !(0 != activate_threads_~tmp___1~0#1); 3886#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3522#L349 assume !(1 == ~t3_pc~0); 3523#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3572#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3360#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3361#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3881#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3882#L368 assume 1 == ~t4_pc~0; 3887#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3599#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3508#L775 assume !(0 != activate_threads_~tmp___3~0#1); 3367#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3368#L387 assume !(1 == ~t5_pc~0); 3747#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3748#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3496#L783 assume !(0 != activate_threads_~tmp___4~0#1); 3497#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3589#L667 assume !(1 == ~M_E~0); 3664#L667-2 assume !(1 == ~T1_E~0); 3839#L672-1 assume !(1 == ~T2_E~0); 3622#L677-1 assume !(1 == ~T3_E~0); 3623#L682-1 assume !(1 == ~T4_E~0); 3815#L687-1 assume !(1 == ~T5_E~0); 3865#L692-1 assume !(1 == ~E_M~0); 3805#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3806#L702-1 assume !(1 == ~E_2~0); 3845#L707-1 assume !(1 == ~E_3~0); 3718#L712-1 assume !(1 == ~E_4~0); 3719#L717-1 assume !(1 == ~E_5~0); 3822#L722-1 assume { :end_inline_reset_delta_events } true; 3375#L928-2 [2023-11-06 22:25:19,558 INFO L750 eck$LassoCheckResult]: Loop: 3375#L928-2 assume !false; 3376#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3611#L574-1 assume !false; 3612#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3880#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3575#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3798#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3411#L499 assume !(0 != eval_~tmp~0#1); 3412#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3525#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3770#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3771#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3681#L604-3 assume !(0 == ~T2_E~0); 3682#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3757#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3382#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3383#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3765#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3812#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3823#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3824#L644-3 assume !(0 == ~E_4~0); 3884#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3691#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3692#L292-21 assume !(1 == ~m_pc~0); 3591#L292-23 is_master_triggered_~__retres1~0#1 := 0; 3458#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3459#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3561#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3675#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3676#L311-21 assume !(1 == ~t1_pc~0); 3602#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 3415#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3416#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3484#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3532#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3533#L330-21 assume 1 == ~t2_pc~0; 3792#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3762#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3669#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3670#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3465#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3466#L349-21 assume 1 == ~t3_pc~0; 3715#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3854#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3860#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3826#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3827#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3551#L368-21 assume 1 == ~t4_pc~0; 3432#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3433#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3859#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3849#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3358#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3359#L387-21 assume !(1 == ~t5_pc~0); 3420#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 3746#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3755#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3756#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 3460#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3461#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3448#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3449#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3528#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3529#L682-3 assume !(1 == ~T4_E~0); 3858#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3570#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3571#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3645#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3646#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3772#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3454#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3455#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3797#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3390#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3743#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3684#L947 assume !(0 == start_simulation_~tmp~3#1); 3685#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3688#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3649#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3399#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 3400#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3836#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3837#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3785#L960 assume !(0 != start_simulation_~tmp___0~1#1); 3375#L928-2 [2023-11-06 22:25:19,558 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,559 INFO L85 PathProgramCache]: Analyzing trace with hash -946788410, now seen corresponding path program 1 times [2023-11-06 22:25:19,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070616976] [2023-11-06 22:25:19,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,657 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,662 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070616976] [2023-11-06 22:25:19,662 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070616976] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,662 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,662 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,663 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600602569] [2023-11-06 22:25:19,663 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,663 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:19,664 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,664 INFO L85 PathProgramCache]: Analyzing trace with hash 902962993, now seen corresponding path program 1 times [2023-11-06 22:25:19,664 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508346970] [2023-11-06 22:25:19,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,665 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,727 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,727 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508346970] [2023-11-06 22:25:19,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508346970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,728 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270742316] [2023-11-06 22:25:19,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,729 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:19,729 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:19,730 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:19,730 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:19,731 INFO L87 Difference]: Start difference. First operand 552 states and 822 transitions. cyclomatic complexity: 271 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:19,749 INFO L93 Difference]: Finished difference Result 552 states and 821 transitions. [2023-11-06 22:25:19,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 821 transitions. [2023-11-06 22:25:19,754 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 821 transitions. [2023-11-06 22:25:19,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-06 22:25:19,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-06 22:25:19,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 821 transitions. [2023-11-06 22:25:19,764 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:19,764 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-06 22:25:19,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 821 transitions. [2023-11-06 22:25:19,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-06 22:25:19,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4873188405797102) internal successors, (821), 551 states have internal predecessors, (821), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 821 transitions. [2023-11-06 22:25:19,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-06 22:25:19,778 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:19,780 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 821 transitions. [2023-11-06 22:25:19,780 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:25:19,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 821 transitions. [2023-11-06 22:25:19,788 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:19,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:19,794 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,794 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,795 INFO L748 eck$LassoCheckResult]: Stem: 4767#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4768#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4888#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4999#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 4837#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4838#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4983#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4814#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4815#L434-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4979#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4810#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 4811#L599-2 assume !(0 == ~T1_E~0); 4477#L604-1 assume !(0 == ~T2_E~0); 4464#L609-1 assume !(0 == ~T3_E~0); 4465#L614-1 assume !(0 == ~T4_E~0); 4632#L619-1 assume !(0 == ~T5_E~0); 4746#L624-1 assume !(0 == ~E_M~0); 4841#L629-1 assume !(0 == ~E_1~0); 4554#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 4555#L639-1 assume !(0 == ~E_3~0); 4942#L644-1 assume !(0 == ~E_4~0); 4957#L649-1 assume !(0 == ~E_5~0); 4518#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4519#L292 assume !(1 == ~m_pc~0); 4645#L292-2 is_master_triggered_~__retres1~0#1 := 0; 4783#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4744#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4745#L743 assume !(0 != activate_threads_~tmp~1#1); 4587#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4588#L311 assume 1 == ~t1_pc~0; 4719#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4720#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4491#L751 assume !(0 != activate_threads_~tmp___0~0#1); 4492#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4943#L330 assume 1 == ~t2_pc~0; 4748#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4647#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4648#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4892#L759 assume !(0 != activate_threads_~tmp___1~0#1); 4997#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4633#L349 assume !(1 == ~t3_pc~0); 4634#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4683#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4471#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4472#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4992#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4993#L368 assume 1 == ~t4_pc~0; 4998#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4712#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4618#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4619#L775 assume !(0 != activate_threads_~tmp___3~0#1); 4478#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4479#L387 assume !(1 == ~t5_pc~0); 4858#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4859#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4751#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4607#L783 assume !(0 != activate_threads_~tmp___4~0#1); 4608#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4700#L667 assume !(1 == ~M_E~0); 4775#L667-2 assume !(1 == ~T1_E~0); 4950#L672-1 assume !(1 == ~T2_E~0); 4733#L677-1 assume !(1 == ~T3_E~0); 4734#L682-1 assume !(1 == ~T4_E~0); 4926#L687-1 assume !(1 == ~T5_E~0); 4976#L692-1 assume !(1 == ~E_M~0); 4916#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4917#L702-1 assume !(1 == ~E_2~0); 4956#L707-1 assume !(1 == ~E_3~0); 4829#L712-1 assume !(1 == ~E_4~0); 4830#L717-1 assume !(1 == ~E_5~0); 4933#L722-1 assume { :end_inline_reset_delta_events } true; 4486#L928-2 [2023-11-06 22:25:19,795 INFO L750 eck$LassoCheckResult]: Loop: 4486#L928-2 assume !false; 4487#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4722#L574-1 assume !false; 4723#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4991#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4686#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4909#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4522#L499 assume !(0 != eval_~tmp~0#1); 4523#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4636#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4881#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4882#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4793#L604-3 assume !(0 == ~T2_E~0); 4794#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4868#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4493#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4494#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4876#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4923#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4934#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4935#L644-3 assume !(0 == ~E_4~0); 4995#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4802#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4803#L292-21 assume 1 == ~m_pc~0; 4884#L293-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4569#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4570#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4670#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4786#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4787#L311-21 assume !(1 == ~t1_pc~0); 4713#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 4526#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4527#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4595#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4643#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4644#L330-21 assume !(1 == ~t2_pc~0); 4903#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 4873#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4781#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4782#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4576#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4577#L349-21 assume 1 == ~t3_pc~0; 4826#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4965#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4971#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4937#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4938#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4662#L368-21 assume !(1 == ~t4_pc~0); 4545#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4544#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4970#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4960#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4469#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4470#L387-21 assume !(1 == ~t5_pc~0); 4531#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4857#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4866#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4867#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 4571#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4572#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4559#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4560#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4639#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4640#L682-3 assume !(1 == ~T4_E~0); 4969#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4681#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4682#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4756#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4757#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4883#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4565#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4566#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4908#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4501#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4854#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4795#L947 assume !(0 == start_simulation_~tmp~3#1); 4796#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4799#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4760#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4510#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 4511#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4947#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4948#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4896#L960 assume !(0 != start_simulation_~tmp___0~1#1); 4486#L928-2 [2023-11-06 22:25:19,796 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,802 INFO L85 PathProgramCache]: Analyzing trace with hash 739391428, now seen corresponding path program 1 times [2023-11-06 22:25:19,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817772761] [2023-11-06 22:25:19,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1817772761] [2023-11-06 22:25:19,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1817772761] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,854 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,854 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [127760353] [2023-11-06 22:25:19,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:19,856 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1827073166, now seen corresponding path program 1 times [2023-11-06 22:25:19,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093260374] [2023-11-06 22:25:19,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:19,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:19,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:19,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093260374] [2023-11-06 22:25:19,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093260374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:19,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:19,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:19,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [739669036] [2023-11-06 22:25:19,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:19,924 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:19,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:19,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:19,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:19,925 INFO L87 Difference]: Start difference. First operand 552 states and 821 transitions. cyclomatic complexity: 270 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:19,943 INFO L93 Difference]: Finished difference Result 552 states and 820 transitions. [2023-11-06 22:25:19,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 552 states and 820 transitions. [2023-11-06 22:25:19,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 552 states to 552 states and 820 transitions. [2023-11-06 22:25:19,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 552 [2023-11-06 22:25:19,955 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 552 [2023-11-06 22:25:19,955 INFO L73 IsDeterministic]: Start isDeterministic. Operand 552 states and 820 transitions. [2023-11-06 22:25:19,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:19,956 INFO L218 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-06 22:25:19,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states and 820 transitions. [2023-11-06 22:25:19,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 552. [2023-11-06 22:25:19,967 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 552 states, 552 states have (on average 1.4855072463768115) internal successors, (820), 551 states have internal predecessors, (820), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:19,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 552 states to 552 states and 820 transitions. [2023-11-06 22:25:19,970 INFO L240 hiAutomatonCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-06 22:25:19,971 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:19,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 552 states and 820 transitions. [2023-11-06 22:25:19,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:25:19,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 552 states and 820 transitions. [2023-11-06 22:25:19,977 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 473 [2023-11-06 22:25:19,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:19,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:19,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:19,982 INFO L748 eck$LassoCheckResult]: Stem: 5879#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5880#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5998#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5999#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6110#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 5948#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5949#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6094#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5925#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5926#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6090#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5921#L599 assume 0 == ~M_E~0;~M_E~0 := 1; 5922#L599-2 assume !(0 == ~T1_E~0); 5588#L604-1 assume !(0 == ~T2_E~0); 5575#L609-1 assume !(0 == ~T3_E~0); 5576#L614-1 assume !(0 == ~T4_E~0); 5743#L619-1 assume !(0 == ~T5_E~0); 5857#L624-1 assume !(0 == ~E_M~0); 5952#L629-1 assume !(0 == ~E_1~0); 5665#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5666#L639-1 assume !(0 == ~E_3~0); 6053#L644-1 assume !(0 == ~E_4~0); 6068#L649-1 assume !(0 == ~E_5~0); 5629#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5630#L292 assume !(1 == ~m_pc~0); 5756#L292-2 is_master_triggered_~__retres1~0#1 := 0; 5894#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5855#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5856#L743 assume !(0 != activate_threads_~tmp~1#1); 5698#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5699#L311 assume 1 == ~t1_pc~0; 5830#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5831#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5623#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5602#L751 assume !(0 != activate_threads_~tmp___0~0#1); 5603#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6056#L330 assume 1 == ~t2_pc~0; 5859#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5759#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5760#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6003#L759 assume !(0 != activate_threads_~tmp___1~0#1); 6108#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5744#L349 assume !(1 == ~t3_pc~0); 5745#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5794#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5583#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6103#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6104#L368 assume 1 == ~t4_pc~0; 6109#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5823#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5729#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5730#L775 assume !(0 != activate_threads_~tmp___3~0#1); 5589#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5590#L387 assume !(1 == ~t5_pc~0); 5969#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5970#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5862#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5718#L783 assume !(0 != activate_threads_~tmp___4~0#1); 5719#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5811#L667 assume !(1 == ~M_E~0); 5886#L667-2 assume !(1 == ~T1_E~0); 6061#L672-1 assume !(1 == ~T2_E~0); 5844#L677-1 assume !(1 == ~T3_E~0); 5845#L682-1 assume !(1 == ~T4_E~0); 6037#L687-1 assume !(1 == ~T5_E~0); 6087#L692-1 assume !(1 == ~E_M~0); 6027#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6028#L702-1 assume !(1 == ~E_2~0); 6067#L707-1 assume !(1 == ~E_3~0); 5940#L712-1 assume !(1 == ~E_4~0); 5941#L717-1 assume !(1 == ~E_5~0); 6044#L722-1 assume { :end_inline_reset_delta_events } true; 5597#L928-2 [2023-11-06 22:25:19,983 INFO L750 eck$LassoCheckResult]: Loop: 5597#L928-2 assume !false; 5598#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5833#L574-1 assume !false; 5834#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6102#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5797#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6020#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5633#L499 assume !(0 != eval_~tmp~0#1); 5634#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5747#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5992#L599-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5993#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5903#L604-3 assume !(0 == ~T2_E~0); 5904#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5976#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5604#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5605#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5987#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6034#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6045#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6046#L644-3 assume !(0 == ~E_4~0); 6106#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5913#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5914#L292-21 assume !(1 == ~m_pc~0); 5813#L292-23 is_master_triggered_~__retres1~0#1 := 0; 5680#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5681#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5781#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5897#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5898#L311-21 assume !(1 == ~t1_pc~0); 5825#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 5637#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5638#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5706#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5754#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5755#L330-21 assume !(1 == ~t2_pc~0); 6014#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 5984#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5892#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5893#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5690#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5691#L349-21 assume 1 == ~t3_pc~0; 5937#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6077#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6082#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6048#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6049#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5773#L368-21 assume 1 == ~t4_pc~0; 5654#L369-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5655#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6081#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6071#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5580#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5581#L387-21 assume !(1 == ~t5_pc~0); 5642#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 5968#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5978#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5979#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 5682#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5683#L667-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5670#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5671#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5752#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5753#L682-3 assume !(1 == ~T4_E~0); 6080#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5792#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5793#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5867#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5868#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5994#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5676#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5677#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6019#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5612#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5965#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5906#L947 assume !(0 == start_simulation_~tmp~3#1); 5907#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5910#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5871#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5621#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 5622#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6058#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6059#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6008#L960 assume !(0 != start_simulation_~tmp___0~1#1); 5597#L928-2 [2023-11-06 22:25:19,984 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:19,984 INFO L85 PathProgramCache]: Analyzing trace with hash 793784326, now seen corresponding path program 1 times [2023-11-06 22:25:19,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:19,985 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932683477] [2023-11-06 22:25:19,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:19,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:19,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,047 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,048 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,048 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932683477] [2023-11-06 22:25:20,048 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932683477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,048 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,049 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:20,049 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1935118394] [2023-11-06 22:25:20,049 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,049 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:20,050 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,050 INFO L85 PathProgramCache]: Analyzing trace with hash -1923800974, now seen corresponding path program 2 times [2023-11-06 22:25:20,050 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,050 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884096109] [2023-11-06 22:25:20,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,094 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,094 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884096109] [2023-11-06 22:25:20,094 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884096109] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,094 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,094 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:20,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [376649276] [2023-11-06 22:25:20,095 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,095 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:20,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:20,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:20,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:20,096 INFO L87 Difference]: Start difference. First operand 552 states and 820 transitions. cyclomatic complexity: 269 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:20,143 INFO L93 Difference]: Finished difference Result 981 states and 1451 transitions. [2023-11-06 22:25:20,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1451 transitions. [2023-11-06 22:25:20,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-06 22:25:20,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1451 transitions. [2023-11-06 22:25:20,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2023-11-06 22:25:20,167 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2023-11-06 22:25:20,167 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1451 transitions. [2023-11-06 22:25:20,169 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:20,169 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-06 22:25:20,172 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1451 transitions. [2023-11-06 22:25:20,207 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2023-11-06 22:25:20,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4791029561671762) internal successors, (1451), 980 states have internal predecessors, (1451), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1451 transitions. [2023-11-06 22:25:20,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-06 22:25:20,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:20,216 INFO L428 stractBuchiCegarLoop]: Abstraction has 981 states and 1451 transitions. [2023-11-06 22:25:20,217 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:25:20,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1451 transitions. [2023-11-06 22:25:20,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-06 22:25:20,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:20,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:20,225 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,225 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,226 INFO L748 eck$LassoCheckResult]: Stem: 7423#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 7424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7693#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 7501#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7502#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7670#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7473#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7474#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7664#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7469#L599 assume !(0 == ~M_E~0); 7470#L599-2 assume !(0 == ~T1_E~0); 7128#L604-1 assume !(0 == ~T2_E~0); 7115#L609-1 assume !(0 == ~T3_E~0); 7116#L614-1 assume !(0 == ~T4_E~0); 7284#L619-1 assume !(0 == ~T5_E~0); 7400#L624-1 assume !(0 == ~E_M~0); 7506#L629-1 assume !(0 == ~E_1~0); 7205#L634-1 assume 0 == ~E_2~0;~E_2~0 := 1; 7206#L639-1 assume !(0 == ~E_3~0); 7613#L644-1 assume !(0 == ~E_4~0); 7630#L649-1 assume !(0 == ~E_5~0); 7169#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7170#L292 assume !(1 == ~m_pc~0); 7297#L292-2 is_master_triggered_~__retres1~0#1 := 0; 7441#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7396#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7397#L743 assume !(0 != activate_threads_~tmp~1#1); 7238#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7239#L311 assume 1 == ~t1_pc~0; 7373#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7374#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7163#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7142#L751 assume !(0 != activate_threads_~tmp___0~0#1); 7143#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7614#L330 assume 1 == ~t2_pc~0; 7402#L331 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7299#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7300#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7559#L759 assume !(0 != activate_threads_~tmp___1~0#1); 7691#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7285#L349 assume !(1 == ~t3_pc~0); 7286#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7333#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7117#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7118#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7684#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7685#L368 assume 1 == ~t4_pc~0; 7692#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7364#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7270#L775 assume !(0 != activate_threads_~tmp___3~0#1); 7129#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7130#L387 assume !(1 == ~t5_pc~0); 7525#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7526#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7405#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7255#L783 assume !(0 != activate_threads_~tmp___4~0#1); 7256#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7351#L667 assume !(1 == ~M_E~0); 7433#L667-2 assume !(1 == ~T1_E~0); 7620#L672-1 assume !(1 == ~T2_E~0); 7387#L677-1 assume !(1 == ~T3_E~0); 7388#L682-1 assume !(1 == ~T4_E~0); 7595#L687-1 assume !(1 == ~T5_E~0); 7659#L692-1 assume !(1 == ~E_M~0); 7583#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7584#L702-1 assume !(1 == ~E_2~0); 7629#L707-1 assume !(1 == ~E_3~0); 7490#L712-1 assume !(1 == ~E_4~0); 7491#L717-1 assume !(1 == ~E_5~0); 7602#L722-1 assume { :end_inline_reset_delta_events } true; 7137#L928-2 [2023-11-06 22:25:20,226 INFO L750 eck$LassoCheckResult]: Loop: 7137#L928-2 assume !false; 7138#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7376#L574-1 assume !false; 7377#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7683#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7338#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7770#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7768#L499 assume !(0 != eval_~tmp~0#1); 7767#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7656#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7546#L599-3 assume !(0 == ~M_E~0); 7547#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7451#L604-3 assume !(0 == ~T2_E~0); 7452#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7532#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7144#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7145#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7543#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7592#L634-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7758#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7757#L644-3 assume !(0 == ~E_4~0); 7756#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7755#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7754#L292-21 assume !(1 == ~m_pc~0); 7752#L292-23 is_master_triggered_~__retres1~0#1 := 0; 7751#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7750#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7678#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7445#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7446#L311-21 assume 1 == ~t1_pc~0; 7747#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7746#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7745#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7744#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7743#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7742#L330-21 assume 1 == ~t2_pc~0; 7699#L331-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7540#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7439#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7440#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7230#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7231#L349-21 assume !(1 == ~t3_pc~0); 7488#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 7643#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7650#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7607#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7608#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7689#L368-21 assume !(1 == ~t4_pc~0); 7729#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 7728#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7682#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7636#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7122#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7123#L387-21 assume !(1 == ~t5_pc~0); 7182#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 7524#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7534#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7535#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 7222#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7223#L667-3 assume !(1 == ~M_E~0); 7444#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7969#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7968#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7967#L682-3 assume !(1 == ~T4_E~0); 7966#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7965#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7964#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7963#L702-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7962#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7961#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7960#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7959#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7947#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7943#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7941#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 7940#L947 assume !(0 == start_simulation_~tmp~3#1); 7938#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 7934#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 7931#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 7930#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 7929#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7618#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7619#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 7564#L960 assume !(0 != start_simulation_~tmp___0~1#1); 7137#L928-2 [2023-11-06 22:25:20,227 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1473056580, now seen corresponding path program 1 times [2023-11-06 22:25:20,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368064951] [2023-11-06 22:25:20,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368064951] [2023-11-06 22:25:20,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368064951] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:20,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808884550] [2023-11-06 22:25:20,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,273 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:20,273 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,274 INFO L85 PathProgramCache]: Analyzing trace with hash 1767686066, now seen corresponding path program 1 times [2023-11-06 22:25:20,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477881211] [2023-11-06 22:25:20,274 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477881211] [2023-11-06 22:25:20,315 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477881211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,315 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:20,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982172410] [2023-11-06 22:25:20,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,316 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:20,316 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:20,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:20,317 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:20,317 INFO L87 Difference]: Start difference. First operand 981 states and 1451 transitions. cyclomatic complexity: 471 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:20,369 INFO L93 Difference]: Finished difference Result 981 states and 1429 transitions. [2023-11-06 22:25:20,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 981 states and 1429 transitions. [2023-11-06 22:25:20,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-06 22:25:20,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 981 states to 981 states and 1429 transitions. [2023-11-06 22:25:20,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 981 [2023-11-06 22:25:20,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 981 [2023-11-06 22:25:20,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 981 states and 1429 transitions. [2023-11-06 22:25:20,388 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:20,389 INFO L218 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-06 22:25:20,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 981 states and 1429 transitions. [2023-11-06 22:25:20,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 981 to 981. [2023-11-06 22:25:20,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4566768603465852) internal successors, (1429), 980 states have internal predecessors, (1429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1429 transitions. [2023-11-06 22:25:20,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-06 22:25:20,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:20,412 INFO L428 stractBuchiCegarLoop]: Abstraction has 981 states and 1429 transitions. [2023-11-06 22:25:20,412 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:25:20,413 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1429 transitions. [2023-11-06 22:25:20,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 902 [2023-11-06 22:25:20,419 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:20,419 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:20,420 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,420 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,421 INFO L748 eck$LassoCheckResult]: Stem: 9387#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9388#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9641#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 9457#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9458#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9617#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9433#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9434#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9612#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9429#L599 assume !(0 == ~M_E~0); 9430#L599-2 assume !(0 == ~T1_E~0); 9097#L604-1 assume !(0 == ~T2_E~0); 9084#L609-1 assume !(0 == ~T3_E~0); 9085#L614-1 assume !(0 == ~T4_E~0); 9252#L619-1 assume !(0 == ~T5_E~0); 9365#L624-1 assume !(0 == ~E_M~0); 9461#L629-1 assume !(0 == ~E_1~0); 9174#L634-1 assume !(0 == ~E_2~0); 9175#L639-1 assume !(0 == ~E_3~0); 9566#L644-1 assume !(0 == ~E_4~0); 9583#L649-1 assume !(0 == ~E_5~0); 9138#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9139#L292 assume !(1 == ~m_pc~0); 9265#L292-2 is_master_triggered_~__retres1~0#1 := 0; 9402#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9363#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9364#L743 assume !(0 != activate_threads_~tmp~1#1); 9207#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9208#L311 assume 1 == ~t1_pc~0; 9339#L312 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9340#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9132#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9111#L751 assume !(0 != activate_threads_~tmp___0~0#1); 9112#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9569#L330 assume !(1 == ~t2_pc~0); 9368#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9268#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9269#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9514#L759 assume !(0 != activate_threads_~tmp___1~0#1); 9639#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9254#L349 assume !(1 == ~t3_pc~0); 9255#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9303#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9091#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9092#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9633#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9634#L368 assume 1 == ~t4_pc~0; 9640#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9332#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9238#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9239#L775 assume !(0 != activate_threads_~tmp___3~0#1); 9098#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9099#L387 assume !(1 == ~t5_pc~0); 9479#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9480#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9370#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9227#L783 assume !(0 != activate_threads_~tmp___4~0#1); 9228#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9320#L667 assume !(1 == ~M_E~0); 9394#L667-2 assume !(1 == ~T1_E~0); 9575#L672-1 assume !(1 == ~T2_E~0); 9352#L677-1 assume !(1 == ~T3_E~0); 9353#L682-1 assume !(1 == ~T4_E~0); 9549#L687-1 assume !(1 == ~T5_E~0); 9607#L692-1 assume !(1 == ~E_M~0); 9538#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9539#L702-1 assume !(1 == ~E_2~0); 9582#L707-1 assume !(1 == ~E_3~0); 9448#L712-1 assume !(1 == ~E_4~0); 9449#L717-1 assume !(1 == ~E_5~0); 9556#L722-1 assume { :end_inline_reset_delta_events } true; 9106#L928-2 [2023-11-06 22:25:20,421 INFO L750 eck$LassoCheckResult]: Loop: 9106#L928-2 assume !false; 9107#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9718#L574-1 assume !false; 9717#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9713#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9615#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9531#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9142#L499 assume !(0 != eval_~tmp~0#1); 9144#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9253#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9707#L599-3 assume !(0 == ~M_E~0); 9706#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9705#L604-3 assume !(0 == ~T2_E~0); 9704#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9703#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9702#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9701#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9700#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9602#L634-3 assume !(0 == ~E_2~0); 9557#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9558#L644-3 assume !(0 == ~E_4~0); 9636#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9653#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9696#L292-21 assume !(1 == ~m_pc~0); 9694#L292-23 is_master_triggered_~__retres1~0#1 := 0; 9693#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9692#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9626#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9406#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9407#L311-21 assume 1 == ~t1_pc~0; 9689#L312-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9688#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9687#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9686#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9685#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9683#L330-21 assume !(1 == ~t2_pc~0); 9618#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 9494#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9400#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9401#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9199#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9200#L349-21 assume 1 == ~t3_pc~0; 9445#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9593#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9598#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9560#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9561#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9638#L368-21 assume !(1 == ~t4_pc~0); 9670#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 9669#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9631#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9587#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9089#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9090#L387-21 assume !(1 == ~t5_pc~0); 9152#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 9478#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9488#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9489#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 9191#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9192#L667-3 assume !(1 == ~M_E~0); 9405#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9841#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9839#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9837#L682-3 assume !(1 == ~T4_E~0); 9835#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9834#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9833#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9832#L702-3 assume !(1 == ~E_2~0); 9831#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9829#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9827#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9825#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9816#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9812#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9810#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9809#L947 assume !(0 == start_simulation_~tmp~3#1); 9807#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9782#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9775#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9771#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 9749#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9742#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9621#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9519#L960 assume !(0 != start_simulation_~tmp___0~1#1); 9106#L928-2 [2023-11-06 22:25:20,422 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,422 INFO L85 PathProgramCache]: Analyzing trace with hash -820631741, now seen corresponding path program 1 times [2023-11-06 22:25:20,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089031094] [2023-11-06 22:25:20,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089031094] [2023-11-06 22:25:20,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089031094] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:20,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1991783708] [2023-11-06 22:25:20,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,481 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:20,481 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,481 INFO L85 PathProgramCache]: Analyzing trace with hash -982956238, now seen corresponding path program 1 times [2023-11-06 22:25:20,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308636292] [2023-11-06 22:25:20,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:20,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:20,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:20,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308636292] [2023-11-06 22:25:20,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308636292] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:20,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:20,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:20,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22438948] [2023-11-06 22:25:20,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:20,525 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:20,525 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:20,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:25:20,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:25:20,526 INFO L87 Difference]: Start difference. First operand 981 states and 1429 transitions. cyclomatic complexity: 449 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:20,761 INFO L93 Difference]: Finished difference Result 2628 states and 3762 transitions. [2023-11-06 22:25:20,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2628 states and 3762 transitions. [2023-11-06 22:25:20,808 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2453 [2023-11-06 22:25:20,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2628 states to 2628 states and 3762 transitions. [2023-11-06 22:25:20,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2628 [2023-11-06 22:25:20,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2628 [2023-11-06 22:25:20,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2628 states and 3762 transitions. [2023-11-06 22:25:20,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:20,839 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2628 states and 3762 transitions. [2023-11-06 22:25:20,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2628 states and 3762 transitions. [2023-11-06 22:25:20,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2628 to 2468. [2023-11-06 22:25:20,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2468 states, 2468 states have (on average 1.4376012965964344) internal successors, (3548), 2467 states have internal predecessors, (3548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:20,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2468 states to 2468 states and 3548 transitions. [2023-11-06 22:25:20,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2468 states and 3548 transitions. [2023-11-06 22:25:20,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:25:20,910 INFO L428 stractBuchiCegarLoop]: Abstraction has 2468 states and 3548 transitions. [2023-11-06 22:25:20,911 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:25:20,911 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2468 states and 3548 transitions. [2023-11-06 22:25:20,928 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2381 [2023-11-06 22:25:20,928 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:20,928 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:20,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:20,931 INFO L748 eck$LassoCheckResult]: Stem: 13017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 13158#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13159#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13349#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 13096#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13097#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13314#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13068#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13069#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13305#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13064#L599 assume !(0 == ~M_E~0); 13065#L599-2 assume !(0 == ~T1_E~0); 12716#L604-1 assume !(0 == ~T2_E~0); 12703#L609-1 assume !(0 == ~T3_E~0); 12704#L614-1 assume !(0 == ~T4_E~0); 12872#L619-1 assume !(0 == ~T5_E~0); 12993#L624-1 assume !(0 == ~E_M~0); 13102#L629-1 assume !(0 == ~E_1~0); 12792#L634-1 assume !(0 == ~E_2~0); 12793#L639-1 assume !(0 == ~E_3~0); 13237#L644-1 assume !(0 == ~E_4~0); 13261#L649-1 assume !(0 == ~E_5~0); 12758#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12759#L292 assume !(1 == ~m_pc~0); 12886#L292-2 is_master_triggered_~__retres1~0#1 := 0; 13038#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12991#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12992#L743 assume !(0 != activate_threads_~tmp~1#1); 12826#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12827#L311 assume !(1 == ~t1_pc~0); 13235#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13111#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12731#L751 assume !(0 != activate_threads_~tmp___0~0#1); 12732#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13238#L330 assume !(1 == ~t2_pc~0); 12996#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12887#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12888#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13164#L759 assume !(0 != activate_threads_~tmp___1~0#1); 13344#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12873#L349 assume !(1 == ~t3_pc~0); 12874#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12924#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12708#L767 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13338#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13339#L368 assume 1 == ~t4_pc~0; 13346#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12957#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12859#L775 assume !(0 != activate_threads_~tmp___3~0#1); 12717#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12718#L387 assume !(1 == ~t5_pc~0); 13126#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13127#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12998#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12844#L783 assume !(0 != activate_threads_~tmp___4~0#1); 12845#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12945#L667 assume !(1 == ~M_E~0); 13029#L667-2 assume !(1 == ~T1_E~0); 13246#L672-1 assume !(1 == ~T2_E~0); 12979#L677-1 assume !(1 == ~T3_E~0); 12980#L682-1 assume !(1 == ~T4_E~0); 13213#L687-1 assume !(1 == ~T5_E~0); 13301#L692-1 assume !(1 == ~E_M~0); 13195#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13196#L702-1 assume !(1 == ~E_2~0); 13260#L707-1 assume !(1 == ~E_3~0); 13088#L712-1 assume !(1 == ~E_4~0); 13089#L717-1 assume !(1 == ~E_5~0); 13221#L722-1 assume { :end_inline_reset_delta_events } true; 12725#L928-2 [2023-11-06 22:25:20,931 INFO L750 eck$LassoCheckResult]: Loop: 12725#L928-2 assume !false; 12726#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12967#L574-1 assume !false; 12968#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13334#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14275#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14276#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14256#L499 assume !(0 != eval_~tmp~0#1); 14258#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14850#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13147#L599-3 assume !(0 == ~M_E~0); 13148#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14991#L604-3 assume !(0 == ~T2_E~0); 14990#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14989#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14988#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14987#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13208#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13209#L634-3 assume !(0 == ~E_2~0); 13222#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13223#L644-3 assume !(0 == ~E_4~0); 13341#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13057#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13058#L292-21 assume !(1 == ~m_pc~0); 12947#L292-23 is_master_triggered_~__retres1~0#1 := 0; 12805#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12806#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12911#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13041#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13042#L311-21 assume !(1 == ~t1_pc~0); 12960#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 12766#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12767#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12834#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12884#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12885#L330-21 assume !(1 == ~t2_pc~0); 13176#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 13142#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13035#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13036#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12817#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12818#L349-21 assume 1 == ~t3_pc~0; 13085#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13275#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13290#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13229#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13230#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12903#L368-21 assume !(1 == ~t4_pc~0); 12784#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 12783#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13287#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13269#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12705#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12706#L387-21 assume !(1 == ~t5_pc~0); 12771#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 13125#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13134#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13135#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 12810#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12811#L667-3 assume !(1 == ~M_E~0); 12794#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12795#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13241#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14925#L682-3 assume !(1 == ~T4_E~0); 14923#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14922#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 14920#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14918#L702-3 assume !(1 == ~E_2~0); 14916#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14914#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14913#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14912#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14906#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 14903#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 14902#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14891#L947 assume !(0 == start_simulation_~tmp~3#1); 13398#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 13055#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13007#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 12750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 12751#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13244#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13245#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13318#L960 assume !(0 != start_simulation_~tmp___0~1#1); 12725#L928-2 [2023-11-06 22:25:20,932 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:20,932 INFO L85 PathProgramCache]: Analyzing trace with hash 1077898564, now seen corresponding path program 1 times [2023-11-06 22:25:20,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:20,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119412439] [2023-11-06 22:25:20,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:20,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:20,947 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:21,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:21,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:21,003 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119412439] [2023-11-06 22:25:21,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119412439] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:21,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:21,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:21,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [960185923] [2023-11-06 22:25:21,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:21,004 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:21,005 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:21,005 INFO L85 PathProgramCache]: Analyzing trace with hash -2091084877, now seen corresponding path program 1 times [2023-11-06 22:25:21,005 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:21,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [684097272] [2023-11-06 22:25:21,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:21,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:21,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:21,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:21,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:21,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [684097272] [2023-11-06 22:25:21,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [684097272] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:21,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:21,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:21,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772909056] [2023-11-06 22:25:21,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:21,046 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:21,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:21,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:25:21,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:25:21,047 INFO L87 Difference]: Start difference. First operand 2468 states and 3548 transitions. cyclomatic complexity: 1082 Second operand has 5 states, 5 states have (on average 14.6) internal successors, (73), 5 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:21,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:21,349 INFO L93 Difference]: Finished difference Result 5373 states and 7638 transitions. [2023-11-06 22:25:21,349 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5373 states and 7638 transitions. [2023-11-06 22:25:21,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5230 [2023-11-06 22:25:21,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5373 states to 5373 states and 7638 transitions. [2023-11-06 22:25:21,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5373 [2023-11-06 22:25:21,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5373 [2023-11-06 22:25:21,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5373 states and 7638 transitions. [2023-11-06 22:25:21,443 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:21,443 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5373 states and 7638 transitions. [2023-11-06 22:25:21,449 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5373 states and 7638 transitions. [2023-11-06 22:25:21,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5373 to 2588. [2023-11-06 22:25:21,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2588 states, 2588 states have (on average 1.4173106646058733) internal successors, (3668), 2587 states have internal predecessors, (3668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:21,559 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2588 states to 2588 states and 3668 transitions. [2023-11-06 22:25:21,560 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2588 states and 3668 transitions. [2023-11-06 22:25:21,560 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:25:21,561 INFO L428 stractBuchiCegarLoop]: Abstraction has 2588 states and 3668 transitions. [2023-11-06 22:25:21,561 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:25:21,561 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2588 states and 3668 transitions. [2023-11-06 22:25:21,572 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2498 [2023-11-06 22:25:21,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:21,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:21,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:21,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:21,574 INFO L748 eck$LassoCheckResult]: Stem: 20861#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 20862#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 20999#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21000#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21173#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 20940#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20941#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21139#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20914#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20915#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21134#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20910#L599 assume !(0 == ~M_E~0); 20911#L599-2 assume !(0 == ~T1_E~0); 20570#L604-1 assume !(0 == ~T2_E~0); 20557#L609-1 assume !(0 == ~T3_E~0); 20558#L614-1 assume !(0 == ~T4_E~0); 20723#L619-1 assume !(0 == ~T5_E~0); 20839#L624-1 assume !(0 == ~E_M~0); 20944#L629-1 assume !(0 == ~E_1~0); 20646#L634-1 assume !(0 == ~E_2~0); 20647#L639-1 assume !(0 == ~E_3~0); 21076#L644-1 assume !(0 == ~E_4~0); 21091#L649-1 assume !(0 == ~E_5~0); 20611#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20612#L292 assume !(1 == ~m_pc~0); 20737#L292-2 is_master_triggered_~__retres1~0#1 := 0; 20878#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20837#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 20838#L743 assume !(0 != activate_threads_~tmp~1#1); 20680#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20681#L311 assume !(1 == ~t1_pc~0); 21073#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 20953#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20605#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20584#L751 assume !(0 != activate_threads_~tmp___0~0#1); 20585#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21079#L330 assume !(1 == ~t2_pc~0); 20842#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20739#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20740#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 21004#L759 assume !(0 != activate_threads_~tmp___1~0#1); 21169#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20726#L349 assume !(1 == ~t3_pc~0); 20727#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21036#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 21037#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21216#L767 assume !(0 != activate_threads_~tmp___2~0#1); 21164#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21165#L368 assume 1 == ~t4_pc~0; 21172#L369 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20806#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20708#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20709#L775 assume !(0 != activate_threads_~tmp___3~0#1); 20571#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20572#L387 assume !(1 == ~t5_pc~0); 20966#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20967#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20844#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20697#L783 assume !(0 != activate_threads_~tmp___4~0#1); 20698#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20792#L667 assume !(1 == ~M_E~0); 20870#L667-2 assume !(1 == ~T1_E~0); 21085#L672-1 assume !(1 == ~T2_E~0); 20825#L677-1 assume !(1 == ~T3_E~0); 20826#L682-1 assume !(1 == ~T4_E~0); 21049#L687-1 assume !(1 == ~T5_E~0); 21126#L692-1 assume !(1 == ~E_M~0); 21034#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21035#L702-1 assume !(1 == ~E_2~0); 21090#L707-1 assume !(1 == ~E_3~0); 20931#L712-1 assume !(1 == ~E_4~0); 20932#L717-1 assume !(1 == ~E_5~0); 21059#L722-1 assume { :end_inline_reset_delta_events } true; 21060#L928-2 [2023-11-06 22:25:21,575 INFO L750 eck$LassoCheckResult]: Loop: 21060#L928-2 assume !false; 22164#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22147#L574-1 assume !false; 22148#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 21205#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 20778#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22319#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22310#L499 assume !(0 != eval_~tmp~0#1); 20724#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20725#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20987#L599-3 assume !(0 == ~M_E~0); 20988#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20889#L604-3 assume !(0 == ~T2_E~0); 20890#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20975#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20586#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20587#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20984#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21045#L634-3 assume !(0 == ~E_2~0); 21061#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21062#L644-3 assume !(0 == ~E_4~0); 21167#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20901#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20902#L292-21 assume !(1 == ~m_pc~0); 21031#L292-23 is_master_triggered_~__retres1~0#1 := 0; 23138#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23137#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 23136#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20881#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20882#L311-21 assume !(1 == ~t1_pc~0); 20807#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 20619#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20620#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 20688#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20735#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20736#L330-21 assume !(1 == ~t2_pc~0); 21016#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 20982#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20875#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20876#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 23125#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20927#L349-21 assume 1 == ~t3_pc~0; 20928#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23123#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23121#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 23119#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23118#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23117#L368-21 assume !(1 == ~t4_pc~0); 23115#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 21115#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21116#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21098#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20559#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20560#L387-21 assume !(1 == ~t5_pc~0); 20624#L387-23 is_transmit5_triggered_~__retres1~5#1 := 0; 20965#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20973#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20974#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 20664#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20665#L667-3 assume !(1 == ~M_E~0); 20648#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20649#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20733#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20734#L682-3 assume !(1 == ~T4_E~0); 21114#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20772#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 20773#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20849#L702-3 assume !(1 == ~E_2~0); 20850#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22956#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22955#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22954#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22950#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22946#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 20962#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 20893#L947 assume !(0 == start_simulation_~tmp~3#1); 20894#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 22609#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 22603#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 22600#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 22598#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22595#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22592#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 22166#L960 assume !(0 != start_simulation_~tmp___0~1#1); 21060#L928-2 [2023-11-06 22:25:21,575 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:21,575 INFO L85 PathProgramCache]: Analyzing trace with hash -1293840698, now seen corresponding path program 1 times [2023-11-06 22:25:21,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:21,576 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [331733914] [2023-11-06 22:25:21,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:21,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:21,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:21,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:21,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:21,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [331733914] [2023-11-06 22:25:21,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [331733914] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:21,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:21,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:21,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104390110] [2023-11-06 22:25:21,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:21,622 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:21,623 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:21,623 INFO L85 PathProgramCache]: Analyzing trace with hash -2091084877, now seen corresponding path program 2 times [2023-11-06 22:25:21,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:21,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600099330] [2023-11-06 22:25:21,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:21,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:21,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:21,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:21,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:21,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600099330] [2023-11-06 22:25:21,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600099330] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:21,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:21,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:21,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220182517] [2023-11-06 22:25:21,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:21,665 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:21,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:21,666 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:21,666 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:21,666 INFO L87 Difference]: Start difference. First operand 2588 states and 3668 transitions. cyclomatic complexity: 1082 Second operand has 3 states, 3 states have (on average 24.333333333333332) internal successors, (73), 2 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:21,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:21,754 INFO L93 Difference]: Finished difference Result 4780 states and 6742 transitions. [2023-11-06 22:25:21,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4780 states and 6742 transitions. [2023-11-06 22:25:21,785 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4669 [2023-11-06 22:25:21,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4780 states to 4780 states and 6742 transitions. [2023-11-06 22:25:21,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4780 [2023-11-06 22:25:21,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4780 [2023-11-06 22:25:21,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4780 states and 6742 transitions. [2023-11-06 22:25:21,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:21,834 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4780 states and 6742 transitions. [2023-11-06 22:25:21,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4780 states and 6742 transitions. [2023-11-06 22:25:21,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4780 to 4768. [2023-11-06 22:25:21,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4768 states, 4768 states have (on average 1.411493288590604) internal successors, (6730), 4767 states have internal predecessors, (6730), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:21,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4768 states to 4768 states and 6730 transitions. [2023-11-06 22:25:21,935 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4768 states and 6730 transitions. [2023-11-06 22:25:21,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:21,936 INFO L428 stractBuchiCegarLoop]: Abstraction has 4768 states and 6730 transitions. [2023-11-06 22:25:21,936 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:25:21,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4768 states and 6730 transitions. [2023-11-06 22:25:21,956 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4657 [2023-11-06 22:25:21,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:21,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:21,958 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:21,958 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:21,958 INFO L748 eck$LassoCheckResult]: Stem: 28243#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 28244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 28367#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28368#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28507#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 28313#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28314#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28486#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28290#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28291#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28483#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28286#L599 assume !(0 == ~M_E~0); 28287#L599-2 assume !(0 == ~T1_E~0); 27945#L604-1 assume !(0 == ~T2_E~0); 27932#L609-1 assume !(0 == ~T3_E~0); 27933#L614-1 assume !(0 == ~T4_E~0); 28098#L619-1 assume !(0 == ~T5_E~0); 28219#L624-1 assume !(0 == ~E_M~0); 28317#L629-1 assume !(0 == ~E_1~0); 28021#L634-1 assume !(0 == ~E_2~0); 28022#L639-1 assume !(0 == ~E_3~0); 28432#L644-1 assume !(0 == ~E_4~0); 28448#L649-1 assume !(0 == ~E_5~0); 27986#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27987#L292 assume !(1 == ~m_pc~0); 28111#L292-2 is_master_triggered_~__retres1~0#1 := 0; 28257#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28217#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 28218#L743 assume !(0 != activate_threads_~tmp~1#1); 28054#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 28055#L311 assume !(1 == ~t1_pc~0); 28430#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28326#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27980#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 27959#L751 assume !(0 != activate_threads_~tmp___0~0#1); 27960#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28435#L330 assume !(1 == ~t2_pc~0); 28223#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 28113#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 28114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 28372#L759 assume !(0 != activate_threads_~tmp___1~0#1); 28506#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28100#L349 assume !(1 == ~t3_pc~0); 28101#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28399#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28400#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 28545#L767 assume !(0 != activate_threads_~tmp___2~0#1); 28501#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28502#L368 assume !(1 == ~t4_pc~0); 28185#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 28186#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28083#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28084#L775 assume !(0 != activate_threads_~tmp___3~0#1); 27946#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27947#L387 assume !(1 == ~t5_pc~0); 28338#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 28339#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28225#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 28072#L783 assume !(0 != activate_threads_~tmp___4~0#1); 28073#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28169#L667 assume !(1 == ~M_E~0); 28250#L667-2 assume !(1 == ~T1_E~0); 28442#L672-1 assume !(1 == ~T2_E~0); 28205#L677-1 assume !(1 == ~T3_E~0); 28206#L682-1 assume !(1 == ~T4_E~0); 28412#L687-1 assume !(1 == ~T5_E~0); 28476#L692-1 assume !(1 == ~E_M~0); 28397#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28398#L702-1 assume !(1 == ~E_2~0); 28447#L707-1 assume !(1 == ~E_3~0); 28306#L712-1 assume !(1 == ~E_4~0); 28307#L717-1 assume !(1 == ~E_5~0); 28419#L722-1 assume { :end_inline_reset_delta_events } true; 28420#L928-2 [2023-11-06 22:25:21,959 INFO L750 eck$LassoCheckResult]: Loop: 28420#L928-2 assume !false; 31752#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31750#L574-1 assume !false; 31749#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31738#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31734#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31732#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 31408#L499 assume !(0 != eval_~tmp~0#1); 31409#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31945#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31943#L599-3 assume !(0 == ~M_E~0); 31941#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31939#L604-3 assume !(0 == ~T2_E~0); 31937#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31935#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31933#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31931#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31929#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31927#L634-3 assume !(0 == ~E_2~0); 31925#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31923#L644-3 assume !(0 == ~E_4~0); 31921#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31919#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31917#L292-21 assume !(1 == ~m_pc~0); 31915#L292-23 is_master_triggered_~__retres1~0#1 := 0; 31913#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31911#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 31909#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31907#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31905#L311-21 assume !(1 == ~t1_pc~0); 31903#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 31902#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31899#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31897#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31895#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31891#L330-21 assume !(1 == ~t2_pc~0); 31889#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 31885#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31883#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31881#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31879#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31876#L349-21 assume !(1 == ~t3_pc~0); 31872#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 31870#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31868#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31866#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 31863#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31861#L368-21 assume !(1 == ~t4_pc~0); 31859#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 31857#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 31854#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31852#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 31850#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31848#L387-21 assume 1 == ~t5_pc~0; 31845#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31844#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31843#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 31841#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 31839#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31837#L667-3 assume !(1 == ~M_E~0); 31833#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31831#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31829#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31827#L682-3 assume !(1 == ~T4_E~0); 31825#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31823#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31821#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31819#L702-3 assume !(1 == ~E_2~0); 31817#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31814#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31812#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31810#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31793#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31789#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31787#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 31785#L947 assume !(0 == start_simulation_~tmp~3#1); 31782#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 31771#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 31767#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31765#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 31761#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31759#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31757#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 31756#L960 assume !(0 != start_simulation_~tmp___0~1#1); 28420#L928-2 [2023-11-06 22:25:21,959 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:21,960 INFO L85 PathProgramCache]: Analyzing trace with hash 943522567, now seen corresponding path program 1 times [2023-11-06 22:25:21,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:21,960 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113321685] [2023-11-06 22:25:21,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:21,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:21,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:22,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:22,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:22,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [113321685] [2023-11-06 22:25:22,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [113321685] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:22,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:22,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:22,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1300278050] [2023-11-06 22:25:22,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:22,087 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:22,088 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:22,088 INFO L85 PathProgramCache]: Analyzing trace with hash -266450763, now seen corresponding path program 1 times [2023-11-06 22:25:22,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:22,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [873209547] [2023-11-06 22:25:22,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:22,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:22,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:22,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:22,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:22,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [873209547] [2023-11-06 22:25:22,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [873209547] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:22,129 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:22,129 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:22,129 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [429054102] [2023-11-06 22:25:22,129 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:22,130 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:22,130 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:22,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:25:22,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:25:22,131 INFO L87 Difference]: Start difference. First operand 4768 states and 6730 transitions. cyclomatic complexity: 1966 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:22,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:22,278 INFO L93 Difference]: Finished difference Result 7594 states and 10646 transitions. [2023-11-06 22:25:22,278 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7594 states and 10646 transitions. [2023-11-06 22:25:22,319 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7389 [2023-11-06 22:25:22,368 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7594 states to 7594 states and 10646 transitions. [2023-11-06 22:25:22,368 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7594 [2023-11-06 22:25:22,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7594 [2023-11-06 22:25:22,377 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7594 states and 10646 transitions. [2023-11-06 22:25:22,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:22,387 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7594 states and 10646 transitions. [2023-11-06 22:25:22,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7594 states and 10646 transitions. [2023-11-06 22:25:22,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7594 to 5497. [2023-11-06 22:25:22,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5497 states, 5497 states have (on average 1.4053119883572858) internal successors, (7725), 5496 states have internal predecessors, (7725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:22,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5497 states to 5497 states and 7725 transitions. [2023-11-06 22:25:22,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5497 states and 7725 transitions. [2023-11-06 22:25:22,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:25:22,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 5497 states and 7725 transitions. [2023-11-06 22:25:22,600 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:25:22,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5497 states and 7725 transitions. [2023-11-06 22:25:22,623 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5331 [2023-11-06 22:25:22,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:22,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:22,625 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:22,625 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:22,626 INFO L748 eck$LassoCheckResult]: Stem: 40611#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 40612#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 40752#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 40753#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40931#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 40686#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40687#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40895#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40662#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40663#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40889#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40658#L599 assume !(0 == ~M_E~0); 40659#L599-2 assume !(0 == ~T1_E~0); 40317#L604-1 assume !(0 == ~T2_E~0); 40304#L609-1 assume !(0 == ~T3_E~0); 40305#L614-1 assume !(0 == ~T4_E~0); 40468#L619-1 assume !(0 == ~T5_E~0); 40585#L624-1 assume !(0 == ~E_M~0); 40690#L629-1 assume 0 == ~E_1~0;~E_1~0 := 1; 40965#L634-1 assume !(0 == ~E_2~0); 40826#L639-1 assume !(0 == ~E_3~0); 40827#L644-1 assume !(0 == ~E_4~0); 40846#L649-1 assume !(0 == ~E_5~0); 40847#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 40482#L292 assume !(1 == ~m_pc~0); 40483#L292-2 is_master_triggered_~__retres1~0#1 := 0; 40746#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40747#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40949#L743 assume !(0 != activate_threads_~tmp~1#1); 40950#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40824#L311 assume !(1 == ~t1_pc~0); 40825#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40698#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40331#L751 assume !(0 != activate_threads_~tmp___0~0#1); 40332#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40830#L330 assume !(1 == ~t2_pc~0); 40589#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 40485#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 40486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 40924#L759 assume !(0 != activate_threads_~tmp___1~0#1); 40925#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40469#L349 assume !(1 == ~t3_pc~0); 40470#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41015#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41013#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40974#L767 assume !(0 != activate_threads_~tmp___2~0#1); 40917#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40918#L368 assume !(1 == ~t4_pc~0); 40550#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40551#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40873#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 41001#L775 assume !(0 != activate_threads_~tmp___3~0#1); 41000#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40999#L387 assume !(1 == ~t5_pc~0); 40997#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40978#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40591#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 40592#L783 assume !(0 != activate_threads_~tmp___4~0#1); 40995#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40994#L667 assume !(1 == ~M_E~0); 40993#L667-2 assume !(1 == ~T1_E~0); 40992#L672-1 assume !(1 == ~T2_E~0); 40991#L677-1 assume !(1 == ~T3_E~0); 40990#L682-1 assume !(1 == ~T4_E~0); 40989#L687-1 assume !(1 == ~T5_E~0); 40988#L692-1 assume !(1 == ~E_M~0); 40987#L697-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40792#L702-1 assume !(1 == ~E_2~0); 40843#L707-1 assume !(1 == ~E_3~0); 40678#L712-1 assume !(1 == ~E_4~0); 40679#L717-1 assume !(1 == ~E_5~0); 40812#L722-1 assume { :end_inline_reset_delta_events } true; 40813#L928-2 [2023-11-06 22:25:22,626 INFO L750 eck$LassoCheckResult]: Loop: 40813#L928-2 assume !false; 43824#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 43822#L574-1 assume !false; 43821#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 43777#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 43773#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 43771#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 43769#L499 assume !(0 != eval_~tmp~0#1); 43770#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45455#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45453#L599-3 assume !(0 == ~M_E~0); 45451#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44193#L604-3 assume !(0 == ~T2_E~0); 44190#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44186#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 44182#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44181#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44179#L629-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44178#L634-3 assume !(0 == ~E_2~0); 44177#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44176#L644-3 assume !(0 == ~E_4~0); 44175#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 44174#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 44173#L292-21 assume !(1 == ~m_pc~0); 44172#L292-23 is_master_triggered_~__retres1~0#1 := 0; 44171#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 44170#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 44169#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 44168#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 44167#L311-21 assume !(1 == ~t1_pc~0); 44166#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 44165#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44164#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 44163#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 44162#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 44160#L330-21 assume !(1 == ~t2_pc~0); 44159#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 44158#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 44157#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 44156#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 44155#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 44154#L349-21 assume 1 == ~t3_pc~0; 44152#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 44150#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 44148#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 44146#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 44145#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 44144#L368-21 assume !(1 == ~t4_pc~0); 44143#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 44142#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44141#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 44140#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 44139#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 44138#L387-21 assume 1 == ~t5_pc~0; 44136#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 44135#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 44134#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 44133#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 44132#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44131#L667-3 assume !(1 == ~M_E~0); 43023#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44130#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44129#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44128#L682-3 assume !(1 == ~T4_E~0); 44127#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44126#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 44124#L697-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44123#L702-3 assume !(1 == ~E_2~0); 44122#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44121#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44120#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44119#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 44115#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 44112#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 44111#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 42820#L947 assume !(0 == start_simulation_~tmp~3#1); 42821#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 43846#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 43843#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 43842#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 43839#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 43835#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 43831#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 43830#L960 assume !(0 != start_simulation_~tmp___0~1#1); 40813#L928-2 [2023-11-06 22:25:22,627 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:22,627 INFO L85 PathProgramCache]: Analyzing trace with hash -443262843, now seen corresponding path program 1 times [2023-11-06 22:25:22,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:22,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572333878] [2023-11-06 22:25:22,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:22,628 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:22,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:22,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:22,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:22,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572333878] [2023-11-06 22:25:22,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572333878] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:22,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:22,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:22,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863238543] [2023-11-06 22:25:22,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:22,681 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:22,682 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:22,682 INFO L85 PathProgramCache]: Analyzing trace with hash -319613902, now seen corresponding path program 1 times [2023-11-06 22:25:22,682 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:22,682 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857308685] [2023-11-06 22:25:22,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:22,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:22,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:22,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:22,731 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:22,731 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857308685] [2023-11-06 22:25:22,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857308685] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:22,731 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:22,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:22,732 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499201438] [2023-11-06 22:25:22,732 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:22,732 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:22,732 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:22,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:25:22,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:25:22,733 INFO L87 Difference]: Start difference. First operand 5497 states and 7725 transitions. cyclomatic complexity: 2232 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:22,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:22,847 INFO L93 Difference]: Finished difference Result 6718 states and 9389 transitions. [2023-11-06 22:25:22,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6718 states and 9389 transitions. [2023-11-06 22:25:22,945 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6573 [2023-11-06 22:25:22,985 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6718 states to 6718 states and 9389 transitions. [2023-11-06 22:25:22,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6718 [2023-11-06 22:25:22,993 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6718 [2023-11-06 22:25:22,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6718 states and 9389 transitions. [2023-11-06 22:25:23,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:23,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6718 states and 9389 transitions. [2023-11-06 22:25:23,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6718 states and 9389 transitions. [2023-11-06 22:25:23,118 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6718 to 4768. [2023-11-06 22:25:23,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4768 states, 4768 states have (on average 1.398489932885906) internal successors, (6668), 4767 states have internal predecessors, (6668), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:23,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4768 states to 4768 states and 6668 transitions. [2023-11-06 22:25:23,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4768 states and 6668 transitions. [2023-11-06 22:25:23,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:25:23,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 4768 states and 6668 transitions. [2023-11-06 22:25:23,163 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:25:23,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4768 states and 6668 transitions. [2023-11-06 22:25:23,187 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4657 [2023-11-06 22:25:23,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:23,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:23,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:23,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:23,189 INFO L748 eck$LassoCheckResult]: Stem: 52835#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 52836#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 52962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 52963#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53102#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 52907#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52908#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53082#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52884#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52885#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53076#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52880#L599 assume !(0 == ~M_E~0); 52881#L599-2 assume !(0 == ~T1_E~0); 52542#L604-1 assume !(0 == ~T2_E~0); 52529#L609-1 assume !(0 == ~T3_E~0); 52530#L614-1 assume !(0 == ~T4_E~0); 52692#L619-1 assume !(0 == ~T5_E~0); 52809#L624-1 assume !(0 == ~E_M~0); 52911#L629-1 assume !(0 == ~E_1~0); 52619#L634-1 assume !(0 == ~E_2~0); 52620#L639-1 assume !(0 == ~E_3~0); 53029#L644-1 assume !(0 == ~E_4~0); 53047#L649-1 assume !(0 == ~E_5~0); 52583#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52584#L292 assume !(1 == ~m_pc~0); 52706#L292-2 is_master_triggered_~__retres1~0#1 := 0; 52850#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 52807#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 52808#L743 assume !(0 != activate_threads_~tmp~1#1); 52651#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52652#L311 assume !(1 == ~t1_pc~0); 53027#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 52919#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52577#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 52556#L751 assume !(0 != activate_threads_~tmp___0~0#1); 52557#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53032#L330 assume !(1 == ~t2_pc~0); 52813#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52708#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52709#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52967#L759 assume !(0 != activate_threads_~tmp___1~0#1); 53101#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52695#L349 assume !(1 == ~t3_pc~0); 52696#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52997#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52998#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53143#L767 assume !(0 != activate_threads_~tmp___2~0#1); 53095#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53096#L368 assume !(1 == ~t4_pc~0); 52776#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 52777#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52678#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52679#L775 assume !(0 != activate_threads_~tmp___3~0#1); 52543#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 52544#L387 assume !(1 == ~t5_pc~0); 52932#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52933#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 52815#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52668#L783 assume !(0 != activate_threads_~tmp___4~0#1); 52669#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52763#L667 assume !(1 == ~M_E~0); 52842#L667-2 assume !(1 == ~T1_E~0); 53038#L672-1 assume !(1 == ~T2_E~0); 52795#L677-1 assume !(1 == ~T3_E~0); 52796#L682-1 assume !(1 == ~T4_E~0); 53009#L687-1 assume !(1 == ~T5_E~0); 53070#L692-1 assume !(1 == ~E_M~0); 52995#L697-1 assume !(1 == ~E_1~0); 52996#L702-1 assume !(1 == ~E_2~0); 53046#L707-1 assume !(1 == ~E_3~0); 52900#L712-1 assume !(1 == ~E_4~0); 52901#L717-1 assume !(1 == ~E_5~0); 53016#L722-1 assume { :end_inline_reset_delta_events } true; 53017#L928-2 [2023-11-06 22:25:23,190 INFO L750 eck$LassoCheckResult]: Loop: 53017#L928-2 assume !false; 54893#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54885#L574-1 assume !false; 54882#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54877#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54872#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54871#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54866#L499 assume !(0 != eval_~tmp~0#1); 54867#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55334#L599-3 assume !(0 == ~M_E~0); 55333#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55332#L604-3 assume !(0 == ~T2_E~0); 55331#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55330#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55329#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55328#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55327#L629-3 assume !(0 == ~E_1~0); 55326#L634-3 assume !(0 == ~E_2~0); 55325#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55324#L644-3 assume !(0 == ~E_4~0); 55323#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55322#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55321#L292-21 assume !(1 == ~m_pc~0); 55320#L292-23 is_master_triggered_~__retres1~0#1 := 0; 55319#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55318#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 55317#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55316#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55315#L311-21 assume !(1 == ~t1_pc~0); 55314#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 55313#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55312#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55311#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55310#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55308#L330-21 assume !(1 == ~t2_pc~0); 55307#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 55306#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55305#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55304#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55303#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55302#L349-21 assume 1 == ~t3_pc~0; 55300#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 55298#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55296#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55294#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 55293#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55292#L368-21 assume !(1 == ~t4_pc~0); 55291#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 55290#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55289#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55288#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55286#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55066#L387-21 assume 1 == ~t5_pc~0; 55062#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54974#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54970#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 54968#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 54966#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54965#L667-3 assume !(1 == ~M_E~0); 54478#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54959#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54955#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54954#L682-3 assume !(1 == ~T4_E~0); 54952#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54912#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54902#L697-3 assume !(1 == ~E_1~0); 54897#L702-3 assume !(1 == ~E_2~0); 54883#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54870#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54865#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54859#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54802#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54776#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54775#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 52862#L947 assume !(0 == start_simulation_~tmp~3#1); 52864#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 54985#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 54982#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 54981#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 54978#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54977#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54920#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 54906#L960 assume !(0 != start_simulation_~tmp___0~1#1); 53017#L928-2 [2023-11-06 22:25:23,191 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:23,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 1 times [2023-11-06 22:25:23,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:23,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789443108] [2023-11-06 22:25:23,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:23,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:23,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:23,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:23,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:23,276 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:23,278 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:23,278 INFO L85 PathProgramCache]: Analyzing trace with hash 765054962, now seen corresponding path program 1 times [2023-11-06 22:25:23,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:23,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893752003] [2023-11-06 22:25:23,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:23,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:23,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:23,333 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:23,334 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:23,334 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893752003] [2023-11-06 22:25:23,334 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893752003] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:23,334 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:23,334 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:23,335 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1368987402] [2023-11-06 22:25:23,335 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:23,335 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:23,336 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:23,336 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:23,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:23,337 INFO L87 Difference]: Start difference. First operand 4768 states and 6668 transitions. cyclomatic complexity: 1904 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:23,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:23,392 INFO L93 Difference]: Finished difference Result 5501 states and 7686 transitions. [2023-11-06 22:25:23,392 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5501 states and 7686 transitions. [2023-11-06 22:25:23,427 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5335 [2023-11-06 22:25:23,451 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5501 states to 5501 states and 7686 transitions. [2023-11-06 22:25:23,451 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5501 [2023-11-06 22:25:23,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5501 [2023-11-06 22:25:23,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5501 states and 7686 transitions. [2023-11-06 22:25:23,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:23,463 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5501 states and 7686 transitions. [2023-11-06 22:25:23,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5501 states and 7686 transitions. [2023-11-06 22:25:23,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5501 to 5501. [2023-11-06 22:25:23,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5501 states, 5501 states have (on average 1.397200508998364) internal successors, (7686), 5500 states have internal predecessors, (7686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:23,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5501 states to 5501 states and 7686 transitions. [2023-11-06 22:25:23,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5501 states and 7686 transitions. [2023-11-06 22:25:23,616 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:23,617 INFO L428 stractBuchiCegarLoop]: Abstraction has 5501 states and 7686 transitions. [2023-11-06 22:25:23,617 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:25:23,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5501 states and 7686 transitions. [2023-11-06 22:25:23,635 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5335 [2023-11-06 22:25:23,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:23,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:23,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:23,638 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:23,638 INFO L748 eck$LassoCheckResult]: Stem: 63116#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 63117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 63246#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 63247#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 63402#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 63187#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63188#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 63378#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 63164#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 63165#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 63372#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 63160#L599 assume !(0 == ~M_E~0); 63161#L599-2 assume !(0 == ~T1_E~0); 62817#L604-1 assume !(0 == ~T2_E~0); 62804#L609-1 assume !(0 == ~T3_E~0); 62805#L614-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62969#L619-1 assume !(0 == ~T5_E~0); 63191#L624-1 assume !(0 == ~E_M~0); 63192#L629-1 assume !(0 == ~E_1~0); 63429#L634-1 assume !(0 == ~E_2~0); 63312#L639-1 assume !(0 == ~E_3~0); 63313#L644-1 assume !(0 == ~E_4~0); 63330#L649-1 assume !(0 == ~E_5~0); 63331#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 62984#L292 assume !(1 == ~m_pc~0); 62985#L292-2 is_master_triggered_~__retres1~0#1 := 0; 63493#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 63089#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 63090#L743 assume !(0 != activate_threads_~tmp~1#1); 63492#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 63310#L311 assume !(1 == ~t1_pc~0); 63311#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 63199#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 62852#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 62853#L751 assume !(0 != activate_threads_~tmp___0~0#1); 63482#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 63479#L330 assume !(1 == ~t2_pc~0); 63268#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 62986#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 62987#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 63474#L759 assume !(0 != activate_threads_~tmp___1~0#1); 63473#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 63472#L349 assume !(1 == ~t3_pc~0); 63470#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 63468#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 63466#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 63463#L767 assume !(0 != activate_threads_~tmp___2~0#1); 63462#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 63437#L368 assume !(1 == ~t4_pc~0); 63438#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 63460#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 63459#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 63458#L775 assume !(0 != activate_threads_~tmp___3~0#1); 63457#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 63456#L387 assume !(1 == ~t5_pc~0); 63454#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 63453#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 63452#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 62942#L783 assume !(0 != activate_threads_~tmp___4~0#1); 62943#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 63040#L667 assume !(1 == ~M_E~0); 63123#L667-2 assume !(1 == ~T1_E~0); 63321#L672-1 assume !(1 == ~T2_E~0); 63078#L677-1 assume !(1 == ~T3_E~0); 63079#L682-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 63292#L687-1 assume !(1 == ~T5_E~0); 63365#L692-1 assume !(1 == ~E_M~0); 63277#L697-1 assume !(1 == ~E_1~0); 63278#L702-1 assume !(1 == ~E_2~0); 63329#L707-1 assume !(1 == ~E_3~0); 63180#L712-1 assume !(1 == ~E_4~0); 63181#L717-1 assume !(1 == ~E_5~0); 63299#L722-1 assume { :end_inline_reset_delta_events } true; 63300#L928-2 [2023-11-06 22:25:23,638 INFO L750 eck$LassoCheckResult]: Loop: 63300#L928-2 assume !false; 65358#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 65355#L574-1 assume !false; 65354#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 65343#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65339#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 65337#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 65335#L499 assume !(0 != eval_~tmp~0#1); 65336#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 65571#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 65569#L599-3 assume !(0 == ~M_E~0); 65567#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 65565#L604-3 assume !(0 == ~T2_E~0); 65563#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 65560#L614-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65558#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 65556#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 65555#L629-3 assume !(0 == ~E_1~0); 65552#L634-3 assume !(0 == ~E_2~0); 65550#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 65548#L644-3 assume !(0 == ~E_4~0); 65546#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 65544#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 65542#L292-21 assume !(1 == ~m_pc~0); 65540#L292-23 is_master_triggered_~__retres1~0#1 := 0; 65537#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 65535#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 65533#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 65532#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 65531#L311-21 assume !(1 == ~t1_pc~0); 65530#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 65527#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 65525#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 65522#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 65519#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 65512#L330-21 assume !(1 == ~t2_pc~0); 65509#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 65506#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 65503#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 65500#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 65497#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 65495#L349-21 assume !(1 == ~t3_pc~0); 65491#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 65489#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 65487#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 65485#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 65482#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 65480#L368-21 assume !(1 == ~t4_pc~0); 65478#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 65475#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 65473#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 65471#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 65469#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 65467#L387-21 assume 1 == ~t5_pc~0; 65464#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 65462#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 65460#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 65458#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 65456#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 65454#L667-3 assume !(1 == ~M_E~0); 65451#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65448#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 65446#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 65444#L682-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 65441#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 65439#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65437#L697-3 assume !(1 == ~E_1~0); 65433#L702-3 assume !(1 == ~E_2~0); 65431#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65429#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 65427#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 65424#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 65415#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65411#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 65409#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 65407#L947 assume !(0 == start_simulation_~tmp~3#1); 65403#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 65390#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 65385#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 65384#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 65383#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 65382#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 65381#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 65378#L960 assume !(0 != start_simulation_~tmp___0~1#1); 63300#L928-2 [2023-11-06 22:25:23,639 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:23,639 INFO L85 PathProgramCache]: Analyzing trace with hash -113006587, now seen corresponding path program 1 times [2023-11-06 22:25:23,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:23,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863668691] [2023-11-06 22:25:23,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:23,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:23,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:23,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:23,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:23,700 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [863668691] [2023-11-06 22:25:23,700 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [863668691] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:23,700 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:23,700 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:23,700 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193166268] [2023-11-06 22:25:23,701 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:23,703 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:23,704 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:23,704 INFO L85 PathProgramCache]: Analyzing trace with hash 395516275, now seen corresponding path program 1 times [2023-11-06 22:25:23,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:23,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1253647157] [2023-11-06 22:25:23,705 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:23,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:23,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:23,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:23,770 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:23,770 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1253647157] [2023-11-06 22:25:23,770 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1253647157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:23,770 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:23,771 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:23,771 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824583930] [2023-11-06 22:25:23,771 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:23,771 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:23,772 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:23,772 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:25:23,772 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:25:23,772 INFO L87 Difference]: Start difference. First operand 5501 states and 7686 transitions. cyclomatic complexity: 2189 Second operand has 4 states, 4 states have (on average 18.25) internal successors, (73), 3 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:23,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:23,859 INFO L93 Difference]: Finished difference Result 6912 states and 9629 transitions. [2023-11-06 22:25:23,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6912 states and 9629 transitions. [2023-11-06 22:25:23,889 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6777 [2023-11-06 22:25:23,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6912 states to 6912 states and 9629 transitions. [2023-11-06 22:25:23,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6912 [2023-11-06 22:25:23,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6912 [2023-11-06 22:25:23,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6912 states and 9629 transitions. [2023-11-06 22:25:23,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:23,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6912 states and 9629 transitions. [2023-11-06 22:25:24,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6912 states and 9629 transitions. [2023-11-06 22:25:24,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6912 to 4768. [2023-11-06 22:25:24,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4768 states, 4768 states have (on average 1.3957634228187918) internal successors, (6655), 4767 states have internal predecessors, (6655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:24,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4768 states to 4768 states and 6655 transitions. [2023-11-06 22:25:24,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4768 states and 6655 transitions. [2023-11-06 22:25:24,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:25:24,083 INFO L428 stractBuchiCegarLoop]: Abstraction has 4768 states and 6655 transitions. [2023-11-06 22:25:24,083 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:25:24,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4768 states and 6655 transitions. [2023-11-06 22:25:24,099 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4657 [2023-11-06 22:25:24,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:24,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:24,100 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:24,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:24,101 INFO L748 eck$LassoCheckResult]: Stem: 75535#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 75536#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 75666#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 75667#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75808#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 75608#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75609#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75782#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75582#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75583#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75777#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75578#L599 assume !(0 == ~M_E~0); 75579#L599-2 assume !(0 == ~T1_E~0); 75240#L604-1 assume !(0 == ~T2_E~0); 75229#L609-1 assume !(0 == ~T3_E~0); 75230#L614-1 assume !(0 == ~T4_E~0); 75394#L619-1 assume !(0 == ~T5_E~0); 75514#L624-1 assume !(0 == ~E_M~0); 75612#L629-1 assume !(0 == ~E_1~0); 75319#L634-1 assume !(0 == ~E_2~0); 75320#L639-1 assume !(0 == ~E_3~0); 75732#L644-1 assume !(0 == ~E_4~0); 75746#L649-1 assume !(0 == ~E_5~0); 75284#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75285#L292 assume !(1 == ~m_pc~0); 75407#L292-2 is_master_triggered_~__retres1~0#1 := 0; 75550#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75510#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 75511#L743 assume !(0 != activate_threads_~tmp~1#1); 75351#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75352#L311 assume !(1 == ~t1_pc~0); 75731#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 75620#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 75278#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75257#L751 assume !(0 != activate_threads_~tmp___0~0#1); 75258#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75733#L330 assume !(1 == ~t2_pc~0); 75517#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 75408#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75409#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75671#L759 assume !(0 != activate_threads_~tmp___1~0#1); 75806#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75395#L349 assume !(1 == ~t3_pc~0); 75396#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 75701#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 75231#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 75232#L767 assume !(0 != activate_threads_~tmp___2~0#1); 75801#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 75802#L368 assume !(1 == ~t4_pc~0); 75480#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 75481#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75381#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 75382#L775 assume !(0 != activate_threads_~tmp___3~0#1); 75243#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 75244#L387 assume !(1 == ~t5_pc~0); 75634#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 75635#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 75519#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 75367#L783 assume !(0 != activate_threads_~tmp___4~0#1); 75368#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75465#L667 assume !(1 == ~M_E~0); 75543#L667-2 assume !(1 == ~T1_E~0); 75739#L672-1 assume !(1 == ~T2_E~0); 75501#L677-1 assume !(1 == ~T3_E~0); 75502#L682-1 assume !(1 == ~T4_E~0); 75713#L687-1 assume !(1 == ~T5_E~0); 75773#L692-1 assume !(1 == ~E_M~0); 75699#L697-1 assume !(1 == ~E_1~0); 75700#L702-1 assume !(1 == ~E_2~0); 75745#L707-1 assume !(1 == ~E_3~0); 75600#L712-1 assume !(1 == ~E_4~0); 75601#L717-1 assume !(1 == ~E_5~0); 75721#L722-1 assume { :end_inline_reset_delta_events } true; 75251#L928-2 [2023-11-06 22:25:24,101 INFO L750 eck$LassoCheckResult]: Loop: 75251#L928-2 assume !false; 75252#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75490#L574-1 assume !false; 75491#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75798#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75453#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75690#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 75288#L499 assume !(0 != eval_~tmp~0#1); 75290#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 75398#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 75655#L599-3 assume !(0 == ~M_E~0); 75656#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 75559#L604-3 assume !(0 == ~T2_E~0); 75560#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 75830#L614-3 assume !(0 == ~T4_E~0); 79977#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 79975#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 79974#L629-3 assume !(0 == ~E_1~0); 79973#L634-3 assume !(0 == ~E_2~0); 79971#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 79969#L644-3 assume !(0 == ~E_4~0); 79967#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 79966#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 75697#L292-21 assume !(1 == ~m_pc~0); 75470#L292-23 is_master_triggered_~__retres1~0#1 := 0; 75332#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 75333#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79962#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 75553#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 75554#L311-21 assume !(1 == ~t1_pc~0); 75772#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 79932#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79925#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 75813#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 75405#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 75406#L330-21 assume !(1 == ~t2_pc~0); 79913#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 79911#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 75548#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 75549#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 79904#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79903#L349-21 assume !(1 == ~t3_pc~0); 79900#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 79898#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79897#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79896#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 79894#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79893#L368-21 assume !(1 == ~t4_pc~0); 79892#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 79890#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79889#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 79888#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 79887#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79886#L387-21 assume 1 == ~t5_pc~0; 79883#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 79881#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79879#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 79877#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 79876#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79873#L667-3 assume !(1 == ~M_E~0); 78339#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 79870#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 79868#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 79866#L682-3 assume !(1 == ~T4_E~0); 79864#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 79860#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 79858#L697-3 assume !(1 == ~E_1~0); 79856#L702-3 assume !(1 == ~E_2~0); 79854#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 79851#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 79849#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 79847#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 79785#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 79667#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 79666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 75562#L947 assume !(0 == start_simulation_~tmp~3#1); 75563#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 75567#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 75528#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 75276#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 75277#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75737#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75738#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 75677#L960 assume !(0 != start_simulation_~tmp___0~1#1); 75251#L928-2 [2023-11-06 22:25:24,102 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:24,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 2 times [2023-11-06 22:25:24,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:24,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316375385] [2023-11-06 22:25:24,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:24,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:24,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:24,117 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:24,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:24,156 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:24,157 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:24,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1568291405, now seen corresponding path program 1 times [2023-11-06 22:25:24,157 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:24,157 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [907144928] [2023-11-06 22:25:24,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:24,158 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:24,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:24,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:24,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:24,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [907144928] [2023-11-06 22:25:24,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [907144928] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:24,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:24,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:24,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899890999] [2023-11-06 22:25:24,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:24,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:24,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:24,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:25:24,232 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:25:24,232 INFO L87 Difference]: Start difference. First operand 4768 states and 6655 transitions. cyclomatic complexity: 1891 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:24,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:24,399 INFO L93 Difference]: Finished difference Result 8527 states and 11736 transitions. [2023-11-06 22:25:24,400 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8527 states and 11736 transitions. [2023-11-06 22:25:24,507 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 8384 [2023-11-06 22:25:24,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8527 states to 8527 states and 11736 transitions. [2023-11-06 22:25:24,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8527 [2023-11-06 22:25:24,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8527 [2023-11-06 22:25:24,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8527 states and 11736 transitions. [2023-11-06 22:25:24,547 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:24,547 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8527 states and 11736 transitions. [2023-11-06 22:25:24,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8527 states and 11736 transitions. [2023-11-06 22:25:24,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8527 to 4804. [2023-11-06 22:25:24,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4804 states, 4804 states have (on average 1.392797668609492) internal successors, (6691), 4803 states have internal predecessors, (6691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:24,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4804 states to 4804 states and 6691 transitions. [2023-11-06 22:25:24,654 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4804 states and 6691 transitions. [2023-11-06 22:25:24,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:25:24,655 INFO L428 stractBuchiCegarLoop]: Abstraction has 4804 states and 6691 transitions. [2023-11-06 22:25:24,656 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:25:24,656 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4804 states and 6691 transitions. [2023-11-06 22:25:24,672 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4693 [2023-11-06 22:25:24,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:24,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:24,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:24,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:24,674 INFO L748 eck$LassoCheckResult]: Stem: 88843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 88844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 88981#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 88982#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89172#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 88918#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 88919#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89137#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 88894#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 88895#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 89127#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 88890#L599 assume !(0 == ~M_E~0); 88891#L599-2 assume !(0 == ~T1_E~0); 88554#L604-1 assume !(0 == ~T2_E~0); 88541#L609-1 assume !(0 == ~T3_E~0); 88542#L614-1 assume !(0 == ~T4_E~0); 88703#L619-1 assume !(0 == ~T5_E~0); 88821#L624-1 assume !(0 == ~E_M~0); 88922#L629-1 assume !(0 == ~E_1~0); 88629#L634-1 assume !(0 == ~E_2~0); 88630#L639-1 assume !(0 == ~E_3~0); 89055#L644-1 assume !(0 == ~E_4~0); 89074#L649-1 assume !(0 == ~E_5~0); 88595#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88596#L292 assume !(1 == ~m_pc~0); 88717#L292-2 is_master_triggered_~__retres1~0#1 := 0; 88858#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88819#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 88820#L743 assume !(0 != activate_threads_~tmp~1#1); 88661#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88662#L311 assume !(1 == ~t1_pc~0); 89054#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 88930#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88589#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 88568#L751 assume !(0 != activate_threads_~tmp___0~0#1); 88569#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 89058#L330 assume !(1 == ~t2_pc~0); 88824#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 88719#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88720#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88986#L759 assume !(0 != activate_threads_~tmp___1~0#1); 89171#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88706#L349 assume !(1 == ~t3_pc~0); 88707#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 89021#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 89022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 89214#L767 assume !(0 != activate_threads_~tmp___2~0#1); 89161#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 89162#L368 assume !(1 == ~t4_pc~0); 88788#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 88789#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 88689#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88690#L775 assume !(0 != activate_threads_~tmp___3~0#1); 88555#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88556#L387 assume !(1 == ~t5_pc~0); 88945#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 88946#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 88826#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88679#L783 assume !(0 != activate_threads_~tmp___4~0#1); 88680#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88775#L667 assume !(1 == ~M_E~0); 88851#L667-2 assume !(1 == ~T1_E~0); 89068#L672-1 assume !(1 == ~T2_E~0); 88808#L677-1 assume !(1 == ~T3_E~0); 88809#L682-1 assume !(1 == ~T4_E~0); 89035#L687-1 assume !(1 == ~T5_E~0); 89121#L692-1 assume !(1 == ~E_M~0); 89019#L697-1 assume !(1 == ~E_1~0); 89020#L702-1 assume !(1 == ~E_2~0); 89073#L707-1 assume !(1 == ~E_3~0); 88911#L712-1 assume !(1 == ~E_4~0); 88912#L717-1 assume !(1 == ~E_5~0); 89043#L722-1 assume { :end_inline_reset_delta_events } true; 88563#L928-2 [2023-11-06 22:25:24,674 INFO L750 eck$LassoCheckResult]: Loop: 88563#L928-2 assume !false; 88564#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 88797#L574-1 assume !false; 88798#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89159#L452 assume !(0 == ~m_st~0); 88760#L456 assume !(0 == ~t1_st~0); 88762#L460 assume !(0 == ~t2_st~0); 89067#L464 assume !(0 == ~t3_st~0); 89125#L468 assume !(0 == ~t4_st~0); 89126#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 89131#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 89132#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 91911#L499 assume !(0 != eval_~tmp~0#1); 88704#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88705#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88969#L599-3 assume !(0 == ~M_E~0); 88970#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89034#L604-3 assume !(0 == ~T2_E~0); 89203#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89204#L614-3 assume !(0 == ~T4_E~0); 88570#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88571#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 89030#L629-3 assume !(0 == ~E_1~0); 89031#L634-3 assume !(0 == ~E_2~0); 89044#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89045#L644-3 assume !(0 == ~E_4~0); 89205#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 89206#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 89017#L292-21 assume !(1 == ~m_pc~0); 89018#L292-23 is_master_triggered_~__retres1~0#1 := 0; 88642#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88643#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 89149#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 89150#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 89117#L311-21 assume !(1 == ~t1_pc~0); 89118#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 88602#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88603#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 89176#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 89177#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88999#L330-21 assume !(1 == ~t2_pc~0); 89000#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 88961#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 88962#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 88988#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 88989#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 88906#L349-21 assume 1 == ~t3_pc~0; 88907#L350-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 91024#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91025#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91017#L767-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 89049#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 88734#L368-21 assume !(1 == ~t4_pc~0); 88735#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 89100#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 89101#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 89085#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 89086#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 88607#L387-21 assume 1 == ~t5_pc~0; 88609#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 89065#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 89066#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 89108#L783-21 assume !(0 != activate_threads_~tmp___4~0#1); 89109#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 88861#L667-3 assume !(1 == ~M_E~0); 88862#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89059#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 89060#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89222#L682-3 assume !(1 == ~T4_E~0); 89098#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 89099#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 89194#L697-3 assume !(1 == ~E_1~0); 89195#L702-3 assume !(1 == ~E_2~0); 88974#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 88975#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 88640#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 88641#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89167#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 88578#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88938#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 88939#L947 assume !(0 == start_simulation_~tmp~3#1); 89201#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 89211#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 93244#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 88587#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 88588#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 89062#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 89063#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 88993#L960 assume !(0 != start_simulation_~tmp___0~1#1); 88563#L928-2 [2023-11-06 22:25:24,675 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:24,675 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 3 times [2023-11-06 22:25:24,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:24,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857865563] [2023-11-06 22:25:24,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:24,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:24,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:24,689 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:24,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:24,720 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:24,721 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:24,721 INFO L85 PathProgramCache]: Analyzing trace with hash -1730562757, now seen corresponding path program 1 times [2023-11-06 22:25:24,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:24,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447448093] [2023-11-06 22:25:24,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:24,722 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:24,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:24,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:24,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:24,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447448093] [2023-11-06 22:25:24,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447448093] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:24,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:24,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:24,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562950573] [2023-11-06 22:25:24,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:24,856 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:24,856 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:24,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:25:24,857 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:25:24,857 INFO L87 Difference]: Start difference. First operand 4804 states and 6691 transitions. cyclomatic complexity: 1891 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:25,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:25,152 INFO L93 Difference]: Finished difference Result 9330 states and 12868 transitions. [2023-11-06 22:25:25,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9330 states and 12868 transitions. [2023-11-06 22:25:25,203 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 9170 [2023-11-06 22:25:25,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9330 states to 9330 states and 12868 transitions. [2023-11-06 22:25:25,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9330 [2023-11-06 22:25:25,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9330 [2023-11-06 22:25:25,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9330 states and 12868 transitions. [2023-11-06 22:25:25,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:25,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9330 states and 12868 transitions. [2023-11-06 22:25:25,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9330 states and 12868 transitions. [2023-11-06 22:25:25,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9330 to 5023. [2023-11-06 22:25:25,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5023 states, 5023 states have (on average 1.375671909217599) internal successors, (6910), 5022 states have internal predecessors, (6910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:25,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5023 states to 5023 states and 6910 transitions. [2023-11-06 22:25:25,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5023 states and 6910 transitions. [2023-11-06 22:25:25,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-06 22:25:25,403 INFO L428 stractBuchiCegarLoop]: Abstraction has 5023 states and 6910 transitions. [2023-11-06 22:25:25,403 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:25:25,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5023 states and 6910 transitions. [2023-11-06 22:25:25,423 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4909 [2023-11-06 22:25:25,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:25,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:25,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:25,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:25,426 INFO L748 eck$LassoCheckResult]: Stem: 103000#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 103001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 103143#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 103144#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103320#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 103079#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103080#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103292#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103051#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103052#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103283#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103045#L599 assume !(0 == ~M_E~0); 103046#L599-2 assume !(0 == ~T1_E~0); 102700#L604-1 assume !(0 == ~T2_E~0); 102687#L609-1 assume !(0 == ~T3_E~0); 102688#L614-1 assume !(0 == ~T4_E~0); 102848#L619-1 assume !(0 == ~T5_E~0); 102971#L624-1 assume !(0 == ~E_M~0); 103086#L629-1 assume !(0 == ~E_1~0); 102775#L634-1 assume !(0 == ~E_2~0); 102776#L639-1 assume !(0 == ~E_3~0); 103214#L644-1 assume !(0 == ~E_4~0); 103232#L649-1 assume !(0 == ~E_5~0); 102741#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 102742#L292 assume !(1 == ~m_pc~0); 102862#L292-2 is_master_triggered_~__retres1~0#1 := 0; 103016#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102969#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 102970#L743 assume !(0 != activate_threads_~tmp~1#1); 102807#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 102808#L311 assume !(1 == ~t1_pc~0); 103213#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 103095#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102735#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 102714#L751 assume !(0 != activate_threads_~tmp___0~0#1); 102715#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103217#L330 assume !(1 == ~t2_pc~0); 102974#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 102864#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 102865#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 103149#L759 assume !(0 != activate_threads_~tmp___1~0#1); 103318#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102851#L349 assume !(1 == ~t3_pc~0); 102852#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103178#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 102695#L767 assume !(0 != activate_threads_~tmp___2~0#1); 103311#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103312#L368 assume !(1 == ~t4_pc~0); 102936#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 102937#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 102834#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 102835#L775 assume !(0 != activate_threads_~tmp___3~0#1); 102701#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 102702#L387 assume !(1 == ~t5_pc~0); 103109#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 103110#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 102978#L783 assume !(0 != activate_threads_~tmp___4~0#1); 102825#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 102921#L667 assume !(1 == ~M_E~0); 103008#L667-2 assume !(1 == ~T1_E~0); 103224#L672-1 assume !(1 == ~T2_E~0); 102956#L677-1 assume !(1 == ~T3_E~0); 102957#L682-1 assume !(1 == ~T4_E~0); 103193#L687-1 assume !(1 == ~T5_E~0); 103275#L692-1 assume !(1 == ~E_M~0); 103176#L697-1 assume !(1 == ~E_1~0); 103177#L702-1 assume !(1 == ~E_2~0); 103230#L707-1 assume !(1 == ~E_3~0); 103068#L712-1 assume !(1 == ~E_4~0); 103069#L717-1 assume !(1 == ~E_5~0); 103201#L722-1 assume { :end_inline_reset_delta_events } true; 103202#L928-2 [2023-11-06 22:25:25,426 INFO L750 eck$LassoCheckResult]: Loop: 103202#L928-2 assume !false; 106212#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 106210#L574-1 assume !false; 106209#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106204#L452 assume !(0 == ~m_st~0); 106205#L456 assume !(0 == ~t1_st~0); 106207#L460 assume !(0 == ~t2_st~0); 106202#L464 assume !(0 == ~t3_st~0); 106203#L468 assume !(0 == ~t4_st~0); 106206#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 106208#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106744#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 106742#L499 assume !(0 != eval_~tmp~0#1); 106740#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106736#L599-3 assume !(0 == ~M_E~0); 106734#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106733#L604-3 assume !(0 == ~T2_E~0); 106732#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 106731#L614-3 assume !(0 == ~T4_E~0); 106730#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106729#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 106722#L629-3 assume !(0 == ~E_1~0); 106720#L634-3 assume !(0 == ~E_2~0); 106718#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 106716#L644-3 assume !(0 == ~E_4~0); 106714#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106712#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106710#L292-21 assume !(1 == ~m_pc~0); 106708#L292-23 is_master_triggered_~__retres1~0#1 := 0; 106707#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106706#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 106702#L743-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106700#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106698#L311-21 assume !(1 == ~t1_pc~0); 106696#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 106694#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106692#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 106690#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106688#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106683#L330-21 assume !(1 == ~t2_pc~0); 106681#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 106679#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106677#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 106675#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 106673#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106671#L349-21 assume !(1 == ~t3_pc~0); 106667#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 106665#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106663#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106661#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 106658#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106656#L368-21 assume !(1 == ~t4_pc~0); 106641#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 106622#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106617#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106594#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106297#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106296#L387-21 assume 1 == ~t5_pc~0; 106295#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106293#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106291#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106289#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106287#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106194#L667-3 assume !(1 == ~M_E~0); 106193#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 106453#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106452#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106451#L682-3 assume !(1 == ~T4_E~0); 106450#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106449#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 106448#L697-3 assume !(1 == ~E_1~0); 106447#L702-3 assume !(1 == ~E_2~0); 106446#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106445#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106444#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106443#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106439#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106436#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106435#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 106432#L947 assume !(0 == start_simulation_~tmp~3#1); 106430#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 106375#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 106372#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 106369#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 106367#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 106365#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 106363#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 106361#L960 assume !(0 != start_simulation_~tmp___0~1#1); 103202#L928-2 [2023-11-06 22:25:25,427 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:25,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 4 times [2023-11-06 22:25:25,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:25,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082508340] [2023-11-06 22:25:25,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:25,429 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:25,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:25,444 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:25,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:25,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:25,477 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:25,477 INFO L85 PathProgramCache]: Analyzing trace with hash 694339644, now seen corresponding path program 1 times [2023-11-06 22:25:25,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:25,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867594492] [2023-11-06 22:25:25,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:25,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:25,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:25,586 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:25,586 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:25,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [867594492] [2023-11-06 22:25:25,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [867594492] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:25,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:25,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:25:25,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834995733] [2023-11-06 22:25:25,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:25,588 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:25,588 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:25,589 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:25:25,589 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:25:25,589 INFO L87 Difference]: Start difference. First operand 5023 states and 6910 transitions. cyclomatic complexity: 1891 Second operand has 5 states, 5 states have (on average 17.8) internal successors, (89), 5 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:25,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:25,834 INFO L93 Difference]: Finished difference Result 10523 states and 14185 transitions. [2023-11-06 22:25:25,835 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10523 states and 14185 transitions. [2023-11-06 22:25:25,927 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10401 [2023-11-06 22:25:25,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10523 states to 10523 states and 14185 transitions. [2023-11-06 22:25:25,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10523 [2023-11-06 22:25:25,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10523 [2023-11-06 22:25:25,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10523 states and 14185 transitions. [2023-11-06 22:25:25,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:25,978 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10523 states and 14185 transitions. [2023-11-06 22:25:25,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10523 states and 14185 transitions. [2023-11-06 22:25:26,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10523 to 5179. [2023-11-06 22:25:26,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5179 states, 5179 states have (on average 1.3603012164510524) internal successors, (7045), 5178 states have internal predecessors, (7045), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:26,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5179 states to 5179 states and 7045 transitions. [2023-11-06 22:25:26,086 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5179 states and 7045 transitions. [2023-11-06 22:25:26,087 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:25:26,087 INFO L428 stractBuchiCegarLoop]: Abstraction has 5179 states and 7045 transitions. [2023-11-06 22:25:26,087 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:25:26,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5179 states and 7045 transitions. [2023-11-06 22:25:26,105 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5065 [2023-11-06 22:25:26,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:26,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:26,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:26,107 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:26,107 INFO L748 eck$LassoCheckResult]: Stem: 118557#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 118558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 118696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 118697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 118883#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 118637#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 118638#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118846#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118609#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118610#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118836#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 118603#L599 assume !(0 == ~M_E~0); 118604#L599-2 assume !(0 == ~T1_E~0); 118258#L604-1 assume !(0 == ~T2_E~0); 118245#L609-1 assume !(0 == ~T3_E~0); 118246#L614-1 assume !(0 == ~T4_E~0); 118407#L619-1 assume !(0 == ~T5_E~0); 118529#L624-1 assume !(0 == ~E_M~0); 118642#L629-1 assume !(0 == ~E_1~0); 118333#L634-1 assume !(0 == ~E_2~0); 118334#L639-1 assume !(0 == ~E_3~0); 118776#L644-1 assume !(0 == ~E_4~0); 118794#L649-1 assume !(0 == ~E_5~0); 118299#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 118300#L292 assume !(1 == ~m_pc~0); 118421#L292-2 is_master_triggered_~__retres1~0#1 := 0; 118572#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 118527#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 118528#L743 assume !(0 != activate_threads_~tmp~1#1); 118365#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118366#L311 assume !(1 == ~t1_pc~0); 118775#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 118650#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118293#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 118272#L751 assume !(0 != activate_threads_~tmp___0~0#1); 118273#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118779#L330 assume !(1 == ~t2_pc~0); 118533#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 118424#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118425#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 118701#L759 assume !(0 != activate_threads_~tmp___1~0#1); 118881#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 118410#L349 assume !(1 == ~t3_pc~0); 118411#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 118737#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 118738#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 118915#L767 assume !(0 != activate_threads_~tmp___2~0#1); 118872#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 118873#L368 assume !(1 == ~t4_pc~0); 118495#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 118496#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 118394#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 118395#L775 assume !(0 != activate_threads_~tmp___3~0#1); 118259#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 118260#L387 assume !(1 == ~t5_pc~0); 118664#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 118665#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 118536#L783 assume !(0 != activate_threads_~tmp___4~0#1); 118385#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118481#L667 assume !(1 == ~M_E~0); 118564#L667-2 assume !(1 == ~T1_E~0); 118786#L672-1 assume !(1 == ~T2_E~0); 118515#L677-1 assume !(1 == ~T3_E~0); 118516#L682-1 assume !(1 == ~T4_E~0); 118751#L687-1 assume !(1 == ~T5_E~0); 118831#L692-1 assume !(1 == ~E_M~0); 118735#L697-1 assume !(1 == ~E_1~0); 118736#L702-1 assume !(1 == ~E_2~0); 118793#L707-1 assume !(1 == ~E_3~0); 118629#L712-1 assume !(1 == ~E_4~0); 118630#L717-1 assume !(1 == ~E_5~0); 118760#L722-1 assume { :end_inline_reset_delta_events } true; 118761#L928-2 [2023-11-06 22:25:26,107 INFO L750 eck$LassoCheckResult]: Loop: 118761#L928-2 assume !false; 119622#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119616#L574-1 assume !false; 119614#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119612#L452 assume !(0 == ~m_st~0); 119610#L456 assume !(0 == ~t1_st~0); 119608#L460 assume !(0 == ~t2_st~0); 119606#L464 assume !(0 == ~t3_st~0); 119604#L468 assume !(0 == ~t4_st~0); 119601#L472 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 119598#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119596#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 119594#L499 assume !(0 != eval_~tmp~0#1); 119591#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119589#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119587#L599-3 assume !(0 == ~M_E~0); 119585#L599-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119583#L604-3 assume !(0 == ~T2_E~0); 119581#L609-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119579#L614-3 assume !(0 == ~T4_E~0); 119577#L619-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119575#L624-3 assume 0 == ~E_M~0;~E_M~0 := 1; 119573#L629-3 assume !(0 == ~E_1~0); 119571#L634-3 assume !(0 == ~E_2~0); 119569#L639-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119567#L644-3 assume !(0 == ~E_4~0); 119565#L649-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119563#L654-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119561#L292-21 assume !(1 == ~m_pc~0); 119559#L292-23 is_master_triggered_~__retres1~0#1 := 0; 119557#L303-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119555#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119553#L743-21 assume !(0 != activate_threads_~tmp~1#1); 119551#L743-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119549#L311-21 assume !(1 == ~t1_pc~0); 119547#L311-23 is_transmit1_triggered_~__retres1~1#1 := 0; 119545#L322-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119543#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119541#L751-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119539#L751-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119536#L330-21 assume !(1 == ~t2_pc~0); 119533#L330-23 is_transmit2_triggered_~__retres1~2#1 := 0; 119531#L341-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119529#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119527#L759-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119525#L759-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119523#L349-21 assume !(1 == ~t3_pc~0); 119521#L349-23 is_transmit3_triggered_~__retres1~3#1 := 0; 119517#L360-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119513#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119509#L767-21 assume !(0 != activate_threads_~tmp___2~0#1); 119505#L767-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119503#L368-21 assume !(1 == ~t4_pc~0); 119501#L368-23 is_transmit4_triggered_~__retres1~4#1 := 0; 119499#L379-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119497#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119495#L775-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119493#L775-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119491#L387-21 assume 1 == ~t5_pc~0; 119489#L388-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 119485#L398-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119481#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119477#L783-21 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119473#L783-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119471#L667-3 assume !(1 == ~M_E~0); 119470#L667-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119749#L672-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 119748#L677-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119747#L682-3 assume !(1 == ~T4_E~0); 119746#L687-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119745#L692-3 assume 1 == ~E_M~0;~E_M~0 := 2; 119744#L697-3 assume !(1 == ~E_1~0); 119743#L702-3 assume !(1 == ~E_2~0); 119742#L707-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119741#L712-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119740#L717-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119739#L722-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119734#L452-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119730#L484-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119728#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 119317#L947 assume !(0 == start_simulation_~tmp~3#1); 119318#L947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 119721#L452-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 119714#L484-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 119645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret18#1;havoc stop_simulation_#t~ret18#1; 119641#L902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119634#L909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119633#stop_simulation_returnLabel#1 start_simulation_#t~ret20#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret18#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 119632#L960 assume !(0 != start_simulation_~tmp___0~1#1); 118761#L928-2 [2023-11-06 22:25:26,108 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:26,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1000780869, now seen corresponding path program 5 times [2023-11-06 22:25:26,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:26,109 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023540667] [2023-11-06 22:25:26,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:26,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:26,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,123 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:26,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,144 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:26,145 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:26,145 INFO L85 PathProgramCache]: Analyzing trace with hash 1955256894, now seen corresponding path program 1 times [2023-11-06 22:25:26,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:26,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221789552] [2023-11-06 22:25:26,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:26,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:26,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:26,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:26,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:26,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221789552] [2023-11-06 22:25:26,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221789552] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:26,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:26,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:26,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388161835] [2023-11-06 22:25:26,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:26,191 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:25:26,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:26,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:26,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:26,193 INFO L87 Difference]: Start difference. First operand 5179 states and 7045 transitions. cyclomatic complexity: 1870 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:26,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:26,271 INFO L93 Difference]: Finished difference Result 8793 states and 11796 transitions. [2023-11-06 22:25:26,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8793 states and 11796 transitions. [2023-11-06 22:25:26,311 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8677 [2023-11-06 22:25:26,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8793 states to 8793 states and 11796 transitions. [2023-11-06 22:25:26,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8793 [2023-11-06 22:25:26,351 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8793 [2023-11-06 22:25:26,351 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8793 states and 11796 transitions. [2023-11-06 22:25:26,358 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:26,358 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8793 states and 11796 transitions. [2023-11-06 22:25:26,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8793 states and 11796 transitions. [2023-11-06 22:25:26,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8793 to 8457. [2023-11-06 22:25:26,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8457 states, 8457 states have (on average 1.343738914508691) internal successors, (11364), 8456 states have internal predecessors, (11364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:26,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8457 states to 8457 states and 11364 transitions. [2023-11-06 22:25:26,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8457 states and 11364 transitions. [2023-11-06 22:25:26,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:26,502 INFO L428 stractBuchiCegarLoop]: Abstraction has 8457 states and 11364 transitions. [2023-11-06 22:25:26,502 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:25:26,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8457 states and 11364 transitions. [2023-11-06 22:25:26,537 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8341 [2023-11-06 22:25:26,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:26,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:26,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:26,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:26,540 INFO L748 eck$LassoCheckResult]: Stem: 132523#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 132524#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 132658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 132659#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132829#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 132598#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132599#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132798#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132573#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132574#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132788#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132567#L599 assume !(0 == ~M_E~0); 132568#L599-2 assume !(0 == ~T1_E~0); 132236#L604-1 assume !(0 == ~T2_E~0); 132223#L609-1 assume !(0 == ~T3_E~0); 132224#L614-1 assume !(0 == ~T4_E~0); 132383#L619-1 assume !(0 == ~T5_E~0); 132499#L624-1 assume !(0 == ~E_M~0); 132603#L629-1 assume !(0 == ~E_1~0); 132311#L634-1 assume !(0 == ~E_2~0); 132312#L639-1 assume !(0 == ~E_3~0); 132729#L644-1 assume !(0 == ~E_4~0); 132749#L649-1 assume !(0 == ~E_5~0); 132277#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132278#L292 assume !(1 == ~m_pc~0); 132397#L292-2 is_master_triggered_~__retres1~0#1 := 0; 132539#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132495#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132496#L743 assume !(0 != activate_threads_~tmp~1#1); 132343#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132344#L311 assume !(1 == ~t1_pc~0); 132728#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 132611#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 132250#L751 assume !(0 != activate_threads_~tmp___0~0#1); 132251#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132731#L330 assume !(1 == ~t2_pc~0); 132502#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 132398#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132663#L759 assume !(0 != activate_threads_~tmp___1~0#1); 132826#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132384#L349 assume !(1 == ~t3_pc~0); 132385#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 132693#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132694#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132860#L767 assume !(0 != activate_threads_~tmp___2~0#1); 132819#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132820#L368 assume !(1 == ~t4_pc~0); 132463#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 132464#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132370#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132371#L775 assume !(0 != activate_threads_~tmp___3~0#1); 132237#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132238#L387 assume !(1 == ~t5_pc~0); 132625#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 132626#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 132505#L783 assume !(0 != activate_threads_~tmp___4~0#1); 132361#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132453#L667 assume !(1 == ~M_E~0); 132531#L667-2 assume !(1 == ~T1_E~0); 132739#L672-1 assume !(1 == ~T2_E~0); 132485#L677-1 assume !(1 == ~T3_E~0); 132486#L682-1 assume !(1 == ~T4_E~0); 132708#L687-1 assume !(1 == ~T5_E~0); 132784#L692-1 assume !(1 == ~E_M~0); 132691#L697-1 assume !(1 == ~E_1~0); 132692#L702-1 assume !(1 == ~E_2~0); 132748#L707-1 assume !(1 == ~E_3~0); 132589#L712-1 assume !(1 == ~E_4~0); 132590#L717-1 assume !(1 == ~E_5~0); 132715#L722-1 assume { :end_inline_reset_delta_events } true; 132716#L928-2 assume !false; 137255#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 137253#L574-1 [2023-11-06 22:25:26,540 INFO L750 eck$LassoCheckResult]: Loop: 137253#L574-1 assume !false; 137252#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 137251#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 137249#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 137149#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 137147#L499 assume 0 != eval_~tmp~0#1; 137144#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 137140#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 137137#L507-2 havoc eval_~tmp_ndt_1~0#1; 137110#L504-1 assume !(0 == ~t1_st~0); 137111#L518-1 assume !(0 == ~t2_st~0); 137273#L532-1 assume !(0 == ~t3_st~0); 137259#L546-1 assume !(0 == ~t4_st~0); 137256#L560-1 assume !(0 == ~t5_st~0); 137253#L574-1 [2023-11-06 22:25:26,541 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:26,541 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 1 times [2023-11-06 22:25:26,541 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:26,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166201890] [2023-11-06 22:25:26,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:26,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:26,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:26,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:26,602 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:26,602 INFO L85 PathProgramCache]: Analyzing trace with hash -2088174432, now seen corresponding path program 1 times [2023-11-06 22:25:26,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:26,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [214416618] [2023-11-06 22:25:26,603 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:26,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:26,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,610 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:26,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:26,617 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:26,618 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:26,618 INFO L85 PathProgramCache]: Analyzing trace with hash 672119718, now seen corresponding path program 1 times [2023-11-06 22:25:26,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:26,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [723674798] [2023-11-06 22:25:26,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:26,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:26,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:26,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:26,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:26,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [723674798] [2023-11-06 22:25:26,685 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [723674798] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:26,685 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:26,685 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:26,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855647763] [2023-11-06 22:25:26,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:26,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:26,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:26,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:26,811 INFO L87 Difference]: Start difference. First operand 8457 states and 11364 transitions. cyclomatic complexity: 2913 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:26,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:26,950 INFO L93 Difference]: Finished difference Result 16116 states and 21475 transitions. [2023-11-06 22:25:26,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16116 states and 21475 transitions. [2023-11-06 22:25:27,043 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15493 [2023-11-06 22:25:27,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16116 states to 16116 states and 21475 transitions. [2023-11-06 22:25:27,113 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16116 [2023-11-06 22:25:27,142 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16116 [2023-11-06 22:25:27,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16116 states and 21475 transitions. [2023-11-06 22:25:27,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:27,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16116 states and 21475 transitions. [2023-11-06 22:25:27,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16116 states and 21475 transitions. [2023-11-06 22:25:27,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16116 to 15816. [2023-11-06 22:25:27,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15816 states, 15816 states have (on average 1.3332701062215477) internal successors, (21087), 15815 states have internal predecessors, (21087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:27,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15816 states to 15816 states and 21087 transitions. [2023-11-06 22:25:27,525 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15816 states and 21087 transitions. [2023-11-06 22:25:27,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:27,526 INFO L428 stractBuchiCegarLoop]: Abstraction has 15816 states and 21087 transitions. [2023-11-06 22:25:27,526 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:25:27,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15816 states and 21087 transitions. [2023-11-06 22:25:27,576 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 15193 [2023-11-06 22:25:27,576 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:27,576 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:27,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:27,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:27,578 INFO L748 eck$LassoCheckResult]: Stem: 157106#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 157107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 157256#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 157257#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 157473#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 157189#L414-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 157190#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 157435#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 157436#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 157423#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 157424#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 157155#L599 assume !(0 == ~M_E~0); 157156#L599-2 assume !(0 == ~T1_E~0); 156815#L604-1 assume !(0 == ~T2_E~0); 156816#L609-1 assume !(0 == ~T3_E~0); 156966#L614-1 assume !(0 == ~T4_E~0); 156967#L619-1 assume !(0 == ~T5_E~0); 157195#L624-1 assume !(0 == ~E_M~0); 157196#L629-1 assume !(0 == ~E_1~0); 156894#L634-1 assume !(0 == ~E_2~0); 156895#L639-1 assume !(0 == ~E_3~0); 157415#L644-1 assume !(0 == ~E_4~0); 157416#L649-1 assume !(0 == ~E_5~0); 156861#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156862#L292 assume !(1 == ~m_pc~0); 157127#L292-2 is_master_triggered_~__retres1~0#1 := 0; 157128#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157077#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 157078#L743 assume !(0 != activate_threads_~tmp~1#1); 156926#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156927#L311 assume !(1 == ~t1_pc~0); 157395#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 157396#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 156854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156855#L751 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 156834#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 157341#L330 assume !(1 == ~t2_pc~0); 157085#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 156983#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 156984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 157468#L759 assume !(0 != activate_threads_~tmp___1~0#1); 157469#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 156968#L349 assume !(1 == ~t3_pc~0); 156969#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 157556#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157557#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 157531#L767 assume !(0 != activate_threads_~tmp___2~0#1); 157532#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157533#L368 assume !(1 == ~t4_pc~0); 157534#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 157404#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157405#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 157452#L775 assume !(0 != activate_threads_~tmp___3~0#1); 157453#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157489#L387 assume !(1 == ~t5_pc~0); 157490#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 157540#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 157541#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 157549#L783 assume !(0 != activate_threads_~tmp___4~0#1); 156941#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 157117#L667 assume !(1 == ~M_E~0); 157118#L667-2 assume !(1 == ~T1_E~0); 157355#L672-1 assume !(1 == ~T2_E~0); 157356#L677-1 assume !(1 == ~T3_E~0); 157314#L682-1 assume !(1 == ~T4_E~0); 157315#L687-1 assume !(1 == ~T5_E~0); 157485#L692-1 assume !(1 == ~E_M~0); 157486#L697-1 assume !(1 == ~E_1~0); 157524#L702-1 assume !(1 == ~E_2~0); 157525#L707-1 assume !(1 == ~E_3~0); 157178#L712-1 assume !(1 == ~E_4~0); 157179#L717-1 assume !(1 == ~E_5~0); 157323#L722-1 assume { :end_inline_reset_delta_events } true; 157324#L928-2 assume !false; 164639#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 164636#L574-1 [2023-11-06 22:25:27,578 INFO L750 eck$LassoCheckResult]: Loop: 164636#L574-1 assume !false; 164634#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 164630#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 164568#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 164569#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 164560#L499 assume 0 != eval_~tmp~0#1; 164561#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 164554#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 164536#L507-2 havoc eval_~tmp_ndt_1~0#1; 164537#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 159109#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 164672#L521-2 havoc eval_~tmp_ndt_2~0#1; 164670#L518-1 assume !(0 == ~t2_st~0); 164659#L532-1 assume !(0 == ~t3_st~0); 164648#L546-1 assume !(0 == ~t4_st~0); 164640#L560-1 assume !(0 == ~t5_st~0); 164636#L574-1 [2023-11-06 22:25:27,579 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:27,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1162562755, now seen corresponding path program 1 times [2023-11-06 22:25:27,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:27,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088436201] [2023-11-06 22:25:27,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:27,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:27,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:27,607 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:27,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:27,608 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1088436201] [2023-11-06 22:25:27,608 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1088436201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:27,608 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:27,608 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:27,608 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984109130] [2023-11-06 22:25:27,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:27,609 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:25:27,609 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:27,609 INFO L85 PathProgramCache]: Analyzing trace with hash -1426982192, now seen corresponding path program 1 times [2023-11-06 22:25:27,610 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:27,610 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145352976] [2023-11-06 22:25:27,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:27,610 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:27,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:27,614 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:27,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:27,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:27,712 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:27,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:27,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:27,713 INFO L87 Difference]: Start difference. First operand 15816 states and 21087 transitions. cyclomatic complexity: 5283 Second operand has 3 states, 3 states have (on average 25.0) internal successors, (75), 3 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:27,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:27,772 INFO L93 Difference]: Finished difference Result 13116 states and 17513 transitions. [2023-11-06 22:25:27,772 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13116 states and 17513 transitions. [2023-11-06 22:25:27,832 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12986 [2023-11-06 22:25:27,880 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13116 states to 13116 states and 17513 transitions. [2023-11-06 22:25:27,880 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13116 [2023-11-06 22:25:27,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13116 [2023-11-06 22:25:27,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13116 states and 17513 transitions. [2023-11-06 22:25:27,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:27,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13116 states and 17513 transitions. [2023-11-06 22:25:27,910 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13116 states and 17513 transitions. [2023-11-06 22:25:28,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13116 to 13116. [2023-11-06 22:25:28,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13116 states, 13116 states have (on average 1.3352394022567855) internal successors, (17513), 13115 states have internal predecessors, (17513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:28,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13116 states to 13116 states and 17513 transitions. [2023-11-06 22:25:28,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13116 states and 17513 transitions. [2023-11-06 22:25:28,083 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:28,083 INFO L428 stractBuchiCegarLoop]: Abstraction has 13116 states and 17513 transitions. [2023-11-06 22:25:28,083 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:25:28,083 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13116 states and 17513 transitions. [2023-11-06 22:25:28,128 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12986 [2023-11-06 22:25:28,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:28,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:28,129 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:28,129 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:28,130 INFO L748 eck$LassoCheckResult]: Stem: 186054#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 186055#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 186190#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 186191#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186360#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 186131#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 186132#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 186325#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 186105#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186106#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186315#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186101#L599 assume !(0 == ~M_E~0); 186102#L599-2 assume !(0 == ~T1_E~0); 185753#L604-1 assume !(0 == ~T2_E~0); 185742#L609-1 assume !(0 == ~T3_E~0); 185743#L614-1 assume !(0 == ~T4_E~0); 185905#L619-1 assume !(0 == ~T5_E~0); 186025#L624-1 assume !(0 == ~E_M~0); 186136#L629-1 assume !(0 == ~E_1~0); 185831#L634-1 assume !(0 == ~E_2~0); 185832#L639-1 assume !(0 == ~E_3~0); 186256#L644-1 assume !(0 == ~E_4~0); 186277#L649-1 assume !(0 == ~E_5~0); 185796#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185797#L292 assume !(1 == ~m_pc~0); 185919#L292-2 is_master_triggered_~__retres1~0#1 := 0; 186071#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186021#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 186022#L743 assume !(0 != activate_threads_~tmp~1#1); 185863#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185864#L311 assume !(1 == ~t1_pc~0); 186255#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 186144#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 185769#L751 assume !(0 != activate_threads_~tmp___0~0#1); 185770#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186257#L330 assume !(1 == ~t2_pc~0); 186029#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185920#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 185921#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 186196#L759 assume !(0 != activate_threads_~tmp___1~0#1); 186357#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185906#L349 assume !(1 == ~t3_pc~0); 185907#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 186397#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186424#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186409#L767 assume !(0 != activate_threads_~tmp___2~0#1); 186349#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186350#L368 assume !(1 == ~t4_pc~0); 185987#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185988#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 185891#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 185892#L775 assume !(0 != activate_threads_~tmp___3~0#1); 185756#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 185757#L387 assume !(1 == ~t5_pc~0); 186158#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 186159#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186031#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186032#L783 assume !(0 != activate_threads_~tmp___4~0#1); 185879#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185976#L667 assume !(1 == ~M_E~0); 186063#L667-2 assume !(1 == ~T1_E~0); 186264#L672-1 assume !(1 == ~T2_E~0); 186011#L677-1 assume !(1 == ~T3_E~0); 186012#L682-1 assume !(1 == ~T4_E~0); 186235#L687-1 assume !(1 == ~T5_E~0); 186310#L692-1 assume !(1 == ~E_M~0); 186221#L697-1 assume !(1 == ~E_1~0); 186222#L702-1 assume !(1 == ~E_2~0); 186276#L707-1 assume !(1 == ~E_3~0); 186123#L712-1 assume !(1 == ~E_4~0); 186124#L717-1 assume !(1 == ~E_5~0); 186242#L722-1 assume { :end_inline_reset_delta_events } true; 186243#L928-2 assume !false; 196571#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 196569#L574-1 [2023-11-06 22:25:28,130 INFO L750 eck$LassoCheckResult]: Loop: 196569#L574-1 assume !false; 196565#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 196563#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 196561#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 196559#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 196556#L499 assume 0 != eval_~tmp~0#1; 196553#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 196551#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 196550#L507-2 havoc eval_~tmp_ndt_1~0#1; 195426#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 194124#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 194125#L521-2 havoc eval_~tmp_ndt_2~0#1; 196599#L518-1 assume !(0 == ~t2_st~0); 196595#L532-1 assume !(0 == ~t3_st~0); 196575#L546-1 assume !(0 == ~t4_st~0); 196572#L560-1 assume !(0 == ~t5_st~0); 196569#L574-1 [2023-11-06 22:25:28,130 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:28,131 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 2 times [2023-11-06 22:25:28,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:28,131 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [960469711] [2023-11-06 22:25:28,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:28,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:28,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:28,148 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:28,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:28,169 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:28,170 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:28,170 INFO L85 PathProgramCache]: Analyzing trace with hash -1426982192, now seen corresponding path program 2 times [2023-11-06 22:25:28,170 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:28,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390314565] [2023-11-06 22:25:28,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:28,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:28,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:28,175 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:28,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:28,180 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:28,180 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:28,181 INFO L85 PathProgramCache]: Analyzing trace with hash 1220874326, now seen corresponding path program 1 times [2023-11-06 22:25:28,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:28,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [994595387] [2023-11-06 22:25:28,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:28,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:28,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:28,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:28,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:28,234 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [994595387] [2023-11-06 22:25:28,234 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [994595387] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:28,234 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:28,235 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:28,235 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1327848299] [2023-11-06 22:25:28,235 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:28,315 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:28,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:28,315 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:28,316 INFO L87 Difference]: Start difference. First operand 13116 states and 17513 transitions. cyclomatic complexity: 4403 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:28,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:28,587 INFO L93 Difference]: Finished difference Result 24560 states and 32679 transitions. [2023-11-06 22:25:28,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24560 states and 32679 transitions. [2023-11-06 22:25:28,695 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 24384 [2023-11-06 22:25:28,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24560 states to 24560 states and 32679 transitions. [2023-11-06 22:25:28,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24560 [2023-11-06 22:25:28,796 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24560 [2023-11-06 22:25:28,797 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24560 states and 32679 transitions. [2023-11-06 22:25:28,816 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:28,816 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24560 states and 32679 transitions. [2023-11-06 22:25:28,834 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24560 states and 32679 transitions. [2023-11-06 22:25:29,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24560 to 23462. [2023-11-06 22:25:29,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23462 states, 23462 states have (on average 1.3337737618276362) internal successors, (31293), 23461 states have internal predecessors, (31293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:29,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23462 states to 23462 states and 31293 transitions. [2023-11-06 22:25:29,116 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23462 states and 31293 transitions. [2023-11-06 22:25:29,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:29,117 INFO L428 stractBuchiCegarLoop]: Abstraction has 23462 states and 31293 transitions. [2023-11-06 22:25:29,117 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:25:29,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23462 states and 31293 transitions. [2023-11-06 22:25:29,194 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 23286 [2023-11-06 22:25:29,195 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:29,195 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:29,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:29,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:29,197 INFO L748 eck$LassoCheckResult]: Stem: 223727#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 223728#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 223868#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223869#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 224056#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 223806#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223807#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224018#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223778#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223779#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 224009#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223774#L599 assume !(0 == ~M_E~0); 223775#L599-2 assume !(0 == ~T1_E~0); 223437#L604-1 assume !(0 == ~T2_E~0); 223426#L609-1 assume !(0 == ~T3_E~0); 223427#L614-1 assume !(0 == ~T4_E~0); 223589#L619-1 assume !(0 == ~T5_E~0); 223704#L624-1 assume !(0 == ~E_M~0); 223811#L629-1 assume !(0 == ~E_1~0); 223515#L634-1 assume !(0 == ~E_2~0); 223516#L639-1 assume !(0 == ~E_3~0); 223944#L644-1 assume !(0 == ~E_4~0); 223962#L649-1 assume !(0 == ~E_5~0); 223480#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223481#L292 assume !(1 == ~m_pc~0); 223603#L292-2 is_master_triggered_~__retres1~0#1 := 0; 223744#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223700#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223701#L743 assume !(0 != activate_threads_~tmp~1#1); 223547#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223548#L311 assume !(1 == ~t1_pc~0); 223943#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 223819#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223474#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223453#L751 assume !(0 != activate_threads_~tmp___0~0#1); 223454#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223945#L330 assume !(1 == ~t2_pc~0); 223707#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 223604#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223605#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 223874#L759 assume !(0 != activate_threads_~tmp___1~0#1); 224053#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223590#L349 assume !(1 == ~t3_pc~0); 223591#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 224086#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 224119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 224103#L767 assume !(0 != activate_threads_~tmp___2~0#1); 224042#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224043#L368 assume !(1 == ~t4_pc~0); 223669#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 223670#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 223575#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223576#L775 assume !(0 != activate_threads_~tmp___3~0#1); 223440#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223441#L387 assume !(1 == ~t5_pc~0); 223833#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 223834#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 223709#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 223710#L783 assume !(0 != activate_threads_~tmp___4~0#1); 223563#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 223655#L667 assume !(1 == ~M_E~0); 223736#L667-2 assume !(1 == ~T1_E~0); 223952#L672-1 assume !(1 == ~T2_E~0); 223691#L677-1 assume !(1 == ~T3_E~0); 223692#L682-1 assume !(1 == ~T4_E~0); 223923#L687-1 assume !(1 == ~T5_E~0); 224004#L692-1 assume !(1 == ~E_M~0); 223907#L697-1 assume !(1 == ~E_1~0); 223908#L702-1 assume !(1 == ~E_2~0); 223961#L707-1 assume !(1 == ~E_3~0); 223797#L712-1 assume !(1 == ~E_4~0); 223798#L717-1 assume !(1 == ~E_5~0); 223930#L722-1 assume { :end_inline_reset_delta_events } true; 223931#L928-2 assume !false; 243618#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 243615#L574-1 [2023-11-06 22:25:29,197 INFO L750 eck$LassoCheckResult]: Loop: 243615#L574-1 assume !false; 243613#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 243606#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 243601#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 243596#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 243590#L499 assume 0 != eval_~tmp~0#1; 243585#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 243577#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 243574#L507-2 havoc eval_~tmp_ndt_1~0#1; 243573#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 243572#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 243568#L521-2 havoc eval_~tmp_ndt_2~0#1; 243562#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 240890#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 243561#L535-2 havoc eval_~tmp_ndt_3~0#1; 244649#L532-1 assume !(0 == ~t3_st~0); 244168#L546-1 assume !(0 == ~t4_st~0); 243619#L560-1 assume !(0 == ~t5_st~0); 243615#L574-1 [2023-11-06 22:25:29,197 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:29,198 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 3 times [2023-11-06 22:25:29,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:29,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157636945] [2023-11-06 22:25:29,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:29,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:29,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:29,210 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:29,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:29,341 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:29,341 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:29,342 INFO L85 PathProgramCache]: Analyzing trace with hash 2075640608, now seen corresponding path program 1 times [2023-11-06 22:25:29,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:29,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [972667370] [2023-11-06 22:25:29,342 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:29,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:29,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:29,349 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:29,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:29,354 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:29,354 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:29,355 INFO L85 PathProgramCache]: Analyzing trace with hash -249852122, now seen corresponding path program 1 times [2023-11-06 22:25:29,355 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:29,355 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [319628647] [2023-11-06 22:25:29,355 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:29,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:29,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:29,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:29,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:29,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [319628647] [2023-11-06 22:25:29,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [319628647] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:29,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:29,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:29,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90980544] [2023-11-06 22:25:29,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:29,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:29,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:29,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:29,529 INFO L87 Difference]: Start difference. First operand 23462 states and 31293 transitions. cyclomatic complexity: 7837 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:29,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:29,777 INFO L93 Difference]: Finished difference Result 42944 states and 57183 transitions. [2023-11-06 22:25:29,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42944 states and 57183 transitions. [2023-11-06 22:25:30,019 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 42676 [2023-11-06 22:25:30,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42944 states to 42944 states and 57183 transitions. [2023-11-06 22:25:30,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42944 [2023-11-06 22:25:30,237 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42944 [2023-11-06 22:25:30,237 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42944 states and 57183 transitions. [2023-11-06 22:25:30,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:30,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42944 states and 57183 transitions. [2023-11-06 22:25:30,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42944 states and 57183 transitions. [2023-11-06 22:25:31,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42944 to 41468. [2023-11-06 22:25:31,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41468 states, 41468 states have (on average 1.3346918105527152) internal successors, (55347), 41467 states have internal predecessors, (55347), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:31,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41468 states to 41468 states and 55347 transitions. [2023-11-06 22:25:31,469 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41468 states and 55347 transitions. [2023-11-06 22:25:31,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:31,470 INFO L428 stractBuchiCegarLoop]: Abstraction has 41468 states and 55347 transitions. [2023-11-06 22:25:31,470 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:25:31,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41468 states and 55347 transitions. [2023-11-06 22:25:31,596 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 41200 [2023-11-06 22:25:31,597 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:31,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:31,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:31,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:31,598 INFO L748 eck$LassoCheckResult]: Stem: 290141#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 290142#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 290283#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 290284#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 290477#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 290220#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 290221#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 290437#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 290194#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 290195#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 290431#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 290190#L599 assume !(0 == ~M_E~0); 290191#L599-2 assume !(0 == ~T1_E~0); 289853#L604-1 assume !(0 == ~T2_E~0); 289840#L609-1 assume !(0 == ~T3_E~0); 289841#L614-1 assume !(0 == ~T4_E~0); 289999#L619-1 assume !(0 == ~T5_E~0); 290116#L624-1 assume !(0 == ~E_M~0); 290225#L629-1 assume !(0 == ~E_1~0); 289925#L634-1 assume !(0 == ~E_2~0); 289926#L639-1 assume !(0 == ~E_3~0); 290359#L644-1 assume !(0 == ~E_4~0); 290382#L649-1 assume !(0 == ~E_5~0); 289893#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 289894#L292 assume !(1 == ~m_pc~0); 290013#L292-2 is_master_triggered_~__retres1~0#1 := 0; 290158#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 290114#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 290115#L743 assume !(0 != activate_threads_~tmp~1#1); 289957#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 289958#L311 assume !(1 == ~t1_pc~0); 290358#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 290233#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 289887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 289867#L751 assume !(0 != activate_threads_~tmp___0~0#1); 289868#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 290362#L330 assume !(1 == ~t2_pc~0); 290119#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 290016#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 290017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 290289#L759 assume !(0 != activate_threads_~tmp___1~0#1); 290474#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 290002#L349 assume !(1 == ~t3_pc~0); 290003#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 290512#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 289847#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 289848#L767 assume !(0 != activate_threads_~tmp___2~0#1); 290463#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 290464#L368 assume !(1 == ~t4_pc~0); 290083#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 290084#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 289986#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 289987#L775 assume !(0 != activate_threads_~tmp___3~0#1); 289854#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 289855#L387 assume !(1 == ~t5_pc~0); 290246#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 290247#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 290122#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 290123#L783 assume !(0 != activate_threads_~tmp___4~0#1); 289977#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 290071#L667 assume !(1 == ~M_E~0); 290150#L667-2 assume !(1 == ~T1_E~0); 290370#L672-1 assume !(1 == ~T2_E~0); 290103#L677-1 assume !(1 == ~T3_E~0); 290104#L682-1 assume !(1 == ~T4_E~0); 290336#L687-1 assume !(1 == ~T5_E~0); 290424#L692-1 assume !(1 == ~E_M~0); 290321#L697-1 assume !(1 == ~E_1~0); 290322#L702-1 assume !(1 == ~E_2~0); 290379#L707-1 assume !(1 == ~E_3~0); 290210#L712-1 assume !(1 == ~E_4~0); 290211#L717-1 assume !(1 == ~E_5~0); 290345#L722-1 assume { :end_inline_reset_delta_events } true; 290346#L928-2 assume !false; 324759#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 324756#L574-1 [2023-11-06 22:25:31,599 INFO L750 eck$LassoCheckResult]: Loop: 324756#L574-1 assume !false; 324754#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 307915#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 307916#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 312072#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 312069#L499 assume 0 != eval_~tmp~0#1; 312067#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 312064#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 306082#L507-2 havoc eval_~tmp_ndt_1~0#1; 306078#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 306075#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 306076#L521-2 havoc eval_~tmp_ndt_2~0#1; 306403#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 306400#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 306398#L535-2 havoc eval_~tmp_ndt_3~0#1; 306396#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 304486#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 306394#L549-2 havoc eval_~tmp_ndt_4~0#1; 322184#L546-1 assume !(0 == ~t4_st~0); 322185#L560-1 assume !(0 == ~t5_st~0); 324756#L574-1 [2023-11-06 22:25:31,599 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:31,599 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 4 times [2023-11-06 22:25:31,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:31,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1618180874] [2023-11-06 22:25:31,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:31,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:31,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:31,611 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:31,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:31,635 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:31,635 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:31,636 INFO L85 PathProgramCache]: Analyzing trace with hash 1655561552, now seen corresponding path program 1 times [2023-11-06 22:25:31,636 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:31,636 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605454932] [2023-11-06 22:25:31,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:31,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:31,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:31,642 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:31,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:31,647 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:31,647 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:31,648 INFO L85 PathProgramCache]: Analyzing trace with hash 240041942, now seen corresponding path program 1 times [2023-11-06 22:25:31,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:31,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817211806] [2023-11-06 22:25:31,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:31,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:31,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:31,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:31,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:31,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817211806] [2023-11-06 22:25:31,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817211806] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:31,696 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:31,696 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:25:31,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73377642] [2023-11-06 22:25:31,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:31,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:31,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:31,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:31,927 INFO L87 Difference]: Start difference. First operand 41468 states and 55347 transitions. cyclomatic complexity: 13885 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:32,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:32,157 INFO L93 Difference]: Finished difference Result 48326 states and 64317 transitions. [2023-11-06 22:25:32,157 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48326 states and 64317 transitions. [2023-11-06 22:25:32,653 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 48102 [2023-11-06 22:25:32,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48326 states to 48326 states and 64317 transitions. [2023-11-06 22:25:32,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48326 [2023-11-06 22:25:32,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48326 [2023-11-06 22:25:32,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48326 states and 64317 transitions. [2023-11-06 22:25:33,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:33,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48326 states and 64317 transitions. [2023-11-06 22:25:33,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48326 states and 64317 transitions. [2023-11-06 22:25:33,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48326 to 47318. [2023-11-06 22:25:33,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47318 states, 47318 states have (on average 1.3333826450822097) internal successors, (63093), 47317 states have internal predecessors, (63093), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:33,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47318 states to 47318 states and 63093 transitions. [2023-11-06 22:25:33,975 INFO L240 hiAutomatonCegarLoop]: Abstraction has 47318 states and 63093 transitions. [2023-11-06 22:25:33,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:33,976 INFO L428 stractBuchiCegarLoop]: Abstraction has 47318 states and 63093 transitions. [2023-11-06 22:25:33,976 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:25:33,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47318 states and 63093 transitions. [2023-11-06 22:25:34,144 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 47094 [2023-11-06 22:25:34,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:34,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:34,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:34,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:34,148 INFO L748 eck$LassoCheckResult]: Stem: 379948#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 379949#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 380092#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 380093#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 380308#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 380029#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 380030#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 380265#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 380003#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 380004#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 380256#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 379999#L599 assume !(0 == ~M_E~0); 380000#L599-2 assume !(0 == ~T1_E~0); 379653#L604-1 assume !(0 == ~T2_E~0); 379642#L609-1 assume !(0 == ~T3_E~0); 379643#L614-1 assume !(0 == ~T4_E~0); 379804#L619-1 assume !(0 == ~T5_E~0); 379923#L624-1 assume !(0 == ~E_M~0); 380035#L629-1 assume !(0 == ~E_1~0); 379730#L634-1 assume !(0 == ~E_2~0); 379731#L639-1 assume !(0 == ~E_3~0); 380173#L644-1 assume !(0 == ~E_4~0); 380201#L649-1 assume !(0 == ~E_5~0); 379696#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 379697#L292 assume !(1 == ~m_pc~0); 379818#L292-2 is_master_triggered_~__retres1~0#1 := 0; 379968#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 379919#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 379920#L743 assume !(0 != activate_threads_~tmp~1#1); 379762#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 379763#L311 assume !(1 == ~t1_pc~0); 380172#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 380043#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 379690#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 379670#L751 assume !(0 != activate_threads_~tmp___0~0#1); 379671#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 380176#L330 assume !(1 == ~t2_pc~0); 379927#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 379819#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 379820#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 380097#L759 assume !(0 != activate_threads_~tmp___1~0#1); 380306#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 379805#L349 assume !(1 == ~t3_pc~0); 379806#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 380345#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 380392#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 380369#L767 assume !(0 != activate_threads_~tmp___2~0#1); 380293#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 380294#L368 assume !(1 == ~t4_pc~0); 379887#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 379888#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 379791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 379792#L775 assume !(0 != activate_threads_~tmp___3~0#1); 379656#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 379657#L387 assume !(1 == ~t5_pc~0); 380058#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 380059#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 379930#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 379931#L783 assume !(0 != activate_threads_~tmp___4~0#1); 379778#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 379873#L667 assume !(1 == ~M_E~0); 379958#L667-2 assume !(1 == ~T1_E~0); 380185#L672-1 assume !(1 == ~T2_E~0); 379908#L677-1 assume !(1 == ~T3_E~0); 379909#L682-1 assume !(1 == ~T4_E~0); 380150#L687-1 assume !(1 == ~T5_E~0); 380252#L692-1 assume !(1 == ~E_M~0); 380134#L697-1 assume !(1 == ~E_1~0); 380135#L702-1 assume !(1 == ~E_2~0); 380200#L707-1 assume !(1 == ~E_3~0); 380021#L712-1 assume !(1 == ~E_4~0); 380022#L717-1 assume !(1 == ~E_5~0); 380157#L722-1 assume { :end_inline_reset_delta_events } true; 380158#L928-2 assume !false; 421259#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 421256#L574-1 [2023-11-06 22:25:34,149 INFO L750 eck$LassoCheckResult]: Loop: 421256#L574-1 assume !false; 421254#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 421252#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 421249#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 421247#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 421245#L499 assume 0 != eval_~tmp~0#1; 421242#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 421237#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 421235#L507-2 havoc eval_~tmp_ndt_1~0#1; 416062#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 416058#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 416060#L521-2 havoc eval_~tmp_ndt_2~0#1; 379953#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 379954#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 380347#L535-2 havoc eval_~tmp_ndt_3~0#1; 421273#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 421270#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 421268#L549-2 havoc eval_~tmp_ndt_4~0#1; 421267#L546-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 421264#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 421263#L563-2 havoc eval_~tmp_ndt_5~0#1; 421260#L560-1 assume !(0 == ~t5_st~0); 421256#L574-1 [2023-11-06 22:25:34,149 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:34,150 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 5 times [2023-11-06 22:25:34,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:34,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1685812800] [2023-11-06 22:25:34,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:34,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:34,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:34,165 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:34,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:34,190 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:34,191 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:34,191 INFO L85 PathProgramCache]: Analyzing trace with hash 1851312544, now seen corresponding path program 1 times [2023-11-06 22:25:34,191 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:34,191 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069162359] [2023-11-06 22:25:34,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:34,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:34,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:34,196 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:34,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:34,201 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:34,202 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:34,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1253367130, now seen corresponding path program 1 times [2023-11-06 22:25:34,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:34,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [878637758] [2023-11-06 22:25:34,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:34,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:34,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:25:34,252 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:25:34,252 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:25:34,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [878637758] [2023-11-06 22:25:34,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [878637758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:25:34,253 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:25:34,253 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:25:34,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1819469442] [2023-11-06 22:25:34,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:25:34,367 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:25:34,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:25:34,368 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:25:34,368 INFO L87 Difference]: Start difference. First operand 47318 states and 63093 transitions. cyclomatic complexity: 15781 Second operand has 3 states, 2 states have (on average 48.5) internal successors, (97), 3 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:34,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:25:34,943 INFO L93 Difference]: Finished difference Result 82340 states and 109661 transitions. [2023-11-06 22:25:34,943 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82340 states and 109661 transitions. [2023-11-06 22:25:35,573 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 81976 [2023-11-06 22:25:35,853 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82340 states to 82340 states and 109661 transitions. [2023-11-06 22:25:35,853 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82340 [2023-11-06 22:25:35,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82340 [2023-11-06 22:25:35,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82340 states and 109661 transitions. [2023-11-06 22:25:35,989 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:25:35,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 82340 states and 109661 transitions. [2023-11-06 22:25:36,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82340 states and 109661 transitions. [2023-11-06 22:25:37,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82340 to 80284. [2023-11-06 22:25:37,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80284 states, 80284 states have (on average 1.3403044193114444) internal successors, (107605), 80283 states have internal predecessors, (107605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:25:37,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80284 states to 80284 states and 107605 transitions. [2023-11-06 22:25:37,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80284 states and 107605 transitions. [2023-11-06 22:25:37,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:25:37,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 80284 states and 107605 transitions. [2023-11-06 22:25:37,209 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-06 22:25:37,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80284 states and 107605 transitions. [2023-11-06 22:25:37,841 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 79920 [2023-11-06 22:25:37,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:25:37,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:25:37,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:37,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:25:37,843 INFO L748 eck$LassoCheckResult]: Stem: 509610#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 509611#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 509760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19#1, start_simulation_#t~ret20#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 509761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 509969#L414 assume 1 == ~m_i~0;~m_st~0 := 0; 509695#L414-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 509696#L419-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 509930#L424-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 509662#L429-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 509663#L434-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 509923#L439-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 509658#L599 assume !(0 == ~M_E~0); 509659#L599-2 assume !(0 == ~T1_E~0); 509319#L604-1 assume !(0 == ~T2_E~0); 509308#L609-1 assume !(0 == ~T3_E~0); 509309#L614-1 assume !(0 == ~T4_E~0); 509470#L619-1 assume !(0 == ~T5_E~0); 509586#L624-1 assume !(0 == ~E_M~0); 509700#L629-1 assume !(0 == ~E_1~0); 509395#L634-1 assume !(0 == ~E_2~0); 509396#L639-1 assume !(0 == ~E_3~0); 509843#L644-1 assume !(0 == ~E_4~0); 509866#L649-1 assume !(0 == ~E_5~0); 509361#L654-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 509362#L292 assume !(1 == ~m_pc~0); 509484#L292-2 is_master_triggered_~__retres1~0#1 := 0; 509629#L303 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 509582#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 509583#L743 assume !(0 != activate_threads_~tmp~1#1); 509427#L743-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 509428#L311 assume !(1 == ~t1_pc~0); 509842#L311-2 is_transmit1_triggered_~__retres1~1#1 := 0; 509708#L322 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 509355#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 509335#L751 assume !(0 != activate_threads_~tmp___0~0#1); 509336#L751-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 509845#L330 assume !(1 == ~t2_pc~0); 509589#L330-2 is_transmit2_triggered_~__retres1~2#1 := 0; 509485#L341 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 509486#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 509765#L759 assume !(0 != activate_threads_~tmp___1~0#1); 509966#L759-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 509471#L349 assume !(1 == ~t3_pc~0); 509472#L349-2 is_transmit3_triggered_~__retres1~3#1 := 0; 510001#L360 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 510040#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 510023#L767 assume !(0 != activate_threads_~tmp___2~0#1); 509952#L767-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 509953#L368 assume !(1 == ~t4_pc~0); 509550#L368-2 is_transmit4_triggered_~__retres1~4#1 := 0; 509551#L379 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 509456#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 509457#L775 assume !(0 != activate_threads_~tmp___3~0#1); 509322#L775-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 509323#L387 assume !(1 == ~t5_pc~0); 509723#L387-2 is_transmit5_triggered_~__retres1~5#1 := 0; 509724#L398 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 509591#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 509592#L783 assume !(0 != activate_threads_~tmp___4~0#1); 509444#L783-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 509538#L667 assume !(1 == ~M_E~0); 509620#L667-2 assume !(1 == ~T1_E~0); 509853#L672-1 assume !(1 == ~T2_E~0); 509573#L677-1 assume !(1 == ~T3_E~0); 509574#L682-1 assume !(1 == ~T4_E~0); 509820#L687-1 assume !(1 == ~T5_E~0); 509919#L692-1 assume !(1 == ~E_M~0); 509803#L697-1 assume !(1 == ~E_1~0); 509804#L702-1 assume !(1 == ~E_2~0); 509865#L707-1 assume !(1 == ~E_3~0); 509685#L712-1 assume !(1 == ~E_4~0); 509686#L717-1 assume !(1 == ~E_5~0); 509828#L722-1 assume { :end_inline_reset_delta_events } true; 509829#L928-2 assume !false; 572714#L929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 572710#L574-1 [2023-11-06 22:25:37,843 INFO L750 eck$LassoCheckResult]: Loop: 572710#L574-1 assume !false; 572708#L495 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 572705#L452 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 572703#L484 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 572702#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 572701#L499 assume 0 != eval_~tmp~0#1; 572557#L499-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 572552#L507 assume !(0 != eval_~tmp_ndt_1~0#1); 572550#L507-2 havoc eval_~tmp_ndt_1~0#1; 572548#L504-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 572545#L521 assume !(0 != eval_~tmp_ndt_2~0#1); 572546#L521-2 havoc eval_~tmp_ndt_2~0#1; 571792#L518-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 571790#L535 assume !(0 != eval_~tmp_ndt_3~0#1); 571787#L535-2 havoc eval_~tmp_ndt_3~0#1; 571786#L532-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 571784#L549 assume !(0 != eval_~tmp_ndt_4~0#1); 571783#L549-2 havoc eval_~tmp_ndt_4~0#1; 571782#L546-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 571780#L563 assume !(0 != eval_~tmp_ndt_5~0#1); 571779#L563-2 havoc eval_~tmp_ndt_5~0#1; 571778#L560-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 571659#L577 assume !(0 != eval_~tmp_ndt_6~0#1); 571777#L577-2 havoc eval_~tmp_ndt_6~0#1; 572710#L574-1 [2023-11-06 22:25:37,844 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:37,844 INFO L85 PathProgramCache]: Analyzing trace with hash -322248313, now seen corresponding path program 6 times [2023-11-06 22:25:37,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:37,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887041597] [2023-11-06 22:25:37,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:37,845 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:37,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,857 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:37,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,879 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:37,879 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:37,879 INFO L85 PathProgramCache]: Analyzing trace with hash 994770896, now seen corresponding path program 1 times [2023-11-06 22:25:37,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:37,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007229292] [2023-11-06 22:25:37,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:37,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:37,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,884 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:37,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:37,889 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:25:37,889 INFO L85 PathProgramCache]: Analyzing trace with hash -1895092394, now seen corresponding path program 1 times [2023-11-06 22:25:37,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:25:37,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1383372434] [2023-11-06 22:25:37,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:25:37,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:25:37,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,902 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:37,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:37,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:25:40,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:40,271 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:25:40,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:25:40,525 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.11 10:25:40 BoogieIcfgContainer [2023-11-06 22:25:40,525 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-06 22:25:40,526 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-06 22:25:40,526 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-06 22:25:40,526 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-06 22:25:40,527 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:25:17" (3/4) ... [2023-11-06 22:25:40,529 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-06 22:25:40,620 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/witness.graphml.graphml [2023-11-06 22:25:40,620 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-06 22:25:40,621 INFO L158 Benchmark]: Toolchain (without parser) took 24839.72ms. Allocated memory was 130.0MB in the beginning and 6.4GB in the end (delta: 6.3GB). Free memory was 91.8MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 980.7MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,622 INFO L158 Benchmark]: CDTParser took 0.66ms. Allocated memory is still 130.0MB. Free memory was 106.3MB in the beginning and 106.2MB in the end (delta: 139.5kB). There was no memory consumed. Max. memory is 16.1GB. [2023-11-06 22:25:40,622 INFO L158 Benchmark]: CACSL2BoogieTranslator took 452.85ms. Allocated memory is still 130.0MB. Free memory was 91.8MB in the beginning and 75.2MB in the end (delta: 16.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,622 INFO L158 Benchmark]: Boogie Procedure Inliner took 98.51ms. Allocated memory is still 130.0MB. Free memory was 75.2MB in the beginning and 70.1MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,623 INFO L158 Benchmark]: Boogie Preprocessor took 121.65ms. Allocated memory is still 130.0MB. Free memory was 70.1MB in the beginning and 65.2MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,623 INFO L158 Benchmark]: RCFGBuilder took 1526.84ms. Allocated memory was 130.0MB in the beginning and 176.2MB in the end (delta: 46.1MB). Free memory was 65.2MB in the beginning and 101.5MB in the end (delta: -36.3MB). Peak memory consumption was 29.3MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,623 INFO L158 Benchmark]: BuchiAutomizer took 22535.04ms. Allocated memory was 176.2MB in the beginning and 6.4GB in the end (delta: 6.2GB). Free memory was 101.5MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 932.5MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,624 INFO L158 Benchmark]: Witness Printer took 94.84ms. Allocated memory is still 6.4GB. Free memory was 5.4GB in the beginning and 5.4GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2023-11-06 22:25:40,626 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.66ms. Allocated memory is still 130.0MB. Free memory was 106.3MB in the beginning and 106.2MB in the end (delta: 139.5kB). There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 452.85ms. Allocated memory is still 130.0MB. Free memory was 91.8MB in the beginning and 75.2MB in the end (delta: 16.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 98.51ms. Allocated memory is still 130.0MB. Free memory was 75.2MB in the beginning and 70.1MB in the end (delta: 5.1MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 121.65ms. Allocated memory is still 130.0MB. Free memory was 70.1MB in the beginning and 65.2MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * RCFGBuilder took 1526.84ms. Allocated memory was 130.0MB in the beginning and 176.2MB in the end (delta: 46.1MB). Free memory was 65.2MB in the beginning and 101.5MB in the end (delta: -36.3MB). Peak memory consumption was 29.3MB. Max. memory is 16.1GB. * BuchiAutomizer took 22535.04ms. Allocated memory was 176.2MB in the beginning and 6.4GB in the end (delta: 6.2GB). Free memory was 101.5MB in the beginning and 5.4GB in the end (delta: -5.3GB). Peak memory consumption was 932.5MB. Max. memory is 16.1GB. * Witness Printer took 94.84ms. Allocated memory is still 6.4GB. Free memory was 5.4GB in the beginning and 5.4GB in the end (delta: 9.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 24 terminating modules (24 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.24 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 80284 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 22.2s and 25 iterations. TraceHistogramMax:1. Analysis of lassos took 6.8s. Construction of modules took 1.0s. Büchi inclusion checks took 12.8s. Highest rank in rank-based complementation 0. Minimization of det autom 24. Minimization of nondet autom 0. Automata minimization 5.8s AutomataMinimizationTime, 24 MinimizatonAttempts, 28796 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 3.6s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 21317 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 21317 mSDsluCounter, 43043 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 21429 mSDsCounter, 344 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 934 IncrementalHoareTripleChecker+Invalid, 1278 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 344 mSolverCounterUnsat, 21614 mSDtfsCounter, 934 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc5 concLT0 SILN1 SILU0 SILI13 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 494]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L504-L515] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L518-L529] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L532-L543] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L546-L557] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L560-L571] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L574-L585] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 494]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, token=0] [L973] int __retres1 ; [L977] CALL init_model() [L884] m_i = 1 [L885] t1_i = 1 [L886] t2_i = 1 [L887] t3_i = 1 [L888] t4_i = 1 [L889] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L977] RET init_model() [L978] CALL start_simulation() [L914] int kernel_st ; [L915] int tmp ; [L916] int tmp___0 ; [L920] kernel_st = 0 [L921] FCALL update_channels() [L922] CALL init_threads() [L414] COND TRUE m_i == 1 [L415] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L419] COND TRUE t1_i == 1 [L420] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L424] COND TRUE t2_i == 1 [L425] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L429] COND TRUE t3_i == 1 [L430] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L434] COND TRUE t4_i == 1 [L435] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L439] COND TRUE t5_i == 1 [L440] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L922] RET init_threads() [L923] CALL fire_delta_events() [L599] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L604] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L609] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L614] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L619] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L624] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L629] COND FALSE !(E_M == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L634] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L639] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L644] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L649] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L654] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L923] RET fire_delta_events() [L924] CALL activate_threads() [L732] int tmp ; [L733] int tmp___0 ; [L734] int tmp___1 ; [L735] int tmp___2 ; [L736] int tmp___3 ; [L737] int tmp___4 ; [L741] CALL, EXPR is_master_triggered() [L289] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L292] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L302] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L304] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L741] RET, EXPR is_master_triggered() [L741] tmp = is_master_triggered() [L743] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, token=0] [L749] CALL, EXPR is_transmit1_triggered() [L308] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L311] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L321] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L323] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L749] RET, EXPR is_transmit1_triggered() [L749] tmp___0 = is_transmit1_triggered() [L751] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, token=0] [L757] CALL, EXPR is_transmit2_triggered() [L327] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L330] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L340] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L342] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L757] RET, EXPR is_transmit2_triggered() [L757] tmp___1 = is_transmit2_triggered() [L759] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, token=0] [L765] CALL, EXPR is_transmit3_triggered() [L346] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L349] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L359] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L361] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L765] RET, EXPR is_transmit3_triggered() [L765] tmp___2 = is_transmit3_triggered() [L767] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, token=0] [L773] CALL, EXPR is_transmit4_triggered() [L365] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L368] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L378] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L380] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L773] RET, EXPR is_transmit4_triggered() [L773] tmp___3 = is_transmit4_triggered() [L775] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, token=0] [L781] CALL, EXPR is_transmit5_triggered() [L384] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L387] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L397] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L399] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L781] RET, EXPR is_transmit5_triggered() [L781] tmp___4 = is_transmit5_triggered() [L783] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, token=0] [L924] RET activate_threads() [L925] CALL reset_delta_events() [L667] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L672] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L677] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L682] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L687] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L692] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L697] COND FALSE !(E_M == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L702] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L707] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L712] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L717] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L722] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L925] RET reset_delta_events() [L928] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] [L931] kernel_st = 1 [L932] CALL eval() [L490] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_M=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, local=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, token=0] Loop: [L494] COND TRUE 1 [L497] CALL, EXPR exists_runnable_thread() [L449] int __retres1 ; [L452] COND TRUE m_st == 0 [L453] __retres1 = 1 [L485] return (__retres1); [L497] RET, EXPR exists_runnable_thread() [L497] tmp = exists_runnable_thread() [L499] COND TRUE \read(tmp) [L504] COND TRUE m_st == 0 [L505] int tmp_ndt_1; [L506] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L507] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L504-L515] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L518] COND TRUE t1_st == 0 [L519] int tmp_ndt_2; [L520] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L521] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L518-L529] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L532] COND TRUE t2_st == 0 [L533] int tmp_ndt_3; [L534] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L535] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L532-L543] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L546] COND TRUE t3_st == 0 [L547] int tmp_ndt_4; [L548] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L549] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L546-L557] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L560] COND TRUE t4_st == 0 [L561] int tmp_ndt_5; [L562] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L563] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L560-L571] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L574] COND TRUE t5_st == 0 [L575] int tmp_ndt_6; [L576] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L577] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L574-L585] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-06 22:25:40,761 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d59f7b96-f258-4574-ba31-1397ee183057/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)