./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:43:01,983 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:43:02,107 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:43:02,116 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:43:02,117 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:43:02,159 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:43:02,160 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:43:02,161 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:43:02,162 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:43:02,163 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:43:02,164 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:43:02,165 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:43:02,165 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:43:02,167 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:43:02,167 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:43:02,168 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:43:02,168 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:43:02,169 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:43:02,169 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:43:02,170 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:43:02,172 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:43:02,172 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:43:02,173 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:43:02,173 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:43:02,173 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:43:02,174 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:43:02,174 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:43:02,175 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:43:02,175 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:43:02,175 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:43:02,177 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:43:02,177 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:43:02,177 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:43:02,178 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:43:02,178 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:43:02,178 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:43:02,179 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4ff0d99c6257365cafb7459615c8e1194d53bcc0d71dc100705abd4bb2d65c37 [2023-11-06 22:43:02,493 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:43:02,514 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:43:02,517 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:43:02,518 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:43:02,519 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:43:02,520 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2023-11-06 22:43:05,771 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:43:06,012 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:43:06,013 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/sv-benchmarks/c/systemc/token_ring.06.cil-1.c [2023-11-06 22:43:06,036 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/data/fe27eae16/64a01dd34087426c9ebfe66f8504a5d8/FLAGeb18fe1b6 [2023-11-06 22:43:06,059 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/data/fe27eae16/64a01dd34087426c9ebfe66f8504a5d8 [2023-11-06 22:43:06,065 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:43:06,068 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:43:06,069 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:43:06,071 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:43:06,076 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:43:06,077 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,078 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@39269420 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06, skipping insertion in model container [2023-11-06 22:43:06,078 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,170 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:43:06,495 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:43:06,518 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:43:06,615 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:43:06,641 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:43:06,641 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06 WrapperNode [2023-11-06 22:43:06,641 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:43:06,643 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:43:06,643 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:43:06,643 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:43:06,651 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,680 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,782 INFO L138 Inliner]: procedures = 40, calls = 51, calls flagged for inlining = 46, calls inlined = 116, statements flattened = 1679 [2023-11-06 22:43:06,783 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:43:06,784 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:43:06,784 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:43:06,784 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:43:06,794 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,794 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,799 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,800 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,829 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,850 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,855 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,862 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,871 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:43:06,872 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:43:06,872 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:43:06,872 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:43:06,873 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (1/1) ... [2023-11-06 22:43:06,880 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:43:06,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:43:06,930 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:43:06,956 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_c4d08d3f-e30f-4471-9083-51d9eff06367/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:43:06,986 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:43:06,986 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:43:06,986 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:43:06,987 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:43:07,153 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:43:07,155 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:43:08,460 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:43:08,489 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:43:08,489 INFO L302 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-06 22:43:08,493 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:43:08 BoogieIcfgContainer [2023-11-06 22:43:08,493 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:43:08,495 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:43:08,495 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:43:08,499 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:43:08,500 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:43:08,500 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:43:06" (1/3) ... [2023-11-06 22:43:08,501 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@de812d3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:43:08, skipping insertion in model container [2023-11-06 22:43:08,502 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:43:08,502 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:43:06" (2/3) ... [2023-11-06 22:43:08,504 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@de812d3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:43:08, skipping insertion in model container [2023-11-06 22:43:08,504 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:43:08,504 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:43:08" (3/3) ... [2023-11-06 22:43:08,506 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-1.c [2023-11-06 22:43:08,603 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:43:08,603 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:43:08,603 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:43:08,603 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:43:08,604 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:43:08,604 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:43:08,604 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:43:08,605 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:43:08,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:08,693 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2023-11-06 22:43:08,693 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:08,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:08,708 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:08,708 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:08,708 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:43:08,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:08,729 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 608 [2023-11-06 22:43:08,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:08,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:08,736 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:08,736 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:08,746 INFO L748 eck$LassoCheckResult]: Stem: 199#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 569#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 333#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 564#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 523#L487true assume !(1 == ~m_i~0);~m_st~0 := 2; 129#L487-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 268#L492-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 40#L497-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 149#L502-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 29#L507-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 115#L512-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 540#L517-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 222#L696true assume !(0 == ~M_E~0); 534#L696-2true assume !(0 == ~T1_E~0); 537#L701-1true assume !(0 == ~T2_E~0); 567#L706-1true assume !(0 == ~T3_E~0); 305#L711-1true assume !(0 == ~T4_E~0); 151#L716-1true assume !(0 == ~T5_E~0); 587#L721-1true assume !(0 == ~T6_E~0); 273#L726-1true assume 0 == ~E_M~0;~E_M~0 := 1; 476#L731-1true assume !(0 == ~E_1~0); 247#L736-1true assume !(0 == ~E_2~0); 317#L741-1true assume !(0 == ~E_3~0); 626#L746-1true assume !(0 == ~E_4~0); 169#L751-1true assume !(0 == ~E_5~0); 232#L756-1true assume !(0 == ~E_6~0); 148#L761-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 51#L346true assume !(1 == ~m_pc~0); 179#L346-2true is_master_triggered_~__retres1~0#1 := 0; 420#L357true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 553#L861true assume !(0 != activate_threads_~tmp~1#1); 475#L861-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69#L365true assume 1 == ~t1_pc~0; 138#L366true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 518#L376true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 64#L869true assume !(0 != activate_threads_~tmp___0~0#1); 371#L869-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 502#L384true assume !(1 == ~t2_pc~0); 367#L384-2true is_transmit2_triggered_~__retres1~2#1 := 0; 628#L395true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 335#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24#L877true assume !(0 != activate_threads_~tmp___1~0#1); 236#L877-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233#L403true assume 1 == ~t3_pc~0; 152#L404true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 681#L414true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 416#L885true assume !(0 != activate_threads_~tmp___2~0#1); 226#L885-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 524#L422true assume 1 == ~t4_pc~0; 22#L423true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 438#L433true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 451#L893true assume !(0 != activate_threads_~tmp___3~0#1); 291#L893-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30#L441true assume !(1 == ~t5_pc~0); 469#L441-2true is_transmit5_triggered_~__retres1~5#1 := 0; 616#L452true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 698#L901true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 297#L901-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 424#L460true assume 1 == ~t6_pc~0; 4#L461true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33#L471true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 319#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 421#L909true assume !(0 != activate_threads_~tmp___5~0#1); 550#L909-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280#L774true assume !(1 == ~M_E~0); 592#L774-2true assume !(1 == ~T1_E~0); 442#L779-1true assume !(1 == ~T2_E~0); 210#L784-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 588#L789-1true assume !(1 == ~T4_E~0); 60#L794-1true assume !(1 == ~T5_E~0); 667#L799-1true assume !(1 == ~T6_E~0); 602#L804-1true assume !(1 == ~E_M~0); 659#L809-1true assume !(1 == ~E_1~0); 270#L814-1true assume !(1 == ~E_2~0); 12#L819-1true assume !(1 == ~E_3~0); 325#L824-1true assume 1 == ~E_4~0;~E_4~0 := 2; 649#L829-1true assume !(1 == ~E_5~0); 429#L834-1true assume !(1 == ~E_6~0); 139#L839-1true assume { :end_inline_reset_delta_events } true; 131#L1065-2true [2023-11-06 22:43:08,749 INFO L750 eck$LassoCheckResult]: Loop: 131#L1065-2true assume !false; 341#L1066true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 397#L671-1true assume false; 105#eval_returnLabel#1true havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 489#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 163#L696-3true assume 0 == ~M_E~0;~M_E~0 := 1; 582#L696-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 198#L701-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 673#L706-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 548#L711-3true assume !(0 == ~T4_E~0); 535#L716-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 321#L721-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 184#L726-3true assume 0 == ~E_M~0;~E_M~0 := 1; 309#L731-3true assume 0 == ~E_1~0;~E_1~0 := 1; 511#L736-3true assume 0 == ~E_2~0;~E_2~0 := 1; 310#L741-3true assume 0 == ~E_3~0;~E_3~0 := 1; 145#L746-3true assume 0 == ~E_4~0;~E_4~0 := 1; 228#L751-3true assume !(0 == ~E_5~0); 430#L756-3true assume 0 == ~E_6~0;~E_6~0 := 1; 73#L761-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91#L346-24true assume 1 == ~m_pc~0; 413#L347-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 311#L357-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114#is_master_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 500#L861-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439#L861-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 111#L365-24true assume 1 == ~t1_pc~0; 322#L366-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 655#L376-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 527#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 392#L869-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 586#L869-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 83#L384-24true assume !(1 == ~t2_pc~0); 94#L384-26true is_transmit2_triggered_~__retres1~2#1 := 0; 640#L395-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 675#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 301#L877-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99#L877-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171#L403-24true assume 1 == ~t3_pc~0; 627#L404-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 200#L414-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 370#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 266#L885-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 577#L885-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 130#L422-24true assume 1 == ~t4_pc~0; 574#L423-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 104#L433-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 481#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539#L893-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 448#L893-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 140#L441-24true assume !(1 == ~t5_pc~0); 292#L441-26true is_transmit5_triggered_~__retres1~5#1 := 0; 286#L452-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 243#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 65#L901-24true assume !(0 != activate_threads_~tmp___4~0#1); 378#L901-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 374#L460-24true assume 1 == ~t6_pc~0; 590#L461-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 687#L471-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 168#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 468#L909-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 368#L909-26true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 636#L774-3true assume !(1 == ~M_E~0); 298#L774-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 183#L779-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 23#L784-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 686#L789-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 13#L794-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 70#L799-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 284#L804-3true assume 1 == ~E_M~0;~E_M~0 := 2; 521#L809-3true assume !(1 == ~E_1~0); 68#L814-3true assume 1 == ~E_2~0;~E_2~0 := 2; 221#L819-3true assume 1 == ~E_3~0;~E_3~0 := 2; 156#L824-3true assume 1 == ~E_4~0;~E_4~0 := 2; 144#L829-3true assume 1 == ~E_5~0;~E_5~0 := 2; 346#L834-3true assume 1 == ~E_6~0;~E_6~0 := 2; 59#L839-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 452#L530-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 109#L567-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 290#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 28#L1084true assume !(0 == start_simulation_~tmp~3#1); 492#L1084-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 167#L530-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 80#L567-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 42#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 170#L1039true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 76#L1046true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 501#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 175#L1097true assume !(0 != start_simulation_~tmp___0~1#1); 131#L1065-2true [2023-11-06 22:43:08,756 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:08,756 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2023-11-06 22:43:08,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:08,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452961286] [2023-11-06 22:43:08,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:08,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:08,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:09,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:09,136 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:09,137 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452961286] [2023-11-06 22:43:09,138 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452961286] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:09,138 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:09,138 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:09,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883562073] [2023-11-06 22:43:09,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:09,151 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:09,153 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:09,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1343600868, now seen corresponding path program 1 times [2023-11-06 22:43:09,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:09,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983375603] [2023-11-06 22:43:09,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:09,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:09,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:09,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:09,301 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:09,301 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983375603] [2023-11-06 22:43:09,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983375603] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:09,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:09,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:43:09,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [61151135] [2023-11-06 22:43:09,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:09,304 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:09,305 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:09,358 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:09,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:09,363 INFO L87 Difference]: Start difference. First operand has 703 states, 702 states have (on average 1.5185185185185186) internal successors, (1066), 702 states have internal predecessors, (1066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:09,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:09,442 INFO L93 Difference]: Finished difference Result 699 states and 1041 transitions. [2023-11-06 22:43:09,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 699 states and 1041 transitions. [2023-11-06 22:43:09,454 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:09,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 699 states to 693 states and 1035 transitions. [2023-11-06 22:43:09,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:09,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:09,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1035 transitions. [2023-11-06 22:43:09,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:09,476 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-06 22:43:09,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1035 transitions. [2023-11-06 22:43:09,538 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:09,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4935064935064934) internal successors, (1035), 692 states have internal predecessors, (1035), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:09,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1035 transitions. [2023-11-06 22:43:09,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-06 22:43:09,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:09,551 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1035 transitions. [2023-11-06 22:43:09,551 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:43:09,552 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1035 transitions. [2023-11-06 22:43:09,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:09,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:09,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:09,563 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:09,563 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:09,564 INFO L748 eck$LassoCheckResult]: Stem: 1771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2069#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1668#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1669#L492-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1500#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1501#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1473#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1474#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1642#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1802#L696 assume !(0 == ~M_E~0); 1803#L696-2 assume !(0 == ~T1_E~0); 2072#L701-1 assume !(0 == ~T2_E~0); 2075#L706-1 assume !(0 == ~T3_E~0); 1910#L711-1 assume !(0 == ~T4_E~0); 1703#L716-1 assume !(0 == ~T5_E~0); 1704#L721-1 assume !(0 == ~T6_E~0); 1868#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1869#L731-1 assume !(0 == ~E_1~0); 1838#L736-1 assume !(0 == ~E_2~0); 1839#L741-1 assume !(0 == ~E_3~0); 1919#L746-1 assume !(0 == ~E_4~0); 1728#L751-1 assume !(0 == ~E_5~0); 1729#L756-1 assume !(0 == ~E_6~0); 1700#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1521#L346 assume !(1 == ~m_pc~0); 1522#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1742#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1734#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1735#L861 assume !(0 != activate_threads_~tmp~1#1); 2051#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1554#L365 assume 1 == ~t1_pc~0; 1555#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1689#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1507#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1508#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1543#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1966#L384 assume !(1 == ~t2_pc~0); 1962#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1963#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1937#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1463#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1464#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1818#L403 assume 1 == ~t3_pc~0; 1705#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1706#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1432#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1813#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1814#L422 assume 1 == ~t4_pc~0; 1458#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1459#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1606#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1607#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1889#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1475#L441 assume !(1 == ~t5_pc~0); 1476#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2048#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1899#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1900#L460 assume 1 == ~t6_pc~0; 1419#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1420#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1483#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1921#L909 assume !(0 != activate_threads_~tmp___5~0#1); 2010#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1877#L774 assume !(1 == ~M_E~0); 1878#L774-2 assume !(1 == ~T1_E~0); 2027#L779-1 assume !(1 == ~T2_E~0); 1788#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1789#L789-1 assume !(1 == ~T4_E~0); 1538#L794-1 assume !(1 == ~T5_E~0); 1539#L799-1 assume !(1 == ~T6_E~0); 2092#L804-1 assume !(1 == ~E_M~0); 2093#L809-1 assume !(1 == ~E_1~0); 1866#L814-1 assume !(1 == ~E_2~0); 1437#L819-1 assume !(1 == ~E_3~0); 1438#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1927#L829-1 assume !(1 == ~E_5~0); 2017#L834-1 assume !(1 == ~E_6~0); 1690#L839-1 assume { :end_inline_reset_delta_events } true; 1673#L1065-2 [2023-11-06 22:43:09,565 INFO L750 eck$LassoCheckResult]: Loop: 1673#L1065-2 assume !false; 1674#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1645#L671-1 assume !false; 1995#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1997#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1510#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1524#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1954#L582 assume !(0 != eval_~tmp~0#1); 1622#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1719#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1720#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1767#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1768#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2079#L711-3 assume !(0 == ~T4_E~0); 2073#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1923#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1749#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1750#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1915#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1916#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1697#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1698#L751-3 assume !(0 == ~E_5~0); 1815#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1561#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1562#L346-24 assume 1 == ~m_pc~0; 1600#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1693#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1640#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1641#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2025#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1632#L365-24 assume 1 == ~t1_pc~0; 1633#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1922#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2070#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1986#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1987#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1579#L384-24 assume !(1 == ~t2_pc~0); 1580#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1601#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2100#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1906#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1611#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1612#L403-24 assume 1 == ~t3_pc~0; 1730#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1769#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1770#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1863#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1864#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1670#L422-24 assume 1 == ~t4_pc~0; 1671#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1617#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1618#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2054#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2033#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1686#L441-24 assume !(1 == ~t5_pc~0); 1687#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1882#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1834#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1544#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1545#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1967#L460-24 assume 1 == ~t6_pc~0; 1968#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2028#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1726#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1727#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1960#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1961#L774-3 assume !(1 == ~M_E~0); 1898#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1748#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1456#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1457#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1435#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1436#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1553#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1881#L809-3 assume !(1 == ~E_1~0); 1551#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1552#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1711#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1695#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1696#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1536#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1537#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1534#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1628#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1470#L1084 assume !(0 == start_simulation_~tmp~3#1); 1471#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1724#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1440#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1498#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1499#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1566#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1567#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1736#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1673#L1065-2 [2023-11-06 22:43:09,565 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:09,566 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2023-11-06 22:43:09,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:09,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [455678983] [2023-11-06 22:43:09,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:09,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:09,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:09,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:09,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:09,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [455678983] [2023-11-06 22:43:09,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [455678983] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:09,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:09,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:09,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [180208274] [2023-11-06 22:43:09,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:09,678 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:09,680 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:09,681 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 1 times [2023-11-06 22:43:09,681 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:09,681 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775756856] [2023-11-06 22:43:09,682 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:09,683 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:09,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:09,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:09,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:09,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775756856] [2023-11-06 22:43:09,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775756856] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:09,852 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:09,852 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:09,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1515392570] [2023-11-06 22:43:09,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:09,853 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:09,854 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:09,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:09,854 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:09,855 INFO L87 Difference]: Start difference. First operand 693 states and 1035 transitions. cyclomatic complexity: 343 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:09,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:09,888 INFO L93 Difference]: Finished difference Result 693 states and 1034 transitions. [2023-11-06 22:43:09,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1034 transitions. [2023-11-06 22:43:09,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:09,905 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1034 transitions. [2023-11-06 22:43:09,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:09,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:09,912 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1034 transitions. [2023-11-06 22:43:09,914 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:09,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-06 22:43:09,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1034 transitions. [2023-11-06 22:43:09,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:09,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.492063492063492) internal successors, (1034), 692 states have internal predecessors, (1034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:09,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1034 transitions. [2023-11-06 22:43:09,943 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-06 22:43:09,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:09,945 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1034 transitions. [2023-11-06 22:43:09,945 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:43:09,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1034 transitions. [2023-11-06 22:43:09,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:09,953 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:09,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:09,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:09,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:09,974 INFO L748 eck$LassoCheckResult]: Stem: 3162#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3163#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3324#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3325#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3462#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 3061#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3062#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2889#L497-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2890#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2866#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2867#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3035#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3195#L696 assume !(0 == ~M_E~0); 3196#L696-2 assume !(0 == ~T1_E~0); 3465#L701-1 assume !(0 == ~T2_E~0); 3467#L706-1 assume !(0 == ~T3_E~0); 3303#L711-1 assume !(0 == ~T4_E~0); 3096#L716-1 assume !(0 == ~T5_E~0); 3097#L721-1 assume !(0 == ~T6_E~0); 3261#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3262#L731-1 assume !(0 == ~E_1~0); 3231#L736-1 assume !(0 == ~E_2~0); 3232#L741-1 assume !(0 == ~E_3~0); 3312#L746-1 assume !(0 == ~E_4~0); 3121#L751-1 assume !(0 == ~E_5~0); 3122#L756-1 assume !(0 == ~E_6~0); 3093#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2912#L346 assume !(1 == ~m_pc~0); 2913#L346-2 is_master_triggered_~__retres1~0#1 := 0; 3135#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3127#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3128#L861 assume !(0 != activate_threads_~tmp~1#1); 3444#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2946#L365 assume 1 == ~t1_pc~0; 2947#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3079#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2896#L869 assume !(0 != activate_threads_~tmp___0~0#1); 2936#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3359#L384 assume !(1 == ~t2_pc~0); 3353#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3354#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3326#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2854#L877 assume !(0 != activate_threads_~tmp___1~0#1); 2855#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3210#L403 assume 1 == ~t3_pc~0; 3098#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3099#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2824#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2825#L885 assume !(0 != activate_threads_~tmp___2~0#1); 3203#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3204#L422 assume 1 == ~t4_pc~0; 2849#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2850#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2999#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3000#L893 assume !(0 != activate_threads_~tmp___3~0#1); 3282#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2868#L441 assume !(1 == ~t5_pc~0); 2869#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3440#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3138#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3139#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3291#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3292#L460 assume 1 == ~t6_pc~0; 2809#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2810#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2876#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3314#L909 assume !(0 != activate_threads_~tmp___5~0#1); 3403#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3270#L774 assume !(1 == ~M_E~0); 3271#L774-2 assume !(1 == ~T1_E~0); 3420#L779-1 assume !(1 == ~T2_E~0); 3181#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3182#L789-1 assume !(1 == ~T4_E~0); 2931#L794-1 assume !(1 == ~T5_E~0); 2932#L799-1 assume !(1 == ~T6_E~0); 3485#L804-1 assume !(1 == ~E_M~0); 3486#L809-1 assume !(1 == ~E_1~0); 3258#L814-1 assume !(1 == ~E_2~0); 2828#L819-1 assume !(1 == ~E_3~0); 2829#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3320#L829-1 assume !(1 == ~E_5~0); 3410#L834-1 assume !(1 == ~E_6~0); 3080#L839-1 assume { :end_inline_reset_delta_events } true; 3066#L1065-2 [2023-11-06 22:43:09,975 INFO L750 eck$LassoCheckResult]: Loop: 3066#L1065-2 assume !false; 3067#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3038#L671-1 assume !false; 3385#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3390#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2903#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2917#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 3346#L582 assume !(0 != eval_~tmp~0#1); 3013#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3014#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3112#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3113#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3160#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3161#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3472#L711-3 assume !(0 == ~T4_E~0); 3466#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3315#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3142#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3143#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3308#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3309#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3090#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3091#L751-3 assume !(0 == ~E_5~0); 3208#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2954#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2955#L346-24 assume !(1 == ~m_pc~0); 2989#L346-26 is_master_triggered_~__retres1~0#1 := 0; 3086#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3033#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3034#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3418#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3025#L365-24 assume 1 == ~t1_pc~0; 3026#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3316#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3463#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3381#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3382#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2974#L384-24 assume 1 == ~t2_pc~0; 2976#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2996#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3493#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3299#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3005#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3006#L403-24 assume 1 == ~t3_pc~0; 3123#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3164#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3165#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3256#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3257#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3063#L422-24 assume 1 == ~t4_pc~0; 3064#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3011#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3012#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3447#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3426#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3081#L441-24 assume !(1 == ~t5_pc~0); 3082#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3276#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3227#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2937#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 2938#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3360#L460-24 assume 1 == ~t6_pc~0; 3361#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3421#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3119#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3120#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3355#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3356#L774-3 assume !(1 == ~M_E~0); 3293#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3141#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2852#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2853#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2830#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2831#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2949#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3274#L809-3 assume !(1 == ~E_1~0); 2944#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2945#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3104#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3088#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3089#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2929#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2930#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2927#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3021#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 2863#L1084 assume !(0 == start_simulation_~tmp~3#1); 2864#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3117#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2833#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2893#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 2894#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2960#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2961#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3129#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 3066#L1065-2 [2023-11-06 22:43:09,983 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:09,984 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2023-11-06 22:43:09,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:09,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125203950] [2023-11-06 22:43:09,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:09,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125203950] [2023-11-06 22:43:10,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125203950] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1059149653] [2023-11-06 22:43:10,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,091 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:10,091 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,092 INFO L85 PathProgramCache]: Analyzing trace with hash -437079207, now seen corresponding path program 1 times [2023-11-06 22:43:10,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632436496] [2023-11-06 22:43:10,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1632436496] [2023-11-06 22:43:10,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1632436496] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [443808443] [2023-11-06 22:43:10,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,156 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:10,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:10,157 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:10,157 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:10,158 INFO L87 Difference]: Start difference. First operand 693 states and 1034 transitions. cyclomatic complexity: 342 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:10,180 INFO L93 Difference]: Finished difference Result 693 states and 1033 transitions. [2023-11-06 22:43:10,180 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1033 transitions. [2023-11-06 22:43:10,185 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1033 transitions. [2023-11-06 22:43:10,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:10,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:10,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1033 transitions. [2023-11-06 22:43:10,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:10,194 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-06 22:43:10,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1033 transitions. [2023-11-06 22:43:10,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:10,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4906204906204905) internal successors, (1033), 692 states have internal predecessors, (1033), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1033 transitions. [2023-11-06 22:43:10,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-06 22:43:10,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:10,211 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1033 transitions. [2023-11-06 22:43:10,211 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:43:10,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1033 transitions. [2023-11-06 22:43:10,215 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,215 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:10,215 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:10,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,218 INFO L748 eck$LassoCheckResult]: Stem: 4555#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4717#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4718#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4855#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 4454#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4455#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4284#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4285#L502-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4259#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4260#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4428#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4588#L696 assume !(0 == ~M_E~0); 4589#L696-2 assume !(0 == ~T1_E~0); 4858#L701-1 assume !(0 == ~T2_E~0); 4860#L706-1 assume !(0 == ~T3_E~0); 4696#L711-1 assume !(0 == ~T4_E~0); 4489#L716-1 assume !(0 == ~T5_E~0); 4490#L721-1 assume !(0 == ~T6_E~0); 4654#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4655#L731-1 assume !(0 == ~E_1~0); 4624#L736-1 assume !(0 == ~E_2~0); 4625#L741-1 assume !(0 == ~E_3~0); 4705#L746-1 assume !(0 == ~E_4~0); 4514#L751-1 assume !(0 == ~E_5~0); 4515#L756-1 assume !(0 == ~E_6~0); 4486#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4305#L346 assume !(1 == ~m_pc~0); 4306#L346-2 is_master_triggered_~__retres1~0#1 := 0; 4528#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4520#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4521#L861 assume !(0 != activate_threads_~tmp~1#1); 4837#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4340#L365 assume 1 == ~t1_pc~0; 4341#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4472#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4288#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4289#L869 assume !(0 != activate_threads_~tmp___0~0#1); 4329#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L384 assume !(1 == ~t2_pc~0); 4746#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4747#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4719#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4247#L877 assume !(0 != activate_threads_~tmp___1~0#1); 4248#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4603#L403 assume 1 == ~t3_pc~0; 4491#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4218#L885 assume !(0 != activate_threads_~tmp___2~0#1); 4596#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4597#L422 assume 1 == ~t4_pc~0; 4244#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4245#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4392#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4393#L893 assume !(0 != activate_threads_~tmp___3~0#1); 4675#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4261#L441 assume !(1 == ~t5_pc~0); 4262#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4833#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4531#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4532#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4684#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4685#L460 assume 1 == ~t6_pc~0; 4202#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4203#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4707#L909 assume !(0 != activate_threads_~tmp___5~0#1); 4796#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4663#L774 assume !(1 == ~M_E~0); 4664#L774-2 assume !(1 == ~T1_E~0); 4813#L779-1 assume !(1 == ~T2_E~0); 4574#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4575#L789-1 assume !(1 == ~T4_E~0); 4324#L794-1 assume !(1 == ~T5_E~0); 4325#L799-1 assume !(1 == ~T6_E~0); 4878#L804-1 assume !(1 == ~E_M~0); 4879#L809-1 assume !(1 == ~E_1~0); 4651#L814-1 assume !(1 == ~E_2~0); 4223#L819-1 assume !(1 == ~E_3~0); 4224#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L829-1 assume !(1 == ~E_5~0); 4803#L834-1 assume !(1 == ~E_6~0); 4473#L839-1 assume { :end_inline_reset_delta_events } true; 4459#L1065-2 [2023-11-06 22:43:10,218 INFO L750 eck$LassoCheckResult]: Loop: 4459#L1065-2 assume !false; 4460#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4431#L671-1 assume !false; 4778#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4783#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4296#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4310#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 4739#L582 assume !(0 != eval_~tmp~0#1); 4406#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4505#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4553#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4554#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4865#L711-3 assume !(0 == ~T4_E~0); 4859#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4708#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4535#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4536#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4701#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4702#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4483#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4484#L751-3 assume !(0 == ~E_5~0); 4601#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4347#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4348#L346-24 assume !(1 == ~m_pc~0); 4382#L346-26 is_master_triggered_~__retres1~0#1 := 0; 4479#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4426#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4427#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4811#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4420#L365-24 assume 1 == ~t1_pc~0; 4421#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4709#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4856#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4774#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4775#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4369#L384-24 assume !(1 == ~t2_pc~0); 4370#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4389#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4886#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4692#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4398#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4399#L403-24 assume 1 == ~t3_pc~0; 4516#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4557#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4558#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4649#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4650#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4456#L422-24 assume 1 == ~t4_pc~0; 4457#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4404#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4405#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4840#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4819#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4474#L441-24 assume !(1 == ~t5_pc~0); 4475#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4669#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4620#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4330#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 4331#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4753#L460-24 assume 1 == ~t6_pc~0; 4754#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4814#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4512#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4513#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4748#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4749#L774-3 assume !(1 == ~M_E~0); 4686#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4534#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4221#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4222#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4339#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4667#L809-3 assume !(1 == ~E_1~0); 4332#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4333#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4495#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4480#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4481#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4322#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4323#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4320#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4414#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4256#L1084 assume !(0 == start_simulation_~tmp~3#1); 4257#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4510#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4226#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4282#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4283#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4349#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4350#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4522#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 4459#L1065-2 [2023-11-06 22:43:10,219 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,219 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2023-11-06 22:43:10,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146090032] [2023-11-06 22:43:10,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146090032] [2023-11-06 22:43:10,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146090032] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427120157] [2023-11-06 22:43:10,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,269 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:10,269 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,269 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 1 times [2023-11-06 22:43:10,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [5127669] [2023-11-06 22:43:10,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [5127669] [2023-11-06 22:43:10,359 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [5127669] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,360 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,360 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,360 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007939400] [2023-11-06 22:43:10,360 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,361 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:10,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:10,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:10,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:10,362 INFO L87 Difference]: Start difference. First operand 693 states and 1033 transitions. cyclomatic complexity: 341 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:10,388 INFO L93 Difference]: Finished difference Result 693 states and 1032 transitions. [2023-11-06 22:43:10,388 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1032 transitions. [2023-11-06 22:43:10,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,399 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1032 transitions. [2023-11-06 22:43:10,399 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:10,400 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:10,400 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1032 transitions. [2023-11-06 22:43:10,401 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:10,402 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-06 22:43:10,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1032 transitions. [2023-11-06 22:43:10,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:10,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4891774891774892) internal successors, (1032), 692 states have internal predecessors, (1032), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,417 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1032 transitions. [2023-11-06 22:43:10,417 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-06 22:43:10,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:10,419 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1032 transitions. [2023-11-06 22:43:10,420 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:43:10,422 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1032 transitions. [2023-11-06 22:43:10,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:10,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:10,434 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,443 INFO L748 eck$LassoCheckResult]: Stem: 5950#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5951#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6110#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6111#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6248#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 5847#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5848#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5679#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5680#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5652#L507-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5653#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5821#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5981#L696 assume !(0 == ~M_E~0); 5982#L696-2 assume !(0 == ~T1_E~0); 6251#L701-1 assume !(0 == ~T2_E~0); 6254#L706-1 assume !(0 == ~T3_E~0); 6089#L711-1 assume !(0 == ~T4_E~0); 5882#L716-1 assume !(0 == ~T5_E~0); 5883#L721-1 assume !(0 == ~T6_E~0); 6047#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 6048#L731-1 assume !(0 == ~E_1~0); 6017#L736-1 assume !(0 == ~E_2~0); 6018#L741-1 assume !(0 == ~E_3~0); 6098#L746-1 assume !(0 == ~E_4~0); 5907#L751-1 assume !(0 == ~E_5~0); 5908#L756-1 assume !(0 == ~E_6~0); 5879#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5700#L346 assume !(1 == ~m_pc~0); 5701#L346-2 is_master_triggered_~__retres1~0#1 := 0; 5921#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5914#L861 assume !(0 != activate_threads_~tmp~1#1); 6230#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5733#L365 assume 1 == ~t1_pc~0; 5734#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5868#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5686#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5687#L869 assume !(0 != activate_threads_~tmp___0~0#1); 5722#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6145#L384 assume !(1 == ~t2_pc~0); 6141#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6142#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6116#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5642#L877 assume !(0 != activate_threads_~tmp___1~0#1); 5643#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5997#L403 assume 1 == ~t3_pc~0; 5884#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5885#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5610#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5611#L885 assume !(0 != activate_threads_~tmp___2~0#1); 5992#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5993#L422 assume 1 == ~t4_pc~0; 5637#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5638#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5785#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5786#L893 assume !(0 != activate_threads_~tmp___3~0#1); 6068#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5654#L441 assume !(1 == ~t5_pc~0); 5655#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6227#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5925#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5926#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6078#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6079#L460 assume 1 == ~t6_pc~0; 5598#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5599#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5662#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6100#L909 assume !(0 != activate_threads_~tmp___5~0#1); 6189#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6056#L774 assume !(1 == ~M_E~0); 6057#L774-2 assume !(1 == ~T1_E~0); 6206#L779-1 assume !(1 == ~T2_E~0); 5967#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5968#L789-1 assume !(1 == ~T4_E~0); 5717#L794-1 assume !(1 == ~T5_E~0); 5718#L799-1 assume !(1 == ~T6_E~0); 6271#L804-1 assume !(1 == ~E_M~0); 6272#L809-1 assume !(1 == ~E_1~0); 6045#L814-1 assume !(1 == ~E_2~0); 5616#L819-1 assume !(1 == ~E_3~0); 5617#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6106#L829-1 assume !(1 == ~E_5~0); 6196#L834-1 assume !(1 == ~E_6~0); 5869#L839-1 assume { :end_inline_reset_delta_events } true; 5856#L1065-2 [2023-11-06 22:43:10,443 INFO L750 eck$LassoCheckResult]: Loop: 5856#L1065-2 assume !false; 5857#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5824#L671-1 assume !false; 6175#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6176#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5689#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5703#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 6133#L582 assume !(0 != eval_~tmp~0#1); 5801#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5802#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5898#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5899#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5946#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5947#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6258#L711-3 assume !(0 == ~T4_E~0); 6252#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6102#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5928#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5929#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6094#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6095#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5876#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5877#L751-3 assume !(0 == ~E_5~0); 5994#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5740#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5741#L346-24 assume 1 == ~m_pc~0; 5776#L347-8 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5870#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5819#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5820#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6204#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5811#L365-24 assume 1 == ~t1_pc~0; 5812#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6101#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6249#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6168#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5760#L384-24 assume !(1 == ~t2_pc~0); 5761#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 5782#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6279#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6085#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5791#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5792#L403-24 assume 1 == ~t3_pc~0; 5909#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5948#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5949#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6042#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6043#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5849#L422-24 assume 1 == ~t4_pc~0; 5850#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5796#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5797#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6233#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6212#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5865#L441-24 assume !(1 == ~t5_pc~0); 5866#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6061#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6013#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5723#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 5724#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6146#L460-24 assume 1 == ~t6_pc~0; 6147#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6207#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5905#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5906#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6139#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6140#L774-3 assume !(1 == ~M_E~0); 6077#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5927#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5635#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5636#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5614#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5615#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5732#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6060#L809-3 assume !(1 == ~E_1~0); 5730#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5731#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5890#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5874#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5875#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5715#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5716#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5713#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5649#L1084 assume !(0 == start_simulation_~tmp~3#1); 5650#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5903#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5619#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5677#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 5678#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5746#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5747#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 5915#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 5856#L1065-2 [2023-11-06 22:43:10,444 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,459 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2023-11-06 22:43:10,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445732986] [2023-11-06 22:43:10,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,520 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,520 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,521 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445732986] [2023-11-06 22:43:10,521 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445732986] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,521 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,521 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,522 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103219099] [2023-11-06 22:43:10,522 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,522 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:10,523 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1334440743, now seen corresponding path program 2 times [2023-11-06 22:43:10,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2111005600] [2023-11-06 22:43:10,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,641 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2111005600] [2023-11-06 22:43:10,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2111005600] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,642 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1995278093] [2023-11-06 22:43:10,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,643 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:10,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:10,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:10,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:10,644 INFO L87 Difference]: Start difference. First operand 693 states and 1032 transitions. cyclomatic complexity: 340 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:10,665 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2023-11-06 22:43:10,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2023-11-06 22:43:10,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1031 transitions. [2023-11-06 22:43:10,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:10,677 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:10,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1031 transitions. [2023-11-06 22:43:10,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:10,679 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-06 22:43:10,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1031 transitions. [2023-11-06 22:43:10,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:10,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4877344877344878) internal successors, (1031), 692 states have internal predecessors, (1031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1031 transitions. [2023-11-06 22:43:10,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-06 22:43:10,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:10,696 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1031 transitions. [2023-11-06 22:43:10,696 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:43:10,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1031 transitions. [2023-11-06 22:43:10,700 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:10,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:10,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,702 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,702 INFO L748 eck$LassoCheckResult]: Stem: 7341#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7503#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7504#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7641#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 7240#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7241#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7068#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7069#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7045#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7046#L512-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7214#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7374#L696 assume !(0 == ~M_E~0); 7375#L696-2 assume !(0 == ~T1_E~0); 7644#L701-1 assume !(0 == ~T2_E~0); 7646#L706-1 assume !(0 == ~T3_E~0); 7482#L711-1 assume !(0 == ~T4_E~0); 7275#L716-1 assume !(0 == ~T5_E~0); 7276#L721-1 assume !(0 == ~T6_E~0); 7440#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7441#L731-1 assume !(0 == ~E_1~0); 7410#L736-1 assume !(0 == ~E_2~0); 7411#L741-1 assume !(0 == ~E_3~0); 7491#L746-1 assume !(0 == ~E_4~0); 7300#L751-1 assume !(0 == ~E_5~0); 7301#L756-1 assume !(0 == ~E_6~0); 7272#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7091#L346 assume !(1 == ~m_pc~0); 7092#L346-2 is_master_triggered_~__retres1~0#1 := 0; 7314#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7306#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7307#L861 assume !(0 != activate_threads_~tmp~1#1); 7623#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7125#L365 assume 1 == ~t1_pc~0; 7126#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7258#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7074#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7075#L869 assume !(0 != activate_threads_~tmp___0~0#1); 7115#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7538#L384 assume !(1 == ~t2_pc~0); 7532#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7533#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7505#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7033#L877 assume !(0 != activate_threads_~tmp___1~0#1); 7034#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7389#L403 assume 1 == ~t3_pc~0; 7277#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7278#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7003#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7004#L885 assume !(0 != activate_threads_~tmp___2~0#1); 7382#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7383#L422 assume 1 == ~t4_pc~0; 7028#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7029#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7178#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7179#L893 assume !(0 != activate_threads_~tmp___3~0#1); 7461#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7047#L441 assume !(1 == ~t5_pc~0); 7048#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7619#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7317#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7318#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7470#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7471#L460 assume 1 == ~t6_pc~0; 6988#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6989#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7055#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7493#L909 assume !(0 != activate_threads_~tmp___5~0#1); 7582#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7449#L774 assume !(1 == ~M_E~0); 7450#L774-2 assume !(1 == ~T1_E~0); 7599#L779-1 assume !(1 == ~T2_E~0); 7360#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7361#L789-1 assume !(1 == ~T4_E~0); 7110#L794-1 assume !(1 == ~T5_E~0); 7111#L799-1 assume !(1 == ~T6_E~0); 7664#L804-1 assume !(1 == ~E_M~0); 7665#L809-1 assume !(1 == ~E_1~0); 7437#L814-1 assume !(1 == ~E_2~0); 7007#L819-1 assume !(1 == ~E_3~0); 7008#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7499#L829-1 assume !(1 == ~E_5~0); 7589#L834-1 assume !(1 == ~E_6~0); 7259#L839-1 assume { :end_inline_reset_delta_events } true; 7245#L1065-2 [2023-11-06 22:43:10,702 INFO L750 eck$LassoCheckResult]: Loop: 7245#L1065-2 assume !false; 7246#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7217#L671-1 assume !false; 7564#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7569#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7096#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 7525#L582 assume !(0 != eval_~tmp~0#1); 7192#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7193#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7291#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7292#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7339#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7340#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7651#L711-3 assume !(0 == ~T4_E~0); 7645#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7494#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7321#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7322#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7487#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7488#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7269#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7270#L751-3 assume !(0 == ~E_5~0); 7387#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7133#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7134#L346-24 assume !(1 == ~m_pc~0); 7168#L346-26 is_master_triggered_~__retres1~0#1 := 0; 7265#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7212#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7213#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7597#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7204#L365-24 assume 1 == ~t1_pc~0; 7205#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7495#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7642#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7560#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7561#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7153#L384-24 assume !(1 == ~t2_pc~0); 7154#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 7175#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7672#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7478#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7184#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7185#L403-24 assume 1 == ~t3_pc~0; 7302#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7343#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7344#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7435#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7436#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7242#L422-24 assume 1 == ~t4_pc~0; 7243#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7190#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7191#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7626#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7605#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7260#L441-24 assume !(1 == ~t5_pc~0); 7261#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7455#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7406#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7116#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 7117#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7539#L460-24 assume 1 == ~t6_pc~0; 7540#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7600#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7298#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7299#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7534#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7535#L774-3 assume !(1 == ~M_E~0); 7472#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7320#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7031#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7032#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7009#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7010#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7128#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7453#L809-3 assume !(1 == ~E_1~0); 7123#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7124#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7283#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7267#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7268#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7108#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7109#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7106#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7042#L1084 assume !(0 == start_simulation_~tmp~3#1); 7043#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7296#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7012#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7073#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7139#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7140#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 7308#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 7245#L1065-2 [2023-11-06 22:43:10,703 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,703 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2023-11-06 22:43:10,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119913207] [2023-11-06 22:43:10,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119913207] [2023-11-06 22:43:10,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119913207] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1164345873] [2023-11-06 22:43:10,744 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,744 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:10,744 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,744 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 2 times [2023-11-06 22:43:10,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305964350] [2023-11-06 22:43:10,749 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,749 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305964350] [2023-11-06 22:43:10,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305964350] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232325928] [2023-11-06 22:43:10,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,805 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:10,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:10,805 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:10,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:10,806 INFO L87 Difference]: Start difference. First operand 693 states and 1031 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:10,825 INFO L93 Difference]: Finished difference Result 693 states and 1030 transitions. [2023-11-06 22:43:10,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1030 transitions. [2023-11-06 22:43:10,831 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 693 states and 1030 transitions. [2023-11-06 22:43:10,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 693 [2023-11-06 22:43:10,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 693 [2023-11-06 22:43:10,838 INFO L73 IsDeterministic]: Start isDeterministic. Operand 693 states and 1030 transitions. [2023-11-06 22:43:10,839 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:10,839 INFO L218 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-06 22:43:10,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 693 states and 1030 transitions. [2023-11-06 22:43:10,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 693 to 693. [2023-11-06 22:43:10,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 693 states, 693 states have (on average 1.4862914862914862) internal successors, (1030), 692 states have internal predecessors, (1030), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:10,853 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 693 states to 693 states and 1030 transitions. [2023-11-06 22:43:10,853 INFO L240 hiAutomatonCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-06 22:43:10,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:10,855 INFO L428 stractBuchiCegarLoop]: Abstraction has 693 states and 1030 transitions. [2023-11-06 22:43:10,856 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:43:10,856 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 693 states and 1030 transitions. [2023-11-06 22:43:10,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 602 [2023-11-06 22:43:10,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:10,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:10,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:10,866 INFO L748 eck$LassoCheckResult]: Stem: 8734#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8735#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8896#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8897#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9034#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 8633#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8634#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8465#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8466#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8438#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8439#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8607#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8767#L696 assume !(0 == ~M_E~0); 8768#L696-2 assume !(0 == ~T1_E~0); 9037#L701-1 assume !(0 == ~T2_E~0); 9039#L706-1 assume !(0 == ~T3_E~0); 8875#L711-1 assume !(0 == ~T4_E~0); 8668#L716-1 assume !(0 == ~T5_E~0); 8669#L721-1 assume !(0 == ~T6_E~0); 8833#L726-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8834#L731-1 assume !(0 == ~E_1~0); 8803#L736-1 assume !(0 == ~E_2~0); 8804#L741-1 assume !(0 == ~E_3~0); 8884#L746-1 assume !(0 == ~E_4~0); 8693#L751-1 assume !(0 == ~E_5~0); 8694#L756-1 assume !(0 == ~E_6~0); 8665#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8484#L346 assume !(1 == ~m_pc~0); 8485#L346-2 is_master_triggered_~__retres1~0#1 := 0; 8707#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8699#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8700#L861 assume !(0 != activate_threads_~tmp~1#1); 9016#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8519#L365 assume 1 == ~t1_pc~0; 8520#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8654#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8469#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8470#L869 assume !(0 != activate_threads_~tmp___0~0#1); 8508#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8931#L384 assume !(1 == ~t2_pc~0); 8927#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8928#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8898#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8426#L877 assume !(0 != activate_threads_~tmp___1~0#1); 8427#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8782#L403 assume 1 == ~t3_pc~0; 8670#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8671#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8396#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8397#L885 assume !(0 != activate_threads_~tmp___2~0#1); 8775#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8776#L422 assume 1 == ~t4_pc~0; 8423#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8424#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8571#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8572#L893 assume !(0 != activate_threads_~tmp___3~0#1); 8854#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8440#L441 assume !(1 == ~t5_pc~0); 8441#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9012#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8710#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8711#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8864#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8865#L460 assume 1 == ~t6_pc~0; 8381#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8382#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8448#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8886#L909 assume !(0 != activate_threads_~tmp___5~0#1); 8975#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8842#L774 assume !(1 == ~M_E~0); 8843#L774-2 assume !(1 == ~T1_E~0); 8992#L779-1 assume !(1 == ~T2_E~0); 8753#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8754#L789-1 assume !(1 == ~T4_E~0); 8503#L794-1 assume !(1 == ~T5_E~0); 8504#L799-1 assume !(1 == ~T6_E~0); 9057#L804-1 assume !(1 == ~E_M~0); 9058#L809-1 assume !(1 == ~E_1~0); 8830#L814-1 assume !(1 == ~E_2~0); 8402#L819-1 assume !(1 == ~E_3~0); 8403#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8892#L829-1 assume !(1 == ~E_5~0); 8982#L834-1 assume !(1 == ~E_6~0); 8655#L839-1 assume { :end_inline_reset_delta_events } true; 8638#L1065-2 [2023-11-06 22:43:10,866 INFO L750 eck$LassoCheckResult]: Loop: 8638#L1065-2 assume !false; 8639#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8610#L671-1 assume !false; 8957#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8962#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8475#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8489#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 8918#L582 assume !(0 != eval_~tmp~0#1); 8585#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8586#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8684#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8685#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8732#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8733#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9044#L711-3 assume !(0 == ~T4_E~0); 9038#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8887#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8714#L726-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8715#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8881#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8662#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8663#L751-3 assume !(0 == ~E_5~0); 8780#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8526#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8527#L346-24 assume !(1 == ~m_pc~0); 8561#L346-26 is_master_triggered_~__retres1~0#1 := 0; 8658#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8605#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8606#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8990#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8599#L365-24 assume 1 == ~t1_pc~0; 8600#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8888#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9035#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8953#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8954#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8548#L384-24 assume !(1 == ~t2_pc~0); 8549#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8568#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9065#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8872#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8577#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8578#L403-24 assume 1 == ~t3_pc~0; 8695#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8736#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8737#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8828#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8829#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8635#L422-24 assume 1 == ~t4_pc~0; 8636#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8582#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8583#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9019#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8998#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8651#L441-24 assume !(1 == ~t5_pc~0); 8652#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8847#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8799#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8509#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 8510#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8932#L460-24 assume 1 == ~t6_pc~0; 8933#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8993#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8691#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8692#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8925#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8926#L774-3 assume !(1 == ~M_E~0); 8863#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8713#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8421#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8422#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8400#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8401#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8518#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8846#L809-3 assume !(1 == ~E_1~0); 8513#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8514#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8674#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8659#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8660#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8501#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8502#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8499#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8593#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8435#L1084 assume !(0 == start_simulation_~tmp~3#1); 8436#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8689#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8405#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8463#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 8464#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8528#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8529#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8701#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 8638#L1065-2 [2023-11-06 22:43:10,867 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,867 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2023-11-06 22:43:10,867 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,867 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763278318] [2023-11-06 22:43:10,869 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:10,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:10,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:10,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763278318] [2023-11-06 22:43:10,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763278318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:10,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:10,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:10,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707724190] [2023-11-06 22:43:10,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:10,971 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:10,971 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:10,972 INFO L85 PathProgramCache]: Analyzing trace with hash -196811878, now seen corresponding path program 3 times [2023-11-06 22:43:10,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:10,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089514274] [2023-11-06 22:43:10,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:10,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:10,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:11,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:11,025 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:11,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089514274] [2023-11-06 22:43:11,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089514274] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:11,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:11,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:11,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824551585] [2023-11-06 22:43:11,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:11,027 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:11,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:11,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:11,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:11,028 INFO L87 Difference]: Start difference. First operand 693 states and 1030 transitions. cyclomatic complexity: 338 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:11,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:11,248 INFO L93 Difference]: Finished difference Result 1194 states and 1770 transitions. [2023-11-06 22:43:11,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1770 transitions. [2023-11-06 22:43:11,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2023-11-06 22:43:11,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1770 transitions. [2023-11-06 22:43:11,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2023-11-06 22:43:11,270 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2023-11-06 22:43:11,270 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1770 transitions. [2023-11-06 22:43:11,272 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:11,272 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1194 states and 1770 transitions. [2023-11-06 22:43:11,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1770 transitions. [2023-11-06 22:43:11,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 1193. [2023-11-06 22:43:11,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1193 states, 1193 states have (on average 1.4828164291701593) internal successors, (1769), 1192 states have internal predecessors, (1769), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:11,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1769 transitions. [2023-11-06 22:43:11,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2023-11-06 22:43:11,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:11,310 INFO L428 stractBuchiCegarLoop]: Abstraction has 1193 states and 1769 transitions. [2023-11-06 22:43:11,310 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:43:11,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1769 transitions. [2023-11-06 22:43:11,318 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1088 [2023-11-06 22:43:11,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:11,319 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:11,320 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:11,320 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:11,321 INFO L748 eck$LassoCheckResult]: Stem: 10636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10808#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10809#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10976#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 10532#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10533#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10358#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10359#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10335#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10336#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10506#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10671#L696 assume !(0 == ~M_E~0); 10672#L696-2 assume !(0 == ~T1_E~0); 10984#L701-1 assume !(0 == ~T2_E~0); 10986#L706-1 assume !(0 == ~T3_E~0); 10784#L711-1 assume !(0 == ~T4_E~0); 10567#L716-1 assume !(0 == ~T5_E~0); 10568#L721-1 assume !(0 == ~T6_E~0); 10740#L726-1 assume !(0 == ~E_M~0); 10741#L731-1 assume !(0 == ~E_1~0); 10709#L736-1 assume !(0 == ~E_2~0); 10710#L741-1 assume !(0 == ~E_3~0); 10795#L746-1 assume !(0 == ~E_4~0); 10595#L751-1 assume !(0 == ~E_5~0); 10596#L756-1 assume !(0 == ~E_6~0); 10564#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10382#L346 assume !(1 == ~m_pc~0); 10383#L346-2 is_master_triggered_~__retres1~0#1 := 0; 10609#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10601#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10602#L861 assume !(0 != activate_threads_~tmp~1#1); 10953#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10417#L365 assume 1 == ~t1_pc~0; 10418#L366 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10365#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10366#L869 assume !(0 != activate_threads_~tmp___0~0#1); 10407#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10851#L384 assume !(1 == ~t2_pc~0); 10845#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10846#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10323#L877 assume !(0 != activate_threads_~tmp___1~0#1); 10324#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10687#L403 assume 1 == ~t3_pc~0; 10569#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10570#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10293#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10294#L885 assume !(0 != activate_threads_~tmp___2~0#1); 10679#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10680#L422 assume 1 == ~t4_pc~0; 10318#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10319#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10470#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10471#L893 assume !(0 != activate_threads_~tmp___3~0#1); 10763#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10337#L441 assume !(1 == ~t5_pc~0); 10338#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10949#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10612#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10613#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10772#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10773#L460 assume 1 == ~t6_pc~0; 10278#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10279#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10797#L909 assume !(0 != activate_threads_~tmp___5~0#1); 10910#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10749#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 10750#L774-2 assume !(1 == ~T1_E~0); 11009#L779-1 assume !(1 == ~T2_E~0); 11072#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11071#L789-1 assume !(1 == ~T4_E~0); 11070#L794-1 assume !(1 == ~T5_E~0); 11069#L799-1 assume !(1 == ~T6_E~0); 11068#L804-1 assume !(1 == ~E_M~0); 11013#L809-1 assume !(1 == ~E_1~0); 10737#L814-1 assume !(1 == ~E_2~0); 10297#L819-1 assume !(1 == ~E_3~0); 10298#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10803#L829-1 assume !(1 == ~E_5~0); 10917#L834-1 assume !(1 == ~E_6~0); 10918#L839-1 assume { :end_inline_reset_delta_events } true; 11055#L1065-2 [2023-11-06 22:43:11,321 INFO L750 eck$LassoCheckResult]: Loop: 11055#L1065-2 assume !false; 10820#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10509#L671-1 assume !false; 11000#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11001#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10387#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10388#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 11039#L582 assume !(0 != eval_~tmp~0#1); 11041#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10962#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10963#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11045#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11412#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11411#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11410#L711-3 assume !(0 == ~T4_E~0); 11409#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11408#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11407#L726-3 assume !(0 == ~E_M~0); 11406#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11405#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11404#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11403#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11402#L751-3 assume !(0 == ~E_5~0); 11401#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11400#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11399#L346-24 assume !(1 == ~m_pc~0); 11397#L346-26 is_master_triggered_~__retres1~0#1 := 0; 11396#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11395#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11394#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11393#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11392#L365-24 assume 1 == ~t1_pc~0; 11390#L366-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11389#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11388#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11387#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11386#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11385#L384-24 assume !(1 == ~t2_pc~0); 11383#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11382#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11381#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11380#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11379#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11378#L403-24 assume 1 == ~t3_pc~0; 11376#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11375#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11374#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11373#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11372#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11371#L422-24 assume !(1 == ~t4_pc~0); 11369#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11368#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11367#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11366#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11365#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11364#L441-24 assume 1 == ~t5_pc~0; 11362#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11361#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11360#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11359#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 11358#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11357#L460-24 assume 1 == ~t6_pc~0; 11355#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11354#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11353#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11352#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11351#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11350#L774-3 assume !(1 == ~M_E~0); 11026#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11349#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11348#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11347#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11346#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11345#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11344#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10754#L809-3 assume !(1 == ~E_1~0); 11343#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11342#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11341#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11340#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11339#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11338#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11334#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11330#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11329#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11328#L1084 assume !(0 == start_simulation_~tmp~3#1); 10941#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 11327#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 11320#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 11319#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 11318#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11317#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11316#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11057#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 11055#L1065-2 [2023-11-06 22:43:11,322 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:11,322 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2023-11-06 22:43:11,322 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:11,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [699411662] [2023-11-06 22:43:11,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:11,323 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:11,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:11,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:11,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:11,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [699411662] [2023-11-06 22:43:11,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [699411662] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:11,420 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:11,420 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:11,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [988426048] [2023-11-06 22:43:11,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:11,421 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:11,422 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:11,422 INFO L85 PathProgramCache]: Analyzing trace with hash -86295588, now seen corresponding path program 1 times [2023-11-06 22:43:11,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:11,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1068072332] [2023-11-06 22:43:11,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:11,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:11,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:11,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:11,467 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:11,467 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1068072332] [2023-11-06 22:43:11,467 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1068072332] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:11,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:11,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:11,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1032241518] [2023-11-06 22:43:11,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:11,469 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:11,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:11,469 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:11,469 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:11,470 INFO L87 Difference]: Start difference. First operand 1193 states and 1769 transitions. cyclomatic complexity: 578 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:11,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:11,768 INFO L93 Difference]: Finished difference Result 3185 states and 4637 transitions. [2023-11-06 22:43:11,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3185 states and 4637 transitions. [2023-11-06 22:43:11,796 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2970 [2023-11-06 22:43:11,822 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3185 states to 3185 states and 4637 transitions. [2023-11-06 22:43:11,823 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3185 [2023-11-06 22:43:11,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3185 [2023-11-06 22:43:11,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3185 states and 4637 transitions. [2023-11-06 22:43:11,832 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:11,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3185 states and 4637 transitions. [2023-11-06 22:43:11,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3185 states and 4637 transitions. [2023-11-06 22:43:11,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3185 to 2997. [2023-11-06 22:43:11,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2997 states, 2997 states have (on average 1.4617951284617952) internal successors, (4381), 2996 states have internal predecessors, (4381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:11,908 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2997 states to 2997 states and 4381 transitions. [2023-11-06 22:43:11,908 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2997 states and 4381 transitions. [2023-11-06 22:43:11,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:11,912 INFO L428 stractBuchiCegarLoop]: Abstraction has 2997 states and 4381 transitions. [2023-11-06 22:43:11,913 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:43:11,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2997 states and 4381 transitions. [2023-11-06 22:43:11,931 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2884 [2023-11-06 22:43:11,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:11,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:11,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:11,934 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:11,934 INFO L748 eck$LassoCheckResult]: Stem: 15019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 15020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15209#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15210#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15393#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 14915#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14916#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14745#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14746#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14722#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14723#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14890#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15056#L696 assume !(0 == ~M_E~0); 15057#L696-2 assume !(0 == ~T1_E~0); 15402#L701-1 assume !(0 == ~T2_E~0); 15405#L706-1 assume !(0 == ~T3_E~0); 15181#L711-1 assume !(0 == ~T4_E~0); 14951#L716-1 assume !(0 == ~T5_E~0); 14952#L721-1 assume !(0 == ~T6_E~0); 15130#L726-1 assume !(0 == ~E_M~0); 15131#L731-1 assume !(0 == ~E_1~0); 15094#L736-1 assume !(0 == ~E_2~0); 15095#L741-1 assume !(0 == ~E_3~0); 15191#L746-1 assume !(0 == ~E_4~0); 14977#L751-1 assume !(0 == ~E_5~0); 14978#L756-1 assume !(0 == ~E_6~0); 14948#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14768#L346 assume !(1 == ~m_pc~0); 14769#L346-2 is_master_triggered_~__retres1~0#1 := 0; 14992#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14984#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14985#L861 assume !(0 != activate_threads_~tmp~1#1); 15365#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14802#L365 assume !(1 == ~t1_pc~0); 14803#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15380#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14751#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14752#L869 assume !(0 != activate_threads_~tmp___0~0#1); 14792#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15256#L384 assume !(1 == ~t2_pc~0); 15250#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15251#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15211#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14710#L877 assume !(0 != activate_threads_~tmp___1~0#1); 14711#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15073#L403 assume 1 == ~t3_pc~0; 14953#L404 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14954#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14680#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14681#L885 assume !(0 != activate_threads_~tmp___2~0#1); 15066#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15067#L422 assume 1 == ~t4_pc~0; 14705#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14706#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14855#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14856#L893 assume !(0 != activate_threads_~tmp___3~0#1); 15158#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14724#L441 assume !(1 == ~t5_pc~0); 14725#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15360#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14995#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14996#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15168#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15169#L460 assume 1 == ~t6_pc~0; 14666#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14667#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14732#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15194#L909 assume !(0 != activate_threads_~tmp___5~0#1); 15314#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15142#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 15143#L774-2 assume !(1 == ~T1_E~0); 15336#L779-1 assume !(1 == ~T2_E~0); 15038#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15039#L789-1 assume !(1 == ~T4_E~0); 14787#L794-1 assume !(1 == ~T5_E~0); 14788#L799-1 assume !(1 == ~T6_E~0); 15445#L804-1 assume !(1 == ~E_M~0); 15446#L809-1 assume !(1 == ~E_1~0); 15127#L814-1 assume !(1 == ~E_2~0); 14684#L819-1 assume !(1 == ~E_3~0); 14685#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15203#L829-1 assume !(1 == ~E_5~0); 15321#L834-1 assume !(1 == ~E_6~0); 15322#L839-1 assume { :end_inline_reset_delta_events } true; 14920#L1065-2 [2023-11-06 22:43:11,934 INFO L750 eck$LassoCheckResult]: Loop: 14920#L1065-2 assume !false; 14921#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15288#L671-1 assume !false; 15289#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15295#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14759#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15241#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 15242#L582 assume !(0 != eval_~tmp~0#1); 16903#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16901#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16898#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16899#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17217#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17216#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17215#L711-3 assume !(0 == ~T4_E~0); 17214#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17213#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17212#L726-3 assume !(0 == ~E_M~0); 17211#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17210#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17209#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17208#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17207#L751-3 assume !(0 == ~E_5~0); 17206#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17205#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17204#L346-24 assume !(1 == ~m_pc~0); 17203#L346-26 is_master_triggered_~__retres1~0#1 := 0; 17202#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17201#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17200#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17199#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17198#L365-24 assume !(1 == ~t1_pc~0); 17197#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 17196#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17195#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17194#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17193#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17192#L384-24 assume 1 == ~t2_pc~0; 15504#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 14852#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15472#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15176#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 14862#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14863#L403-24 assume 1 == ~t3_pc~0; 14979#L404-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15021#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15122#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15123#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14917#L422-24 assume 1 == ~t4_pc~0; 14918#L423-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14868#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14869#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15368#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15344#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14935#L441-24 assume !(1 == ~t5_pc~0); 14936#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 15150#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15090#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14793#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 14794#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15259#L460-24 assume 1 == ~t6_pc~0; 15260#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15337#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 14975#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14976#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15252#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15253#L774-3 assume !(1 == ~M_E~0); 15170#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14998#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14708#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14709#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14686#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14687#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14804#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15148#L809-3 assume !(1 == ~E_1~0); 17149#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17147#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17145#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17143#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17141#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17139#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15346#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 14783#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15156#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15157#L1084 assume !(0 == start_simulation_~tmp~3#1); 15352#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15377#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16957#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 14749#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14750#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14815#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14816#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 15381#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 14920#L1065-2 [2023-11-06 22:43:11,935 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:11,935 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2023-11-06 22:43:11,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:11,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1276477532] [2023-11-06 22:43:11,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:11,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:11,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:12,004 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:12,005 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:12,005 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1276477532] [2023-11-06 22:43:12,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1276477532] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:12,005 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:12,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:12,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79771071] [2023-11-06 22:43:12,006 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:12,006 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:12,006 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:12,007 INFO L85 PathProgramCache]: Analyzing trace with hash 166915036, now seen corresponding path program 1 times [2023-11-06 22:43:12,007 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:12,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1337897780] [2023-11-06 22:43:12,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:12,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:12,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:12,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:12,063 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:12,063 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1337897780] [2023-11-06 22:43:12,063 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1337897780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:12,064 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:12,064 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:12,064 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694878997] [2023-11-06 22:43:12,064 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:12,064 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:12,065 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:12,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:12,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:12,065 INFO L87 Difference]: Start difference. First operand 2997 states and 4381 transitions. cyclomatic complexity: 1388 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:12,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:12,333 INFO L93 Difference]: Finished difference Result 8208 states and 11848 transitions. [2023-11-06 22:43:12,333 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8208 states and 11848 transitions. [2023-11-06 22:43:12,384 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7846 [2023-11-06 22:43:12,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8208 states to 8208 states and 11848 transitions. [2023-11-06 22:43:12,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8208 [2023-11-06 22:43:12,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8208 [2023-11-06 22:43:12,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8208 states and 11848 transitions. [2023-11-06 22:43:12,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:12,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8208 states and 11848 transitions. [2023-11-06 22:43:12,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8208 states and 11848 transitions. [2023-11-06 22:43:12,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8208 to 7804. [2023-11-06 22:43:12,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7804 states, 7804 states have (on average 1.4492567913890313) internal successors, (11310), 7803 states have internal predecessors, (11310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:12,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7804 states to 7804 states and 11310 transitions. [2023-11-06 22:43:12,724 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7804 states and 11310 transitions. [2023-11-06 22:43:12,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:12,726 INFO L428 stractBuchiCegarLoop]: Abstraction has 7804 states and 11310 transitions. [2023-11-06 22:43:12,726 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:43:12,726 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7804 states and 11310 transitions. [2023-11-06 22:43:12,816 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7672 [2023-11-06 22:43:12,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:12,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:12,818 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:12,818 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:12,819 INFO L748 eck$LassoCheckResult]: Stem: 26235#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 26236#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26423#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26424#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26608#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 26130#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26131#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25959#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25960#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25935#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25936#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26105#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26270#L696 assume !(0 == ~M_E~0); 26271#L696-2 assume !(0 == ~T1_E~0); 26614#L701-1 assume !(0 == ~T2_E~0); 26616#L706-1 assume !(0 == ~T3_E~0); 26392#L711-1 assume !(0 == ~T4_E~0); 26166#L716-1 assume !(0 == ~T5_E~0); 26167#L721-1 assume !(0 == ~T6_E~0); 26344#L726-1 assume !(0 == ~E_M~0); 26345#L731-1 assume !(0 == ~E_1~0); 26308#L736-1 assume !(0 == ~E_2~0); 26309#L741-1 assume !(0 == ~E_3~0); 26401#L746-1 assume !(0 == ~E_4~0); 26189#L751-1 assume !(0 == ~E_5~0); 26190#L756-1 assume !(0 == ~E_6~0); 26163#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25981#L346 assume !(1 == ~m_pc~0); 25982#L346-2 is_master_triggered_~__retres1~0#1 := 0; 26202#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26194#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 26195#L861 assume !(0 != activate_threads_~tmp~1#1); 26574#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26015#L365 assume !(1 == ~t1_pc~0); 26016#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26593#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25965#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25966#L869 assume !(0 != activate_threads_~tmp___0~0#1); 26005#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26467#L384 assume !(1 == ~t2_pc~0); 26461#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26462#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26426#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25923#L877 assume !(0 != activate_threads_~tmp___1~0#1); 25924#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 26287#L403 assume !(1 == ~t3_pc~0); 26288#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26505#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25896#L885 assume !(0 != activate_threads_~tmp___2~0#1); 26279#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26280#L422 assume 1 == ~t4_pc~0; 25918#L423 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25919#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26068#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26069#L893 assume !(0 != activate_threads_~tmp___3~0#1); 26370#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25937#L441 assume !(1 == ~t5_pc~0); 25938#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 26569#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26205#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26206#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26379#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26380#L460 assume 1 == ~t6_pc~0; 25881#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25882#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 26404#L909 assume !(0 != activate_threads_~tmp___5~0#1); 26522#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26355#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 26356#L774-2 assume !(1 == ~T1_E~0); 28914#L779-1 assume !(1 == ~T2_E~0); 28912#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28910#L789-1 assume !(1 == ~T4_E~0); 28908#L794-1 assume !(1 == ~T5_E~0); 26704#L799-1 assume !(1 == ~T6_E~0); 26669#L804-1 assume !(1 == ~E_M~0); 26670#L809-1 assume !(1 == ~E_1~0); 26701#L814-1 assume !(1 == ~E_2~0); 28600#L819-1 assume !(1 == ~E_3~0); 28599#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28598#L829-1 assume !(1 == ~E_5~0); 28596#L834-1 assume !(1 == ~E_6~0); 26147#L839-1 assume { :end_inline_reset_delta_events } true; 26148#L1065-2 [2023-11-06 22:43:12,819 INFO L750 eck$LassoCheckResult]: Loop: 26148#L1065-2 assume !false; 29347#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29341#L671-1 assume !false; 29342#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29334#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29329#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 32996#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 32994#L582 assume !(0 != eval_~tmp~0#1); 30569#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 30564#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30562#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30559#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30557#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30555#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30552#L711-3 assume !(0 == ~T4_E~0); 30549#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 30546#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30543#L726-3 assume !(0 == ~E_M~0); 30539#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30536#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 30533#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30530#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30527#L751-3 assume !(0 == ~E_5~0); 30523#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 30519#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30516#L346-24 assume !(1 == ~m_pc~0); 30513#L346-26 is_master_triggered_~__retres1~0#1 := 0; 30510#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30507#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30503#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30499#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30496#L365-24 assume !(1 == ~t1_pc~0); 30493#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 30490#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30485#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30480#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 30477#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30471#L384-24 assume !(1 == ~t2_pc~0); 30467#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 30424#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30421#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30417#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30411#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30406#L403-24 assume !(1 == ~t3_pc~0); 30402#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 30398#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30391#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30371#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30368#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30357#L422-24 assume !(1 == ~t4_pc~0); 29489#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 29488#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29487#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29486#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29485#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29484#L441-24 assume 1 == ~t5_pc~0; 29482#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29481#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29478#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29477#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 29476#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29475#L460-24 assume 1 == ~t6_pc~0; 29473#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29472#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29466#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29464#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29462#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29460#L774-3 assume !(1 == ~M_E~0); 29459#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29456#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29453#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29451#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29449#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29447#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29445#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29443#L809-3 assume !(1 == ~E_1~0); 29442#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29440#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29438#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29436#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29433#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29434#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29410#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29407#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 33162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 29398#L1084 assume !(0 == start_simulation_~tmp~3#1); 29397#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29370#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29363#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 29359#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29356#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29354#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 29352#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 26148#L1065-2 [2023-11-06 22:43:12,820 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:12,820 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2023-11-06 22:43:12,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:12,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416211787] [2023-11-06 22:43:12,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:12,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:12,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:12,879 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:12,879 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:12,879 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416211787] [2023-11-06 22:43:12,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416211787] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:12,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:12,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:43:12,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442495086] [2023-11-06 22:43:12,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:12,885 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:12,885 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:12,885 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 1 times [2023-11-06 22:43:12,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:12,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965975575] [2023-11-06 22:43:12,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:12,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:12,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:12,940 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:12,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:12,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965975575] [2023-11-06 22:43:12,941 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965975575] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:12,941 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:12,942 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:12,942 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1732557909] [2023-11-06 22:43:12,942 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:12,942 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:12,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:12,943 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:12,943 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:12,944 INFO L87 Difference]: Start difference. First operand 7804 states and 11310 transitions. cyclomatic complexity: 3514 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:13,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:13,093 INFO L93 Difference]: Finished difference Result 14511 states and 20954 transitions. [2023-11-06 22:43:13,094 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14511 states and 20954 transitions. [2023-11-06 22:43:13,187 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14314 [2023-11-06 22:43:13,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14511 states to 14511 states and 20954 transitions. [2023-11-06 22:43:13,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14511 [2023-11-06 22:43:13,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14511 [2023-11-06 22:43:13,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14511 states and 20954 transitions. [2023-11-06 22:43:13,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:13,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14511 states and 20954 transitions. [2023-11-06 22:43:13,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14511 states and 20954 transitions. [2023-11-06 22:43:13,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14511 to 14475. [2023-11-06 22:43:13,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14475 states, 14475 states have (on average 1.4451122625215889) internal successors, (20918), 14474 states have internal predecessors, (20918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:13,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14475 states to 14475 states and 20918 transitions. [2023-11-06 22:43:13,877 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14475 states and 20918 transitions. [2023-11-06 22:43:13,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:13,880 INFO L428 stractBuchiCegarLoop]: Abstraction has 14475 states and 20918 transitions. [2023-11-06 22:43:13,881 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:43:13,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14475 states and 20918 transitions. [2023-11-06 22:43:13,957 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14278 [2023-11-06 22:43:13,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:13,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:13,960 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:13,960 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:13,961 INFO L748 eck$LassoCheckResult]: Stem: 48545#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 48546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48723#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48724#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48888#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 48441#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48442#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48276#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48277#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48253#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48254#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48416#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48581#L696 assume !(0 == ~M_E~0); 48582#L696-2 assume !(0 == ~T1_E~0); 48894#L701-1 assume !(0 == ~T2_E~0); 48896#L706-1 assume !(0 == ~T3_E~0); 48696#L711-1 assume !(0 == ~T4_E~0); 48476#L716-1 assume !(0 == ~T5_E~0); 48477#L721-1 assume !(0 == ~T6_E~0); 48653#L726-1 assume !(0 == ~E_M~0); 48654#L731-1 assume !(0 == ~E_1~0); 48619#L736-1 assume !(0 == ~E_2~0); 48620#L741-1 assume !(0 == ~E_3~0); 48705#L746-1 assume !(0 == ~E_4~0); 48500#L751-1 assume !(0 == ~E_5~0); 48501#L756-1 assume !(0 == ~E_6~0); 48473#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48298#L346 assume !(1 == ~m_pc~0); 48299#L346-2 is_master_triggered_~__retres1~0#1 := 0; 48513#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48505#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48506#L861 assume !(0 != activate_threads_~tmp~1#1); 48864#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48331#L365 assume !(1 == ~t1_pc~0); 48332#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48876#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48283#L869 assume !(0 != activate_threads_~tmp___0~0#1); 48321#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48759#L384 assume !(1 == ~t2_pc~0); 48754#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48755#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48725#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48242#L877 assume !(0 != activate_threads_~tmp___1~0#1); 48243#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48598#L403 assume !(1 == ~t3_pc~0); 48599#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 48798#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 48217#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48218#L885 assume !(0 != activate_threads_~tmp___2~0#1); 48591#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48592#L422 assume !(1 == ~t4_pc~0); 48721#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48722#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48382#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48383#L893 assume !(0 != activate_threads_~tmp___3~0#1); 48676#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48255#L441 assume !(1 == ~t5_pc~0); 48256#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48859#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48516#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48517#L901 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48684#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48685#L460 assume 1 == ~t6_pc~0; 48203#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48204#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48263#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 48707#L909 assume !(0 != activate_threads_~tmp___5~0#1); 48813#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48662#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 48663#L774-2 assume !(1 == ~T1_E~0); 48834#L779-1 assume !(1 == ~T2_E~0); 48563#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48564#L789-1 assume !(1 == ~T4_E~0); 48316#L794-1 assume !(1 == ~T5_E~0); 48317#L799-1 assume !(1 == ~T6_E~0); 48945#L804-1 assume !(1 == ~E_M~0); 48946#L809-1 assume !(1 == ~E_1~0); 48648#L814-1 assume !(1 == ~E_2~0); 48221#L819-1 assume !(1 == ~E_3~0); 48222#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48715#L829-1 assume !(1 == ~E_5~0); 48821#L834-1 assume !(1 == ~E_6~0); 48457#L839-1 assume { :end_inline_reset_delta_events } true; 48458#L1065-2 [2023-11-06 22:43:13,962 INFO L750 eck$LassoCheckResult]: Loop: 48458#L1065-2 assume !false; 61413#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 61410#L671-1 assume !false; 61408#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 61399#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 61392#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 61390#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 61386#L582 assume !(0 != eval_~tmp~0#1); 61387#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 61799#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 61798#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 61797#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 61796#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61795#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 61794#L711-3 assume !(0 == ~T4_E~0); 61793#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 61792#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 61791#L726-3 assume !(0 == ~E_M~0); 61790#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 61789#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 61788#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 61787#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 61786#L751-3 assume !(0 == ~E_5~0); 61785#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61783#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 61781#L346-24 assume !(1 == ~m_pc~0); 61779#L346-26 is_master_triggered_~__retres1~0#1 := 0; 61777#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 61775#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 61773#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 61771#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 61769#L365-24 assume !(1 == ~t1_pc~0); 61767#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 61765#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 61763#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 61761#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 61759#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 61756#L384-24 assume !(1 == ~t2_pc~0); 61753#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 61751#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 61749#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 61747#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 61745#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 61743#L403-24 assume !(1 == ~t3_pc~0); 61741#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 61739#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 61737#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 61735#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61733#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 61731#L422-24 assume !(1 == ~t4_pc~0); 61729#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 61727#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 61725#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 61723#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61721#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 61718#L441-24 assume 1 == ~t5_pc~0; 61715#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 61713#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 61711#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 61709#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 61707#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 61704#L460-24 assume 1 == ~t6_pc~0; 61701#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 61699#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 61697#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 61695#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 61693#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 61691#L774-3 assume !(1 == ~M_E~0); 59343#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61688#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 61686#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 61684#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 61682#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 61680#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61678#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59328#L809-3 assume !(1 == ~E_1~0); 61675#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61673#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61671#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 61669#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 61668#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61667#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 61600#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 61595#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 61593#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 61591#L1084 assume !(0 == start_simulation_~tmp~3#1); 61588#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 61586#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 61577#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 61575#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 61573#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61571#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61447#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 61432#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 48458#L1065-2 [2023-11-06 22:43:13,962 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:13,963 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2023-11-06 22:43:13,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:13,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2108230320] [2023-11-06 22:43:13,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:13,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:13,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:14,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:14,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:14,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2108230320] [2023-11-06 22:43:14,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2108230320] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:14,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:14,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:43:14,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [684748809] [2023-11-06 22:43:14,054 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:14,054 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:14,055 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:14,055 INFO L85 PathProgramCache]: Analyzing trace with hash -1610208162, now seen corresponding path program 2 times [2023-11-06 22:43:14,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:14,056 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1809597003] [2023-11-06 22:43:14,056 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:14,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:14,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:14,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:14,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:14,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1809597003] [2023-11-06 22:43:14,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1809597003] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:14,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:14,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:14,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520507907] [2023-11-06 22:43:14,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:14,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:14,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:14,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:43:14,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:43:14,119 INFO L87 Difference]: Start difference. First operand 14475 states and 20918 transitions. cyclomatic complexity: 6459 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:14,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:14,620 INFO L93 Difference]: Finished difference Result 29907 states and 42773 transitions. [2023-11-06 22:43:14,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29907 states and 42773 transitions. [2023-11-06 22:43:14,853 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29566 [2023-11-06 22:43:14,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29907 states to 29907 states and 42773 transitions. [2023-11-06 22:43:14,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29907 [2023-11-06 22:43:15,001 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29907 [2023-11-06 22:43:15,001 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29907 states and 42773 transitions. [2023-11-06 22:43:15,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:15,027 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29907 states and 42773 transitions. [2023-11-06 22:43:15,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29907 states and 42773 transitions. [2023-11-06 22:43:15,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29907 to 15084. [2023-11-06 22:43:15,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15084 states, 15084 states have (on average 1.427141341819146) internal successors, (21527), 15083 states have internal predecessors, (21527), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:15,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15084 states to 15084 states and 21527 transitions. [2023-11-06 22:43:15,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15084 states and 21527 transitions. [2023-11-06 22:43:15,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:43:15,481 INFO L428 stractBuchiCegarLoop]: Abstraction has 15084 states and 21527 transitions. [2023-11-06 22:43:15,481 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:43:15,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15084 states and 21527 transitions. [2023-11-06 22:43:15,532 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14884 [2023-11-06 22:43:15,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:15,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:15,534 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:15,534 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:15,534 INFO L748 eck$LassoCheckResult]: Stem: 92957#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 92958#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 93151#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 93152#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 93357#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 92845#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92846#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92677#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92678#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92649#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 92650#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92823#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92996#L696 assume !(0 == ~M_E~0); 92997#L696-2 assume !(0 == ~T1_E~0); 93368#L701-1 assume !(0 == ~T2_E~0); 93370#L706-1 assume !(0 == ~T3_E~0); 93119#L711-1 assume !(0 == ~T4_E~0); 92882#L716-1 assume !(0 == ~T5_E~0); 92883#L721-1 assume !(0 == ~T6_E~0); 93070#L726-1 assume !(0 == ~E_M~0); 93071#L731-1 assume !(0 == ~E_1~0); 93033#L736-1 assume !(0 == ~E_2~0); 93034#L741-1 assume !(0 == ~E_3~0); 93128#L746-1 assume !(0 == ~E_4~0); 92906#L751-1 assume !(0 == ~E_5~0); 92907#L756-1 assume !(0 == ~E_6~0); 92879#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92697#L346 assume !(1 == ~m_pc~0); 92698#L346-2 is_master_triggered_~__retres1~0#1 := 0; 92924#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92914#L861 assume !(0 != activate_threads_~tmp~1#1); 93319#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92731#L365 assume !(1 == ~t1_pc~0); 92732#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93338#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92683#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92684#L869 assume !(0 != activate_threads_~tmp___0~0#1); 92719#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 93198#L384 assume !(1 == ~t2_pc~0); 93194#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 93195#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 93158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92639#L877 assume !(0 != activate_threads_~tmp___1~0#1); 92640#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 93012#L403 assume !(1 == ~t3_pc~0); 93013#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 93241#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92612#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92613#L885 assume !(0 != activate_threads_~tmp___2~0#1); 93006#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 93007#L422 assume !(1 == ~t4_pc~0); 93149#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 93150#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92784#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92785#L893 assume !(0 != activate_threads_~tmp___3~0#1); 93098#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92651#L441 assume !(1 == ~t5_pc~0); 92652#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 93315#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 93436#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 93494#L901 assume !(0 != activate_threads_~tmp___4~0#1); 93108#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 93109#L460 assume 1 == ~t6_pc~0; 92601#L461 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 92602#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92661#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 93131#L909 assume !(0 != activate_threads_~tmp___5~0#1); 93260#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 93079#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 93080#L774-2 assume !(1 == ~T1_E~0); 98799#L779-1 assume !(1 == ~T2_E~0); 98798#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98797#L789-1 assume !(1 == ~T4_E~0); 98796#L794-1 assume !(1 == ~T5_E~0); 98795#L799-1 assume !(1 == ~T6_E~0); 98794#L804-1 assume !(1 == ~E_M~0); 93421#L809-1 assume !(1 == ~E_1~0); 98793#L814-1 assume !(1 == ~E_2~0); 98792#L819-1 assume !(1 == ~E_3~0); 98791#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 93459#L829-1 assume !(1 == ~E_5~0); 93267#L834-1 assume !(1 == ~E_6~0); 92865#L839-1 assume { :end_inline_reset_delta_events } true; 92866#L1065-2 [2023-11-06 22:43:15,535 INFO L750 eck$LassoCheckResult]: Loop: 92866#L1065-2 assume !false; 99860#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 99851#L671-1 assume !false; 99849#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 99846#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 99837#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 99834#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 99830#L582 assume !(0 != eval_~tmp~0#1); 99831#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 100316#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 100315#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 100314#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 100313#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 100312#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 100311#L711-3 assume !(0 == ~T4_E~0); 100310#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100309#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 100308#L726-3 assume !(0 == ~E_M~0); 100307#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 100306#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100305#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100304#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 100303#L751-3 assume !(0 == ~E_5~0); 100302#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 100301#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 100300#L346-24 assume !(1 == ~m_pc~0); 100299#L346-26 is_master_triggered_~__retres1~0#1 := 0; 100298#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100297#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 100296#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 100295#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 100294#L365-24 assume !(1 == ~t1_pc~0); 100293#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 100292#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100291#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100290#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100289#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100288#L384-24 assume 1 == ~t2_pc~0; 100287#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 100285#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100284#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 100283#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 100282#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100281#L403-24 assume !(1 == ~t3_pc~0); 100280#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 100279#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 100278#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100277#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 100276#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 100275#L422-24 assume !(1 == ~t4_pc~0); 100274#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 100273#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 100272#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 100271#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 100270#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100269#L441-24 assume !(1 == ~t5_pc~0); 100267#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 100265#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 100263#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 100261#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 100258#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100256#L460-24 assume 1 == ~t6_pc~0; 100253#L461-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100195#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100188#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100182#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 100129#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100127#L774-3 assume !(1 == ~M_E~0); 98902#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 100123#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100120#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 100117#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100114#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 100111#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 100108#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98887#L809-3 assume !(1 == ~E_1~0); 100086#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 100079#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 100074#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 100069#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 100066#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 100064#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 100058#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 100050#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 100045#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 100040#L1084 assume !(0 == start_simulation_~tmp~3#1); 100036#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 99925#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 99917#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 99915#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 99913#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 99911#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 99909#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 99907#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 92866#L1065-2 [2023-11-06 22:43:15,535 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:15,536 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2023-11-06 22:43:15,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:15,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497702736] [2023-11-06 22:43:15,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:15,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:15,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:15,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:15,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:15,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497702736] [2023-11-06 22:43:15,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497702736] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:15,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:15,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:15,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [158170684] [2023-11-06 22:43:15,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:15,606 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:15,606 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:15,607 INFO L85 PathProgramCache]: Analyzing trace with hash 1487563422, now seen corresponding path program 1 times [2023-11-06 22:43:15,607 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:15,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143186620] [2023-11-06 22:43:15,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:15,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:15,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:15,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:15,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:15,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143186620] [2023-11-06 22:43:15,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143186620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:15,661 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:15,661 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:15,662 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808061983] [2023-11-06 22:43:15,662 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:15,662 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:15,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:15,663 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:15,663 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:15,663 INFO L87 Difference]: Start difference. First operand 15084 states and 21527 transitions. cyclomatic complexity: 6459 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:16,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:16,360 INFO L93 Difference]: Finished difference Result 42609 states and 60184 transitions. [2023-11-06 22:43:16,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42609 states and 60184 transitions. [2023-11-06 22:43:16,746 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41218 [2023-11-06 22:43:16,904 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42609 states to 42609 states and 60184 transitions. [2023-11-06 22:43:16,904 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42609 [2023-11-06 22:43:16,932 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42609 [2023-11-06 22:43:16,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42609 states and 60184 transitions. [2023-11-06 22:43:17,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:17,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42609 states and 60184 transitions. [2023-11-06 22:43:17,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42609 states and 60184 transitions. [2023-11-06 22:43:17,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42609 to 41425. [2023-11-06 22:43:17,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41425 states, 41425 states have (on average 1.4169704284852143) internal successors, (58698), 41424 states have internal predecessors, (58698), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:18,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41425 states to 41425 states and 58698 transitions. [2023-11-06 22:43:18,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41425 states and 58698 transitions. [2023-11-06 22:43:18,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:18,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 41425 states and 58698 transitions. [2023-11-06 22:43:18,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:43:18,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41425 states and 58698 transitions. [2023-11-06 22:43:18,227 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41074 [2023-11-06 22:43:18,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:18,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:18,229 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:18,230 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:18,230 INFO L748 eck$LassoCheckResult]: Stem: 150647#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 150648#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 150838#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 150839#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151055#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 150543#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150544#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150376#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150377#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 150350#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 150351#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 150521#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 150683#L696 assume !(0 == ~M_E~0); 150684#L696-2 assume !(0 == ~T1_E~0); 151064#L701-1 assume !(0 == ~T2_E~0); 151065#L706-1 assume !(0 == ~T3_E~0); 150806#L711-1 assume !(0 == ~T4_E~0); 150578#L716-1 assume !(0 == ~T5_E~0); 150579#L721-1 assume !(0 == ~T6_E~0); 150755#L726-1 assume !(0 == ~E_M~0); 150756#L731-1 assume !(0 == ~E_1~0); 150717#L736-1 assume !(0 == ~E_2~0); 150718#L741-1 assume !(0 == ~E_3~0); 150818#L746-1 assume !(0 == ~E_4~0); 150600#L751-1 assume !(0 == ~E_5~0); 150601#L756-1 assume !(0 == ~E_6~0); 150575#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 150396#L346 assume !(1 == ~m_pc~0); 150397#L346-2 is_master_triggered_~__retres1~0#1 := 0; 150615#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 150605#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 150606#L861 assume !(0 != activate_threads_~tmp~1#1); 151019#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 150429#L365 assume !(1 == ~t1_pc~0); 150430#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 151042#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 150382#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150383#L869 assume !(0 != activate_threads_~tmp___0~0#1); 150418#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 150888#L384 assume !(1 == ~t2_pc~0); 150884#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 150885#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 150845#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 150340#L877 assume !(0 != activate_threads_~tmp___1~0#1); 150341#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 150698#L403 assume !(1 == ~t3_pc~0); 150699#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 150932#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 150312#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 150313#L885 assume !(0 != activate_threads_~tmp___2~0#1); 150690#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 150691#L422 assume !(1 == ~t4_pc~0); 150836#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 150837#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 150481#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 150482#L893 assume !(0 != activate_threads_~tmp___3~0#1); 150781#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 150352#L441 assume !(1 == ~t5_pc~0); 150353#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 151013#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 150617#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 150618#L901 assume !(0 != activate_threads_~tmp___4~0#1); 150793#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 150794#L460 assume !(1 == ~t6_pc~0); 150960#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 150361#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150362#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 150820#L909 assume !(0 != activate_threads_~tmp___5~0#1); 150955#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150765#L774 assume 1 == ~M_E~0;~M_E~0 := 2; 150766#L774-2 assume !(1 == ~T1_E~0); 150985#L779-1 assume !(1 == ~T2_E~0); 150986#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 151112#L789-1 assume !(1 == ~T4_E~0); 151113#L794-1 assume !(1 == ~T5_E~0); 151172#L799-1 assume !(1 == ~T6_E~0); 151173#L804-1 assume !(1 == ~E_M~0); 151125#L809-1 assume !(1 == ~E_1~0); 151165#L814-1 assume !(1 == ~E_2~0); 150318#L819-1 assume !(1 == ~E_3~0); 150319#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 151159#L829-1 assume !(1 == ~E_5~0); 151160#L834-1 assume !(1 == ~E_6~0); 150562#L839-1 assume { :end_inline_reset_delta_events } true; 150563#L1065-2 [2023-11-06 22:43:18,231 INFO L750 eck$LassoCheckResult]: Loop: 150563#L1065-2 assume !false; 179593#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179551#L671-1 assume !false; 179591#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 179577#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 179571#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 179570#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 179569#L582 assume !(0 != eval_~tmp~0#1); 158011#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 158010#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 158009#L696-3 assume 0 == ~M_E~0;~M_E~0 := 1; 158008#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 158007#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 158006#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 158005#L711-3 assume !(0 == ~T4_E~0); 158004#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 158003#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 158002#L726-3 assume !(0 == ~E_M~0); 158001#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 158000#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 157999#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 157998#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 157997#L751-3 assume !(0 == ~E_5~0); 157996#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 157995#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 157994#L346-24 assume !(1 == ~m_pc~0); 157993#L346-26 is_master_triggered_~__retres1~0#1 := 0; 157992#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 157991#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 157990#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 157989#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 157988#L365-24 assume !(1 == ~t1_pc~0); 157987#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 157986#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 157985#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 157984#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 157982#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 157983#L384-24 assume 1 == ~t2_pc~0; 157978#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 157977#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 157973#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 157971#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 157972#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 157967#L403-24 assume !(1 == ~t3_pc~0); 157968#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 157963#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 157964#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 157959#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 157960#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 157955#L422-24 assume !(1 == ~t4_pc~0); 157956#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 157951#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 157952#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 157947#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 157948#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 157944#L441-24 assume !(1 == ~t5_pc~0); 157943#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 179702#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 179703#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 179695#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 179696#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 179691#L460-24 assume !(1 == ~t6_pc~0); 179692#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 179687#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 179688#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 179683#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 179684#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 179680#L774-3 assume !(1 == ~M_E~0); 174689#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 179677#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 179678#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 179673#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 179674#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 179669#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 179670#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 157148#L809-3 assume !(1 == ~E_1~0); 179667#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 179662#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 179663#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 179657#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 179658#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 179653#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 179654#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 179615#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 179616#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 179612#L1084 assume !(0 == start_simulation_~tmp~3#1); 156898#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 156899#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 179599#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 179598#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 179597#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 179596#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179595#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 179594#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 150563#L1065-2 [2023-11-06 22:43:18,232 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:18,232 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2023-11-06 22:43:18,232 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:18,232 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [545089316] [2023-11-06 22:43:18,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:18,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:18,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:18,339 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:18,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:18,340 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [545089316] [2023-11-06 22:43:18,340 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [545089316] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:18,340 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:18,340 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:43:18,341 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448763019] [2023-11-06 22:43:18,341 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:18,342 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:18,342 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:18,342 INFO L85 PathProgramCache]: Analyzing trace with hash -88994337, now seen corresponding path program 1 times [2023-11-06 22:43:18,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:18,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643965903] [2023-11-06 22:43:18,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:18,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:18,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:18,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:18,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:18,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1643965903] [2023-11-06 22:43:18,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1643965903] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:18,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:18,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:18,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281853596] [2023-11-06 22:43:18,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:18,554 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:18,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:18,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:18,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:18,555 INFO L87 Difference]: Start difference. First operand 41425 states and 58698 transitions. cyclomatic complexity: 17305 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:18,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:18,795 INFO L93 Difference]: Finished difference Result 61550 states and 87367 transitions. [2023-11-06 22:43:18,795 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61550 states and 87367 transitions. [2023-11-06 22:43:19,335 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61082 [2023-11-06 22:43:19,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61550 states to 61550 states and 87367 transitions. [2023-11-06 22:43:19,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61550 [2023-11-06 22:43:19,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61550 [2023-11-06 22:43:19,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61550 states and 87367 transitions. [2023-11-06 22:43:19,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:19,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61550 states and 87367 transitions. [2023-11-06 22:43:19,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61550 states and 87367 transitions. [2023-11-06 22:43:20,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61550 to 43096. [2023-11-06 22:43:20,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43096 states, 43096 states have (on average 1.4222897716725451) internal successors, (61295), 43095 states have internal predecessors, (61295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:20,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43096 states to 43096 states and 61295 transitions. [2023-11-06 22:43:20,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43096 states and 61295 transitions. [2023-11-06 22:43:20,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:20,811 INFO L428 stractBuchiCegarLoop]: Abstraction has 43096 states and 61295 transitions. [2023-11-06 22:43:20,811 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:43:20,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43096 states and 61295 transitions. [2023-11-06 22:43:20,988 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42759 [2023-11-06 22:43:20,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:20,989 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:20,991 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:20,991 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:20,991 INFO L748 eck$LassoCheckResult]: Stem: 253627#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 253628#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 253812#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253813#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 253994#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 253525#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253526#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253354#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253355#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253331#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253332#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 253500#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253660#L696 assume !(0 == ~M_E~0); 253661#L696-2 assume !(0 == ~T1_E~0); 254000#L701-1 assume !(0 == ~T2_E~0); 254002#L706-1 assume !(0 == ~T3_E~0); 253783#L711-1 assume !(0 == ~T4_E~0); 253561#L716-1 assume !(0 == ~T5_E~0); 253562#L721-1 assume !(0 == ~T6_E~0); 253734#L726-1 assume !(0 == ~E_M~0); 253735#L731-1 assume !(0 == ~E_1~0); 253698#L736-1 assume !(0 == ~E_2~0); 253699#L741-1 assume !(0 == ~E_3~0); 253794#L746-1 assume !(0 == ~E_4~0); 253585#L751-1 assume !(0 == ~E_5~0); 253586#L756-1 assume !(0 == ~E_6~0); 253558#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253377#L346 assume !(1 == ~m_pc~0); 253378#L346-2 is_master_triggered_~__retres1~0#1 := 0; 253599#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253591#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253592#L861 assume !(0 != activate_threads_~tmp~1#1); 253962#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253412#L365 assume !(1 == ~t1_pc~0); 253413#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 253977#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253361#L869 assume !(0 != activate_threads_~tmp___0~0#1); 253402#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253854#L384 assume !(1 == ~t2_pc~0); 253848#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 253849#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253814#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253319#L877 assume !(0 != activate_threads_~tmp___1~0#1); 253320#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253677#L403 assume !(1 == ~t3_pc~0); 253678#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 253891#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253294#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253295#L885 assume !(0 != activate_threads_~tmp___2~0#1); 253670#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 253671#L422 assume !(1 == ~t4_pc~0); 253810#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253811#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 253467#L893 assume !(0 != activate_threads_~tmp___3~0#1); 253762#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253333#L441 assume !(1 == ~t5_pc~0); 253334#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 253955#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253602#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 253603#L901 assume !(0 != activate_threads_~tmp___4~0#1); 253771#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 253772#L460 assume !(1 == ~t6_pc~0); 253910#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 253340#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 253341#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 253796#L909 assume !(0 != activate_threads_~tmp___5~0#1); 253907#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253747#L774 assume !(1 == ~M_E~0); 253748#L774-2 assume !(1 == ~T1_E~0); 253927#L779-1 assume !(1 == ~T2_E~0); 253645#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 253646#L789-1 assume !(1 == ~T4_E~0); 253396#L794-1 assume !(1 == ~T5_E~0); 253397#L799-1 assume !(1 == ~T6_E~0); 254048#L804-1 assume !(1 == ~E_M~0); 254049#L809-1 assume !(1 == ~E_1~0); 253729#L814-1 assume !(1 == ~E_2~0); 253298#L819-1 assume !(1 == ~E_3~0); 253299#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 253804#L829-1 assume !(1 == ~E_5~0); 253915#L834-1 assume !(1 == ~E_6~0); 253542#L839-1 assume { :end_inline_reset_delta_events } true; 253543#L1065-2 [2023-11-06 22:43:20,992 INFO L750 eck$LassoCheckResult]: Loop: 253543#L1065-2 assume !false; 273444#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 273442#L671-1 assume !false; 273441#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273439#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273433#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273432#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 273430#L582 assume !(0 != eval_~tmp~0#1); 273429#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 273428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 273427#L696-3 assume !(0 == ~M_E~0); 273426#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 273425#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 273423#L706-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 273421#L711-3 assume !(0 == ~T4_E~0); 273419#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 273417#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 273415#L726-3 assume !(0 == ~E_M~0); 273413#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 273410#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 273408#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 273406#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 273404#L751-3 assume !(0 == ~E_5~0); 273402#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 273400#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 273398#L346-24 assume !(1 == ~m_pc~0); 273396#L346-26 is_master_triggered_~__retres1~0#1 := 0; 273394#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 273392#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 273390#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 273388#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 273386#L365-24 assume !(1 == ~t1_pc~0); 273384#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 273382#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 273380#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 273378#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 273376#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 273373#L384-24 assume !(1 == ~t2_pc~0); 273370#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 273368#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 273365#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 273363#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 273361#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 273360#L403-24 assume !(1 == ~t3_pc~0); 273358#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 273356#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 273354#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 273352#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 273350#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 273349#L422-24 assume !(1 == ~t4_pc~0); 273347#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 273345#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 273343#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 273341#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 273339#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 273337#L441-24 assume !(1 == ~t5_pc~0); 273333#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 273331#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 273329#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 273327#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 273324#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273322#L460-24 assume !(1 == ~t6_pc~0); 273320#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 273319#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 273318#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 273317#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 273316#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273315#L774-3 assume !(1 == ~M_E~0); 271138#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 273314#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 273313#L784-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 273305#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 273303#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 273302#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 273301#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 273300#L809-3 assume !(1 == ~E_1~0); 273299#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 273298#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 273297#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 273296#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 273295#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 273294#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273285#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273280#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273278#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 259195#L1084 assume !(0 == start_simulation_~tmp~3#1); 259196#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 273468#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 273461#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 273459#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 273457#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 273456#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 273455#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 273453#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 253543#L1065-2 [2023-11-06 22:43:20,992 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:20,993 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2023-11-06 22:43:20,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:20,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [622444157] [2023-11-06 22:43:20,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:20,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:21,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:21,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:21,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:21,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [622444157] [2023-11-06 22:43:21,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [622444157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:21,080 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:21,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:21,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997405233] [2023-11-06 22:43:21,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:21,083 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:21,084 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:21,084 INFO L85 PathProgramCache]: Analyzing trace with hash -1727857954, now seen corresponding path program 1 times [2023-11-06 22:43:21,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:21,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950505822] [2023-11-06 22:43:21,085 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:21,085 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:21,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:21,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:21,145 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:21,145 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1950505822] [2023-11-06 22:43:21,145 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1950505822] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:21,145 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:21,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:21,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556555335] [2023-11-06 22:43:21,146 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:21,147 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:21,147 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:21,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:21,148 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:21,148 INFO L87 Difference]: Start difference. First operand 43096 states and 61295 transitions. cyclomatic complexity: 18215 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:21,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:21,774 INFO L93 Difference]: Finished difference Result 69435 states and 98226 transitions. [2023-11-06 22:43:21,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69435 states and 98226 transitions. [2023-11-06 22:43:22,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68901 [2023-11-06 22:43:22,360 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69435 states to 69435 states and 98226 transitions. [2023-11-06 22:43:22,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69435 [2023-11-06 22:43:22,408 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69435 [2023-11-06 22:43:22,408 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69435 states and 98226 transitions. [2023-11-06 22:43:22,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:22,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69435 states and 98226 transitions. [2023-11-06 22:43:22,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69435 states and 98226 transitions. [2023-11-06 22:43:23,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69435 to 50048. [2023-11-06 22:43:23,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50048 states, 50048 states have (on average 1.418218510230179) internal successors, (70979), 50047 states have internal predecessors, (70979), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:23,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50048 states to 50048 states and 70979 transitions. [2023-11-06 22:43:23,701 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50048 states and 70979 transitions. [2023-11-06 22:43:23,702 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:23,703 INFO L428 stractBuchiCegarLoop]: Abstraction has 50048 states and 70979 transitions. [2023-11-06 22:43:23,703 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:43:23,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50048 states and 70979 transitions. [2023-11-06 22:43:23,894 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49649 [2023-11-06 22:43:23,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:23,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:23,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:23,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:23,897 INFO L748 eck$LassoCheckResult]: Stem: 366165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 366166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 366355#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 366356#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 366545#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 366063#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 366064#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 365895#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 365896#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 365872#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 365873#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 366038#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 366198#L696 assume !(0 == ~M_E~0); 366199#L696-2 assume !(0 == ~T1_E~0); 366553#L701-1 assume !(0 == ~T2_E~0); 366555#L706-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 366320#L711-1 assume !(0 == ~T4_E~0); 366321#L716-1 assume !(0 == ~T5_E~0); 366599#L721-1 assume !(0 == ~T6_E~0); 366600#L726-1 assume !(0 == ~E_M~0); 366708#L731-1 assume !(0 == ~E_1~0); 366707#L736-1 assume !(0 == ~E_2~0); 366332#L741-1 assume !(0 == ~E_3~0); 366333#L746-1 assume !(0 == ~E_4~0); 366120#L751-1 assume !(0 == ~E_5~0); 366121#L756-1 assume !(0 == ~E_6~0); 366216#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366705#L346 assume !(1 == ~m_pc~0); 366135#L346-2 is_master_triggered_~__retres1~0#1 := 0; 366136#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366459#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 366574#L861 assume !(0 != activate_threads_~tmp~1#1); 366512#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 366513#L365 assume !(1 == ~t1_pc~0); 366702#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 366701#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365901#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 365902#L869 assume !(0 != activate_threads_~tmp___0~0#1); 365942#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 366397#L384 assume !(1 == ~t2_pc~0); 366391#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 366392#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 366630#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 366693#L877 assume !(0 != activate_threads_~tmp___1~0#1); 366692#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 366691#L403 assume !(1 == ~t3_pc~0); 366690#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 366689#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 366688#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 366687#L885 assume !(0 != activate_threads_~tmp___2~0#1); 366686#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 366685#L422 assume !(1 == ~t4_pc~0); 366353#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 366354#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 366005#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 366006#L893 assume !(0 != activate_threads_~tmp___3~0#1); 366490#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 366681#L441 assume !(1 == ~t5_pc~0); 366679#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 366677#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 366675#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 366673#L901 assume !(0 != activate_threads_~tmp___4~0#1); 366308#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 366309#L460 assume !(1 == ~t6_pc~0); 366463#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 366671#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 366335#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 366336#L909 assume !(0 != activate_threads_~tmp___5~0#1); 366460#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 366285#L774 assume !(1 == ~M_E~0); 366286#L774-2 assume !(1 == ~T1_E~0); 366669#L779-1 assume !(1 == ~T2_E~0); 366668#L784-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 366185#L789-1 assume !(1 == ~T4_E~0); 365936#L794-1 assume !(1 == ~T5_E~0); 365937#L799-1 assume !(1 == ~T6_E~0); 366609#L804-1 assume !(1 == ~E_M~0); 366610#L809-1 assume !(1 == ~E_1~0); 366270#L814-1 assume !(1 == ~E_2~0); 365839#L819-1 assume !(1 == ~E_3~0); 365840#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 366345#L829-1 assume !(1 == ~E_5~0); 366469#L834-1 assume !(1 == ~E_6~0); 366080#L839-1 assume { :end_inline_reset_delta_events } true; 366081#L1065-2 [2023-11-06 22:43:23,897 INFO L750 eck$LassoCheckResult]: Loop: 366081#L1065-2 assume !false; 400237#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 400234#L671-1 assume !false; 400232#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 400226#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 400220#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 400218#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 400215#L582 assume !(0 != eval_~tmp~0#1); 400216#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 414023#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 414022#L696-3 assume !(0 == ~M_E~0); 414021#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 414020#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 414016#L706-3 assume !(0 == ~T3_E~0); 414017#L711-3 assume !(0 == ~T4_E~0); 415342#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 415341#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 415340#L726-3 assume !(0 == ~E_M~0); 415339#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 415338#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 415337#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 415335#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 415333#L751-3 assume !(0 == ~E_5~0); 415331#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 415329#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415328#L346-24 assume !(1 == ~m_pc~0); 415327#L346-26 is_master_triggered_~__retres1~0#1 := 0; 415326#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 415325#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 415324#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 415323#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 415322#L365-24 assume !(1 == ~t1_pc~0); 415321#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 415320#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 415318#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 414551#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 414550#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414549#L384-24 assume !(1 == ~t2_pc~0); 414546#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 414542#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 414471#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 414466#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 414462#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 414461#L403-24 assume !(1 == ~t3_pc~0); 414460#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 414459#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414458#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 414456#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 414454#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 414452#L422-24 assume !(1 == ~t4_pc~0); 414450#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 414446#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 414441#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 414436#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 414430#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 414241#L441-24 assume 1 == ~t5_pc~0; 414239#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 414240#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 414267#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 414068#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 414063#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 414058#L460-24 assume !(1 == ~t6_pc~0); 414053#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 414048#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 414044#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414038#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 414035#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414032#L774-3 assume !(1 == ~M_E~0); 377435#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 414025#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 413957#L784-3 assume !(1 == ~T3_E~0); 413948#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 413942#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 413936#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 413930#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 413924#L809-3 assume !(1 == ~E_1~0); 413919#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 413905#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 413903#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 413901#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 413899#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 413897#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 413847#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 413830#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 413824#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 377675#L1084 assume !(0 == start_simulation_~tmp~3#1); 377676#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 400384#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 400376#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 400374#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 400372#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 400370#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 400368#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 400366#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 366081#L1065-2 [2023-11-06 22:43:23,898 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:23,899 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2023-11-06 22:43:23,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:23,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001676704] [2023-11-06 22:43:23,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:23,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:23,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:23,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:23,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:23,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001676704] [2023-11-06 22:43:23,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001676704] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:23,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:23,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:23,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1697889453] [2023-11-06 22:43:23,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:23,952 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:23,952 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:23,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1962781155, now seen corresponding path program 1 times [2023-11-06 22:43:23,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:23,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653821624] [2023-11-06 22:43:23,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:23,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:23,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:24,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:24,298 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:24,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653821624] [2023-11-06 22:43:24,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653821624] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:24,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:24,299 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:24,299 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [76605475] [2023-11-06 22:43:24,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:24,299 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:24,299 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:24,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:24,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:24,300 INFO L87 Difference]: Start difference. First operand 50048 states and 70979 transitions. cyclomatic complexity: 20947 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:24,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:24,584 INFO L93 Difference]: Finished difference Result 62472 states and 88141 transitions. [2023-11-06 22:43:24,585 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62472 states and 88141 transitions. [2023-11-06 22:43:24,891 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 62011 [2023-11-06 22:43:25,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62472 states to 62472 states and 88141 transitions. [2023-11-06 22:43:25,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62472 [2023-11-06 22:43:25,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62472 [2023-11-06 22:43:25,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62472 states and 88141 transitions. [2023-11-06 22:43:25,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:25,327 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62472 states and 88141 transitions. [2023-11-06 22:43:25,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62472 states and 88141 transitions. [2023-11-06 22:43:26,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62472 to 43096. [2023-11-06 22:43:26,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43096 states, 43096 states have (on average 1.41472526452571) internal successors, (60969), 43095 states have internal predecessors, (60969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:26,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43096 states to 43096 states and 60969 transitions. [2023-11-06 22:43:26,492 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43096 states and 60969 transitions. [2023-11-06 22:43:26,493 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:26,493 INFO L428 stractBuchiCegarLoop]: Abstraction has 43096 states and 60969 transitions. [2023-11-06 22:43:26,495 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:43:26,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43096 states and 60969 transitions. [2023-11-06 22:43:26,664 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42759 [2023-11-06 22:43:26,664 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:26,664 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:26,666 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:26,666 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:26,667 INFO L748 eck$LassoCheckResult]: Stem: 478697#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 478698#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 478887#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 478888#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 479083#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 478591#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 478592#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 478424#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 478425#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 478401#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 478402#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 478566#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 478733#L696 assume !(0 == ~M_E~0); 478734#L696-2 assume !(0 == ~T1_E~0); 479087#L701-1 assume !(0 == ~T2_E~0); 479089#L706-1 assume !(0 == ~T3_E~0); 478856#L711-1 assume !(0 == ~T4_E~0); 478626#L716-1 assume !(0 == ~T5_E~0); 478627#L721-1 assume !(0 == ~T6_E~0); 478807#L726-1 assume !(0 == ~E_M~0); 478808#L731-1 assume !(0 == ~E_1~0); 478771#L736-1 assume !(0 == ~E_2~0); 478772#L741-1 assume !(0 == ~E_3~0); 478865#L746-1 assume !(0 == ~E_4~0); 478651#L751-1 assume !(0 == ~E_5~0); 478652#L756-1 assume !(0 == ~E_6~0); 478623#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 478445#L346 assume !(1 == ~m_pc~0); 478446#L346-2 is_master_triggered_~__retres1~0#1 := 0; 478666#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 478657#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 478658#L861 assume !(0 != activate_threads_~tmp~1#1); 479057#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 478479#L365 assume !(1 == ~t1_pc~0); 478480#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 479072#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 478429#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 478430#L869 assume !(0 != activate_threads_~tmp___0~0#1); 478469#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 478931#L384 assume !(1 == ~t2_pc~0); 478924#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 478925#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 478890#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 478390#L877 assume !(0 != activate_threads_~tmp___1~0#1); 478391#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 478750#L403 assume !(1 == ~t3_pc~0); 478751#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 478978#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 478365#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 478366#L885 assume !(0 != activate_threads_~tmp___2~0#1); 478743#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 478744#L422 assume !(1 == ~t4_pc~0); 478885#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 478886#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 478530#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 478531#L893 assume !(0 != activate_threads_~tmp___3~0#1); 478832#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478403#L441 assume !(1 == ~t5_pc~0); 478404#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 479051#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 478669#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 478670#L901 assume !(0 != activate_threads_~tmp___4~0#1); 478842#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 478843#L460 assume !(1 == ~t6_pc~0); 479006#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 478410#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 478411#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 478867#L909 assume !(0 != activate_threads_~tmp___5~0#1); 479003#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 478817#L774 assume !(1 == ~M_E~0); 478818#L774-2 assume !(1 == ~T1_E~0); 479024#L779-1 assume !(1 == ~T2_E~0); 478715#L784-1 assume !(1 == ~T3_E~0); 478716#L789-1 assume !(1 == ~T4_E~0); 478464#L794-1 assume !(1 == ~T5_E~0); 478465#L799-1 assume !(1 == ~T6_E~0); 479144#L804-1 assume !(1 == ~E_M~0); 479145#L809-1 assume !(1 == ~E_1~0); 478802#L814-1 assume !(1 == ~E_2~0); 478369#L819-1 assume !(1 == ~E_3~0); 478370#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 478875#L829-1 assume !(1 == ~E_5~0); 479012#L834-1 assume !(1 == ~E_6~0); 478607#L839-1 assume { :end_inline_reset_delta_events } true; 478608#L1065-2 [2023-11-06 22:43:26,668 INFO L750 eck$LassoCheckResult]: Loop: 478608#L1065-2 assume !false; 507163#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 507160#L671-1 assume !false; 507158#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 507153#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 507146#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 507144#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 507141#L582 assume !(0 != eval_~tmp~0#1); 507142#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 516514#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 516512#L696-3 assume !(0 == ~M_E~0); 516510#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 516508#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 516506#L706-3 assume !(0 == ~T3_E~0); 516504#L711-3 assume !(0 == ~T4_E~0); 516502#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 516500#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 516498#L726-3 assume !(0 == ~E_M~0); 516496#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 516494#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 516492#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 516490#L746-3 assume 0 == ~E_4~0;~E_4~0 := 1; 516488#L751-3 assume !(0 == ~E_5~0); 516486#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 516484#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 516482#L346-24 assume !(1 == ~m_pc~0); 516480#L346-26 is_master_triggered_~__retres1~0#1 := 0; 516478#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516476#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 516474#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 516472#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 516470#L365-24 assume !(1 == ~t1_pc~0); 516467#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 516465#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 516463#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 516461#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 516459#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 516457#L384-24 assume !(1 == ~t2_pc~0); 516455#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 516452#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 516450#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 516448#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 516446#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516444#L403-24 assume !(1 == ~t3_pc~0); 516442#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 516440#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 516438#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 516436#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 516434#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516432#L422-24 assume !(1 == ~t4_pc~0); 516428#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 516426#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 516424#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 516422#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 516421#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516420#L441-24 assume !(1 == ~t5_pc~0); 516417#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 516522#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 516520#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 516410#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 516408#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516406#L460-24 assume !(1 == ~t6_pc~0); 516404#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 516402#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 516400#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 516399#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 516397#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516395#L774-3 assume !(1 == ~M_E~0); 499405#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 516392#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 516390#L784-3 assume !(1 == ~T3_E~0); 516388#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 516386#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 516384#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 516382#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 516380#L809-3 assume !(1 == ~E_1~0); 516378#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 516319#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 515715#L824-3 assume 1 == ~E_4~0;~E_4~0 := 2; 515714#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 515713#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 515712#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 515708#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 515704#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 515702#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 500927#L1084 assume !(0 == start_simulation_~tmp~3#1); 500928#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 507243#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 507235#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 507233#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 507231#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 507229#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 507227#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 507225#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 478608#L1065-2 [2023-11-06 22:43:26,668 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:26,668 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2023-11-06 22:43:26,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:26,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077303115] [2023-11-06 22:43:26,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:26,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:26,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:26,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:26,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:26,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077303115] [2023-11-06 22:43:26,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077303115] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:26,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:26,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:26,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209421360] [2023-11-06 22:43:26,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:26,754 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:26,755 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:26,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1375257758, now seen corresponding path program 1 times [2023-11-06 22:43:26,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:26,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1973411678] [2023-11-06 22:43:26,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:26,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:26,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:26,809 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:26,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:26,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1973411678] [2023-11-06 22:43:26,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1973411678] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:26,810 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:26,810 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:26,810 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1947070505] [2023-11-06 22:43:26,810 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:26,811 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:26,811 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:26,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:26,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:26,812 INFO L87 Difference]: Start difference. First operand 43096 states and 60969 transitions. cyclomatic complexity: 17889 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:27,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:27,210 INFO L93 Difference]: Finished difference Result 68918 states and 96648 transitions. [2023-11-06 22:43:27,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68918 states and 96648 transitions. [2023-11-06 22:43:28,045 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68374 [2023-11-06 22:43:28,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68918 states to 68918 states and 96648 transitions. [2023-11-06 22:43:28,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68918 [2023-11-06 22:43:28,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68918 [2023-11-06 22:43:28,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68918 states and 96648 transitions. [2023-11-06 22:43:28,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:28,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68918 states and 96648 transitions. [2023-11-06 22:43:28,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68918 states and 96648 transitions. [2023-11-06 22:43:29,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68918 to 50048. [2023-11-06 22:43:29,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50048 states, 50048 states have (on average 1.4058104219948848) internal successors, (70358), 50047 states have internal predecessors, (70358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:29,479 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50048 states to 50048 states and 70358 transitions. [2023-11-06 22:43:29,480 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50048 states and 70358 transitions. [2023-11-06 22:43:29,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:29,481 INFO L428 stractBuchiCegarLoop]: Abstraction has 50048 states and 70358 transitions. [2023-11-06 22:43:29,481 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:43:29,481 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50048 states and 70358 transitions. [2023-11-06 22:43:29,614 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49649 [2023-11-06 22:43:29,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:29,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:29,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:29,616 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:29,616 INFO L748 eck$LassoCheckResult]: Stem: 590720#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 590721#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 590907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 590908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 591100#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 590615#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 590616#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 590452#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 590453#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 590426#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 590427#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 590593#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 590754#L696 assume !(0 == ~M_E~0); 590755#L696-2 assume !(0 == ~T1_E~0); 591114#L701-1 assume !(0 == ~T2_E~0); 591116#L706-1 assume !(0 == ~T3_E~0); 590875#L711-1 assume !(0 == ~T4_E~0); 590653#L716-1 assume !(0 == ~T5_E~0); 590654#L721-1 assume !(0 == ~T6_E~0); 590829#L726-1 assume !(0 == ~E_M~0); 590830#L731-1 assume !(0 == ~E_1~0); 590792#L736-1 assume !(0 == ~E_2~0); 590793#L741-1 assume !(0 == ~E_3~0); 590885#L746-1 assume 0 == ~E_4~0;~E_4~0 := 1; 590675#L751-1 assume !(0 == ~E_5~0); 590676#L756-1 assume !(0 == ~E_6~0); 590771#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 590472#L346 assume !(1 == ~m_pc~0); 590473#L346-2 is_master_triggered_~__retres1~0#1 := 0; 591260#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 590680#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 590681#L861 assume !(0 != activate_threads_~tmp~1#1); 591259#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 590504#L365 assume !(1 == ~t1_pc~0); 590505#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 591085#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 591097#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 591256#L869 assume !(0 != activate_threads_~tmp___0~0#1); 590950#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 590951#L384 assume !(1 == ~t2_pc~0); 591086#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 591192#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 591193#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 590416#L877 assume !(0 != activate_threads_~tmp___1~0#1); 590417#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 590772#L403 assume !(1 == ~t3_pc~0); 590773#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 590995#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 591251#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 591250#L885 assume !(0 != activate_threads_~tmp___2~0#1); 591249#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 591105#L422 assume !(1 == ~t4_pc~0); 591106#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 591248#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 591247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 591246#L893 assume !(0 != activate_threads_~tmp___3~0#1); 590852#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 590428#L441 assume !(1 == ~t5_pc~0); 590429#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 591181#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 590693#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 590694#L901 assume !(0 != activate_threads_~tmp___4~0#1); 591228#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 591238#L460 assume !(1 == ~t6_pc~0); 591109#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 590437#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 590438#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 591236#L909 assume !(0 != activate_threads_~tmp___5~0#1); 591130#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 591131#L774 assume !(1 == ~M_E~0); 591165#L774-2 assume !(1 == ~T1_E~0); 591037#L779-1 assume !(1 == ~T2_E~0); 590737#L784-1 assume !(1 == ~T3_E~0); 590738#L789-1 assume !(1 == ~T4_E~0); 591233#L794-1 assume !(1 == ~T5_E~0); 591209#L799-1 assume !(1 == ~T6_E~0); 591210#L804-1 assume !(1 == ~E_M~0); 591203#L809-1 assume !(1 == ~E_1~0); 591204#L814-1 assume !(1 == ~E_2~0); 590395#L819-1 assume !(1 == ~E_3~0); 590396#L824-1 assume 1 == ~E_4~0;~E_4~0 := 2; 590897#L829-1 assume !(1 == ~E_5~0); 591025#L834-1 assume !(1 == ~E_6~0); 590635#L839-1 assume { :end_inline_reset_delta_events } true; 590636#L1065-2 [2023-11-06 22:43:29,617 INFO L750 eck$LassoCheckResult]: Loop: 590636#L1065-2 assume !false; 613697#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 613508#L671-1 assume !false; 613694#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 613681#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 613674#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 613671#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 613668#L582 assume !(0 != eval_~tmp~0#1); 613669#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 621888#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 621885#L696-3 assume !(0 == ~M_E~0); 599629#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 599630#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 617814#L706-3 assume !(0 == ~T3_E~0); 614273#L711-3 assume !(0 == ~T4_E~0); 614272#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 614269#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 614266#L726-3 assume !(0 == ~E_M~0); 614263#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 614260#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 614257#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 614253#L746-3 assume !(0 == ~E_4~0); 614250#L751-3 assume !(0 == ~E_5~0); 614246#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 614242#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 614237#L346-24 assume !(1 == ~m_pc~0); 614232#L346-26 is_master_triggered_~__retres1~0#1 := 0; 614226#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 614220#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 614215#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 614210#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 614206#L365-24 assume !(1 == ~t1_pc~0); 614203#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 614199#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 614195#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 614167#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 614162#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 614154#L384-24 assume 1 == ~t2_pc~0; 614143#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 614135#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 614127#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 614119#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 614112#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 614107#L403-24 assume !(1 == ~t3_pc~0); 614104#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 614101#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 614092#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 614089#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 614086#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 614082#L422-24 assume !(1 == ~t4_pc~0); 614079#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 614076#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 614073#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 614070#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 614067#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 614063#L441-24 assume !(1 == ~t5_pc~0); 614059#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 614054#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 614048#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 614043#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 614038#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 614034#L460-24 assume !(1 == ~t6_pc~0); 614030#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 613957#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 613956#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 613955#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 613954#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 613953#L774-3 assume !(1 == ~M_E~0); 597737#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 613775#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 613773#L784-3 assume !(1 == ~T3_E~0); 613771#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 613769#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 613767#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 613765#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 613763#L809-3 assume !(1 == ~E_1~0); 613760#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 613758#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 613756#L824-3 assume !(1 == ~E_4~0); 613753#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 613751#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 613748#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 613738#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 613733#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 613731#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 613729#L1084 assume !(0 == start_simulation_~tmp~3#1); 613727#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 613719#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 613711#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 613709#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 613706#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 613705#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 613703#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 613700#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 590636#L1065-2 [2023-11-06 22:43:29,617 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:29,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2023-11-06 22:43:29,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:29,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1744971181] [2023-11-06 22:43:29,618 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:29,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:29,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:29,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:29,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:29,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1744971181] [2023-11-06 22:43:29,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1744971181] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:29,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:29,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:29,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1828235803] [2023-11-06 22:43:29,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:29,675 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:29,676 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:29,676 INFO L85 PathProgramCache]: Analyzing trace with hash -1797120483, now seen corresponding path program 1 times [2023-11-06 22:43:29,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:29,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607520266] [2023-11-06 22:43:29,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:29,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:29,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:29,716 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:29,716 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:29,716 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607520266] [2023-11-06 22:43:29,716 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607520266] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:29,716 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:29,716 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:29,717 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278645546] [2023-11-06 22:43:29,717 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:29,717 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:29,717 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:29,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:29,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:29,718 INFO L87 Difference]: Start difference. First operand 50048 states and 70358 transitions. cyclomatic complexity: 20326 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:30,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:30,357 INFO L93 Difference]: Finished difference Result 61561 states and 86075 transitions. [2023-11-06 22:43:30,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61561 states and 86075 transitions. [2023-11-06 22:43:30,629 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61082 [2023-11-06 22:43:30,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61561 states to 61561 states and 86075 transitions. [2023-11-06 22:43:30,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61561 [2023-11-06 22:43:30,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61561 [2023-11-06 22:43:30,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61561 states and 86075 transitions. [2023-11-06 22:43:30,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:30,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61561 states and 86075 transitions. [2023-11-06 22:43:30,911 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61561 states and 86075 transitions. [2023-11-06 22:43:31,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61561 to 43096. [2023-11-06 22:43:31,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43096 states, 43096 states have (on average 1.400315574531279) internal successors, (60348), 43095 states have internal predecessors, (60348), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:32,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43096 states to 43096 states and 60348 transitions. [2023-11-06 22:43:32,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43096 states and 60348 transitions. [2023-11-06 22:43:32,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:32,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 43096 states and 60348 transitions. [2023-11-06 22:43:32,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:43:32,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43096 states and 60348 transitions. [2023-11-06 22:43:32,137 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42759 [2023-11-06 22:43:32,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:32,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:32,139 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:32,139 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:32,140 INFO L748 eck$LassoCheckResult]: Stem: 702339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 702340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 702529#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 702530#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 702709#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 702235#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 702236#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 702071#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 702072#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 702044#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 702045#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 702213#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 702378#L696 assume !(0 == ~M_E~0); 702379#L696-2 assume !(0 == ~T1_E~0); 702714#L701-1 assume !(0 == ~T2_E~0); 702716#L706-1 assume !(0 == ~T3_E~0); 702498#L711-1 assume !(0 == ~T4_E~0); 702271#L716-1 assume !(0 == ~T5_E~0); 702272#L721-1 assume !(0 == ~T6_E~0); 702451#L726-1 assume !(0 == ~E_M~0); 702452#L731-1 assume !(0 == ~E_1~0); 702416#L736-1 assume !(0 == ~E_2~0); 702417#L741-1 assume !(0 == ~E_3~0); 702507#L746-1 assume !(0 == ~E_4~0); 702293#L751-1 assume !(0 == ~E_5~0); 702294#L756-1 assume !(0 == ~E_6~0); 702268#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 702091#L346 assume !(1 == ~m_pc~0); 702092#L346-2 is_master_triggered_~__retres1~0#1 := 0; 702309#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 702299#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 702300#L861 assume !(0 != activate_threads_~tmp~1#1); 702677#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 702123#L365 assume !(1 == ~t1_pc~0); 702124#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 702695#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 702077#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 702078#L869 assume !(0 != activate_threads_~tmp___0~0#1); 702112#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 702570#L384 assume !(1 == ~t2_pc~0); 702565#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 702566#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 702534#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 702035#L877 assume !(0 != activate_threads_~tmp___1~0#1); 702036#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 702395#L403 assume !(1 == ~t3_pc~0); 702396#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 702608#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 702008#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 702009#L885 assume !(0 != activate_threads_~tmp___2~0#1); 702388#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 702389#L422 assume !(1 == ~t4_pc~0); 702527#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 702528#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 702176#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 702177#L893 assume !(0 != activate_threads_~tmp___3~0#1); 702476#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 702046#L441 assume !(1 == ~t5_pc~0); 702047#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 702672#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 702311#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 702312#L901 assume !(0 != activate_threads_~tmp___4~0#1); 702487#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 702488#L460 assume !(1 == ~t6_pc~0); 702631#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 702055#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 702056#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 702510#L909 assume !(0 != activate_threads_~tmp___5~0#1); 702626#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 702462#L774 assume !(1 == ~M_E~0); 702463#L774-2 assume !(1 == ~T1_E~0); 702645#L779-1 assume !(1 == ~T2_E~0); 702357#L784-1 assume !(1 == ~T3_E~0); 702358#L789-1 assume !(1 == ~T4_E~0); 702107#L794-1 assume !(1 == ~T5_E~0); 702108#L799-1 assume !(1 == ~T6_E~0); 702765#L804-1 assume !(1 == ~E_M~0); 702766#L809-1 assume !(1 == ~E_1~0); 702447#L814-1 assume !(1 == ~E_2~0); 702014#L819-1 assume !(1 == ~E_3~0); 702015#L824-1 assume !(1 == ~E_4~0); 702518#L829-1 assume !(1 == ~E_5~0); 702635#L834-1 assume !(1 == ~E_6~0); 702255#L839-1 assume { :end_inline_reset_delta_events } true; 702256#L1065-2 [2023-11-06 22:43:32,140 INFO L750 eck$LassoCheckResult]: Loop: 702256#L1065-2 assume !false; 727252#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 718688#L671-1 assume !false; 727249#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 727244#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 727237#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 727234#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 727231#L582 assume !(0 != eval_~tmp~0#1); 727232#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 727901#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 727899#L696-3 assume !(0 == ~M_E~0); 727897#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 727895#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 727893#L706-3 assume !(0 == ~T3_E~0); 727891#L711-3 assume !(0 == ~T4_E~0); 727889#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 727886#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 727884#L726-3 assume !(0 == ~E_M~0); 727882#L731-3 assume 0 == ~E_1~0;~E_1~0 := 1; 727880#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 727878#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 727875#L746-3 assume !(0 == ~E_4~0); 727874#L751-3 assume !(0 == ~E_5~0); 727871#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 727869#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 727867#L346-24 assume !(1 == ~m_pc~0); 727865#L346-26 is_master_triggered_~__retres1~0#1 := 0; 727863#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 727860#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 727858#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 727856#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 727854#L365-24 assume !(1 == ~t1_pc~0); 727852#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 727850#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 727848#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 727845#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 727843#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 727841#L384-24 assume 1 == ~t2_pc~0; 727838#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 727835#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 727832#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 727831#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 727828#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 727826#L403-24 assume !(1 == ~t3_pc~0); 727824#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 727822#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 727820#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 727818#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 727817#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 727815#L422-24 assume !(1 == ~t4_pc~0); 727813#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 727811#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 727809#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 727807#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 727805#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 727803#L441-24 assume 1 == ~t5_pc~0; 727801#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 727802#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 727905#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 727792#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 727790#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 727788#L460-24 assume !(1 == ~t6_pc~0); 727787#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 727786#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 727785#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 727784#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 727776#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 727730#L774-3 assume !(1 == ~M_E~0); 727728#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 727726#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 727724#L784-3 assume !(1 == ~T3_E~0); 727722#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 727720#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 727718#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 727716#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 727714#L809-3 assume !(1 == ~E_1~0); 727712#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 727711#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 727710#L824-3 assume !(1 == ~E_4~0); 727709#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 727708#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 727707#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 727703#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 727692#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 727690#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 727687#L1084 assume !(0 == start_simulation_~tmp~3#1); 727682#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 727679#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 727665#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 727265#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 727262#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 727260#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 727258#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 727256#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 702256#L1065-2 [2023-11-06 22:43:32,140 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:32,141 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2023-11-06 22:43:32,141 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:32,141 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599585752] [2023-11-06 22:43:32,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:32,141 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:32,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:32,154 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:32,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:32,206 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:32,207 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:32,207 INFO L85 PathProgramCache]: Analyzing trace with hash -840192100, now seen corresponding path program 1 times [2023-11-06 22:43:32,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:32,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [23902380] [2023-11-06 22:43:32,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:32,208 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:32,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:32,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:32,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:32,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [23902380] [2023-11-06 22:43:32,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [23902380] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:32,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:32,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:32,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1154861967] [2023-11-06 22:43:32,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:32,252 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:32,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:32,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:32,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:32,253 INFO L87 Difference]: Start difference. First operand 43096 states and 60348 transitions. cyclomatic complexity: 17268 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:32,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:32,535 INFO L93 Difference]: Finished difference Result 69627 states and 96683 transitions. [2023-11-06 22:43:32,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69627 states and 96683 transitions. [2023-11-06 22:43:32,797 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 69060 [2023-11-06 22:43:33,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69627 states to 69627 states and 96683 transitions. [2023-11-06 22:43:33,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69627 [2023-11-06 22:43:33,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69627 [2023-11-06 22:43:33,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69627 states and 96683 transitions. [2023-11-06 22:43:33,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:33,092 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69627 states and 96683 transitions. [2023-11-06 22:43:33,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69627 states and 96683 transitions. [2023-11-06 22:43:34,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69627 to 69211. [2023-11-06 22:43:34,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69211 states, 69211 states have (on average 1.387799627226886) internal successors, (96051), 69210 states have internal predecessors, (96051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:34,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69211 states to 69211 states and 96051 transitions. [2023-11-06 22:43:34,662 INFO L240 hiAutomatonCegarLoop]: Abstraction has 69211 states and 96051 transitions. [2023-11-06 22:43:34,662 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:34,663 INFO L428 stractBuchiCegarLoop]: Abstraction has 69211 states and 96051 transitions. [2023-11-06 22:43:34,663 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:43:34,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69211 states and 96051 transitions. [2023-11-06 22:43:34,867 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 68740 [2023-11-06 22:43:34,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:34,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:34,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:34,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:34,870 INFO L748 eck$LassoCheckResult]: Stem: 815082#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 815083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 815272#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 815273#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 815490#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 814971#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 814972#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 814799#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 814800#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 814774#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 814775#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 814950#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 815114#L696 assume !(0 == ~M_E~0); 815115#L696-2 assume !(0 == ~T1_E~0); 815499#L701-1 assume !(0 == ~T2_E~0); 815501#L706-1 assume !(0 == ~T3_E~0); 815237#L711-1 assume !(0 == ~T4_E~0); 815009#L716-1 assume !(0 == ~T5_E~0); 815010#L721-1 assume !(0 == ~T6_E~0); 815186#L726-1 assume !(0 == ~E_M~0); 815187#L731-1 assume 0 == ~E_1~0;~E_1~0 := 1; 815451#L736-1 assume !(0 == ~E_2~0); 815249#L741-1 assume !(0 == ~E_3~0); 815250#L746-1 assume !(0 == ~E_4~0); 815032#L751-1 assume !(0 == ~E_5~0); 815033#L756-1 assume !(0 == ~E_6~0); 815130#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 814821#L346 assume !(1 == ~m_pc~0); 814822#L346-2 is_master_triggered_~__retres1~0#1 := 0; 815666#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 815039#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 815040#L861 assume !(0 != activate_threads_~tmp~1#1); 815665#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 814856#L365 assume !(1 == ~t1_pc~0); 814857#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 815476#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 815488#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 815662#L869 assume !(0 != activate_threads_~tmp___0~0#1); 815320#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 815321#L384 assume !(1 == ~t2_pc~0); 815317#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 815318#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 815279#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 815280#L877 assume !(0 != activate_threads_~tmp___1~0#1); 815658#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 815657#L403 assume !(1 == ~t3_pc~0); 815656#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 815616#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 815617#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 815655#L885 assume !(0 != activate_threads_~tmp___2~0#1); 815654#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 815494#L422 assume !(1 == ~t4_pc~0); 815270#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 815271#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 814911#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 814912#L893 assume !(0 != activate_threads_~tmp___3~0#1); 815427#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 815649#L441 assume !(1 == ~t5_pc~0); 815647#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 815645#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 815643#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 815642#L901 assume !(0 != activate_threads_~tmp___4~0#1); 815224#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 815225#L460 assume !(1 == ~t6_pc~0); 815400#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 815638#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 815253#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 815254#L909 assume !(0 != activate_threads_~tmp___5~0#1); 815393#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 815197#L774 assume !(1 == ~M_E~0); 815198#L774-2 assume !(1 == ~T1_E~0); 815415#L779-1 assume !(1 == ~T2_E~0); 815099#L784-1 assume !(1 == ~T3_E~0); 815100#L789-1 assume !(1 == ~T4_E~0); 814837#L794-1 assume !(1 == ~T5_E~0); 814838#L799-1 assume !(1 == ~T6_E~0); 815553#L804-1 assume !(1 == ~E_M~0); 815554#L809-1 assume 1 == ~E_1~0;~E_1~0 := 2; 815182#L814-1 assume !(1 == ~E_2~0); 814743#L819-1 assume !(1 == ~E_3~0); 814744#L824-1 assume !(1 == ~E_4~0); 815263#L829-1 assume !(1 == ~E_5~0); 815404#L834-1 assume !(1 == ~E_6~0); 814992#L839-1 assume { :end_inline_reset_delta_events } true; 814993#L1065-2 [2023-11-06 22:43:34,870 INFO L750 eck$LassoCheckResult]: Loop: 814993#L1065-2 assume !false; 820504#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 820489#L671-1 assume !false; 820490#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 820483#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 820474#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 820469#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 820470#L582 assume !(0 != eval_~tmp~0#1); 822333#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 850847#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 850846#L696-3 assume !(0 == ~M_E~0); 850845#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 850844#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 850843#L706-3 assume !(0 == ~T3_E~0); 850842#L711-3 assume !(0 == ~T4_E~0); 850841#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 850840#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 850839#L726-3 assume !(0 == ~E_M~0); 850837#L731-3 assume !(0 == ~E_1~0); 850836#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 850835#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 850834#L746-3 assume !(0 == ~E_4~0); 850833#L751-3 assume !(0 == ~E_5~0); 850832#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 850831#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 850830#L346-24 assume !(1 == ~m_pc~0); 850829#L346-26 is_master_triggered_~__retres1~0#1 := 0; 850828#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 850827#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 850826#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 850825#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 850824#L365-24 assume !(1 == ~t1_pc~0); 850823#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 850822#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 850821#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 850820#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 850819#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 850818#L384-24 assume !(1 == ~t2_pc~0); 850816#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 850815#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 850814#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 850813#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 850812#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 850811#L403-24 assume !(1 == ~t3_pc~0); 850810#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 850809#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 850808#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 850807#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 850806#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 850805#L422-24 assume !(1 == ~t4_pc~0); 850804#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 850803#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 850802#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 850801#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 850800#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 850799#L441-24 assume 1 == ~t5_pc~0; 850798#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 850797#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 850796#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 822965#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 822963#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 822962#L460-24 assume !(1 == ~t6_pc~0); 822961#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 822960#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 822958#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 822959#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 822954#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 822955#L774-3 assume !(1 == ~M_E~0); 822951#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 822952#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 822947#L784-3 assume !(1 == ~T3_E~0); 822948#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 822943#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 822944#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 822939#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 822940#L809-3 assume !(1 == ~E_1~0); 822848#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 822849#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 822844#L824-3 assume !(1 == ~E_4~0); 822845#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 822840#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 822841#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 822834#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 822831#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 822826#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 822827#L1084 assume !(0 == start_simulation_~tmp~3#1); 823013#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 823014#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 820549#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 820550#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 820537#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 820538#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 820521#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 820522#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 814993#L1065-2 [2023-11-06 22:43:34,870 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:34,871 INFO L85 PathProgramCache]: Analyzing trace with hash 1678656137, now seen corresponding path program 1 times [2023-11-06 22:43:34,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:34,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1394874542] [2023-11-06 22:43:34,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:34,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:34,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:34,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:34,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:34,939 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1394874542] [2023-11-06 22:43:34,939 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1394874542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:34,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:34,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:34,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [199073592] [2023-11-06 22:43:34,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:34,941 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:43:34,942 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:34,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1617705627, now seen corresponding path program 1 times [2023-11-06 22:43:34,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:34,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763496992] [2023-11-06 22:43:34,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:34,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:34,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:35,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:35,024 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:35,025 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763496992] [2023-11-06 22:43:35,025 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763496992] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:35,025 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:35,025 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:43:35,025 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633097693] [2023-11-06 22:43:35,025 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:35,027 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:35,027 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:35,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:43:35,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:43:35,030 INFO L87 Difference]: Start difference. First operand 69211 states and 96051 transitions. cyclomatic complexity: 26856 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:35,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:35,464 INFO L93 Difference]: Finished difference Result 96794 states and 134016 transitions. [2023-11-06 22:43:35,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96794 states and 134016 transitions. [2023-11-06 22:43:36,458 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 93387 [2023-11-06 22:43:36,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96794 states to 96794 states and 134016 transitions. [2023-11-06 22:43:36,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96794 [2023-11-06 22:43:36,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96794 [2023-11-06 22:43:36,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96794 states and 134016 transitions. [2023-11-06 22:43:36,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:36,721 INFO L218 hiAutomatonCegarLoop]: Abstraction has 96794 states and 134016 transitions. [2023-11-06 22:43:36,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96794 states and 134016 transitions. [2023-11-06 22:43:37,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96794 to 66875. [2023-11-06 22:43:37,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66875 states, 66875 states have (on average 1.3868411214953271) internal successors, (92745), 66874 states have internal predecessors, (92745), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:38,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66875 states to 66875 states and 92745 transitions. [2023-11-06 22:43:38,153 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66875 states and 92745 transitions. [2023-11-06 22:43:38,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:43:38,154 INFO L428 stractBuchiCegarLoop]: Abstraction has 66875 states and 92745 transitions. [2023-11-06 22:43:38,154 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:43:38,154 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66875 states and 92745 transitions. [2023-11-06 22:43:38,330 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 66466 [2023-11-06 22:43:38,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:38,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:38,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:38,332 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:38,333 INFO L748 eck$LassoCheckResult]: Stem: 981086#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 981087#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 981277#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 981278#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 981465#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 980983#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 980984#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 980818#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 980819#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 980790#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 980791#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 980962#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 981124#L696 assume !(0 == ~M_E~0); 981125#L696-2 assume !(0 == ~T1_E~0); 981475#L701-1 assume !(0 == ~T2_E~0); 981477#L706-1 assume !(0 == ~T3_E~0); 981247#L711-1 assume !(0 == ~T4_E~0); 981018#L716-1 assume !(0 == ~T5_E~0); 981019#L721-1 assume !(0 == ~T6_E~0); 981198#L726-1 assume !(0 == ~E_M~0); 981199#L731-1 assume !(0 == ~E_1~0); 981161#L736-1 assume !(0 == ~E_2~0); 981162#L741-1 assume !(0 == ~E_3~0); 981257#L746-1 assume !(0 == ~E_4~0); 981043#L751-1 assume !(0 == ~E_5~0); 981044#L756-1 assume !(0 == ~E_6~0); 981015#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 980838#L346 assume !(1 == ~m_pc~0); 980839#L346-2 is_master_triggered_~__retres1~0#1 := 0; 981058#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 981048#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 981049#L861 assume !(0 != activate_threads_~tmp~1#1); 981435#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 980871#L365 assume !(1 == ~t1_pc~0); 980872#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 981452#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 980824#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 980825#L869 assume !(0 != activate_threads_~tmp___0~0#1); 980860#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 981325#L384 assume !(1 == ~t2_pc~0); 981321#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 981322#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 981284#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 980781#L877 assume !(0 != activate_threads_~tmp___1~0#1); 980782#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 981140#L403 assume !(1 == ~t3_pc~0); 981141#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 981365#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 980754#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 980755#L885 assume !(0 != activate_threads_~tmp___2~0#1); 981134#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 981135#L422 assume !(1 == ~t4_pc~0); 981275#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 981276#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 980924#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 980925#L893 assume !(0 != activate_threads_~tmp___3~0#1); 981225#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 980792#L441 assume !(1 == ~t5_pc~0); 980793#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 981431#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 981060#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 981061#L901 assume !(0 != activate_threads_~tmp___4~0#1); 981235#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 981236#L460 assume !(1 == ~t6_pc~0); 981388#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 980801#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 980802#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 981261#L909 assume !(0 != activate_threads_~tmp___5~0#1); 981383#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 981210#L774 assume !(1 == ~M_E~0); 981211#L774-2 assume !(1 == ~T1_E~0); 981402#L779-1 assume !(1 == ~T2_E~0); 981104#L784-1 assume !(1 == ~T3_E~0); 981105#L789-1 assume !(1 == ~T4_E~0); 980854#L794-1 assume !(1 == ~T5_E~0); 980855#L799-1 assume !(1 == ~T6_E~0); 981530#L804-1 assume !(1 == ~E_M~0); 981531#L809-1 assume !(1 == ~E_1~0); 981194#L814-1 assume !(1 == ~E_2~0); 980760#L819-1 assume !(1 == ~E_3~0); 980761#L824-1 assume !(1 == ~E_4~0); 981268#L829-1 assume !(1 == ~E_5~0); 981392#L834-1 assume !(1 == ~E_6~0); 981004#L839-1 assume { :end_inline_reset_delta_events } true; 981005#L1065-2 [2023-11-06 22:43:38,333 INFO L750 eck$LassoCheckResult]: Loop: 981005#L1065-2 assume !false; 1000164#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1000162#L671-1 assume !false; 1000161#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1000159#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 999976#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 999841#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 999832#L582 assume !(0 != eval_~tmp~0#1); 999833#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1027116#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1027115#L696-3 assume !(0 == ~M_E~0); 1027114#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1027113#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1027112#L706-3 assume !(0 == ~T3_E~0); 1027111#L711-3 assume !(0 == ~T4_E~0); 1027110#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1027109#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1027108#L726-3 assume !(0 == ~E_M~0); 1027107#L731-3 assume !(0 == ~E_1~0); 1027106#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1027105#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1027104#L746-3 assume !(0 == ~E_4~0); 1027103#L751-3 assume !(0 == ~E_5~0); 1027102#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1027101#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1027100#L346-24 assume !(1 == ~m_pc~0); 1027099#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1027098#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1027097#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1027096#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1027095#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1027094#L365-24 assume !(1 == ~t1_pc~0); 1027093#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1027092#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1027091#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1027090#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1027089#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1027088#L384-24 assume 1 == ~t2_pc~0; 1027087#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1027085#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1027084#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1027083#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1027082#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1027081#L403-24 assume !(1 == ~t3_pc~0); 1027080#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1027079#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1027078#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1027077#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1027076#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1027075#L422-24 assume !(1 == ~t4_pc~0); 1027074#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1027073#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1027072#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1027071#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1027070#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1027069#L441-24 assume !(1 == ~t5_pc~0); 1027068#L441-26 is_transmit5_triggered_~__retres1~5#1 := 0; 1027118#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1027117#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1027063#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1027062#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1027061#L460-24 assume !(1 == ~t6_pc~0); 1027060#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1027059#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1027058#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1027057#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1027056#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1027055#L774-3 assume !(1 == ~M_E~0); 1016079#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1027054#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1027053#L784-3 assume !(1 == ~T3_E~0); 1027052#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1027051#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1027050#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1027049#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1027048#L809-3 assume !(1 == ~E_1~0); 1027047#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1027046#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1027045#L824-3 assume !(1 == ~E_4~0); 1027044#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1027043#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1027042#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1027038#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1027034#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 995136#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 994365#L1084 assume !(0 == start_simulation_~tmp~3#1); 994366#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1000187#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1000180#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1000177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1000176#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1000175#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1000174#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1000172#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 981005#L1065-2 [2023-11-06 22:43:38,334 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:38,334 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2023-11-06 22:43:38,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:38,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [603994576] [2023-11-06 22:43:38,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:38,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:38,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:38,347 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:38,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:38,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:38,389 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:38,390 INFO L85 PathProgramCache]: Analyzing trace with hash 420509915, now seen corresponding path program 1 times [2023-11-06 22:43:38,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:38,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672083985] [2023-11-06 22:43:38,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:38,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:38,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:38,450 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:38,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:38,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672083985] [2023-11-06 22:43:38,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672083985] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:38,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:38,451 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:43:38,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369610532] [2023-11-06 22:43:38,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:38,452 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:38,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:38,452 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:43:38,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:43:38,453 INFO L87 Difference]: Start difference. First operand 66875 states and 92745 transitions. cyclomatic complexity: 25886 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:38,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:38,963 INFO L93 Difference]: Finished difference Result 118987 states and 163037 transitions. [2023-11-06 22:43:38,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118987 states and 163037 transitions. [2023-11-06 22:43:39,446 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 118258 [2023-11-06 22:43:40,372 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118987 states to 118987 states and 163037 transitions. [2023-11-06 22:43:40,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118987 [2023-11-06 22:43:40,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118987 [2023-11-06 22:43:40,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118987 states and 163037 transitions. [2023-11-06 22:43:40,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:40,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118987 states and 163037 transitions. [2023-11-06 22:43:40,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118987 states and 163037 transitions. [2023-11-06 22:43:41,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118987 to 67415. [2023-11-06 22:43:41,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67415 states, 67415 states have (on average 1.3837424905436475) internal successors, (93285), 67414 states have internal predecessors, (93285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:41,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67415 states to 67415 states and 93285 transitions. [2023-11-06 22:43:41,355 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67415 states and 93285 transitions. [2023-11-06 22:43:41,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:43:41,356 INFO L428 stractBuchiCegarLoop]: Abstraction has 67415 states and 93285 transitions. [2023-11-06 22:43:41,356 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:43:41,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67415 states and 93285 transitions. [2023-11-06 22:43:41,523 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67006 [2023-11-06 22:43:41,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:41,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:41,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:41,525 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:41,525 INFO L748 eck$LassoCheckResult]: Stem: 1166968#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1166969#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1167149#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1167150#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1167339#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1166864#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1166865#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1166697#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1166698#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1166670#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1166671#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1166843#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1167006#L696 assume !(0 == ~M_E~0); 1167007#L696-2 assume !(0 == ~T1_E~0); 1167347#L701-1 assume !(0 == ~T2_E~0); 1167349#L706-1 assume !(0 == ~T3_E~0); 1167123#L711-1 assume !(0 == ~T4_E~0); 1166900#L716-1 assume !(0 == ~T5_E~0); 1166901#L721-1 assume !(0 == ~T6_E~0); 1167077#L726-1 assume !(0 == ~E_M~0); 1167078#L731-1 assume !(0 == ~E_1~0); 1167042#L736-1 assume !(0 == ~E_2~0); 1167043#L741-1 assume !(0 == ~E_3~0); 1167134#L746-1 assume !(0 == ~E_4~0); 1166922#L751-1 assume !(0 == ~E_5~0); 1166923#L756-1 assume !(0 == ~E_6~0); 1166897#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1166717#L346 assume !(1 == ~m_pc~0); 1166718#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1166938#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1166928#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1166929#L861 assume !(0 != activate_threads_~tmp~1#1); 1167310#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1166751#L365 assume !(1 == ~t1_pc~0); 1166752#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1167323#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1166703#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1166704#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1166740#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1167197#L384 assume !(1 == ~t2_pc~0); 1167194#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1167195#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1167154#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166660#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1166661#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1167022#L403 assume !(1 == ~t3_pc~0); 1167023#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1167240#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1166633#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1166634#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1167016#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1167017#L422 assume !(1 == ~t4_pc~0); 1167147#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1167148#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1166805#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1166806#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1167101#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1166672#L441 assume !(1 == ~t5_pc~0); 1166673#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1167306#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1166940#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1166941#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1167112#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1167113#L460 assume !(1 == ~t6_pc~0); 1167265#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1166681#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1166682#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1167136#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1167260#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1167087#L774 assume !(1 == ~M_E~0); 1167088#L774-2 assume !(1 == ~T1_E~0); 1167279#L779-1 assume !(1 == ~T2_E~0); 1166988#L784-1 assume !(1 == ~T3_E~0); 1166989#L789-1 assume !(1 == ~T4_E~0); 1166734#L794-1 assume !(1 == ~T5_E~0); 1166735#L799-1 assume !(1 == ~T6_E~0); 1167394#L804-1 assume !(1 == ~E_M~0); 1167395#L809-1 assume !(1 == ~E_1~0); 1167073#L814-1 assume !(1 == ~E_2~0); 1166639#L819-1 assume !(1 == ~E_3~0); 1166640#L824-1 assume !(1 == ~E_4~0); 1167143#L829-1 assume !(1 == ~E_5~0); 1167268#L834-1 assume !(1 == ~E_6~0); 1166884#L839-1 assume { :end_inline_reset_delta_events } true; 1166885#L1065-2 [2023-11-06 22:43:41,526 INFO L750 eck$LassoCheckResult]: Loop: 1166885#L1065-2 assume !false; 1183281#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1200022#L671-1 assume !false; 1182416#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1182414#L530 assume !(0 == ~m_st~0); 1182415#L534 assume !(0 == ~t1_st~0); 1182410#L538 assume !(0 == ~t2_st~0); 1182411#L542 assume !(0 == ~t3_st~0); 1182413#L546 assume !(0 == ~t4_st~0); 1182408#L550 assume !(0 == ~t5_st~0); 1182409#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1182412#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1179977#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1179978#L582 assume !(0 != eval_~tmp~0#1); 1182401#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1182402#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1182397#L696-3 assume !(0 == ~M_E~0); 1182398#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1182393#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1182394#L706-3 assume !(0 == ~T3_E~0); 1182389#L711-3 assume !(0 == ~T4_E~0); 1182390#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1182385#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1182386#L726-3 assume !(0 == ~E_M~0); 1182381#L731-3 assume !(0 == ~E_1~0); 1182382#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1182377#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1182378#L746-3 assume !(0 == ~E_4~0); 1182373#L751-3 assume !(0 == ~E_5~0); 1182374#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1182369#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1182370#L346-24 assume !(1 == ~m_pc~0); 1182365#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1182366#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1182361#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1182362#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1182357#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1182358#L365-24 assume !(1 == ~t1_pc~0); 1182353#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1182354#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1182349#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1182350#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1182345#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1182346#L384-24 assume !(1 == ~t2_pc~0); 1182339#L384-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1182340#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1182335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1182336#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1182331#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1182332#L403-24 assume !(1 == ~t3_pc~0); 1182328#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1182329#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1182324#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1182325#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1182320#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182321#L422-24 assume !(1 == ~t4_pc~0); 1182316#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1182317#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1182312#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1182313#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1182308#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1182309#L441-24 assume 1 == ~t5_pc~0; 1182303#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1182304#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1182295#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1182296#L901-24 assume !(0 != activate_threads_~tmp___4~0#1); 1182288#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1182289#L460-24 assume !(1 == ~t6_pc~0); 1182284#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1182285#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1182280#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1182281#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1182276#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1182277#L774-3 assume !(1 == ~M_E~0); 1182273#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1182274#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1182269#L784-3 assume !(1 == ~T3_E~0); 1182270#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1182265#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1182266#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1182261#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1182262#L809-3 assume !(1 == ~E_1~0); 1182257#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1182258#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1182253#L824-3 assume !(1 == ~E_4~0); 1182254#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1182249#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1182250#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1182243#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1182240#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1182235#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1182236#L1084 assume !(0 == start_simulation_~tmp~3#1); 1183318#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1183319#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1200406#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1200405#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1200404#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1200400#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1200398#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1200396#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1166885#L1065-2 [2023-11-06 22:43:41,526 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:41,526 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2023-11-06 22:43:41,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:41,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085407227] [2023-11-06 22:43:41,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:41,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:41,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:41,540 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:41,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:41,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:41,568 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:41,568 INFO L85 PathProgramCache]: Analyzing trace with hash -650385366, now seen corresponding path program 1 times [2023-11-06 22:43:41,568 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:41,568 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608610653] [2023-11-06 22:43:41,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:41,569 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:42,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:42,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:42,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:42,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608610653] [2023-11-06 22:43:42,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608610653] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:42,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:42,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:43:42,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1949429333] [2023-11-06 22:43:42,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:42,319 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:42,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:42,320 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:43:42,320 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:43:42,320 INFO L87 Difference]: Start difference. First operand 67415 states and 93285 transitions. cyclomatic complexity: 25886 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:43,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:43,042 INFO L93 Difference]: Finished difference Result 126429 states and 174444 transitions. [2023-11-06 22:43:43,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126429 states and 174444 transitions. [2023-11-06 22:43:43,640 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 125678 [2023-11-06 22:43:43,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126429 states to 126429 states and 174444 transitions. [2023-11-06 22:43:43,988 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126429 [2023-11-06 22:43:44,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126429 [2023-11-06 22:43:44,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126429 states and 174444 transitions. [2023-11-06 22:43:44,146 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:44,146 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126429 states and 174444 transitions. [2023-11-06 22:43:44,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126429 states and 174444 transitions. [2023-11-06 22:43:45,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126429 to 67415. [2023-11-06 22:43:45,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67415 states, 67415 states have (on average 1.3699918415782837) internal successors, (92358), 67414 states have internal predecessors, (92358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:45,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67415 states to 67415 states and 92358 transitions. [2023-11-06 22:43:45,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67415 states and 92358 transitions. [2023-11-06 22:43:45,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-06 22:43:45,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 67415 states and 92358 transitions. [2023-11-06 22:43:45,949 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:43:45,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67415 states and 92358 transitions. [2023-11-06 22:43:46,142 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 67006 [2023-11-06 22:43:46,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:46,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:46,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:46,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:46,147 INFO L748 eck$LassoCheckResult]: Stem: 1360825#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1360826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1361007#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1361008#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1361205#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1360719#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1360720#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1360551#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1360552#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1360526#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1360527#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1360698#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1360860#L696 assume !(0 == ~M_E~0); 1360861#L696-2 assume !(0 == ~T1_E~0); 1361215#L701-1 assume !(0 == ~T2_E~0); 1361217#L706-1 assume !(0 == ~T3_E~0); 1360980#L711-1 assume !(0 == ~T4_E~0); 1360758#L716-1 assume !(0 == ~T5_E~0); 1360759#L721-1 assume !(0 == ~T6_E~0); 1360931#L726-1 assume !(0 == ~E_M~0); 1360932#L731-1 assume !(0 == ~E_1~0); 1360896#L736-1 assume !(0 == ~E_2~0); 1360897#L741-1 assume !(0 == ~E_3~0); 1360990#L746-1 assume !(0 == ~E_4~0); 1360781#L751-1 assume !(0 == ~E_5~0); 1360782#L756-1 assume !(0 == ~E_6~0); 1360755#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1360573#L346 assume !(1 == ~m_pc~0); 1360574#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1360796#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1360786#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1360787#L861 assume !(0 != activate_threads_~tmp~1#1); 1361170#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1360608#L365 assume !(1 == ~t1_pc~0); 1360609#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1361188#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1360559#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1360560#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1360597#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1361052#L384 assume !(1 == ~t2_pc~0); 1361049#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1361050#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1361013#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1360516#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1360517#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1360876#L403 assume !(1 == ~t3_pc~0); 1360877#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1361094#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1360489#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1360490#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1360870#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1360871#L422 assume !(1 == ~t4_pc~0); 1361005#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1361006#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1360661#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1360662#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1360957#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1360528#L441 assume !(1 == ~t5_pc~0); 1360529#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1361166#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1361343#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1361342#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1360969#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1360970#L460 assume !(1 == ~t6_pc~0); 1361119#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1360537#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1360538#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1360992#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1361114#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1360943#L774 assume !(1 == ~M_E~0); 1360944#L774-2 assume !(1 == ~T1_E~0); 1361136#L779-1 assume !(1 == ~T2_E~0); 1360843#L784-1 assume !(1 == ~T3_E~0); 1360844#L789-1 assume !(1 == ~T4_E~0); 1360591#L794-1 assume !(1 == ~T5_E~0); 1360592#L799-1 assume !(1 == ~T6_E~0); 1361270#L804-1 assume !(1 == ~E_M~0); 1361271#L809-1 assume !(1 == ~E_1~0); 1360927#L814-1 assume !(1 == ~E_2~0); 1360495#L819-1 assume !(1 == ~E_3~0); 1360496#L824-1 assume !(1 == ~E_4~0); 1360999#L829-1 assume !(1 == ~E_5~0); 1361123#L834-1 assume !(1 == ~E_6~0); 1360740#L839-1 assume { :end_inline_reset_delta_events } true; 1360741#L1065-2 [2023-11-06 22:43:46,148 INFO L750 eck$LassoCheckResult]: Loop: 1360741#L1065-2 assume !false; 1375318#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1375312#L671-1 assume !false; 1375307#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1374689#L530 assume !(0 == ~m_st~0); 1374690#L534 assume !(0 == ~t1_st~0); 1374685#L538 assume !(0 == ~t2_st~0); 1374686#L542 assume !(0 == ~t3_st~0); 1374688#L546 assume !(0 == ~t4_st~0); 1374682#L550 assume !(0 == ~t5_st~0); 1374684#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1374687#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1374676#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1374677#L582 assume !(0 != eval_~tmp~0#1); 1376576#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1385230#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1385229#L696-3 assume !(0 == ~M_E~0); 1385228#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1385227#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1385226#L706-3 assume !(0 == ~T3_E~0); 1385225#L711-3 assume !(0 == ~T4_E~0); 1385224#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1385223#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1385222#L726-3 assume !(0 == ~E_M~0); 1385221#L731-3 assume !(0 == ~E_1~0); 1385220#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1385219#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1385218#L746-3 assume !(0 == ~E_4~0); 1385217#L751-3 assume !(0 == ~E_5~0); 1385216#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1385215#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1385214#L346-24 assume !(1 == ~m_pc~0); 1385213#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1385212#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1385211#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1385210#L861-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1385209#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1385208#L365-24 assume !(1 == ~t1_pc~0); 1385207#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1385206#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1385205#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1385204#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1385203#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1385202#L384-24 assume 1 == ~t2_pc~0; 1385201#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1385199#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1385198#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1385197#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1385196#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385195#L403-24 assume !(1 == ~t3_pc~0); 1385194#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1385193#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1385192#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1385191#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1385190#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1385189#L422-24 assume !(1 == ~t4_pc~0); 1385188#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1385187#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1385186#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1385185#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1385184#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1376397#L441-24 assume 1 == ~t5_pc~0; 1376399#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1376391#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1376392#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1376384#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1375897#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1375894#L460-24 assume !(1 == ~t6_pc~0); 1375891#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1375888#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1375887#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1375886#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1375884#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1375875#L774-3 assume !(1 == ~M_E~0); 1375873#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1375871#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1375869#L784-3 assume !(1 == ~T3_E~0); 1375867#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1375865#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1375863#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1375861#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1375859#L809-3 assume !(1 == ~E_1~0); 1375857#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1375855#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1375853#L824-3 assume !(1 == ~E_4~0); 1375851#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1375847#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1375848#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1375702#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1375697#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1375695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1375692#L1084 assume !(0 == start_simulation_~tmp~3#1); 1375690#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1375688#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1375680#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1375678#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1375676#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1375674#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1375671#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1375340#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1360741#L1065-2 [2023-11-06 22:43:46,148 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:46,149 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2023-11-06 22:43:46,149 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:46,149 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262967158] [2023-11-06 22:43:46,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:46,149 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:46,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:46,169 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:46,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:46,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:46,198 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:46,198 INFO L85 PathProgramCache]: Analyzing trace with hash -46647193, now seen corresponding path program 1 times [2023-11-06 22:43:46,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:46,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400732284] [2023-11-06 22:43:46,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:46,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:46,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:46,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:46,286 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:46,287 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1400732284] [2023-11-06 22:43:46,287 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1400732284] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:46,287 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:46,287 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:43:46,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006466062] [2023-11-06 22:43:46,287 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:46,288 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:46,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:46,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:43:46,288 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:43:46,288 INFO L87 Difference]: Start difference. First operand 67415 states and 92358 transitions. cyclomatic complexity: 24959 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:46,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:46,762 INFO L93 Difference]: Finished difference Result 109543 states and 147785 transitions. [2023-11-06 22:43:46,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109543 states and 147785 transitions. [2023-11-06 22:43:48,028 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 109070 [2023-11-06 22:43:48,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109543 states to 109543 states and 147785 transitions. [2023-11-06 22:43:48,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109543 [2023-11-06 22:43:48,331 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109543 [2023-11-06 22:43:48,331 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109543 states and 147785 transitions. [2023-11-06 22:43:48,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:48,370 INFO L218 hiAutomatonCegarLoop]: Abstraction has 109543 states and 147785 transitions. [2023-11-06 22:43:48,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109543 states and 147785 transitions. [2023-11-06 22:43:48,933 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109543 to 68519. [2023-11-06 22:43:48,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68519 states, 68519 states have (on average 1.3561347947284694) internal successors, (92921), 68518 states have internal predecessors, (92921), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:49,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68519 states to 68519 states and 92921 transitions. [2023-11-06 22:43:49,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68519 states and 92921 transitions. [2023-11-06 22:43:49,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:43:49,737 INFO L428 stractBuchiCegarLoop]: Abstraction has 68519 states and 92921 transitions. [2023-11-06 22:43:49,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:43:49,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68519 states and 92921 transitions. [2023-11-06 22:43:49,891 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 68110 [2023-11-06 22:43:49,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:49,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:49,892 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:49,892 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:49,893 INFO L748 eck$LassoCheckResult]: Stem: 1537792#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1537793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1537978#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1537979#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1538163#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1537687#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1537688#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1537520#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1537521#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1537496#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1537497#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1537663#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1537828#L696 assume !(0 == ~M_E~0); 1537829#L696-2 assume !(0 == ~T1_E~0); 1538169#L701-1 assume !(0 == ~T2_E~0); 1538171#L706-1 assume !(0 == ~T3_E~0); 1537948#L711-1 assume !(0 == ~T4_E~0); 1537725#L716-1 assume !(0 == ~T5_E~0); 1537726#L721-1 assume !(0 == ~T6_E~0); 1537901#L726-1 assume !(0 == ~E_M~0); 1537902#L731-1 assume !(0 == ~E_1~0); 1537865#L736-1 assume !(0 == ~E_2~0); 1537866#L741-1 assume !(0 == ~E_3~0); 1537959#L746-1 assume !(0 == ~E_4~0); 1537747#L751-1 assume !(0 == ~E_5~0); 1537748#L756-1 assume !(0 == ~E_6~0); 1537722#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1537542#L346 assume !(1 == ~m_pc~0); 1537543#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1537762#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1537753#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1537754#L861 assume !(0 != activate_threads_~tmp~1#1); 1538134#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1537576#L365 assume !(1 == ~t1_pc~0); 1537577#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1538147#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1537526#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1537527#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1537566#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1538024#L384 assume !(1 == ~t2_pc~0); 1538018#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1538019#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1537980#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1537484#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1537485#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1537845#L403 assume !(1 == ~t3_pc~0); 1537846#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1538064#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1537459#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1537460#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1537838#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1537839#L422 assume !(1 == ~t4_pc~0); 1537976#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1537977#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1537630#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1537631#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1537925#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1537498#L441 assume !(1 == ~t5_pc~0); 1537499#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1538128#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1538224#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1538266#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1537935#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1537936#L460 assume !(1 == ~t6_pc~0); 1538087#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1537505#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1537506#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1537961#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1538084#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1537911#L774 assume !(1 == ~M_E~0); 1537912#L774-2 assume !(1 == ~T1_E~0); 1538105#L779-1 assume !(1 == ~T2_E~0); 1537813#L784-1 assume !(1 == ~T3_E~0); 1537814#L789-1 assume !(1 == ~T4_E~0); 1537561#L794-1 assume !(1 == ~T5_E~0); 1537562#L799-1 assume !(1 == ~T6_E~0); 1538210#L804-1 assume !(1 == ~E_M~0); 1538211#L809-1 assume !(1 == ~E_1~0); 1537896#L814-1 assume !(1 == ~E_2~0); 1537463#L819-1 assume !(1 == ~E_3~0); 1537464#L824-1 assume !(1 == ~E_4~0); 1537968#L829-1 assume !(1 == ~E_5~0); 1538093#L834-1 assume !(1 == ~E_6~0); 1537704#L839-1 assume { :end_inline_reset_delta_events } true; 1537705#L1065-2 [2023-11-06 22:43:49,893 INFO L750 eck$LassoCheckResult]: Loop: 1537705#L1065-2 assume !false; 1566384#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1561632#L671-1 assume !false; 1566381#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1566379#L530 assume !(0 == ~m_st~0); 1566380#L534 assume !(0 == ~t1_st~0); 1566376#L538 assume !(0 == ~t2_st~0); 1566377#L542 assume !(0 == ~t3_st~0); 1566378#L546 assume !(0 == ~t4_st~0); 1566375#L550 assume !(0 == ~t5_st~0); 1566374#L554 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1566372#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1566370#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1566368#L582 assume !(0 != eval_~tmp~0#1); 1566369#eval_returnLabel#1 havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1566364#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1566365#L696-3 assume !(0 == ~M_E~0); 1566360#L696-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1566361#L701-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1566356#L706-3 assume !(0 == ~T3_E~0); 1566357#L711-3 assume !(0 == ~T4_E~0); 1566352#L716-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1566353#L721-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1566348#L726-3 assume !(0 == ~E_M~0); 1566349#L731-3 assume !(0 == ~E_1~0); 1566344#L736-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1566345#L741-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1566340#L746-3 assume !(0 == ~E_4~0); 1566341#L751-3 assume !(0 == ~E_5~0); 1566336#L756-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1566337#L761-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1566332#L346-24 assume !(1 == ~m_pc~0); 1566333#L346-26 is_master_triggered_~__retres1~0#1 := 0; 1566328#L357-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1566329#is_master_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1566324#L861-24 assume !(0 != activate_threads_~tmp~1#1); 1566325#L861-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1566320#L365-24 assume !(1 == ~t1_pc~0); 1566321#L365-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1566317#L376-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1566318#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1566313#L869-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1566314#L869-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1566308#L384-24 assume 1 == ~t2_pc~0; 1566310#L385-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1566303#L395-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1566304#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1566299#L877-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1566300#L877-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1566295#L403-24 assume !(1 == ~t3_pc~0); 1566296#L403-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1566291#L414-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1566292#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1566287#L885-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1566288#L885-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1566283#L422-24 assume !(1 == ~t4_pc~0); 1566284#L422-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1566279#L433-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1566280#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1566275#L893-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1566276#L893-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1566270#L441-24 assume 1 == ~t5_pc~0; 1566272#L442-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1566264#L452-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1566265#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1566257#L901-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1566256#L901-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1566251#L460-24 assume !(1 == ~t6_pc~0); 1566252#L460-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1566247#L471-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1566248#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1566243#L909-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1566244#L909-26 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1566238#L774-3 assume !(1 == ~M_E~0); 1566019#L774-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1566232#L779-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1566233#L784-3 assume !(1 == ~T3_E~0); 1566226#L789-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1566227#L794-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1566220#L799-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1566221#L804-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1566143#L809-3 assume !(1 == ~E_1~0); 1566144#L814-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1566137#L819-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1566138#L824-3 assume !(1 == ~E_4~0); 1566131#L829-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1566132#L834-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1566125#L839-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1566126#L530-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1566113#L567-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1566114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1566107#L1084 assume !(0 == start_simulation_~tmp~3#1); 1566108#L1084-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1566401#L530-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1566394#L567-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1566393#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1566392#L1039 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1566391#L1046 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1566389#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1566386#L1097 assume !(0 != start_simulation_~tmp___0~1#1); 1537705#L1065-2 [2023-11-06 22:43:49,893 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:49,893 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 5 times [2023-11-06 22:43:49,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:49,894 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552135050] [2023-11-06 22:43:49,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:49,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:49,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:49,906 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:49,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:49,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:49,932 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:49,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1732827031, now seen corresponding path program 1 times [2023-11-06 22:43:49,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:49,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617288655] [2023-11-06 22:43:49,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:49,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:49,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:49,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:49,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:49,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617288655] [2023-11-06 22:43:49,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617288655] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:49,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:49,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:49,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560899862] [2023-11-06 22:43:49,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:49,975 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:43:49,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:49,975 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:49,976 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:49,976 INFO L87 Difference]: Start difference. First operand 68519 states and 92921 transitions. cyclomatic complexity: 24418 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:50,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:50,364 INFO L93 Difference]: Finished difference Result 105115 states and 140580 transitions. [2023-11-06 22:43:50,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105115 states and 140580 transitions. [2023-11-06 22:43:50,775 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 104652 [2023-11-06 22:43:51,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105115 states to 105115 states and 140580 transitions. [2023-11-06 22:43:51,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 105115 [2023-11-06 22:43:51,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 105115 [2023-11-06 22:43:51,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105115 states and 140580 transitions. [2023-11-06 22:43:51,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:43:51,128 INFO L218 hiAutomatonCegarLoop]: Abstraction has 105115 states and 140580 transitions. [2023-11-06 22:43:51,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105115 states and 140580 transitions. [2023-11-06 22:43:52,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105115 to 103691. [2023-11-06 22:43:52,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103691 states, 103691 states have (on average 1.3383225159367738) internal successors, (138772), 103690 states have internal predecessors, (138772), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:53,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103691 states to 103691 states and 138772 transitions. [2023-11-06 22:43:53,176 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103691 states and 138772 transitions. [2023-11-06 22:43:53,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:43:53,177 INFO L428 stractBuchiCegarLoop]: Abstraction has 103691 states and 138772 transitions. [2023-11-06 22:43:53,177 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:43:53,177 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103691 states and 138772 transitions. [2023-11-06 22:43:53,529 INFO L131 ngComponentsAnalysis]: Automaton has 36 accepting balls. 103228 [2023-11-06 22:43:53,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:43:53,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:43:53,530 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:53,530 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:43:53,531 INFO L748 eck$LassoCheckResult]: Stem: 1711439#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1711440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1711634#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1711635#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1711832#L487 assume 1 == ~m_i~0;~m_st~0 := 0; 1711330#L487-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1711331#L492-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1711160#L497-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1711161#L502-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1711136#L507-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1711137#L512-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1711306#L517-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1711472#L696 assume !(0 == ~M_E~0); 1711473#L696-2 assume !(0 == ~T1_E~0); 1711837#L701-1 assume !(0 == ~T2_E~0); 1711839#L706-1 assume !(0 == ~T3_E~0); 1711600#L711-1 assume !(0 == ~T4_E~0); 1711368#L716-1 assume !(0 == ~T5_E~0); 1711369#L721-1 assume !(0 == ~T6_E~0); 1711548#L726-1 assume !(0 == ~E_M~0); 1711549#L731-1 assume !(0 == ~E_1~0); 1711511#L736-1 assume !(0 == ~E_2~0); 1711512#L741-1 assume !(0 == ~E_3~0); 1711613#L746-1 assume !(0 == ~E_4~0); 1711390#L751-1 assume !(0 == ~E_5~0); 1711391#L756-1 assume !(0 == ~E_6~0); 1711365#L761-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1711181#L346 assume !(1 == ~m_pc~0); 1711182#L346-2 is_master_triggered_~__retres1~0#1 := 0; 1711406#L357 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1711398#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1711399#L861 assume !(0 != activate_threads_~tmp~1#1); 1711797#L861-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1711216#L365 assume !(1 == ~t1_pc~0); 1711217#L365-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1711815#L376 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1711165#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1711166#L869 assume !(0 != activate_threads_~tmp___0~0#1); 1711206#L869-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1711683#L384 assume !(1 == ~t2_pc~0); 1711677#L384-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1711678#L395 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1711636#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1711124#L877 assume !(0 != activate_threads_~tmp___1~0#1); 1711125#L877-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1711488#L403 assume !(1 == ~t3_pc~0); 1711489#L403-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1711725#L414 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1711099#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1711100#L885 assume !(0 != activate_threads_~tmp___2~0#1); 1711481#L885-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1711482#L422 assume !(1 == ~t4_pc~0); 1711632#L422-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1711633#L433 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1711270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1711271#L893 assume !(0 != activate_threads_~tmp___3~0#1); 1711576#L893-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1711138#L441 assume !(1 == ~t5_pc~0); 1711139#L441-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1711793#L452 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1711905#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1711956#L901 assume !(0 != activate_threads_~tmp___4~0#1); 1711585#L901-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1711586#L460 assume !(1 == ~t6_pc~0); 1711748#L460-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1711145#L471 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1711146#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1711615#L909 assume !(0 != activate_threads_~tmp___5~0#1); 1711745#L909-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1711558#L774 assume !(1 == ~M_E~0); 1711559#L774-2 assume !(1 == ~T1_E~0); 1711766#L779-1 assume !(1 == ~T2_E~0); 1711458#L784-1 assume !(1 == ~T3_E~0); 1711459#L789-1 assume !(1 == ~T4_E~0); 1711201#L794-1 assume !(1 == ~T5_E~0); 1711202#L799-1 assume !(1 == ~T6_E~0); 1711889#L804-1 assume !(1 == ~E_M~0); 1711890#L809-1 assume !(1 == ~E_1~0); 1711543#L814-1 assume !(1 == ~E_2~0); 1711103#L819-1 assume !(1 == ~E_3~0); 1711104#L824-1 assume !(1 == ~E_4~0); 1711622#L829-1 assume !(1 == ~E_5~0); 1711754#L834-1 assume !(1 == ~E_6~0); 1711347#L839-1 assume { :end_inline_reset_delta_events } true; 1711348#L1065-2 assume !false; 1723762#L1066 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret6#1, eval_#t~nondet7#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1723763#L671-1 [2023-11-06 22:43:53,531 INFO L750 eck$LassoCheckResult]: Loop: 1723763#L671-1 assume !false; 1751725#L578 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1751723#L530 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1751722#L567 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1751721#exists_runnable_thread_returnLabel#1 eval_#t~ret6#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret6#1;havoc eval_#t~ret6#1; 1751720#L582 assume 0 != eval_~tmp~0#1; 1751718#L582-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1751719#L590 assume !(0 != eval_~tmp_ndt_1~0#1); 1733881#L590-2 havoc eval_~tmp_ndt_1~0#1; 1733882#L587-1 assume !(0 == ~t1_st~0); 1751410#L601-1 assume !(0 == ~t2_st~0); 1751407#L615-1 assume !(0 == ~t3_st~0); 1751405#L629-1 assume !(0 == ~t4_st~0); 1751403#L643-1 assume !(0 == ~t5_st~0); 1751401#L657-1 assume !(0 == ~t6_st~0); 1723763#L671-1 [2023-11-06 22:43:53,532 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:53,533 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2023-11-06 22:43:53,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:53,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028463579] [2023-11-06 22:43:53,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:53,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:53,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:53,550 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:53,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:53,580 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:53,580 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:53,581 INFO L85 PathProgramCache]: Analyzing trace with hash 387080551, now seen corresponding path program 1 times [2023-11-06 22:43:53,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:53,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760053570] [2023-11-06 22:43:53,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:53,581 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:53,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:53,586 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:43:53,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:43:53,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:43:53,593 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:43:53,593 INFO L85 PathProgramCache]: Analyzing trace with hash 392000637, now seen corresponding path program 1 times [2023-11-06 22:43:53,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:43:53,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554113041] [2023-11-06 22:43:53,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:43:53,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:43:53,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:43:53,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:43:53,646 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:43:53,646 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554113041] [2023-11-06 22:43:53,646 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554113041] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:43:53,647 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:43:53,647 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:43:53,647 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324173453] [2023-11-06 22:43:53,647 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:43:53,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:43:53,782 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:43:53,794 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:43:53,794 INFO L87 Difference]: Start difference. First operand 103691 states and 138772 transitions. cyclomatic complexity: 35117 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:43:55,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:43:55,187 INFO L93 Difference]: Finished difference Result 196156 states and 259981 transitions. [2023-11-06 22:43:55,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 196156 states and 259981 transitions. [2023-11-06 22:43:55,851 INFO L131 ngComponentsAnalysis]: Automaton has 60 accepting balls. 191375 [2023-11-06 22:43:56,279 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 196156 states to 196156 states and 259981 transitions. [2023-11-06 22:43:56,279 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 196156 [2023-11-06 22:43:56,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 196156 [2023-11-06 22:43:56,391 INFO L73 IsDeterministic]: Start isDeterministic. Operand 196156 states and 259981 transitions.