./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version e7bb482b Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 --- Real Ultimate output --- This is Ultimate 0.2.3-dev-e7bb482 [2023-11-06 22:33:05,793 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-06 22:33:05,877 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-06 22:33:05,888 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-06 22:33:05,889 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-06 22:33:05,919 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-06 22:33:05,920 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-06 22:33:05,920 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-06 22:33:05,921 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-06 22:33:05,922 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-06 22:33:05,922 INFO L153 SettingsManager]: * Use SBE=true [2023-11-06 22:33:05,923 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-06 22:33:05,924 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-06 22:33:05,924 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-06 22:33:05,925 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-06 22:33:05,925 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-06 22:33:05,926 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-06 22:33:05,927 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-06 22:33:05,927 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-06 22:33:05,928 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-06 22:33:05,928 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-06 22:33:05,929 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-06 22:33:05,930 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-06 22:33:05,930 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-06 22:33:05,931 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-06 22:33:05,931 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-06 22:33:05,932 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-06 22:33:05,932 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-06 22:33:05,933 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-06 22:33:05,933 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-06 22:33:05,934 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-06 22:33:05,934 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-06 22:33:05,935 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-06 22:33:05,935 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-06 22:33:05,936 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-06 22:33:05,936 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-06 22:33:05,937 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 4d0fbec14d1477738cb6d25ea9b61fc7005f787f2c8a0ac2c555d7e4fa1dbf47 [2023-11-06 22:33:06,168 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-06 22:33:06,203 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-06 22:33:06,206 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-06 22:33:06,207 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-06 22:33:06,208 INFO L274 PluginConnector]: CDTParser initialized [2023-11-06 22:33:06,209 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/../../sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2023-11-06 22:33:09,357 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-06 22:33:09,618 INFO L384 CDTParser]: Found 1 translation units. [2023-11-06 22:33:09,618 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/sv-benchmarks/c/systemc/token_ring.06.cil-2.c [2023-11-06 22:33:09,643 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/data/8fc86ea00/63c9bf822a604e3ba22256d210825e12/FLAG8b0380785 [2023-11-06 22:33:09,675 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/data/8fc86ea00/63c9bf822a604e3ba22256d210825e12 [2023-11-06 22:33:09,681 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-06 22:33:09,683 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-06 22:33:09,685 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-06 22:33:09,685 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-06 22:33:09,690 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-06 22:33:09,690 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:33:09" (1/1) ... [2023-11-06 22:33:09,691 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@50f37ce0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:09, skipping insertion in model container [2023-11-06 22:33:09,692 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.11 10:33:09" (1/1) ... [2023-11-06 22:33:09,746 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-06 22:33:10,014 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:33:10,045 INFO L202 MainTranslator]: Completed pre-run [2023-11-06 22:33:10,102 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-06 22:33:10,122 INFO L206 MainTranslator]: Completed translation [2023-11-06 22:33:10,122 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10 WrapperNode [2023-11-06 22:33:10,123 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-06 22:33:10,124 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-06 22:33:10,124 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-06 22:33:10,124 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-06 22:33:10,132 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,143 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,248 INFO L138 Inliner]: procedures = 40, calls = 50, calls flagged for inlining = 45, calls inlined = 114, statements flattened = 1665 [2023-11-06 22:33:10,249 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-06 22:33:10,249 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-06 22:33:10,250 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-06 22:33:10,250 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-06 22:33:10,259 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,259 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,266 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,267 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,327 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,345 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,350 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,356 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,366 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-06 22:33:10,380 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-06 22:33:10,381 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-06 22:33:10,381 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-06 22:33:10,382 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (1/1) ... [2023-11-06 22:33:10,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-06 22:33:10,412 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/z3 [2023-11-06 22:33:10,430 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-06 22:33:10,432 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f2eefd9f-415c-4363-a67b-734378362590/bin/uautomizer-verify-WvqO1wxjHP/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-06 22:33:10,462 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-06 22:33:10,462 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2023-11-06 22:33:10,462 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-06 22:33:10,463 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-06 22:33:10,555 INFO L236 CfgBuilder]: Building ICFG [2023-11-06 22:33:10,558 INFO L262 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-06 22:33:11,885 INFO L277 CfgBuilder]: Performing block encoding [2023-11-06 22:33:11,905 INFO L297 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-06 22:33:11,906 INFO L302 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-06 22:33:11,909 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:33:11 BoogieIcfgContainer [2023-11-06 22:33:11,910 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-06 22:33:11,911 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-06 22:33:11,911 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-06 22:33:11,915 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-06 22:33:11,916 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:33:11,917 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.11 10:33:09" (1/3) ... [2023-11-06 22:33:11,918 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53b49c33 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:33:11, skipping insertion in model container [2023-11-06 22:33:11,918 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:33:11,918 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.11 10:33:10" (2/3) ... [2023-11-06 22:33:11,919 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@53b49c33 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.11 10:33:11, skipping insertion in model container [2023-11-06 22:33:11,919 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-06 22:33:11,919 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 06.11 10:33:11" (3/3) ... [2023-11-06 22:33:11,921 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.06.cil-2.c [2023-11-06 22:33:11,997 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-06 22:33:11,997 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-06 22:33:11,997 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-06 22:33:11,997 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-06 22:33:11,998 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-06 22:33:11,998 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-06 22:33:11,998 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-06 22:33:11,998 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-06 22:33:12,006 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:12,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2023-11-06 22:33:12,065 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:12,065 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:12,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-06 22:33:12,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:12,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 600 [2023-11-06 22:33:12,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:12,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:12,108 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,118 INFO L748 eck$LassoCheckResult]: Stem: 216#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 578#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 324#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 573#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91#L475true assume !(1 == ~m_i~0);~m_st~0 := 2; 561#L475-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 323#L480-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 628#L485-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 263#L490-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 126#L495-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 467#L500-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 80#L505-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L684true assume !(0 == ~M_E~0); 451#L684-2true assume !(0 == ~T1_E~0); 291#L689-1true assume !(0 == ~T2_E~0); 671#L694-1true assume !(0 == ~T3_E~0); 290#L699-1true assume !(0 == ~T4_E~0); 445#L704-1true assume !(0 == ~T5_E~0); 249#L709-1true assume !(0 == ~T6_E~0); 205#L714-1true assume 0 == ~E_M~0;~E_M~0 := 1; 410#L719-1true assume !(0 == ~E_1~0); 595#L724-1true assume !(0 == ~E_2~0); 65#L729-1true assume !(0 == ~E_3~0); 569#L734-1true assume !(0 == ~E_4~0); 503#L739-1true assume !(0 == ~E_5~0); 179#L744-1true assume !(0 == ~E_6~0); 411#L749-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43#L334true assume !(1 == ~m_pc~0); 244#L334-2true is_master_triggered_~__retres1~0#1 := 0; 514#L345true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 182#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 161#L849true assume !(0 != activate_threads_~tmp~1#1); 375#L849-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 125#L353true assume 1 == ~t1_pc~0; 603#L354true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 327#L364true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 302#L857true assume !(0 != activate_threads_~tmp___0~0#1); 94#L857-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 567#L372true assume !(1 == ~t2_pc~0); 167#L372-2true is_transmit2_triggered_~__retres1~2#1 := 0; 240#L383true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 328#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 488#L865true assume !(0 != activate_threads_~tmp___1~0#1); 38#L865-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 463#L391true assume 1 == ~t3_pc~0; 586#L392true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 114#L402true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 401#L873true assume !(0 != activate_threads_~tmp___2~0#1); 164#L873-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 485#L410true assume 1 == ~t4_pc~0; 602#L411true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 380#L421true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 490#L881true assume !(0 != activate_threads_~tmp___3~0#1); 169#L881-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 284#L429true assume !(1 == ~t5_pc~0); 68#L429-2true is_transmit5_triggered_~__retres1~5#1 := 0; 660#L440true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 189#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 349#L889true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 372#L889-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 159#L448true assume 1 == ~t6_pc~0; 88#L449true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 346#L459true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 314#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 541#L897true assume !(0 != activate_threads_~tmp___5~0#1); 648#L897-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 640#L762true assume !(1 == ~M_E~0); 193#L762-2true assume !(1 == ~T1_E~0); 600#L767-1true assume !(1 == ~T2_E~0); 550#L772-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 373#L777-1true assume !(1 == ~T4_E~0); 276#L782-1true assume !(1 == ~T5_E~0); 83#L787-1true assume !(1 == ~T6_E~0); 82#L792-1true assume !(1 == ~E_M~0); 106#L797-1true assume !(1 == ~E_1~0); 429#L802-1true assume !(1 == ~E_2~0); 247#L807-1true assume !(1 == ~E_3~0); 498#L812-1true assume 1 == ~E_4~0;~E_4~0 := 2; 619#L817-1true assume !(1 == ~E_5~0); 292#L822-1true assume !(1 == ~E_6~0); 512#L827-1true assume { :end_inline_reset_delta_events } true; 162#L1053-2true [2023-11-06 22:33:12,121 INFO L750 eck$LassoCheckResult]: Loop: 162#L1053-2true assume !false; 487#L1054true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 376#L659-1true assume false; 110#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 507#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 266#L684-3true assume 0 == ~M_E~0;~M_E~0 := 1; 438#L684-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 2#L689-3true assume !(0 == ~T2_E~0); 191#L694-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 28#L699-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 359#L704-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 492#L709-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 337#L714-3true assume 0 == ~E_M~0;~E_M~0 := 1; 186#L719-3true assume 0 == ~E_1~0;~E_1~0 := 1; 25#L724-3true assume 0 == ~E_2~0;~E_2~0 := 1; 318#L729-3true assume !(0 == ~E_3~0); 382#L734-3true assume 0 == ~E_4~0;~E_4~0 := 1; 363#L739-3true assume 0 == ~E_5~0;~E_5~0 := 1; 542#L744-3true assume 0 == ~E_6~0;~E_6~0 := 1; 494#L749-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31#L334-24true assume 1 == ~m_pc~0; 310#L335-8true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 332#L345-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 121#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17#L849-24true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 625#L849-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 361#L353-24true assume !(1 == ~t1_pc~0); 634#L353-26true is_transmit1_triggered_~__retres1~1#1 := 0; 556#L364-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 553#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 589#L857-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39#L857-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72#L372-24true assume 1 == ~t2_pc~0; 22#L373-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 230#L383-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 679#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 535#L865-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 662#L865-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 207#L391-24true assume !(1 == ~t3_pc~0); 633#L391-26true is_transmit3_triggered_~__retres1~3#1 := 0; 412#L402-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 362#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277#L873-24true assume !(0 != activate_threads_~tmp___2~0#1); 254#L873-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 141#L410-24true assume 1 == ~t4_pc~0; 107#L411-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 386#L421-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 493#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168#L881-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 81#L881-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 139#L429-24true assume 1 == ~t5_pc~0; 282#L430-8true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 385#L440-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109#L889-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 223#L889-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 79#L448-24true assume 1 == ~t6_pc~0; 112#L449-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 74#L459-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 175#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 520#L897-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 285#L897-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 511#L762-3true assume 1 == ~M_E~0;~M_E~0 := 2; 251#L762-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 580#L767-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 668#L772-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 546#L777-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 69#L782-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 647#L787-3true assume !(1 == ~T6_E~0); 394#L792-3true assume 1 == ~E_M~0;~E_M~0 := 2; 206#L797-3true assume 1 == ~E_1~0;~E_1~0 := 2; 453#L802-3true assume 1 == ~E_2~0;~E_2~0 := 2; 664#L807-3true assume 1 == ~E_3~0;~E_3~0 := 2; 315#L812-3true assume 1 == ~E_4~0;~E_4~0 := 2; 506#L817-3true assume 1 == ~E_5~0;~E_5~0 := 2; 404#L822-3true assume 1 == ~E_6~0;~E_6~0 := 2; 388#L827-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 221#L518-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 389#L555-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 301#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 620#L1072true assume !(0 == start_simulation_~tmp~3#1); 151#L1072-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 502#L518-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75#L555-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 49#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 34#L1027true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 605#L1034true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 524#stop_simulation_returnLabel#1true start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 407#L1085true assume !(0 != start_simulation_~tmp___0~1#1); 162#L1053-2true [2023-11-06 22:33:12,130 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:12,130 INFO L85 PathProgramCache]: Analyzing trace with hash -376834623, now seen corresponding path program 1 times [2023-11-06 22:33:12,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:12,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888629982] [2023-11-06 22:33:12,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:12,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:12,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:12,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:12,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:12,490 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888629982] [2023-11-06 22:33:12,491 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888629982] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:12,491 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:12,491 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:12,493 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040166818] [2023-11-06 22:33:12,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:12,499 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:12,500 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:12,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1316317370, now seen corresponding path program 1 times [2023-11-06 22:33:12,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:12,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1671041942] [2023-11-06 22:33:12,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:12,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:12,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:12,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:12,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:12,632 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1671041942] [2023-11-06 22:33:12,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1671041942] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:12,632 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:12,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:33:12,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1109838024] [2023-11-06 22:33:12,633 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:12,634 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:12,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:12,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:12,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:12,700 INFO L87 Difference]: Start difference. First operand has 695 states, 694 states have (on average 1.5172910662824208) internal successors, (1053), 694 states have internal predecessors, (1053), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:12,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:12,787 INFO L93 Difference]: Finished difference Result 693 states and 1031 transitions. [2023-11-06 22:33:12,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 693 states and 1031 transitions. [2023-11-06 22:33:12,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:12,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 693 states to 688 states and 1026 transitions. [2023-11-06 22:33:12,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:12,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:12,816 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1026 transitions. [2023-11-06 22:33:12,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:12,827 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-06 22:33:12,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1026 transitions. [2023-11-06 22:33:12,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:12,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4912790697674418) internal successors, (1026), 687 states have internal predecessors, (1026), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:12,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1026 transitions. [2023-11-06 22:33:12,897 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-06 22:33:12,898 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:12,904 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1026 transitions. [2023-11-06 22:33:12,904 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-06 22:33:12,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1026 transitions. [2023-11-06 22:33:12,910 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:12,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:12,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:12,924 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,924 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:12,925 INFO L748 eck$LassoCheckResult]: Stem: 1789#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1790#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1915#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1916#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1583#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1584#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1911#L480-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1912#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1843#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1637#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1638#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1561#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1562#L684 assume !(0 == ~M_E~0); 2013#L684-2 assume !(0 == ~T1_E~0); 1872#L689-1 assume !(0 == ~T2_E~0); 1873#L694-1 assume !(0 == ~T3_E~0); 1870#L699-1 assume !(0 == ~T4_E~0); 1871#L704-1 assume !(0 == ~T5_E~0); 1828#L709-1 assume !(0 == ~T6_E~0); 1767#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 1768#L719-1 assume !(0 == ~E_1~0); 1987#L724-1 assume !(0 == ~E_2~0); 1533#L729-1 assume !(0 == ~E_3~0); 1534#L734-1 assume !(0 == ~E_4~0); 2040#L739-1 assume !(0 == ~E_5~0); 1730#L744-1 assume !(0 == ~E_6~0); 1731#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1490#L334 assume !(1 == ~m_pc~0); 1491#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1820#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1733#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1701#L849 assume !(0 != activate_threads_~tmp~1#1); 1702#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1634#L353 assume 1 == ~t1_pc~0; 1635#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1917#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1505#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1506#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1586#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1587#L372 assume !(1 == ~t2_pc~0); 1690#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1689#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1815#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1918#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1479#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1480#L391 assume 1 == ~t3_pc~0; 2024#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1402#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1428#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1429#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1708#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1709#L410 assume 1 == ~t4_pc~0; 2031#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1932#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1600#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1601#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1717#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1718#L429 assume !(1 == ~t5_pc~0); 1539#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1540#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1743#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1744#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1935#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1700#L448 assume 1 == ~t6_pc~0; 1574#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1575#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1903#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1904#L897 assume !(0 != activate_threads_~tmp___5~0#1); 2059#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082#L762 assume !(1 == ~M_E~0); 1747#L762-2 assume !(1 == ~T1_E~0); 1748#L767-1 assume !(1 == ~T2_E~0); 2064#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1963#L777-1 assume !(1 == ~T4_E~0); 1858#L782-1 assume !(1 == ~T5_E~0); 1565#L787-1 assume !(1 == ~T6_E~0); 1563#L792-1 assume !(1 == ~E_M~0); 1564#L797-1 assume !(1 == ~E_1~0); 1606#L802-1 assume !(1 == ~E_2~0); 1824#L807-1 assume !(1 == ~E_3~0); 1825#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2035#L817-1 assume !(1 == ~E_5~0); 1876#L822-1 assume !(1 == ~E_6~0); 1877#L827-1 assume { :end_inline_reset_delta_events } true; 1703#L1053-2 [2023-11-06 22:33:12,925 INFO L750 eck$LassoCheckResult]: Loop: 1703#L1053-2 assume !false; 1704#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1679#L659-1 assume !false; 1668#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1669#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1937#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1938#L570 assume !(0 != eval_~tmp~0#1); 1611#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1612#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1849#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1850#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1397#L689-3 assume !(0 == ~T2_E~0); 1398#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1457#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1458#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1944#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1929#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1742#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1450#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1451#L729-3 assume !(0 == ~E_3~0); 1908#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1950#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1951#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2033#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1464#L334-24 assume !(1 == ~m_pc~0); 1465#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1604#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1629#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1436#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1437#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1945#L353-24 assume 1 == ~t1_pc~0; 1946#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1975#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2065#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1481#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1482#L372-24 assume 1 == ~t2_pc~0; 1443#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1444#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1803#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2052#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2053#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1772#L391-24 assume !(1 == ~t3_pc~0); 1773#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1988#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1948#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1859#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1834#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1667#L410-24 assume 1 == ~t4_pc~0; 1605#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1531#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1968#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1713#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1559#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1560#L429-24 assume 1 == ~t5_pc~0; 1664#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1863#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1835#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1609#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1610#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1554#L448-24 assume 1 == ~t6_pc~0; 1555#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1548#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1549#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1724#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1866#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1867#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1832#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1833#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2071#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2061#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1541#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1542#L787-3 assume !(1 == ~T6_E~0); 1976#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1769#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1770#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2015#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1901#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1902#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1982#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1972#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1796#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1441#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1888#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1889#L1072 assume !(0 == start_simulation_~tmp~3#1); 1684#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1685#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1550#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1504#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1469#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1470#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2047#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1985#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1703#L1053-2 [2023-11-06 22:33:12,926 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:12,926 INFO L85 PathProgramCache]: Analyzing trace with hash 765667843, now seen corresponding path program 1 times [2023-11-06 22:33:12,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:12,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155777819] [2023-11-06 22:33:12,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:12,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:12,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155777819] [2023-11-06 22:33:13,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155777819] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491490082] [2023-11-06 22:33:13,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,058 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:13,059 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,059 INFO L85 PathProgramCache]: Analyzing trace with hash 1886177719, now seen corresponding path program 1 times [2023-11-06 22:33:13,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,060 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844886758] [2023-11-06 22:33:13,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,060 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,085 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,146 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844886758] [2023-11-06 22:33:13,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844886758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1152750954] [2023-11-06 22:33:13,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,148 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:13,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:13,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:13,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:13,150 INFO L87 Difference]: Start difference. First operand 688 states and 1026 transitions. cyclomatic complexity: 339 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:13,174 INFO L93 Difference]: Finished difference Result 688 states and 1025 transitions. [2023-11-06 22:33:13,174 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1025 transitions. [2023-11-06 22:33:13,181 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1025 transitions. [2023-11-06 22:33:13,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:13,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:13,189 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1025 transitions. [2023-11-06 22:33:13,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:13,193 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-06 22:33:13,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1025 transitions. [2023-11-06 22:33:13,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:13,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.489825581395349) internal successors, (1025), 687 states have internal predecessors, (1025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1025 transitions. [2023-11-06 22:33:13,216 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-06 22:33:13,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:13,218 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1025 transitions. [2023-11-06 22:33:13,218 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-06 22:33:13,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1025 transitions. [2023-11-06 22:33:13,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:13,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:13,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,227 INFO L748 eck$LassoCheckResult]: Stem: 3170#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 3171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3296#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3297#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2964#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 2965#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3294#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3295#L485-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3226#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3020#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3021#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2942#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2943#L684 assume !(0 == ~M_E~0); 3396#L684-2 assume !(0 == ~T1_E~0); 3255#L689-1 assume !(0 == ~T2_E~0); 3256#L694-1 assume !(0 == ~T3_E~0); 3253#L699-1 assume !(0 == ~T4_E~0); 3254#L704-1 assume !(0 == ~T5_E~0); 3211#L709-1 assume !(0 == ~T6_E~0); 3150#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 3151#L719-1 assume !(0 == ~E_1~0); 3370#L724-1 assume !(0 == ~E_2~0); 2916#L729-1 assume !(0 == ~E_3~0); 2917#L734-1 assume !(0 == ~E_4~0); 3423#L739-1 assume !(0 == ~E_5~0); 3113#L744-1 assume !(0 == ~E_6~0); 3114#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2873#L334 assume !(1 == ~m_pc~0); 2874#L334-2 is_master_triggered_~__retres1~0#1 := 0; 3203#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3115#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3084#L849 assume !(0 != activate_threads_~tmp~1#1); 3085#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3017#L353 assume 1 == ~t1_pc~0; 3018#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3300#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2888#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2889#L857 assume !(0 != activate_threads_~tmp___0~0#1); 2969#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2970#L372 assume !(1 == ~t2_pc~0); 3073#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3072#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3198#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3301#L865 assume !(0 != activate_threads_~tmp___1~0#1); 2862#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2863#L391 assume 1 == ~t3_pc~0; 3405#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2785#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2812#L873 assume !(0 != activate_threads_~tmp___2~0#1); 3091#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3092#L410 assume 1 == ~t4_pc~0; 3413#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3314#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2983#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2984#L881 assume !(0 != activate_threads_~tmp___3~0#1); 3097#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3098#L429 assume !(1 == ~t5_pc~0); 2922#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2923#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3126#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3127#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3318#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3083#L448 assume 1 == ~t6_pc~0; 2957#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2958#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3285#L897 assume !(0 != activate_threads_~tmp___5~0#1); 3442#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3465#L762 assume !(1 == ~M_E~0); 3130#L762-2 assume !(1 == ~T1_E~0); 3131#L767-1 assume !(1 == ~T2_E~0); 3447#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3346#L777-1 assume !(1 == ~T4_E~0); 3241#L782-1 assume !(1 == ~T5_E~0); 2948#L787-1 assume !(1 == ~T6_E~0); 2946#L792-1 assume !(1 == ~E_M~0); 2947#L797-1 assume !(1 == ~E_1~0); 2988#L802-1 assume !(1 == ~E_2~0); 3207#L807-1 assume !(1 == ~E_3~0); 3208#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3418#L817-1 assume !(1 == ~E_5~0); 3257#L822-1 assume !(1 == ~E_6~0); 3258#L827-1 assume { :end_inline_reset_delta_events } true; 3086#L1053-2 [2023-11-06 22:33:13,227 INFO L750 eck$LassoCheckResult]: Loop: 3086#L1053-2 assume !false; 3087#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3062#L659-1 assume !false; 3051#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3052#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3054#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3320#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3321#L570 assume !(0 != eval_~tmp~0#1); 2994#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2995#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3230#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3231#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2780#L689-3 assume !(0 == ~T2_E~0); 2781#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2840#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2841#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3327#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3310#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3120#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2833#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2834#L729-3 assume !(0 == ~E_3~0); 3290#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3334#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3416#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2847#L334-24 assume !(1 == ~m_pc~0); 2848#L334-26 is_master_triggered_~__retres1~0#1 := 0; 2987#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3012#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2817#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2818#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3329#L353-24 assume 1 == ~t1_pc~0; 3330#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3358#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3448#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3449#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2864#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2865#L372-24 assume 1 == ~t2_pc~0; 2826#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2827#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3186#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3436#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3437#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3155#L391-24 assume !(1 == ~t3_pc~0); 3156#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3371#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3242#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 3220#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3050#L410-24 assume !(1 == ~t4_pc~0); 2913#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3351#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3096#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2944#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2945#L429-24 assume !(1 == ~t5_pc~0); 3046#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 3246#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3221#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2992#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2993#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2939#L448-24 assume 1 == ~t6_pc~0; 2940#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2931#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2932#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3107#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3249#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3250#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3215#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3216#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3454#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3444#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2924#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2925#L787-3 assume !(1 == ~T6_E~0); 3359#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3152#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3153#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3398#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3286#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3287#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3365#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3355#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3179#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2824#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3271#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 3272#L1072 assume !(0 == start_simulation_~tmp~3#1); 3067#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3068#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2933#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2887#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 2854#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2855#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3430#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3368#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 3086#L1053-2 [2023-11-06 22:33:13,228 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,228 INFO L85 PathProgramCache]: Analyzing trace with hash -73365819, now seen corresponding path program 1 times [2023-11-06 22:33:13,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [396426578] [2023-11-06 22:33:13,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [396426578] [2023-11-06 22:33:13,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [396426578] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987971868] [2023-11-06 22:33:13,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,291 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:13,292 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,292 INFO L85 PathProgramCache]: Analyzing trace with hash 55771641, now seen corresponding path program 1 times [2023-11-06 22:33:13,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,292 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254030251] [2023-11-06 22:33:13,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,359 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,359 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254030251] [2023-11-06 22:33:13,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254030251] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48623549] [2023-11-06 22:33:13,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,368 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:13,368 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:13,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:13,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:13,369 INFO L87 Difference]: Start difference. First operand 688 states and 1025 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,401 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:13,402 INFO L93 Difference]: Finished difference Result 688 states and 1024 transitions. [2023-11-06 22:33:13,402 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1024 transitions. [2023-11-06 22:33:13,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1024 transitions. [2023-11-06 22:33:13,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:13,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:13,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1024 transitions. [2023-11-06 22:33:13,446 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:13,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-06 22:33:13,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1024 transitions. [2023-11-06 22:33:13,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:13,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4883720930232558) internal successors, (1024), 687 states have internal predecessors, (1024), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1024 transitions. [2023-11-06 22:33:13,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-06 22:33:13,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:13,466 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1024 transitions. [2023-11-06 22:33:13,466 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-06 22:33:13,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1024 transitions. [2023-11-06 22:33:13,471 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:13,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:13,473 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,474 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,474 INFO L748 eck$LassoCheckResult]: Stem: 4553#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 4554#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4679#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4680#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4347#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 4348#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4677#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4678#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4609#L490-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4403#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4404#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4325#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4326#L684 assume !(0 == ~M_E~0); 4779#L684-2 assume !(0 == ~T1_E~0); 4638#L689-1 assume !(0 == ~T2_E~0); 4639#L694-1 assume !(0 == ~T3_E~0); 4636#L699-1 assume !(0 == ~T4_E~0); 4637#L704-1 assume !(0 == ~T5_E~0); 4594#L709-1 assume !(0 == ~T6_E~0); 4533#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 4534#L719-1 assume !(0 == ~E_1~0); 4753#L724-1 assume !(0 == ~E_2~0); 4299#L729-1 assume !(0 == ~E_3~0); 4300#L734-1 assume !(0 == ~E_4~0); 4806#L739-1 assume !(0 == ~E_5~0); 4496#L744-1 assume !(0 == ~E_6~0); 4497#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4256#L334 assume !(1 == ~m_pc~0); 4257#L334-2 is_master_triggered_~__retres1~0#1 := 0; 4586#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4498#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4467#L849 assume !(0 != activate_threads_~tmp~1#1); 4468#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4400#L353 assume 1 == ~t1_pc~0; 4401#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4683#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4271#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4272#L857 assume !(0 != activate_threads_~tmp___0~0#1); 4352#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4353#L372 assume !(1 == ~t2_pc~0); 4456#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4455#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4581#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4684#L865 assume !(0 != activate_threads_~tmp___1~0#1); 4245#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4246#L391 assume 1 == ~t3_pc~0; 4788#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4168#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4194#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4195#L873 assume !(0 != activate_threads_~tmp___2~0#1); 4474#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4475#L410 assume 1 == ~t4_pc~0; 4797#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4697#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4367#L881 assume !(0 != activate_threads_~tmp___3~0#1); 4480#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4481#L429 assume !(1 == ~t5_pc~0); 4305#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4306#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4510#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4701#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4466#L448 assume 1 == ~t6_pc~0; 4340#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4341#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4667#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4668#L897 assume !(0 != activate_threads_~tmp___5~0#1); 4825#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4848#L762 assume !(1 == ~M_E~0); 4513#L762-2 assume !(1 == ~T1_E~0); 4514#L767-1 assume !(1 == ~T2_E~0); 4830#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4729#L777-1 assume !(1 == ~T4_E~0); 4624#L782-1 assume !(1 == ~T5_E~0); 4331#L787-1 assume !(1 == ~T6_E~0); 4329#L792-1 assume !(1 == ~E_M~0); 4330#L797-1 assume !(1 == ~E_1~0); 4371#L802-1 assume !(1 == ~E_2~0); 4590#L807-1 assume !(1 == ~E_3~0); 4591#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4801#L817-1 assume !(1 == ~E_5~0); 4642#L822-1 assume !(1 == ~E_6~0); 4643#L827-1 assume { :end_inline_reset_delta_events } true; 4469#L1053-2 [2023-11-06 22:33:13,475 INFO L750 eck$LassoCheckResult]: Loop: 4469#L1053-2 assume !false; 4470#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4445#L659-1 assume !false; 4434#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4435#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4437#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4703#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4704#L570 assume !(0 != eval_~tmp~0#1); 4377#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4378#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4615#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4616#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4163#L689-3 assume !(0 == ~T2_E~0); 4164#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4223#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4224#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4710#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4693#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4503#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4216#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4217#L729-3 assume !(0 == ~E_3~0); 4673#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4716#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4717#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4799#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4230#L334-24 assume !(1 == ~m_pc~0); 4231#L334-26 is_master_triggered_~__retres1~0#1 := 0; 4370#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4395#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4200#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4201#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4712#L353-24 assume 1 == ~t1_pc~0; 4713#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4741#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4831#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4832#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4247#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4248#L372-24 assume 1 == ~t2_pc~0; 4209#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4210#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4569#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4819#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4820#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4538#L391-24 assume !(1 == ~t3_pc~0); 4539#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4754#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4715#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4625#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 4603#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4433#L410-24 assume 1 == ~t4_pc~0; 4372#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4297#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4734#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4479#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4327#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4328#L429-24 assume !(1 == ~t5_pc~0); 4429#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 4629#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4604#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4375#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4376#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4322#L448-24 assume 1 == ~t6_pc~0; 4323#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4314#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4315#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4490#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4632#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4633#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4598#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4599#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4837#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4827#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4307#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4308#L787-3 assume !(1 == ~T6_E~0); 4742#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4535#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4536#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4781#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4669#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4670#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4748#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4738#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4562#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4207#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4654#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4655#L1072 assume !(0 == start_simulation_~tmp~3#1); 4450#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4451#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4316#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4270#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 4237#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4238#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4813#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 4751#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 4469#L1053-2 [2023-11-06 22:33:13,475 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,475 INFO L85 PathProgramCache]: Analyzing trace with hash -100431421, now seen corresponding path program 1 times [2023-11-06 22:33:13,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,476 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534600129] [2023-11-06 22:33:13,476 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,476 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534600129] [2023-11-06 22:33:13,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534600129] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,522 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [47119237] [2023-11-06 22:33:13,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,523 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:13,524 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,524 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 1 times [2023-11-06 22:33:13,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [956526157] [2023-11-06 22:33:13,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [956526157] [2023-11-06 22:33:13,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [956526157] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854602648] [2023-11-06 22:33:13,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,627 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:13,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:13,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:13,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:13,628 INFO L87 Difference]: Start difference. First operand 688 states and 1024 transitions. cyclomatic complexity: 337 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:13,652 INFO L93 Difference]: Finished difference Result 688 states and 1023 transitions. [2023-11-06 22:33:13,653 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1023 transitions. [2023-11-06 22:33:13,659 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,668 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1023 transitions. [2023-11-06 22:33:13,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:13,669 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:13,669 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1023 transitions. [2023-11-06 22:33:13,671 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:13,671 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-06 22:33:13,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1023 transitions. [2023-11-06 22:33:13,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:13,684 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4869186046511629) internal successors, (1023), 687 states have internal predecessors, (1023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1023 transitions. [2023-11-06 22:33:13,687 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-06 22:33:13,688 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:13,689 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1023 transitions. [2023-11-06 22:33:13,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-06 22:33:13,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1023 transitions. [2023-11-06 22:33:13,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:13,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:13,700 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,701 INFO L748 eck$LassoCheckResult]: Stem: 5938#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 5939#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6064#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6065#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5733#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 5734#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6060#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6061#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5992#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5786#L495-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5787#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5710#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5711#L684 assume !(0 == ~M_E~0); 6163#L684-2 assume !(0 == ~T1_E~0); 6021#L689-1 assume !(0 == ~T2_E~0); 6022#L694-1 assume !(0 == ~T3_E~0); 6019#L699-1 assume !(0 == ~T4_E~0); 6020#L704-1 assume !(0 == ~T5_E~0); 5977#L709-1 assume !(0 == ~T6_E~0); 5916#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 5917#L719-1 assume !(0 == ~E_1~0); 6136#L724-1 assume !(0 == ~E_2~0); 5682#L729-1 assume !(0 == ~E_3~0); 5683#L734-1 assume !(0 == ~E_4~0); 6189#L739-1 assume !(0 == ~E_5~0); 5879#L744-1 assume !(0 == ~E_6~0); 5880#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5639#L334 assume !(1 == ~m_pc~0); 5640#L334-2 is_master_triggered_~__retres1~0#1 := 0; 5969#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5882#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5850#L849 assume !(0 != activate_threads_~tmp~1#1); 5851#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5783#L353 assume 1 == ~t1_pc~0; 5784#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6066#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5654#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5655#L857 assume !(0 != activate_threads_~tmp___0~0#1); 5735#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5736#L372 assume !(1 == ~t2_pc~0); 5839#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5838#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5964#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6067#L865 assume !(0 != activate_threads_~tmp___1~0#1); 5628#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5629#L391 assume 1 == ~t3_pc~0; 6173#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5551#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5577#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5578#L873 assume !(0 != activate_threads_~tmp___2~0#1); 5857#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5858#L410 assume 1 == ~t4_pc~0; 6180#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6081#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5749#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5750#L881 assume !(0 != activate_threads_~tmp___3~0#1); 5866#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5867#L429 assume !(1 == ~t5_pc~0); 5688#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5689#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5893#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6084#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5849#L448 assume 1 == ~t6_pc~0; 5723#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5724#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6053#L897 assume !(0 != activate_threads_~tmp___5~0#1); 6208#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6231#L762 assume !(1 == ~M_E~0); 5896#L762-2 assume !(1 == ~T1_E~0); 5897#L767-1 assume !(1 == ~T2_E~0); 6213#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6112#L777-1 assume !(1 == ~T4_E~0); 6007#L782-1 assume !(1 == ~T5_E~0); 5714#L787-1 assume !(1 == ~T6_E~0); 5712#L792-1 assume !(1 == ~E_M~0); 5713#L797-1 assume !(1 == ~E_1~0); 5755#L802-1 assume !(1 == ~E_2~0); 5973#L807-1 assume !(1 == ~E_3~0); 5974#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6184#L817-1 assume !(1 == ~E_5~0); 6025#L822-1 assume !(1 == ~E_6~0); 6026#L827-1 assume { :end_inline_reset_delta_events } true; 5852#L1053-2 [2023-11-06 22:33:13,702 INFO L750 eck$LassoCheckResult]: Loop: 5852#L1053-2 assume !false; 5853#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5828#L659-1 assume !false; 5817#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5818#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5820#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6086#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 6087#L570 assume !(0 != eval_~tmp~0#1); 5762#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5998#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5999#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5546#L689-3 assume !(0 == ~T2_E~0); 5547#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5606#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5607#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6093#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6078#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5891#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5599#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5600#L729-3 assume !(0 == ~E_3~0); 6057#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6099#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6100#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6182#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5613#L334-24 assume !(1 == ~m_pc~0); 5614#L334-26 is_master_triggered_~__retres1~0#1 := 0; 5753#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5778#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5583#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5584#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6094#L353-24 assume !(1 == ~t1_pc~0); 6096#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 6124#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6214#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6215#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5630#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5631#L372-24 assume 1 == ~t2_pc~0; 5592#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5593#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5952#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6201#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6202#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5921#L391-24 assume !(1 == ~t3_pc~0); 5922#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 6137#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6097#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6008#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 5983#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5816#L410-24 assume 1 == ~t4_pc~0; 5754#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5680#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6117#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5862#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5708#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5709#L429-24 assume !(1 == ~t5_pc~0); 5812#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 6012#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5984#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5758#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5759#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5703#L448-24 assume 1 == ~t6_pc~0; 5704#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5697#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5698#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5873#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6015#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6016#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5981#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5982#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6220#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6210#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5690#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5691#L787-3 assume !(1 == ~T6_E~0); 6125#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5918#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5919#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6164#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6050#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6051#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6131#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6121#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5945#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5590#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6037#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6038#L1072 assume !(0 == start_simulation_~tmp~3#1); 5833#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5834#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5699#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5653#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 5620#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5621#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6196#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6134#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 5852#L1053-2 [2023-11-06 22:33:13,703 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1976905477, now seen corresponding path program 1 times [2023-11-06 22:33:13,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085286085] [2023-11-06 22:33:13,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085286085] [2023-11-06 22:33:13,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085286085] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,764 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [938196684] [2023-11-06 22:33:13,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,765 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:13,766 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,766 INFO L85 PathProgramCache]: Analyzing trace with hash 1506177977, now seen corresponding path program 1 times [2023-11-06 22:33:13,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212707064] [2023-11-06 22:33:13,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,832 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212707064] [2023-11-06 22:33:13,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212707064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,833 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672835437] [2023-11-06 22:33:13,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:13,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:13,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:13,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:13,835 INFO L87 Difference]: Start difference. First operand 688 states and 1023 transitions. cyclomatic complexity: 336 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:13,856 INFO L93 Difference]: Finished difference Result 688 states and 1022 transitions. [2023-11-06 22:33:13,857 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1022 transitions. [2023-11-06 22:33:13,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,870 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1022 transitions. [2023-11-06 22:33:13,870 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:13,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:13,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1022 transitions. [2023-11-06 22:33:13,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:13,873 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-06 22:33:13,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1022 transitions. [2023-11-06 22:33:13,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:13,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4854651162790697) internal successors, (1022), 687 states have internal predecessors, (1022), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:13,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1022 transitions. [2023-11-06 22:33:13,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-06 22:33:13,890 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:13,895 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1022 transitions. [2023-11-06 22:33:13,895 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-06 22:33:13,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1022 transitions. [2023-11-06 22:33:13,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:13,900 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:13,900 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:13,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:13,903 INFO L748 eck$LassoCheckResult]: Stem: 7319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 7320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 7445#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7446#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7113#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 7114#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7443#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7444#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7375#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7169#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7170#L500-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7091#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7092#L684 assume !(0 == ~M_E~0); 7545#L684-2 assume !(0 == ~T1_E~0); 7404#L689-1 assume !(0 == ~T2_E~0); 7405#L694-1 assume !(0 == ~T3_E~0); 7402#L699-1 assume !(0 == ~T4_E~0); 7403#L704-1 assume !(0 == ~T5_E~0); 7360#L709-1 assume !(0 == ~T6_E~0); 7299#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 7300#L719-1 assume !(0 == ~E_1~0); 7519#L724-1 assume !(0 == ~E_2~0); 7065#L729-1 assume !(0 == ~E_3~0); 7066#L734-1 assume !(0 == ~E_4~0); 7572#L739-1 assume !(0 == ~E_5~0); 7262#L744-1 assume !(0 == ~E_6~0); 7263#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7022#L334 assume !(1 == ~m_pc~0); 7023#L334-2 is_master_triggered_~__retres1~0#1 := 0; 7352#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7264#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7233#L849 assume !(0 != activate_threads_~tmp~1#1); 7234#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7166#L353 assume 1 == ~t1_pc~0; 7167#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7449#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7037#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7038#L857 assume !(0 != activate_threads_~tmp___0~0#1); 7118#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7119#L372 assume !(1 == ~t2_pc~0); 7222#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7221#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7347#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7450#L865 assume !(0 != activate_threads_~tmp___1~0#1); 7011#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7012#L391 assume 1 == ~t3_pc~0; 7554#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6934#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6960#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6961#L873 assume !(0 != activate_threads_~tmp___2~0#1); 7240#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7241#L410 assume 1 == ~t4_pc~0; 7562#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7463#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7132#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7133#L881 assume !(0 != activate_threads_~tmp___3~0#1); 7246#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L429 assume !(1 == ~t5_pc~0); 7071#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7072#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7275#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7276#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7467#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7232#L448 assume 1 == ~t6_pc~0; 7106#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7107#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7433#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7434#L897 assume !(0 != activate_threads_~tmp___5~0#1); 7591#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7614#L762 assume !(1 == ~M_E~0); 7279#L762-2 assume !(1 == ~T1_E~0); 7280#L767-1 assume !(1 == ~T2_E~0); 7596#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7495#L777-1 assume !(1 == ~T4_E~0); 7390#L782-1 assume !(1 == ~T5_E~0); 7097#L787-1 assume !(1 == ~T6_E~0); 7095#L792-1 assume !(1 == ~E_M~0); 7096#L797-1 assume !(1 == ~E_1~0); 7137#L802-1 assume !(1 == ~E_2~0); 7356#L807-1 assume !(1 == ~E_3~0); 7357#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L817-1 assume !(1 == ~E_5~0); 7406#L822-1 assume !(1 == ~E_6~0); 7407#L827-1 assume { :end_inline_reset_delta_events } true; 7235#L1053-2 [2023-11-06 22:33:13,903 INFO L750 eck$LassoCheckResult]: Loop: 7235#L1053-2 assume !false; 7236#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7211#L659-1 assume !false; 7200#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7201#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7203#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7469#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7470#L570 assume !(0 != eval_~tmp~0#1); 7143#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7144#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7379#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7380#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6929#L689-3 assume !(0 == ~T2_E~0); 6930#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6989#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6990#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7476#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7459#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7269#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6982#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6983#L729-3 assume !(0 == ~E_3~0); 7439#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7482#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7483#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7565#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6996#L334-24 assume !(1 == ~m_pc~0); 6997#L334-26 is_master_triggered_~__retres1~0#1 := 0; 7136#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7161#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6966#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6967#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7478#L353-24 assume 1 == ~t1_pc~0; 7479#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7507#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7597#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7598#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7013#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7014#L372-24 assume !(1 == ~t2_pc~0); 6977#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6976#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7335#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7585#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7586#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7304#L391-24 assume !(1 == ~t3_pc~0); 7305#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7520#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7481#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7391#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 7369#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7199#L410-24 assume 1 == ~t4_pc~0; 7138#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7063#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7500#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7245#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7093#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7094#L429-24 assume !(1 == ~t5_pc~0); 7195#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 7395#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7370#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7141#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7142#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7088#L448-24 assume 1 == ~t6_pc~0; 7089#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7080#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7081#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7256#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7398#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7399#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7364#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7365#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7603#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7593#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7073#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7074#L787-3 assume !(1 == ~T6_E~0); 7508#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7301#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7302#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7547#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7435#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7436#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7514#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7504#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7328#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6973#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7420#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 7421#L1072 assume !(0 == start_simulation_~tmp~3#1); 7216#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7217#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7082#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7036#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 7003#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7004#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7579#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 7517#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 7235#L1053-2 [2023-11-06 22:33:13,904 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,904 INFO L85 PathProgramCache]: Analyzing trace with hash 242801027, now seen corresponding path program 1 times [2023-11-06 22:33:13,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [829187518] [2023-11-06 22:33:13,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:13,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:13,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:13,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [829187518] [2023-11-06 22:33:13,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [829187518] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:13,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:13,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:13,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [516950411] [2023-11-06 22:33:13,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:13,953 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:13,953 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:13,953 INFO L85 PathProgramCache]: Analyzing trace with hash 1169516665, now seen corresponding path program 1 times [2023-11-06 22:33:13,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:13,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [431467530] [2023-11-06 22:33:13,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:13,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:13,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:14,021 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:14,021 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:14,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [431467530] [2023-11-06 22:33:14,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [431467530] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:14,022 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:14,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:14,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412145965] [2023-11-06 22:33:14,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:14,045 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:14,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:14,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:14,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:14,046 INFO L87 Difference]: Start difference. First operand 688 states and 1022 transitions. cyclomatic complexity: 335 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:14,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:14,068 INFO L93 Difference]: Finished difference Result 688 states and 1021 transitions. [2023-11-06 22:33:14,068 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 688 states and 1021 transitions. [2023-11-06 22:33:14,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:14,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 688 states to 688 states and 1021 transitions. [2023-11-06 22:33:14,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-06 22:33:14,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-06 22:33:14,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 688 states and 1021 transitions. [2023-11-06 22:33:14,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:14,083 INFO L218 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-06 22:33:14,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 688 states and 1021 transitions. [2023-11-06 22:33:14,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 688 to 688. [2023-11-06 22:33:14,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 688 states, 688 states have (on average 1.4840116279069768) internal successors, (1021), 687 states have internal predecessors, (1021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:14,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 688 states to 688 states and 1021 transitions. [2023-11-06 22:33:14,098 INFO L240 hiAutomatonCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-06 22:33:14,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:14,100 INFO L428 stractBuchiCegarLoop]: Abstraction has 688 states and 1021 transitions. [2023-11-06 22:33:14,100 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-06 22:33:14,100 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 688 states and 1021 transitions. [2023-11-06 22:33:14,105 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 597 [2023-11-06 22:33:14,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:14,108 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:14,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:14,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:14,110 INFO L748 eck$LassoCheckResult]: Stem: 8702#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 8703#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8496#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 8497#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8826#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8827#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8758#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8552#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8553#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8474#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8475#L684 assume !(0 == ~M_E~0); 8928#L684-2 assume !(0 == ~T1_E~0); 8787#L689-1 assume !(0 == ~T2_E~0); 8788#L694-1 assume !(0 == ~T3_E~0); 8785#L699-1 assume !(0 == ~T4_E~0); 8786#L704-1 assume !(0 == ~T5_E~0); 8743#L709-1 assume !(0 == ~T6_E~0); 8682#L714-1 assume 0 == ~E_M~0;~E_M~0 := 1; 8683#L719-1 assume !(0 == ~E_1~0); 8902#L724-1 assume !(0 == ~E_2~0); 8448#L729-1 assume !(0 == ~E_3~0); 8449#L734-1 assume !(0 == ~E_4~0); 8955#L739-1 assume !(0 == ~E_5~0); 8645#L744-1 assume !(0 == ~E_6~0); 8646#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8405#L334 assume !(1 == ~m_pc~0); 8406#L334-2 is_master_triggered_~__retres1~0#1 := 0; 8735#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8647#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8616#L849 assume !(0 != activate_threads_~tmp~1#1); 8617#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8549#L353 assume 1 == ~t1_pc~0; 8550#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8832#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8421#L857 assume !(0 != activate_threads_~tmp___0~0#1); 8501#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8502#L372 assume !(1 == ~t2_pc~0); 8605#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8604#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8730#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8833#L865 assume !(0 != activate_threads_~tmp___1~0#1); 8394#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8395#L391 assume 1 == ~t3_pc~0; 8937#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8317#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8343#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8344#L873 assume !(0 != activate_threads_~tmp___2~0#1); 8623#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8624#L410 assume 1 == ~t4_pc~0; 8946#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8846#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8515#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8516#L881 assume !(0 != activate_threads_~tmp___3~0#1); 8629#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8630#L429 assume !(1 == ~t5_pc~0); 8454#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8455#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8658#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8659#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8850#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8615#L448 assume 1 == ~t6_pc~0; 8489#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8490#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8818#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8819#L897 assume !(0 != activate_threads_~tmp___5~0#1); 8974#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8997#L762 assume !(1 == ~M_E~0); 8662#L762-2 assume !(1 == ~T1_E~0); 8663#L767-1 assume !(1 == ~T2_E~0); 8979#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8878#L777-1 assume !(1 == ~T4_E~0); 8773#L782-1 assume !(1 == ~T5_E~0); 8480#L787-1 assume !(1 == ~T6_E~0); 8478#L792-1 assume !(1 == ~E_M~0); 8479#L797-1 assume !(1 == ~E_1~0); 8520#L802-1 assume !(1 == ~E_2~0); 8739#L807-1 assume !(1 == ~E_3~0); 8740#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8950#L817-1 assume !(1 == ~E_5~0); 8791#L822-1 assume !(1 == ~E_6~0); 8792#L827-1 assume { :end_inline_reset_delta_events } true; 8618#L1053-2 [2023-11-06 22:33:14,111 INFO L750 eck$LassoCheckResult]: Loop: 8618#L1053-2 assume !false; 8619#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8594#L659-1 assume !false; 8583#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8584#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8586#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8853#L570 assume !(0 != eval_~tmp~0#1); 8526#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8527#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8764#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8765#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8312#L689-3 assume !(0 == ~T2_E~0); 8313#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8372#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8373#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8859#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8842#L714-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8652#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8365#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8366#L729-3 assume !(0 == ~E_3~0); 8822#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8865#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8866#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8948#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8379#L334-24 assume !(1 == ~m_pc~0); 8380#L334-26 is_master_triggered_~__retres1~0#1 := 0; 8519#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8544#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8349#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8350#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8861#L353-24 assume 1 == ~t1_pc~0; 8862#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8890#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8980#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8981#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8396#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8397#L372-24 assume 1 == ~t2_pc~0; 8358#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8359#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8718#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8968#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8969#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8687#L391-24 assume !(1 == ~t3_pc~0); 8688#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 8903#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8864#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8774#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 8753#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8582#L410-24 assume 1 == ~t4_pc~0; 8521#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8446#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8883#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8628#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8476#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8477#L429-24 assume !(1 == ~t5_pc~0); 8578#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 8778#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8749#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8522#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8523#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8468#L448-24 assume 1 == ~t6_pc~0; 8469#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8463#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8464#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8639#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8781#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8782#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8747#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8748#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8986#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8976#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8456#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8457#L787-3 assume !(1 == ~T6_E~0); 8891#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8684#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8685#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8930#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8816#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8817#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8897#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8887#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8710#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8354#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8803#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8804#L1072 assume !(0 == start_simulation_~tmp~3#1); 8599#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8600#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 8465#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8419#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 8384#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8385#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8962#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8900#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 8618#L1053-2 [2023-11-06 22:33:14,111 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:14,111 INFO L85 PathProgramCache]: Analyzing trace with hash -644421819, now seen corresponding path program 1 times [2023-11-06 22:33:14,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:14,112 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511448645] [2023-11-06 22:33:14,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:14,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:14,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:14,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:14,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:14,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511448645] [2023-11-06 22:33:14,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511448645] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:14,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:14,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:14,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175884799] [2023-11-06 22:33:14,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:14,197 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:14,198 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:14,198 INFO L85 PathProgramCache]: Analyzing trace with hash 929249336, now seen corresponding path program 2 times [2023-11-06 22:33:14,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:14,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1924356774] [2023-11-06 22:33:14,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:14,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:14,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:14,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:14,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:14,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1924356774] [2023-11-06 22:33:14,247 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1924356774] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:14,247 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:14,247 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:14,247 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1016786158] [2023-11-06 22:33:14,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:14,248 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:14,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:14,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:14,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:14,249 INFO L87 Difference]: Start difference. First operand 688 states and 1021 transitions. cyclomatic complexity: 334 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:14,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:14,449 INFO L93 Difference]: Finished difference Result 1184 states and 1752 transitions. [2023-11-06 22:33:14,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1184 states and 1752 transitions. [2023-11-06 22:33:14,459 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2023-11-06 22:33:14,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1184 states to 1184 states and 1752 transitions. [2023-11-06 22:33:14,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1184 [2023-11-06 22:33:14,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1184 [2023-11-06 22:33:14,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1184 states and 1752 transitions. [2023-11-06 22:33:14,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:14,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1184 states and 1752 transitions. [2023-11-06 22:33:14,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1184 states and 1752 transitions. [2023-11-06 22:33:14,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1184 to 1183. [2023-11-06 22:33:14,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1183 states, 1183 states have (on average 1.4801352493660187) internal successors, (1751), 1182 states have internal predecessors, (1751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:14,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1183 states to 1183 states and 1751 transitions. [2023-11-06 22:33:14,503 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2023-11-06 22:33:14,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:14,507 INFO L428 stractBuchiCegarLoop]: Abstraction has 1183 states and 1751 transitions. [2023-11-06 22:33:14,507 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-06 22:33:14,507 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1183 states and 1751 transitions. [2023-11-06 22:33:14,520 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1078 [2023-11-06 22:33:14,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:14,521 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:14,522 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:14,522 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:14,523 INFO L748 eck$LassoCheckResult]: Stem: 10586#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 10587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 10718#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10719#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10380#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 10381#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10716#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10717#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10646#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10436#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10437#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10357#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10358#L684 assume !(0 == ~M_E~0); 10823#L684-2 assume !(0 == ~T1_E~0); 10676#L689-1 assume !(0 == ~T2_E~0); 10677#L694-1 assume !(0 == ~T3_E~0); 10674#L699-1 assume !(0 == ~T4_E~0); 10675#L704-1 assume !(0 == ~T5_E~0); 10631#L709-1 assume !(0 == ~T6_E~0); 10566#L714-1 assume !(0 == ~E_M~0); 10567#L719-1 assume !(0 == ~E_1~0); 10795#L724-1 assume !(0 == ~E_2~0); 10331#L729-1 assume !(0 == ~E_3~0); 10332#L734-1 assume !(0 == ~E_4~0); 10851#L739-1 assume !(0 == ~E_5~0); 10529#L744-1 assume !(0 == ~E_6~0); 10530#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10287#L334 assume !(1 == ~m_pc~0); 10288#L334-2 is_master_triggered_~__retres1~0#1 := 0; 10623#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10531#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10500#L849 assume !(0 != activate_threads_~tmp~1#1); 10501#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10433#L353 assume 1 == ~t1_pc~0; 10434#L354 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10722#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10303#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10304#L857 assume !(0 != activate_threads_~tmp___0~0#1); 10385#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10386#L372 assume !(1 == ~t2_pc~0); 10489#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10488#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10617#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10723#L865 assume !(0 != activate_threads_~tmp___1~0#1); 10276#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10277#L391 assume 1 == ~t3_pc~0; 10832#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10199#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10226#L873 assume !(0 != activate_threads_~tmp___2~0#1); 10507#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10508#L410 assume 1 == ~t4_pc~0; 10840#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10736#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10400#L881 assume !(0 != activate_threads_~tmp___3~0#1); 10513#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10514#L429 assume !(1 == ~t5_pc~0); 10337#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10338#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10542#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10543#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10741#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10499#L448 assume 1 == ~t6_pc~0; 10373#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10374#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10706#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10707#L897 assume !(0 != activate_threads_~tmp___5~0#1); 10872#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10899#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 10546#L762-2 assume !(1 == ~T1_E~0); 10547#L767-1 assume !(1 == ~T2_E~0); 10977#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10974#L777-1 assume !(1 == ~T4_E~0); 10972#L782-1 assume !(1 == ~T5_E~0); 10970#L787-1 assume !(1 == ~T6_E~0); 10968#L792-1 assume !(1 == ~E_M~0); 10362#L797-1 assume !(1 == ~E_1~0); 10963#L802-1 assume !(1 == ~E_2~0); 10961#L807-1 assume !(1 == ~E_3~0); 10959#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10958#L817-1 assume !(1 == ~E_5~0); 10942#L822-1 assume !(1 == ~E_6~0); 10934#L827-1 assume { :end_inline_reset_delta_events } true; 10929#L1053-2 [2023-11-06 22:33:14,523 INFO L750 eck$LassoCheckResult]: Loop: 10929#L1053-2 assume !false; 10842#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10478#L659-1 assume !false; 10467#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10468#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10470#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10743#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 10744#L570 assume !(0 != eval_~tmp~0#1); 10788#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10907#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10908#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11370#L689-3 assume !(0 == ~T2_E~0); 11369#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11368#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11367#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11366#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11365#L714-3 assume !(0 == ~E_M~0); 11364#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11363#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11362#L729-3 assume !(0 == ~E_3~0); 11361#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11360#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11359#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11358#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11357#L334-24 assume !(1 == ~m_pc~0); 11355#L334-26 is_master_triggered_~__retres1~0#1 := 0; 11354#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11353#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11352#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11351#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11350#L353-24 assume 1 == ~t1_pc~0; 11348#L354-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11347#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11346#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11345#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11344#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11343#L372-24 assume !(1 == ~t2_pc~0); 11341#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11340#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11339#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11338#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11337#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11336#L391-24 assume 1 == ~t3_pc~0; 11334#L392-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11333#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11332#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11331#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 11330#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11329#L410-24 assume !(1 == ~t4_pc~0); 11328#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 11326#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11325#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11324#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11323#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11322#L429-24 assume !(1 == ~t5_pc~0); 11320#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 11318#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11315#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11313#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11311#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11309#L448-24 assume 1 == ~t6_pc~0; 11306#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11304#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11301#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11299#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11297#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11296#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10854#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11295#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11294#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11293#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11292#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11291#L787-3 assume !(1 == ~T6_E~0); 11290#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10783#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11289#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11288#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10708#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10709#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10790#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10778#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10597#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10238#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10692#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 10693#L1072 assume !(0 == start_simulation_~tmp~3#1); 10483#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 10484#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 10348#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 10301#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 10302#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10978#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10943#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 10935#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 10929#L1053-2 [2023-11-06 22:33:14,524 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:14,524 INFO L85 PathProgramCache]: Analyzing trace with hash -1050737979, now seen corresponding path program 1 times [2023-11-06 22:33:14,524 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:14,524 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957775926] [2023-11-06 22:33:14,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:14,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:14,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:14,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:14,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:14,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957775926] [2023-11-06 22:33:14,599 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957775926] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:14,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:14,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:14,604 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1151783060] [2023-11-06 22:33:14,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:14,605 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:14,605 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:14,606 INFO L85 PathProgramCache]: Analyzing trace with hash -1871021509, now seen corresponding path program 1 times [2023-11-06 22:33:14,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:14,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [690452304] [2023-11-06 22:33:14,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:14,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:14,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:14,661 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:14,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:14,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [690452304] [2023-11-06 22:33:14,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [690452304] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:14,663 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:14,663 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:14,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [703281288] [2023-11-06 22:33:14,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:14,664 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:14,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:14,665 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:14,665 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:14,665 INFO L87 Difference]: Start difference. First operand 1183 states and 1751 transitions. cyclomatic complexity: 570 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:14,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:14,946 INFO L93 Difference]: Finished difference Result 3165 states and 4601 transitions. [2023-11-06 22:33:14,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3165 states and 4601 transitions. [2023-11-06 22:33:14,982 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2950 [2023-11-06 22:33:15,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3165 states to 3165 states and 4601 transitions. [2023-11-06 22:33:15,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3165 [2023-11-06 22:33:15,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3165 [2023-11-06 22:33:15,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3165 states and 4601 transitions. [2023-11-06 22:33:15,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:15,022 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3165 states and 4601 transitions. [2023-11-06 22:33:15,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3165 states and 4601 transitions. [2023-11-06 22:33:15,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3165 to 2977. [2023-11-06 22:33:15,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2977 states, 2977 states have (on average 1.4595230097413503) internal successors, (4345), 2976 states have internal predecessors, (4345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:15,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2977 states to 2977 states and 4345 transitions. [2023-11-06 22:33:15,114 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2977 states and 4345 transitions. [2023-11-06 22:33:15,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:15,115 INFO L428 stractBuchiCegarLoop]: Abstraction has 2977 states and 4345 transitions. [2023-11-06 22:33:15,115 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-06 22:33:15,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2977 states and 4345 transitions. [2023-11-06 22:33:15,137 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2864 [2023-11-06 22:33:15,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:15,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:15,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:15,140 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:15,140 INFO L748 eck$LassoCheckResult]: Stem: 14961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 14962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 15122#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15123#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14739#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 14740#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15120#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15121#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15025#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14796#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14797#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14717#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14718#L684 assume !(0 == ~M_E~0); 15249#L684-2 assume !(0 == ~T1_E~0); 15067#L689-1 assume !(0 == ~T2_E~0); 15068#L694-1 assume !(0 == ~T3_E~0); 15065#L699-1 assume !(0 == ~T4_E~0); 15066#L704-1 assume !(0 == ~T5_E~0); 15007#L709-1 assume !(0 == ~T6_E~0); 14939#L714-1 assume !(0 == ~E_M~0); 14940#L719-1 assume !(0 == ~E_1~0); 15216#L724-1 assume !(0 == ~E_2~0); 14686#L729-1 assume !(0 == ~E_3~0); 14687#L734-1 assume !(0 == ~E_4~0); 15298#L739-1 assume !(0 == ~E_5~0); 14899#L744-1 assume !(0 == ~E_6~0); 14900#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14643#L334 assume !(1 == ~m_pc~0); 14644#L334-2 is_master_triggered_~__retres1~0#1 := 0; 14998#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14901#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14868#L849 assume !(0 != activate_threads_~tmp~1#1); 14869#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14794#L353 assume !(1 == ~t1_pc~0); 14795#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15126#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14657#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14658#L857 assume !(0 != activate_threads_~tmp___0~0#1); 14745#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14746#L372 assume !(1 == ~t2_pc~0); 14855#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14854#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14992#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15127#L865 assume !(0 != activate_threads_~tmp___1~0#1); 14632#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14633#L391 assume 1 == ~t3_pc~0; 15260#L392 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14557#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14582#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14583#L873 assume !(0 != activate_threads_~tmp___2~0#1); 14875#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14876#L410 assume 1 == ~t4_pc~0; 15279#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15144#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14759#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14760#L881 assume !(0 != activate_threads_~tmp___3~0#1); 14881#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14882#L429 assume !(1 == ~t5_pc~0); 14692#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 14693#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14913#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14914#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15152#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14865#L448 assume 1 == ~t6_pc~0; 14732#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 14733#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15103#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15104#L897 assume !(0 != activate_threads_~tmp___5~0#1); 15331#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15405#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 14918#L762-2 assume !(1 == ~T1_E~0); 14919#L767-1 assume !(1 == ~T2_E~0); 15343#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15182#L777-1 assume !(1 == ~T4_E~0); 15046#L782-1 assume !(1 == ~T5_E~0); 14723#L787-1 assume !(1 == ~T6_E~0); 14721#L792-1 assume !(1 == ~E_M~0); 14722#L797-1 assume !(1 == ~E_1~0); 14764#L802-1 assume !(1 == ~E_2~0); 15002#L807-1 assume !(1 == ~E_3~0); 15003#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15292#L817-1 assume !(1 == ~E_5~0); 15069#L822-1 assume !(1 == ~E_6~0); 15070#L827-1 assume { :end_inline_reset_delta_events } true; 15304#L1053-2 [2023-11-06 22:33:15,141 INFO L750 eck$LassoCheckResult]: Loop: 15304#L1053-2 assume !false; 15930#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15927#L659-1 assume !false; 15893#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15894#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15848#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15846#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 15844#L570 assume !(0 != eval_~tmp~0#1); 14770#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14771#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15301#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17160#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17069#L689-3 assume !(0 == ~T2_E~0); 14916#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14611#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14612#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15163#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15140#L714-3 assume !(0 == ~E_M~0); 14907#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14602#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14603#L729-3 assume !(0 == ~E_3~0); 16314#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16313#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15333#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15334#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14618#L334-24 assume !(1 == ~m_pc~0); 14619#L334-26 is_master_triggered_~__retres1~0#1 := 0; 14763#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16310#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 14588#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14589#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15166#L353-24 assume !(1 == ~t1_pc~0); 15167#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 15399#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15346#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15347#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16306#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14700#L372-24 assume 1 == ~t2_pc~0; 14701#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16302#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15426#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15325#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15326#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14944#L391-24 assume !(1 == ~t3_pc~0); 14945#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 15217#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15168#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15047#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 15016#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14828#L410-24 assume !(1 == ~t4_pc~0); 14683#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14684#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15190#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14880#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14719#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14720#L429-24 assume !(1 == ~t5_pc~0); 14825#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 15053#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15915#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15911#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15908#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15905#L448-24 assume 1 == ~t6_pc~0; 15901#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15890#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15887#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15885#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15883#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15881#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15879#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15877#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15874#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15824#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15814#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15810#L787-3 assume !(1 == ~T6_E~0); 15803#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15798#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15794#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15788#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15782#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15485#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15486#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15481#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15482#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17268#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17267#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 15389#L1072 assume !(0 == start_simulation_~tmp~3#1); 15390#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 15984#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 15979#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 15965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 15958#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15953#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15949#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 15942#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 15304#L1053-2 [2023-11-06 22:33:15,141 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:15,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1143388102, now seen corresponding path program 1 times [2023-11-06 22:33:15,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:15,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913648681] [2023-11-06 22:33:15,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:15,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:15,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:15,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:15,223 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:15,224 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913648681] [2023-11-06 22:33:15,224 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913648681] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:15,224 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:15,224 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:15,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651614147] [2023-11-06 22:33:15,225 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:15,225 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:15,225 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:15,225 INFO L85 PathProgramCache]: Analyzing trace with hash 659765884, now seen corresponding path program 1 times [2023-11-06 22:33:15,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:15,226 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583455780] [2023-11-06 22:33:15,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:15,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:15,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:15,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:15,284 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:15,284 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583455780] [2023-11-06 22:33:15,285 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583455780] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:15,285 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:15,285 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:15,285 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096740210] [2023-11-06 22:33:15,285 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:15,286 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:15,286 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:15,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:15,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:15,287 INFO L87 Difference]: Start difference. First operand 2977 states and 4345 transitions. cyclomatic complexity: 1372 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:15,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:15,529 INFO L93 Difference]: Finished difference Result 8168 states and 11776 transitions. [2023-11-06 22:33:15,529 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8168 states and 11776 transitions. [2023-11-06 22:33:15,597 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7806 [2023-11-06 22:33:15,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8168 states to 8168 states and 11776 transitions. [2023-11-06 22:33:15,667 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8168 [2023-11-06 22:33:15,676 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8168 [2023-11-06 22:33:15,677 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8168 states and 11776 transitions. [2023-11-06 22:33:15,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:15,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8168 states and 11776 transitions. [2023-11-06 22:33:15,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8168 states and 11776 transitions. [2023-11-06 22:33:15,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8168 to 7764. [2023-11-06 22:33:15,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7764 states, 7764 states have (on average 1.447449768160742) internal successors, (11238), 7763 states have internal predecessors, (11238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:16,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7764 states to 7764 states and 11238 transitions. [2023-11-06 22:33:16,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7764 states and 11238 transitions. [2023-11-06 22:33:16,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:16,014 INFO L428 stractBuchiCegarLoop]: Abstraction has 7764 states and 11238 transitions. [2023-11-06 22:33:16,014 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-06 22:33:16,015 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7764 states and 11238 transitions. [2023-11-06 22:33:16,050 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7632 [2023-11-06 22:33:16,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:16,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:16,052 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:16,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:16,053 INFO L748 eck$LassoCheckResult]: Stem: 26108#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 26109#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 26247#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26248#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25892#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 25893#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26245#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26246#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26167#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25948#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25949#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25869#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25870#L684 assume !(0 == ~M_E~0); 26379#L684-2 assume !(0 == ~T1_E~0); 26203#L689-1 assume !(0 == ~T2_E~0); 26204#L694-1 assume !(0 == ~T3_E~0); 26201#L699-1 assume !(0 == ~T4_E~0); 26202#L704-1 assume !(0 == ~T5_E~0); 26152#L709-1 assume !(0 == ~T6_E~0); 26089#L714-1 assume !(0 == ~E_M~0); 26090#L719-1 assume !(0 == ~E_1~0); 26344#L724-1 assume !(0 == ~E_2~0); 25843#L729-1 assume !(0 == ~E_3~0); 25844#L734-1 assume !(0 == ~E_4~0); 26419#L739-1 assume !(0 == ~E_5~0); 26049#L744-1 assume !(0 == ~E_6~0); 26050#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25799#L334 assume !(1 == ~m_pc~0); 25800#L334-2 is_master_triggered_~__retres1~0#1 := 0; 26144#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26051#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 26018#L849 assume !(0 != activate_threads_~tmp~1#1); 26019#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25946#L353 assume !(1 == ~t1_pc~0); 25947#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 26251#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25814#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25815#L857 assume !(0 != activate_threads_~tmp___0~0#1); 25897#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25898#L372 assume !(1 == ~t2_pc~0); 26005#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 26004#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 26252#L865 assume !(0 != activate_threads_~tmp___1~0#1); 25788#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25789#L391 assume !(1 == ~t3_pc~0); 25711#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25712#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25737#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25738#L873 assume !(0 != activate_threads_~tmp___2~0#1); 26025#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26026#L410 assume 1 == ~t4_pc~0; 26406#L411 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26267#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25912#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25913#L881 assume !(0 != activate_threads_~tmp___3~0#1); 26032#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26033#L429 assume !(1 == ~t5_pc~0); 25849#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25850#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26062#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 26063#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26274#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26015#L448 assume 1 == ~t6_pc~0; 25885#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25886#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26232#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 26233#L897 assume !(0 != activate_threads_~tmp___5~0#1); 26446#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26513#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 26069#L762-2 assume !(1 == ~T1_E~0); 26070#L767-1 assume !(1 == ~T2_E~0); 26455#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26456#L777-1 assume !(1 == ~T4_E~0); 26184#L782-1 assume !(1 == ~T5_E~0); 26185#L787-1 assume !(1 == ~T6_E~0); 25873#L792-1 assume !(1 == ~E_M~0); 25874#L797-1 assume !(1 == ~E_1~0); 25917#L802-1 assume !(1 == ~E_2~0); 26148#L807-1 assume !(1 == ~E_3~0); 26149#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 26414#L817-1 assume !(1 == ~E_5~0); 26205#L822-1 assume !(1 == ~E_6~0); 26206#L827-1 assume { :end_inline_reset_delta_events } true; 26424#L1053-2 [2023-11-06 22:33:16,054 INFO L750 eck$LassoCheckResult]: Loop: 26424#L1053-2 assume !false; 29738#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29714#L659-1 assume !false; 29715#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29658#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29648#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29639#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 29632#L570 assume !(0 != eval_~tmp~0#1); 29633#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31214#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31084#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31083#L689-3 assume !(0 == ~T2_E~0); 31082#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31081#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31080#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31079#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31078#L714-3 assume !(0 == ~E_M~0); 31077#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31076#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31075#L729-3 assume !(0 == ~E_3~0); 31073#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31071#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31069#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31067#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31065#L334-24 assume !(1 == ~m_pc~0); 31063#L334-26 is_master_triggered_~__retres1~0#1 := 0; 31061#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31059#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 31057#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 31055#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 31053#L353-24 assume !(1 == ~t1_pc~0); 31051#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 31049#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31046#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 31044#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 31042#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31041#L372-24 assume 1 == ~t2_pc~0; 31040#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31038#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 31037#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 31036#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31035#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31034#L391-24 assume !(1 == ~t3_pc~0); 31033#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 31032#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31031#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 31030#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 31029#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31028#L410-24 assume 1 == ~t4_pc~0; 31026#L411-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31025#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30446#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30447#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30368#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30369#L429-24 assume !(1 == ~t5_pc~0); 30363#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 30360#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30359#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30358#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 30357#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30356#L448-24 assume 1 == ~t6_pc~0; 30354#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30353#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 30301#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30300#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30299#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30298#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28458#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30297#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30296#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30294#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30292#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30290#L787-3 assume !(1 == ~T6_E~0); 30288#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28442#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30284#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30282#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30280#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30278#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30276#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30272#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 30273#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29843#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29844#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 29834#L1072 assume !(0 == start_simulation_~tmp~3#1); 29833#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 29822#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29813#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29810#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 29808#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29806#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29804#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 29802#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 26424#L1053-2 [2023-11-06 22:33:16,054 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:16,054 INFO L85 PathProgramCache]: Analyzing trace with hash 186459719, now seen corresponding path program 1 times [2023-11-06 22:33:16,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:16,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531937989] [2023-11-06 22:33:16,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:16,055 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:16,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:16,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:16,118 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:16,118 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531937989] [2023-11-06 22:33:16,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531937989] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:16,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:16,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:33:16,119 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792494207] [2023-11-06 22:33:16,119 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:16,120 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:16,121 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:16,121 INFO L85 PathProgramCache]: Analyzing trace with hash 1533243579, now seen corresponding path program 1 times [2023-11-06 22:33:16,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:16,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1341981073] [2023-11-06 22:33:16,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:16,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:16,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:16,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:16,167 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:16,167 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1341981073] [2023-11-06 22:33:16,167 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1341981073] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:16,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:16,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:16,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2050429110] [2023-11-06 22:33:16,168 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:16,168 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:16,168 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:16,169 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:16,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:16,169 INFO L87 Difference]: Start difference. First operand 7764 states and 11238 transitions. cyclomatic complexity: 3482 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:16,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:16,371 INFO L93 Difference]: Finished difference Result 14431 states and 20810 transitions. [2023-11-06 22:33:16,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14431 states and 20810 transitions. [2023-11-06 22:33:16,458 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14234 [2023-11-06 22:33:16,559 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14431 states to 14431 states and 20810 transitions. [2023-11-06 22:33:16,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14431 [2023-11-06 22:33:16,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14431 [2023-11-06 22:33:16,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14431 states and 20810 transitions. [2023-11-06 22:33:16,598 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:16,599 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14431 states and 20810 transitions. [2023-11-06 22:33:16,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14431 states and 20810 transitions. [2023-11-06 22:33:16,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14431 to 14395. [2023-11-06 22:33:16,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14395 states, 14395 states have (on average 1.4431399791594304) internal successors, (20774), 14394 states have internal predecessors, (20774), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:17,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14395 states to 14395 states and 20774 transitions. [2023-11-06 22:33:17,045 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14395 states and 20774 transitions. [2023-11-06 22:33:17,048 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:17,049 INFO L428 stractBuchiCegarLoop]: Abstraction has 14395 states and 20774 transitions. [2023-11-06 22:33:17,049 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-06 22:33:17,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14395 states and 20774 transitions. [2023-11-06 22:33:17,125 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14198 [2023-11-06 22:33:17,125 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:17,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:17,127 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:17,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:17,128 INFO L748 eck$LassoCheckResult]: Stem: 48309#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 48310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 48447#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48448#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48096#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 48097#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48445#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48446#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48368#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48153#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48154#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48073#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 48074#L684 assume !(0 == ~M_E~0); 48571#L684-2 assume !(0 == ~T1_E~0); 48403#L689-1 assume !(0 == ~T2_E~0); 48404#L694-1 assume !(0 == ~T3_E~0); 48401#L699-1 assume !(0 == ~T4_E~0); 48402#L704-1 assume !(0 == ~T5_E~0); 48354#L709-1 assume !(0 == ~T6_E~0); 48290#L714-1 assume !(0 == ~E_M~0); 48291#L719-1 assume !(0 == ~E_1~0); 48540#L724-1 assume !(0 == ~E_2~0); 48044#L729-1 assume !(0 == ~E_3~0); 48045#L734-1 assume !(0 == ~E_4~0); 48608#L739-1 assume !(0 == ~E_5~0); 48248#L744-1 assume !(0 == ~E_6~0); 48249#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48001#L334 assume !(1 == ~m_pc~0); 48002#L334-2 is_master_triggered_~__retres1~0#1 := 0; 48345#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48250#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 48219#L849 assume !(0 != activate_threads_~tmp~1#1); 48220#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48151#L353 assume !(1 == ~t1_pc~0); 48152#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 48451#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 48015#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 48016#L857 assume !(0 != activate_threads_~tmp___0~0#1); 48101#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 48102#L372 assume !(1 == ~t2_pc~0); 48206#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 48205#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 48340#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 48452#L865 assume !(0 != activate_threads_~tmp___1~0#1); 47990#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47991#L391 assume !(1 == ~t3_pc~0); 47913#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 47914#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47939#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 47940#L873 assume !(0 != activate_threads_~tmp___2~0#1); 48226#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48227#L410 assume !(1 == ~t4_pc~0); 48466#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 48467#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 48116#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 48117#L881 assume !(0 != activate_threads_~tmp___3~0#1); 48232#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 48233#L429 assume !(1 == ~t5_pc~0); 48050#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 48051#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 48263#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48264#L889 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 48476#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48216#L448 assume 1 == ~t6_pc~0; 48089#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 48090#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48434#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 48435#L897 assume !(0 != activate_threads_~tmp___5~0#1); 48636#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48686#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 48687#L762-2 assume !(1 == ~T1_E~0); 53234#L767-1 assume !(1 == ~T2_E~0); 53233#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 53232#L777-1 assume !(1 == ~T4_E~0); 53231#L782-1 assume !(1 == ~T5_E~0); 53230#L787-1 assume !(1 == ~T6_E~0); 53229#L792-1 assume !(1 == ~E_M~0); 48078#L797-1 assume !(1 == ~E_1~0); 53228#L802-1 assume !(1 == ~E_2~0); 53227#L807-1 assume !(1 == ~E_3~0); 53226#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 53223#L817-1 assume !(1 == ~E_5~0); 53219#L822-1 assume !(1 == ~E_6~0); 48613#L827-1 assume { :end_inline_reset_delta_events } true; 48614#L1053-2 [2023-11-06 22:33:17,129 INFO L750 eck$LassoCheckResult]: Loop: 48614#L1053-2 assume !false; 55178#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 55174#L659-1 assume !false; 55172#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 55166#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 55159#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 55157#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 55154#L570 assume !(0 != eval_~tmp~0#1); 55155#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56966#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56963#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 56961#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56960#L689-3 assume !(0 == ~T2_E~0); 55839#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55838#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55837#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55835#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 55832#L714-3 assume !(0 == ~E_M~0); 55830#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55828#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55826#L729-3 assume !(0 == ~E_3~0); 55824#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55822#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55819#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 55817#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55815#L334-24 assume !(1 == ~m_pc~0); 55813#L334-26 is_master_triggered_~__retres1~0#1 := 0; 55811#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55809#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 55806#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 55804#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55802#L353-24 assume !(1 == ~t1_pc~0); 55800#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 55798#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55796#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 55795#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55793#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55788#L372-24 assume !(1 == ~t2_pc~0); 55784#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 55780#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55775#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 55771#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 55767#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 55763#L391-24 assume !(1 == ~t3_pc~0); 55759#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 55755#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55752#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 55747#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 55743#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 55739#L410-24 assume !(1 == ~t4_pc~0); 55735#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 55731#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55726#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 55721#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55717#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55714#L429-24 assume !(1 == ~t5_pc~0); 55710#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 55706#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 55701#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 55697#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 55693#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 55689#L448-24 assume 1 == ~t6_pc~0; 55684#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 55679#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55674#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 55670#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 55666#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55662#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 53793#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55656#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55652#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55648#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 55644#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55640#L787-3 assume !(1 == ~T6_E~0); 55636#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53084#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55628#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55625#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 55621#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 55617#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55613#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 55580#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 55573#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 55569#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 55567#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 55565#L1072 assume !(0 == start_simulation_~tmp~3#1); 55560#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 55200#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 55193#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 55190#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 55187#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55185#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55183#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 55181#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 48614#L1053-2 [2023-11-06 22:33:17,129 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:17,129 INFO L85 PathProgramCache]: Analyzing trace with hash -1390098040, now seen corresponding path program 1 times [2023-11-06 22:33:17,130 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:17,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157029722] [2023-11-06 22:33:17,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:17,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:17,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:17,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:17,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:17,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157029722] [2023-11-06 22:33:17,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157029722] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:17,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:17,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:33:17,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215039513] [2023-11-06 22:33:17,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:17,324 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:17,324 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:17,324 INFO L85 PathProgramCache]: Analyzing trace with hash 900033213, now seen corresponding path program 1 times [2023-11-06 22:33:17,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:17,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608961292] [2023-11-06 22:33:17,325 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:17,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:17,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:17,370 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:17,370 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:17,370 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [608961292] [2023-11-06 22:33:17,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [608961292] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:17,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:17,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:17,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [523320086] [2023-11-06 22:33:17,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:17,372 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:17,372 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:17,372 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:33:17,372 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:33:17,373 INFO L87 Difference]: Start difference. First operand 14395 states and 20774 transitions. cyclomatic complexity: 6395 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:17,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:17,724 INFO L93 Difference]: Finished difference Result 29747 states and 42485 transitions. [2023-11-06 22:33:17,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29747 states and 42485 transitions. [2023-11-06 22:33:18,005 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 29406 [2023-11-06 22:33:18,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29747 states to 29747 states and 42485 transitions. [2023-11-06 22:33:18,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29747 [2023-11-06 22:33:18,239 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29747 [2023-11-06 22:33:18,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29747 states and 42485 transitions. [2023-11-06 22:33:18,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:18,271 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29747 states and 42485 transitions. [2023-11-06 22:33:18,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29747 states and 42485 transitions. [2023-11-06 22:33:18,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29747 to 15004. [2023-11-06 22:33:18,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15004 states, 15004 states have (on average 1.4251532924553452) internal successors, (21383), 15003 states have internal predecessors, (21383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:18,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15004 states to 15004 states and 21383 transitions. [2023-11-06 22:33:18,874 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15004 states and 21383 transitions. [2023-11-06 22:33:18,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:33:18,875 INFO L428 stractBuchiCegarLoop]: Abstraction has 15004 states and 21383 transitions. [2023-11-06 22:33:18,875 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-06 22:33:18,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15004 states and 21383 transitions. [2023-11-06 22:33:18,968 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 14804 [2023-11-06 22:33:18,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:18,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:18,971 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:18,971 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:18,971 INFO L748 eck$LassoCheckResult]: Stem: 92472#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 92473#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 92605#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 92606#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92254#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 92255#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92601#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92602#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92529#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92310#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 92311#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92230#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 92231#L684 assume !(0 == ~M_E~0); 92738#L684-2 assume !(0 == ~T1_E~0); 92562#L689-1 assume !(0 == ~T2_E~0); 92563#L694-1 assume !(0 == ~T3_E~0); 92560#L699-1 assume !(0 == ~T4_E~0); 92561#L704-1 assume !(0 == ~T5_E~0); 92516#L709-1 assume !(0 == ~T6_E~0); 92447#L714-1 assume !(0 == ~E_M~0); 92448#L719-1 assume !(0 == ~E_1~0); 92698#L724-1 assume !(0 == ~E_2~0); 92200#L729-1 assume !(0 == ~E_3~0); 92201#L734-1 assume !(0 == ~E_4~0); 92777#L739-1 assume !(0 == ~E_5~0); 92407#L744-1 assume !(0 == ~E_6~0); 92408#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 92156#L334 assume !(1 == ~m_pc~0); 92157#L334-2 is_master_triggered_~__retres1~0#1 := 0; 92506#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 92410#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 92377#L849 assume !(0 != activate_threads_~tmp~1#1); 92378#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 92306#L353 assume !(1 == ~t1_pc~0); 92307#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 92608#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 92170#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 92171#L857 assume !(0 != activate_threads_~tmp___0~0#1); 92256#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 92257#L372 assume !(1 == ~t2_pc~0); 92365#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92364#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 92500#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 92609#L865 assume !(0 != activate_threads_~tmp___1~0#1); 92145#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 92146#L391 assume !(1 == ~t3_pc~0); 92068#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 92069#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 92094#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 92095#L873 assume !(0 != activate_threads_~tmp___2~0#1); 92384#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 92385#L410 assume !(1 == ~t4_pc~0); 92623#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 92624#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 92270#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 92271#L881 assume !(0 != activate_threads_~tmp___3~0#1); 92394#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 92395#L429 assume !(1 == ~t5_pc~0); 92206#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 92207#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 92879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 92628#L889 assume !(0 != activate_threads_~tmp___4~0#1); 92629#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 92376#L448 assume 1 == ~t6_pc~0; 92244#L449 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 92245#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 92593#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 92594#L897 assume !(0 != activate_threads_~tmp___5~0#1); 92809#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92867#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 92428#L762-2 assume !(1 == ~T1_E~0); 92429#L767-1 assume !(1 == ~T2_E~0); 92815#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 92816#L777-1 assume !(1 == ~T4_E~0); 92545#L782-1 assume !(1 == ~T5_E~0); 92546#L787-1 assume !(1 == ~T6_E~0); 92232#L792-1 assume !(1 == ~E_M~0); 92233#L797-1 assume !(1 == ~E_1~0); 92714#L802-1 assume !(1 == ~E_2~0); 92715#L807-1 assume !(1 == ~E_3~0); 92773#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 92774#L817-1 assume !(1 == ~E_5~0); 92566#L822-1 assume !(1 == ~E_6~0); 92567#L827-1 assume { :end_inline_reset_delta_events } true; 96210#L1053-2 [2023-11-06 22:33:18,972 INFO L750 eck$LassoCheckResult]: Loop: 96210#L1053-2 assume !false; 96189#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96186#L659-1 assume !false; 96181#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96182#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96171#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96172#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 96166#L570 assume !(0 != eval_~tmp~0#1); 96168#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96963#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96964#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 96959#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96960#L689-3 assume !(0 == ~T2_E~0); 96955#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96956#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96951#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96952#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 96947#L714-3 assume !(0 == ~E_M~0); 96948#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96943#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96944#L729-3 assume !(0 == ~E_3~0); 96939#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96940#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96935#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 96936#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96931#L334-24 assume !(1 == ~m_pc~0); 96932#L334-26 is_master_triggered_~__retres1~0#1 := 0; 96927#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96928#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 96923#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96924#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96919#L353-24 assume !(1 == ~t1_pc~0); 96920#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 96916#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96917#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96912#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96913#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96907#L372-24 assume !(1 == ~t2_pc~0); 96909#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 96902#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96903#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96898#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 96899#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96894#L391-24 assume !(1 == ~t3_pc~0); 96895#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 96890#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96891#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96886#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 96887#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96882#L410-24 assume !(1 == ~t4_pc~0); 96883#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 96878#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96879#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96874#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96875#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96869#L429-24 assume 1 == ~t5_pc~0; 96871#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 96861#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96862#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96855#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 96621#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96613#L448-24 assume 1 == ~t6_pc~0; 96521#L449-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96509#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96500#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 96501#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96335#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96334#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 96330#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96328#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96325#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 96323#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96321#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96319#L787-3 assume !(1 == ~T6_E~0); 96317#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 96313#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 96311#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96309#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96307#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96305#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 96303#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 96299#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96300#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96285#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96286#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 96277#L1072 assume !(0 == start_simulation_~tmp~3#1); 96276#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96269#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96264#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96252#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 96253#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96232#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96233#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 104648#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 96210#L1053-2 [2023-11-06 22:33:18,973 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:18,973 INFO L85 PathProgramCache]: Analyzing trace with hash 1099430922, now seen corresponding path program 1 times [2023-11-06 22:33:18,973 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:18,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [596947868] [2023-11-06 22:33:18,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:18,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:19,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:19,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:19,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:19,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [596947868] [2023-11-06 22:33:19,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [596947868] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:19,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:19,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:19,162 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629312729] [2023-11-06 22:33:19,162 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:19,163 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:19,163 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:19,164 INFO L85 PathProgramCache]: Analyzing trace with hash 1856961596, now seen corresponding path program 1 times [2023-11-06 22:33:19,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:19,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588117173] [2023-11-06 22:33:19,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:19,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:19,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:19,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:19,262 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:19,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588117173] [2023-11-06 22:33:19,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588117173] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:19,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:19,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:19,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [681712314] [2023-11-06 22:33:19,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:19,264 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:19,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:19,265 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:19,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:19,265 INFO L87 Difference]: Start difference. First operand 15004 states and 21383 transitions. cyclomatic complexity: 6395 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:19,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:19,767 INFO L93 Difference]: Finished difference Result 42449 states and 59896 transitions. [2023-11-06 22:33:19,768 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42449 states and 59896 transitions. [2023-11-06 22:33:20,221 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41058 [2023-11-06 22:33:20,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42449 states to 42449 states and 59896 transitions. [2023-11-06 22:33:20,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42449 [2023-11-06 22:33:20,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42449 [2023-11-06 22:33:20,409 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42449 states and 59896 transitions. [2023-11-06 22:33:20,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:20,437 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42449 states and 59896 transitions. [2023-11-06 22:33:20,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42449 states and 59896 transitions. [2023-11-06 22:33:21,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42449 to 41265. [2023-11-06 22:33:21,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41265 states, 41265 states have (on average 1.415485278080698) internal successors, (58410), 41264 states have internal predecessors, (58410), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:21,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41265 states to 41265 states and 58410 transitions. [2023-11-06 22:33:21,457 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41265 states and 58410 transitions. [2023-11-06 22:33:21,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:21,458 INFO L428 stractBuchiCegarLoop]: Abstraction has 41265 states and 58410 transitions. [2023-11-06 22:33:21,458 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-06 22:33:21,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41265 states and 58410 transitions. [2023-11-06 22:33:21,596 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40914 [2023-11-06 22:33:21,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:21,597 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:21,598 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:21,598 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:21,599 INFO L748 eck$LassoCheckResult]: Stem: 149944#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 149945#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 150098#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 150099#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 149716#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 149717#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 150096#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 150097#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 150009#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 149779#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 149780#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 149694#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 149695#L684 assume !(0 == ~M_E~0); 150248#L684-2 assume !(0 == ~T1_E~0); 150052#L689-1 assume !(0 == ~T2_E~0); 150053#L694-1 assume !(0 == ~T3_E~0); 150050#L699-1 assume !(0 == ~T4_E~0); 150051#L704-1 assume !(0 == ~T5_E~0); 149990#L709-1 assume !(0 == ~T6_E~0); 149918#L714-1 assume !(0 == ~E_M~0); 149919#L719-1 assume !(0 == ~E_1~0); 150205#L724-1 assume !(0 == ~E_2~0); 149662#L729-1 assume !(0 == ~E_3~0); 149663#L734-1 assume !(0 == ~E_4~0); 150291#L739-1 assume !(0 == ~E_5~0); 149878#L744-1 assume !(0 == ~E_6~0); 149879#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 149617#L334 assume !(1 == ~m_pc~0); 149618#L334-2 is_master_triggered_~__retres1~0#1 := 0; 149979#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 149881#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 149846#L849 assume !(0 != activate_threads_~tmp~1#1); 149847#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 149775#L353 assume !(1 == ~t1_pc~0); 149776#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 150102#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 149631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 149632#L857 assume !(0 != activate_threads_~tmp___0~0#1); 149718#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 149719#L372 assume !(1 == ~t2_pc~0); 149833#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 149832#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 149973#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 150103#L865 assume !(0 != activate_threads_~tmp___1~0#1); 149606#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 149607#L391 assume !(1 == ~t3_pc~0); 149531#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 149532#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 149556#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 149557#L873 assume !(0 != activate_threads_~tmp___2~0#1); 149853#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 149854#L410 assume !(1 == ~t4_pc~0); 150119#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 150120#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 149735#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 149736#L881 assume !(0 != activate_threads_~tmp___3~0#1); 149864#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 149865#L429 assume !(1 == ~t5_pc~0); 149668#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 149669#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 149892#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 149893#L889 assume !(0 != activate_threads_~tmp___4~0#1); 150126#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 149845#L448 assume !(1 == ~t6_pc~0); 149758#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 149759#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 150088#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 150089#L897 assume !(0 != activate_threads_~tmp___5~0#1); 150325#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150385#L762 assume 1 == ~M_E~0;~M_E~0 := 2; 149899#L762-2 assume !(1 == ~T1_E~0); 149900#L767-1 assume !(1 == ~T2_E~0); 150331#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 150332#L777-1 assume !(1 == ~T4_E~0); 150030#L782-1 assume !(1 == ~T5_E~0); 150031#L787-1 assume !(1 == ~T6_E~0); 149696#L792-1 assume !(1 == ~E_M~0); 149697#L797-1 assume !(1 == ~E_1~0); 150223#L802-1 assume !(1 == ~E_2~0); 150224#L807-1 assume !(1 == ~E_3~0); 150286#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 150287#L817-1 assume !(1 == ~E_5~0); 150056#L822-1 assume !(1 == ~E_6~0); 150057#L827-1 assume { :end_inline_reset_delta_events } true; 155380#L1053-2 [2023-11-06 22:33:21,599 INFO L750 eck$LassoCheckResult]: Loop: 155380#L1053-2 assume !false; 179336#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179331#L659-1 assume !false; 179329#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 179324#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 179317#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 179315#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 179313#L570 assume !(0 != eval_~tmp~0#1); 156285#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 156283#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 156281#L684-3 assume 0 == ~M_E~0;~M_E~0 := 1; 156279#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 156276#L689-3 assume !(0 == ~T2_E~0); 156273#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 156269#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 156267#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 156265#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 156263#L714-3 assume !(0 == ~E_M~0); 156260#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 156258#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 156256#L729-3 assume !(0 == ~E_3~0); 156255#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 156253#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 156251#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 156249#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 156247#L334-24 assume !(1 == ~m_pc~0); 156246#L334-26 is_master_triggered_~__retres1~0#1 := 0; 156245#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 156240#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 156238#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 156237#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 156236#L353-24 assume !(1 == ~t1_pc~0); 156233#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 156234#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180870#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 180864#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 180863#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180861#L372-24 assume 1 == ~t2_pc~0; 180858#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 180855#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180852#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 180849#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 180846#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180843#L391-24 assume !(1 == ~t3_pc~0); 180840#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 180837#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180834#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180831#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 180828#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180825#L410-24 assume !(1 == ~t4_pc~0); 180822#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 180819#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180815#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 180742#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 180743#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180735#L429-24 assume 1 == ~t5_pc~0; 180736#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 180805#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180801#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 180797#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180793#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180789#L448-24 assume !(1 == ~t6_pc~0); 180786#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 180783#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180779#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 180775#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 180771#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180767#L762-3 assume 1 == ~M_E~0;~M_E~0 := 2; 167455#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 180759#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 180755#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 180751#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 180747#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 180731#L787-3 assume !(1 == ~T6_E~0); 156131#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 156132#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 179998#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 179995#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 179992#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 179987#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 179984#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 179983#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 179970#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 179963#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 179958#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 179953#L1072 assume !(0 == start_simulation_~tmp~3#1); 179948#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 179937#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 155423#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 155424#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 155404#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 155405#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179917#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 155381#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 155380#L1053-2 [2023-11-06 22:33:21,600 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:21,600 INFO L85 PathProgramCache]: Analyzing trace with hash 125941963, now seen corresponding path program 1 times [2023-11-06 22:33:21,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:21,601 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536078529] [2023-11-06 22:33:21,601 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:21,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:21,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:21,782 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:21,782 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:21,782 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536078529] [2023-11-06 22:33:21,782 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536078529] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:21,782 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:21,783 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-06 22:33:21,783 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1872146134] [2023-11-06 22:33:21,783 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:21,784 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:21,784 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:21,785 INFO L85 PathProgramCache]: Analyzing trace with hash 40136508, now seen corresponding path program 1 times [2023-11-06 22:33:21,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:21,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648822089] [2023-11-06 22:33:21,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:21,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:21,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:21,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:21,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:21,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648822089] [2023-11-06 22:33:21,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648822089] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:21,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:21,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:21,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499670502] [2023-11-06 22:33:21,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:21,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:21,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:21,839 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:21,839 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:21,839 INFO L87 Difference]: Start difference. First operand 41265 states and 58410 transitions. cyclomatic complexity: 17177 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 2 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:22,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:22,407 INFO L93 Difference]: Finished difference Result 61310 states and 86935 transitions. [2023-11-06 22:33:22,407 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61310 states and 86935 transitions. [2023-11-06 22:33:22,750 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60842 [2023-11-06 22:33:23,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61310 states to 61310 states and 86935 transitions. [2023-11-06 22:33:23,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61310 [2023-11-06 22:33:23,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61310 [2023-11-06 22:33:23,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61310 states and 86935 transitions. [2023-11-06 22:33:23,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:23,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61310 states and 86935 transitions. [2023-11-06 22:33:23,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61310 states and 86935 transitions. [2023-11-06 22:33:23,828 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61310 to 42936. [2023-11-06 22:33:24,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42936 states, 42936 states have (on average 1.420882243338923) internal successors, (61007), 42935 states have internal predecessors, (61007), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:24,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42936 states to 42936 states and 61007 transitions. [2023-11-06 22:33:24,193 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42936 states and 61007 transitions. [2023-11-06 22:33:24,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:24,195 INFO L428 stractBuchiCegarLoop]: Abstraction has 42936 states and 61007 transitions. [2023-11-06 22:33:24,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-06 22:33:24,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42936 states and 61007 transitions. [2023-11-06 22:33:24,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42599 [2023-11-06 22:33:24,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:24,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:24,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:24,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:24,341 INFO L748 eck$LassoCheckResult]: Stem: 252510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 252511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 252659#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 252660#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252287#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 252288#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252657#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 252658#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 252574#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 252350#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 252351#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 252268#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 252269#L684 assume !(0 == ~M_E~0); 252794#L684-2 assume !(0 == ~T1_E~0); 252609#L689-1 assume !(0 == ~T2_E~0); 252610#L694-1 assume !(0 == ~T3_E~0); 252607#L699-1 assume !(0 == ~T4_E~0); 252608#L704-1 assume !(0 == ~T5_E~0); 252558#L709-1 assume !(0 == ~T6_E~0); 252489#L714-1 assume !(0 == ~E_M~0); 252490#L719-1 assume !(0 == ~E_1~0); 252757#L724-1 assume !(0 == ~E_2~0); 252241#L729-1 assume !(0 == ~E_3~0); 252242#L734-1 assume !(0 == ~E_4~0); 252834#L739-1 assume !(0 == ~E_5~0); 252447#L744-1 assume !(0 == ~E_6~0); 252448#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 252198#L334 assume !(1 == ~m_pc~0); 252199#L334-2 is_master_triggered_~__retres1~0#1 := 0; 252549#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252450#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252417#L849 assume !(0 != activate_threads_~tmp~1#1); 252418#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 252348#L353 assume !(1 == ~t1_pc~0); 252349#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252663#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252212#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252213#L857 assume !(0 != activate_threads_~tmp___0~0#1); 252293#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252294#L372 assume !(1 == ~t2_pc~0); 252406#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 252405#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 252543#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 252664#L865 assume !(0 != activate_threads_~tmp___1~0#1); 252187#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252188#L391 assume !(1 == ~t3_pc~0); 252113#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 252114#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252138#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252139#L873 assume !(0 != activate_threads_~tmp___2~0#1); 252424#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252425#L410 assume !(1 == ~t4_pc~0); 252678#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 252679#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252307#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 252308#L881 assume !(0 != activate_threads_~tmp___3~0#1); 252430#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252431#L429 assume !(1 == ~t5_pc~0); 252247#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 252248#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252461#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252462#L889 assume !(0 != activate_threads_~tmp___4~0#1); 252684#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252416#L448 assume !(1 == ~t6_pc~0); 252331#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 252332#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252645#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 252646#L897 assume !(0 != activate_threads_~tmp___5~0#1); 252863#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252923#L762 assume !(1 == ~M_E~0); 252467#L762-2 assume !(1 == ~T1_E~0); 252468#L767-1 assume !(1 == ~T2_E~0); 252873#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 252715#L777-1 assume !(1 == ~T4_E~0); 252592#L782-1 assume !(1 == ~T5_E~0); 252274#L787-1 assume !(1 == ~T6_E~0); 252272#L792-1 assume !(1 == ~E_M~0); 252273#L797-1 assume !(1 == ~E_1~0); 252312#L802-1 assume !(1 == ~E_2~0); 252553#L807-1 assume !(1 == ~E_3~0); 252554#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 252828#L817-1 assume !(1 == ~E_5~0); 252611#L822-1 assume !(1 == ~E_6~0); 252612#L827-1 assume { :end_inline_reset_delta_events } true; 252840#L1053-2 [2023-11-06 22:33:24,342 INFO L750 eck$LassoCheckResult]: Loop: 252840#L1053-2 assume !false; 286848#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 285250#L659-1 assume !false; 286842#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 285325#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 285318#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 285315#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 285312#L570 assume !(0 != eval_~tmp~0#1); 259696#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 259693#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 259690#L684-3 assume !(0 == ~M_E~0); 259686#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 259682#L689-3 assume !(0 == ~T2_E~0); 259678#L694-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 259673#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 259655#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 259652#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 259651#L714-3 assume !(0 == ~E_M~0); 259650#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 259648#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 259647#L729-3 assume !(0 == ~E_3~0); 259646#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 259645#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 259644#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 259642#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 259640#L334-24 assume !(1 == ~m_pc~0); 259638#L334-26 is_master_triggered_~__retres1~0#1 := 0; 259636#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 259634#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 259632#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 259630#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 259628#L353-24 assume !(1 == ~t1_pc~0); 259626#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 259624#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 259622#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 259620#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 259618#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 259615#L372-24 assume !(1 == ~t2_pc~0); 259611#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 259609#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 259607#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 259605#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 259603#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 259601#L391-24 assume !(1 == ~t3_pc~0); 259599#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 259597#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 259595#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 259593#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 259591#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 259589#L410-24 assume !(1 == ~t4_pc~0); 259587#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 259585#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 259583#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 259579#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 259577#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 259575#L429-24 assume !(1 == ~t5_pc~0); 259573#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 259674#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 259656#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 259563#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 259559#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 259557#L448-24 assume !(1 == ~t6_pc~0); 259555#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 259553#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 259551#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 259540#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 259535#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 259530#L762-3 assume !(1 == ~M_E~0); 259525#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 259518#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 259514#L772-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 259507#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 259506#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 259493#L787-3 assume !(1 == ~T6_E~0); 259365#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 259357#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 259353#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 259351#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 259349#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 259347#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 259337#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 259329#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 259242#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 259236#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 259229#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 259230#L1072 assume !(0 == start_simulation_~tmp~3#1); 280217#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 287560#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 287553#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 287551#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 287549#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 287547#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 287545#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 287543#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 252840#L1053-2 [2023-11-06 22:33:24,342 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:24,343 INFO L85 PathProgramCache]: Analyzing trace with hash -1153921715, now seen corresponding path program 1 times [2023-11-06 22:33:24,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:24,343 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682109164] [2023-11-06 22:33:24,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:24,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:24,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:24,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:24,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:24,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1682109164] [2023-11-06 22:33:24,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1682109164] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:24,421 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:24,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:24,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080782614] [2023-11-06 22:33:24,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:24,424 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:24,424 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:24,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1476432960, now seen corresponding path program 1 times [2023-11-06 22:33:24,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:24,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [62960791] [2023-11-06 22:33:24,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:24,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:24,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:24,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:24,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:24,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [62960791] [2023-11-06 22:33:24,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [62960791] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:24,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:24,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:24,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104567174] [2023-11-06 22:33:24,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:24,475 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:24,475 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:24,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:24,476 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:24,476 INFO L87 Difference]: Start difference. First operand 42936 states and 61007 transitions. cyclomatic complexity: 18087 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:25,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:25,145 INFO L93 Difference]: Finished difference Result 69195 states and 97794 transitions. [2023-11-06 22:33:25,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69195 states and 97794 transitions. [2023-11-06 22:33:25,448 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68661 [2023-11-06 22:33:25,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69195 states to 69195 states and 97794 transitions. [2023-11-06 22:33:25,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69195 [2023-11-06 22:33:25,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69195 [2023-11-06 22:33:25,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69195 states and 97794 transitions. [2023-11-06 22:33:26,013 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:26,014 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69195 states and 97794 transitions. [2023-11-06 22:33:26,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69195 states and 97794 transitions. [2023-11-06 22:33:26,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69195 to 49888. [2023-11-06 22:33:26,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49888 states, 49888 states have (on average 1.4169940667094292) internal successors, (70691), 49887 states have internal predecessors, (70691), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:26,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49888 states to 49888 states and 70691 transitions. [2023-11-06 22:33:26,874 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49888 states and 70691 transitions. [2023-11-06 22:33:26,874 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:26,875 INFO L428 stractBuchiCegarLoop]: Abstraction has 49888 states and 70691 transitions. [2023-11-06 22:33:26,875 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-06 22:33:26,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49888 states and 70691 transitions. [2023-11-06 22:33:27,083 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49489 [2023-11-06 22:33:27,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:27,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:27,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:27,086 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:27,086 INFO L748 eck$LassoCheckResult]: Stem: 364655#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 364656#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 364800#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 364801#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364430#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 364431#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 364798#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 364799#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 364717#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 364492#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 364493#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 364411#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 364412#L684 assume !(0 == ~M_E~0); 364940#L684-2 assume !(0 == ~T1_E~0); 364751#L689-1 assume !(0 == ~T2_E~0); 364752#L694-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 365099#L699-1 assume !(0 == ~T4_E~0); 365138#L704-1 assume !(0 == ~T5_E~0); 365137#L709-1 assume !(0 == ~T6_E~0); 364636#L714-1 assume !(0 == ~E_M~0); 364637#L719-1 assume !(0 == ~E_1~0); 364902#L724-1 assume !(0 == ~E_2~0); 364383#L729-1 assume !(0 == ~E_3~0); 364384#L734-1 assume !(0 == ~E_4~0); 365135#L739-1 assume !(0 == ~E_5~0); 364592#L744-1 assume !(0 == ~E_6~0); 364593#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 364903#L334 assume !(1 == ~m_pc~0); 365133#L334-2 is_master_triggered_~__retres1~0#1 := 0; 365132#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 364595#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 364596#L849 assume !(0 != activate_threads_~tmp~1#1); 364862#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 364490#L353 assume !(1 == ~t1_pc~0); 364491#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 364976#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 365129#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 364771#L857 assume !(0 != activate_threads_~tmp___0~0#1); 364772#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 365040#L372 assume !(1 == ~t2_pc~0); 365041#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 365128#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 364805#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 364806#L865 assume !(0 != activate_threads_~tmp___1~0#1); 364975#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 365126#L391 assume !(1 == ~t3_pc~0); 364254#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 364255#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 364279#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 364280#L873 assume !(0 != activate_threads_~tmp___2~0#1); 364895#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 365122#L410 assume !(1 == ~t4_pc~0); 364818#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 364819#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 364449#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 364450#L881 assume !(0 != activate_threads_~tmp___3~0#1); 364977#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 364740#L429 assume !(1 == ~t5_pc~0); 364389#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 364390#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 364608#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 364609#L889 assume !(0 != activate_threads_~tmp___4~0#1); 364826#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 364559#L448 assume !(1 == ~t6_pc~0); 364473#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 364474#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 364787#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 364788#L897 assume !(0 != activate_threads_~tmp___5~0#1); 365088#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 365089#L762 assume !(1 == ~M_E~0); 365110#L762-2 assume !(1 == ~T1_E~0); 365062#L767-1 assume !(1 == ~T2_E~0); 365063#L772-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 364858#L777-1 assume !(1 == ~T4_E~0); 364733#L782-1 assume !(1 == ~T5_E~0); 364417#L787-1 assume !(1 == ~T6_E~0); 364415#L792-1 assume !(1 == ~E_M~0); 364416#L797-1 assume !(1 == ~E_1~0); 364454#L802-1 assume !(1 == ~E_2~0); 364695#L807-1 assume !(1 == ~E_3~0); 364696#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 364984#L817-1 assume !(1 == ~E_5~0); 364753#L822-1 assume !(1 == ~E_6~0); 364754#L827-1 assume { :end_inline_reset_delta_events } true; 364997#L1053-2 [2023-11-06 22:33:27,087 INFO L750 eck$LassoCheckResult]: Loop: 364997#L1053-2 assume !false; 386689#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 386684#L659-1 assume !false; 386682#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 386677#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 386671#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 386670#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 386668#L570 assume !(0 != eval_~tmp~0#1); 386667#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 386666#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 386664#L684-3 assume !(0 == ~M_E~0); 386663#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 386662#L689-3 assume !(0 == ~T2_E~0); 386660#L694-3 assume !(0 == ~T3_E~0); 386661#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 388001#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 387996#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 387980#L714-3 assume !(0 == ~E_M~0); 387975#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 387973#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 387958#L729-3 assume !(0 == ~E_3~0); 387319#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 387312#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 387306#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 387300#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 387293#L334-24 assume !(1 == ~m_pc~0); 387286#L334-26 is_master_triggered_~__retres1~0#1 := 0; 387279#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 387272#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 386900#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 386896#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 386894#L353-24 assume !(1 == ~t1_pc~0); 386892#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 386888#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 386885#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 386882#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 386879#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 386876#L372-24 assume 1 == ~t2_pc~0; 386873#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 386869#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 386866#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 386863#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 386860#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 386857#L391-24 assume !(1 == ~t3_pc~0); 386854#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 386850#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 386846#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 386843#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 386840#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 386837#L410-24 assume !(1 == ~t4_pc~0); 386834#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 386832#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 386829#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 386826#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 386823#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 386820#L429-24 assume !(1 == ~t5_pc~0); 386817#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 387252#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 387245#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 386808#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 386804#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 386800#L448-24 assume !(1 == ~t6_pc~0); 386796#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 386793#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 386790#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 386787#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 386784#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 386780#L762-3 assume !(1 == ~M_E~0); 379938#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 386776#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 386599#L772-3 assume !(1 == ~T3_E~0); 386594#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 386592#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 386590#L787-3 assume !(1 == ~T6_E~0); 386588#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 386585#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 386583#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 386580#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 386577#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 386575#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 386573#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 386571#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 386537#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 386063#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 386040#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 380024#L1072 assume !(0 == start_simulation_~tmp~3#1); 380025#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 386908#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 386901#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 386700#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 386698#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 386696#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 386694#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 386692#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 364997#L1053-2 [2023-11-06 22:33:27,087 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:27,088 INFO L85 PathProgramCache]: Analyzing trace with hash -661295541, now seen corresponding path program 1 times [2023-11-06 22:33:27,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:27,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868153765] [2023-11-06 22:33:27,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:27,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:27,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:27,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:27,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:27,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868153765] [2023-11-06 22:33:27,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868153765] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:27,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:27,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:27,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554631099] [2023-11-06 22:33:27,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:27,159 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:27,159 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:27,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1386415423, now seen corresponding path program 1 times [2023-11-06 22:33:27,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:27,160 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393738472] [2023-11-06 22:33:27,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:27,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:27,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:27,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:27,210 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:27,210 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1393738472] [2023-11-06 22:33:27,210 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1393738472] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:27,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:27,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:27,211 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [583810342] [2023-11-06 22:33:27,211 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:27,211 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:27,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:27,212 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:27,212 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:27,212 INFO L87 Difference]: Start difference. First operand 49888 states and 70691 transitions. cyclomatic complexity: 20819 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:27,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:27,772 INFO L93 Difference]: Finished difference Result 62232 states and 87709 transitions. [2023-11-06 22:33:27,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62232 states and 87709 transitions. [2023-11-06 22:33:28,036 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61771 [2023-11-06 22:33:28,214 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62232 states to 62232 states and 87709 transitions. [2023-11-06 22:33:28,215 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62232 [2023-11-06 22:33:28,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62232 [2023-11-06 22:33:28,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62232 states and 87709 transitions. [2023-11-06 22:33:28,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:28,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62232 states and 87709 transitions. [2023-11-06 22:33:28,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62232 states and 87709 transitions. [2023-11-06 22:33:29,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62232 to 42936. [2023-11-06 22:33:29,289 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42936 states, 42936 states have (on average 1.413289547233091) internal successors, (60681), 42935 states have internal predecessors, (60681), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:29,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42936 states to 42936 states and 60681 transitions. [2023-11-06 22:33:29,405 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42936 states and 60681 transitions. [2023-11-06 22:33:29,405 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:29,406 INFO L428 stractBuchiCegarLoop]: Abstraction has 42936 states and 60681 transitions. [2023-11-06 22:33:29,406 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-06 22:33:29,406 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42936 states and 60681 transitions. [2023-11-06 22:33:29,554 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42599 [2023-11-06 22:33:29,554 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:29,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:29,557 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:29,557 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:29,557 INFO L748 eck$LassoCheckResult]: Stem: 476785#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 476786#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 476930#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 476931#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 476560#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 476561#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 476928#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 476929#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 476854#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 476623#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 476624#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 476541#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 476542#L684 assume !(0 == ~M_E~0); 477068#L684-2 assume !(0 == ~T1_E~0); 476885#L689-1 assume !(0 == ~T2_E~0); 476886#L694-1 assume !(0 == ~T3_E~0); 476883#L699-1 assume !(0 == ~T4_E~0); 476884#L704-1 assume !(0 == ~T5_E~0); 476837#L709-1 assume !(0 == ~T6_E~0); 476767#L714-1 assume !(0 == ~E_M~0); 476768#L719-1 assume !(0 == ~E_1~0); 477029#L724-1 assume !(0 == ~E_2~0); 476513#L729-1 assume !(0 == ~E_3~0); 476514#L734-1 assume !(0 == ~E_4~0); 477106#L739-1 assume !(0 == ~E_5~0); 476725#L744-1 assume !(0 == ~E_6~0); 476726#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 476469#L334 assume !(1 == ~m_pc~0); 476470#L334-2 is_master_triggered_~__retres1~0#1 := 0; 476828#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 476729#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 476695#L849 assume !(0 != activate_threads_~tmp~1#1); 476696#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 476621#L353 assume !(1 == ~t1_pc~0); 476622#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 476935#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 476483#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 476484#L857 assume !(0 != activate_threads_~tmp___0~0#1); 476566#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 476567#L372 assume !(1 == ~t2_pc~0); 476682#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 476681#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 476821#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 476936#L865 assume !(0 != activate_threads_~tmp___1~0#1); 476458#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 476459#L391 assume !(1 == ~t3_pc~0); 476384#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 476385#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 476409#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 476410#L873 assume !(0 != activate_threads_~tmp___2~0#1); 476702#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 476703#L410 assume !(1 == ~t4_pc~0); 476949#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 476950#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 476581#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 476582#L881 assume !(0 != activate_threads_~tmp___3~0#1); 476708#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 476709#L429 assume !(1 == ~t5_pc~0); 476519#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 476520#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 476741#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 476742#L889 assume !(0 != activate_threads_~tmp___4~0#1); 476955#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 476692#L448 assume !(1 == ~t6_pc~0); 476604#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 476605#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 476917#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 476918#L897 assume !(0 != activate_threads_~tmp___5~0#1); 477137#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 477194#L762 assume !(1 == ~M_E~0); 476747#L762-2 assume !(1 == ~T1_E~0); 476748#L767-1 assume !(1 == ~T2_E~0); 477142#L772-1 assume !(1 == ~T3_E~0); 476988#L777-1 assume !(1 == ~T4_E~0); 476871#L782-1 assume !(1 == ~T5_E~0); 476547#L787-1 assume !(1 == ~T6_E~0); 476545#L792-1 assume !(1 == ~E_M~0); 476546#L797-1 assume !(1 == ~E_1~0); 476587#L802-1 assume !(1 == ~E_2~0); 476832#L807-1 assume !(1 == ~E_3~0); 476833#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 477101#L817-1 assume !(1 == ~E_5~0); 476887#L822-1 assume !(1 == ~E_6~0); 476888#L827-1 assume { :end_inline_reset_delta_events } true; 477115#L1053-2 [2023-11-06 22:33:29,558 INFO L750 eck$LassoCheckResult]: Loop: 477115#L1053-2 assume !false; 488137#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 488132#L659-1 assume !false; 488129#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 488124#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 488117#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 488115#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 488112#L570 assume !(0 != eval_~tmp~0#1); 488110#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 488108#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 488106#L684-3 assume !(0 == ~M_E~0); 488104#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 488102#L689-3 assume !(0 == ~T2_E~0); 488100#L694-3 assume !(0 == ~T3_E~0); 488098#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 488096#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 488094#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 488092#L714-3 assume !(0 == ~E_M~0); 488090#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 488088#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 488086#L729-3 assume !(0 == ~E_3~0); 488084#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 488082#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 488080#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 488078#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 488075#L334-24 assume !(1 == ~m_pc~0); 488074#L334-26 is_master_triggered_~__retres1~0#1 := 0; 488071#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 488069#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 488067#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 488065#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 488063#L353-24 assume !(1 == ~t1_pc~0); 488061#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 488058#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 488056#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 488054#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 488052#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 488050#L372-24 assume 1 == ~t2_pc~0; 488048#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 488045#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 488043#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 488041#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 488039#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 488037#L391-24 assume !(1 == ~t3_pc~0); 488035#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 488033#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 488031#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 488029#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 488027#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 488025#L410-24 assume !(1 == ~t4_pc~0); 488021#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 488019#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 488017#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 488015#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 488012#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 488010#L429-24 assume !(1 == ~t5_pc~0); 488006#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 488004#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 488002#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 488000#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 487997#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 487995#L448-24 assume !(1 == ~t6_pc~0); 487993#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 487992#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 487990#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 487988#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 487986#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 487984#L762-3 assume !(1 == ~M_E~0); 487796#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 487981#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 487979#L772-3 assume !(1 == ~T3_E~0); 487977#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 487975#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 487973#L787-3 assume !(1 == ~T6_E~0); 487971#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 487969#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 487967#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 487966#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 487965#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 487964#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 487963#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 487962#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 487957#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 487947#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 487946#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 487925#L1072 assume !(0 == start_simulation_~tmp~3#1); 487926#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 488164#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 488157#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 488152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 488150#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 488148#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 488147#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 488146#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 477115#L1053-2 [2023-11-06 22:33:29,558 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:29,559 INFO L85 PathProgramCache]: Analyzing trace with hash -895756277, now seen corresponding path program 1 times [2023-11-06 22:33:29,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:29,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537547574] [2023-11-06 22:33:29,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:29,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:29,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:29,632 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:29,632 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:29,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537547574] [2023-11-06 22:33:29,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537547574] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:29,633 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:29,633 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:29,633 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1034662998] [2023-11-06 22:33:29,634 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:29,634 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:29,634 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:29,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1386415423, now seen corresponding path program 2 times [2023-11-06 22:33:29,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:29,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685873225] [2023-11-06 22:33:29,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:29,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:29,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:29,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:29,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:29,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685873225] [2023-11-06 22:33:29,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685873225] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:29,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:29,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:29,685 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417226348] [2023-11-06 22:33:29,685 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:29,685 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:29,685 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:29,686 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:29,686 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:29,686 INFO L87 Difference]: Start difference. First operand 42936 states and 60681 transitions. cyclomatic complexity: 17761 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:30,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:30,031 INFO L93 Difference]: Finished difference Result 68678 states and 96216 transitions. [2023-11-06 22:33:30,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68678 states and 96216 transitions. [2023-11-06 22:33:30,290 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68134 [2023-11-06 22:33:30,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68678 states to 68678 states and 96216 transitions. [2023-11-06 22:33:30,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68678 [2023-11-06 22:33:30,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68678 [2023-11-06 22:33:30,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68678 states and 96216 transitions. [2023-11-06 22:33:31,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:31,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 68678 states and 96216 transitions. [2023-11-06 22:33:31,053 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68678 states and 96216 transitions. [2023-11-06 22:33:31,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68678 to 49888. [2023-11-06 22:33:31,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49888 states, 49888 states have (on average 1.40454618345093) internal successors, (70070), 49887 states have internal predecessors, (70070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:31,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49888 states to 49888 states and 70070 transitions. [2023-11-06 22:33:31,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49888 states and 70070 transitions. [2023-11-06 22:33:31,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:31,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 49888 states and 70070 transitions. [2023-11-06 22:33:31,668 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-06 22:33:31,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49888 states and 70070 transitions. [2023-11-06 22:33:31,799 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49489 [2023-11-06 22:33:31,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:31,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:31,801 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:31,802 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:31,802 INFO L748 eck$LassoCheckResult]: Stem: 588411#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 588412#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 588553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 588554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 588188#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 588189#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 588549#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 588550#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 588468#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 588248#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 588249#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 588168#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 588169#L684 assume !(0 == ~M_E~0); 588699#L684-2 assume !(0 == ~T1_E~0); 588503#L689-1 assume !(0 == ~T2_E~0); 588504#L694-1 assume !(0 == ~T3_E~0); 588501#L699-1 assume !(0 == ~T4_E~0); 588502#L704-1 assume !(0 == ~T5_E~0); 588455#L709-1 assume !(0 == ~T6_E~0); 588387#L714-1 assume !(0 == ~E_M~0); 588388#L719-1 assume !(0 == ~E_1~0); 588659#L724-1 assume !(0 == ~E_2~0); 588139#L729-1 assume !(0 == ~E_3~0); 588140#L734-1 assume 0 == ~E_4~0;~E_4~0 := 1; 588739#L739-1 assume !(0 == ~E_5~0); 588740#L744-1 assume !(0 == ~E_6~0); 588892#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 588094#L334 assume !(1 == ~m_pc~0); 588095#L334-2 is_master_triggered_~__retres1~0#1 := 0; 588445#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 588348#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 588349#L849 assume !(0 != activate_threads_~tmp~1#1); 588887#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 588886#L353 assume !(1 == ~t1_pc~0); 588885#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 588555#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 588108#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 588109#L857 assume !(0 != activate_threads_~tmp___0~0#1); 588883#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 588789#L372 assume !(1 == ~t2_pc~0); 588302#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 588301#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 588439#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 588879#L865 assume !(0 != activate_threads_~tmp___1~0#1); 588083#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 588084#L391 assume !(1 == ~t3_pc~0); 588008#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 588009#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 588033#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 588034#L873 assume !(0 != activate_threads_~tmp___2~0#1); 588647#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 588873#L410 assume !(1 == ~t4_pc~0); 588872#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 588871#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 588870#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 588869#L881 assume !(0 != activate_threads_~tmp___3~0#1); 588868#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 588491#L429 assume !(1 == ~t5_pc~0); 588492#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 588867#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 588865#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 588862#L889 assume !(0 != activate_threads_~tmp___4~0#1); 588861#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 588313#L448 assume !(1 == ~t6_pc~0); 588227#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 588228#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 588577#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 588769#L897 assume !(0 != activate_threads_~tmp___5~0#1); 588770#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 588826#L762 assume !(1 == ~M_E~0); 588367#L762-2 assume !(1 == ~T1_E~0); 588368#L767-1 assume !(1 == ~T2_E~0); 588776#L772-1 assume !(1 == ~T3_E~0); 588612#L777-1 assume !(1 == ~T4_E~0); 588613#L782-1 assume !(1 == ~T5_E~0); 588856#L787-1 assume !(1 == ~T6_E~0); 588855#L792-1 assume !(1 == ~E_M~0); 588854#L797-1 assume !(1 == ~E_1~0); 588853#L802-1 assume !(1 == ~E_2~0); 588852#L807-1 assume !(1 == ~E_3~0); 588851#L812-1 assume 1 == ~E_4~0;~E_4~0 := 2; 588736#L817-1 assume !(1 == ~E_5~0); 588507#L822-1 assume !(1 == ~E_6~0); 588508#L827-1 assume { :end_inline_reset_delta_events } true; 588747#L1053-2 [2023-11-06 22:33:31,802 INFO L750 eck$LassoCheckResult]: Loop: 588747#L1053-2 assume !false; 615722#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 613584#L659-1 assume !false; 615691#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 596139#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 596132#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 596130#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 596126#L570 assume !(0 != eval_~tmp~0#1); 596128#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 616294#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 615596#L684-3 assume !(0 == ~M_E~0); 615594#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 615592#L689-3 assume !(0 == ~T2_E~0); 615590#L694-3 assume !(0 == ~T3_E~0); 615588#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 615586#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 615585#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 615581#L714-3 assume !(0 == ~E_M~0); 615579#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 615577#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 615576#L729-3 assume !(0 == ~E_3~0); 615572#L734-3 assume 0 == ~E_4~0;~E_4~0 := 1; 615571#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 615570#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 615569#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 615568#L334-24 assume !(1 == ~m_pc~0); 615567#L334-26 is_master_triggered_~__retres1~0#1 := 0; 615566#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 615565#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 615564#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 615563#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 615562#L353-24 assume !(1 == ~t1_pc~0); 615561#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 615560#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 615559#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 615558#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 615557#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 615556#L372-24 assume 1 == ~t2_pc~0; 615555#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 615553#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 615552#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 615551#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 615550#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 615549#L391-24 assume !(1 == ~t3_pc~0); 615548#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 615547#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 615546#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 615545#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 615544#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 615543#L410-24 assume !(1 == ~t4_pc~0); 615542#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 615541#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 615540#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 615539#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 615537#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 615535#L429-24 assume !(1 == ~t5_pc~0); 615533#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 615531#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 615529#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 615527#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 615525#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 615524#L448-24 assume !(1 == ~t6_pc~0); 615523#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 615522#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 615521#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 615520#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 615519#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 615518#L762-3 assume !(1 == ~M_E~0); 607791#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 615517#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 615516#L772-3 assume !(1 == ~T3_E~0); 615515#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 615514#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 615513#L787-3 assume !(1 == ~T6_E~0); 615512#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 615511#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 615510#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 615509#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 615507#L812-3 assume 1 == ~E_4~0;~E_4~0 := 2; 615505#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 615503#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 615501#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 615393#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 615388#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 615385#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 608317#L1072 assume !(0 == start_simulation_~tmp~3#1); 596183#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 596179#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 596170#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 596171#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 627298#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 627297#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 627294#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 627291#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 588747#L1053-2 [2023-11-06 22:33:31,803 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:31,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1437636361, now seen corresponding path program 1 times [2023-11-06 22:33:31,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:31,804 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345018361] [2023-11-06 22:33:31,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:31,804 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:31,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:32,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:32,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:32,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345018361] [2023-11-06 22:33:32,253 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345018361] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:32,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:32,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:32,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [71809259] [2023-11-06 22:33:32,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:32,254 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:32,255 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:32,255 INFO L85 PathProgramCache]: Analyzing trace with hash 1386415423, now seen corresponding path program 3 times [2023-11-06 22:33:32,255 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:32,255 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169999331] [2023-11-06 22:33:32,255 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:32,255 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:32,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:32,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:32,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:32,323 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1169999331] [2023-11-06 22:33:32,323 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1169999331] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:32,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:32,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:32,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [958405172] [2023-11-06 22:33:32,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:32,324 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:32,324 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:32,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:32,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:32,325 INFO L87 Difference]: Start difference. First operand 49888 states and 70070 transitions. cyclomatic complexity: 20198 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:32,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:32,673 INFO L93 Difference]: Finished difference Result 61321 states and 85643 transitions. [2023-11-06 22:33:32,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61321 states and 85643 transitions. [2023-11-06 22:33:33,047 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 60842 [2023-11-06 22:33:33,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61321 states to 61321 states and 85643 transitions. [2023-11-06 22:33:33,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61321 [2023-11-06 22:33:33,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61321 [2023-11-06 22:33:33,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61321 states and 85643 transitions. [2023-11-06 22:33:33,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:33,289 INFO L218 hiAutomatonCegarLoop]: Abstraction has 61321 states and 85643 transitions. [2023-11-06 22:33:33,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61321 states and 85643 transitions. [2023-11-06 22:33:33,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61321 to 42936. [2023-11-06 22:33:33,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42936 states, 42936 states have (on average 1.398826159865847) internal successors, (60060), 42935 states have internal predecessors, (60060), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:33,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42936 states to 42936 states and 60060 transitions. [2023-11-06 22:33:33,912 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42936 states and 60060 transitions. [2023-11-06 22:33:33,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:33,912 INFO L428 stractBuchiCegarLoop]: Abstraction has 42936 states and 60060 transitions. [2023-11-06 22:33:33,912 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-06 22:33:33,913 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42936 states and 60060 transitions. [2023-11-06 22:33:34,288 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42599 [2023-11-06 22:33:34,288 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:34,288 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:34,289 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:34,289 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:34,289 INFO L748 eck$LassoCheckResult]: Stem: 699637#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 699638#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 699787#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 699788#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 699406#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 699407#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 699783#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 699784#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 699701#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 699469#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 699470#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 699386#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 699387#L684 assume !(0 == ~M_E~0); 699925#L684-2 assume !(0 == ~T1_E~0); 699735#L689-1 assume !(0 == ~T2_E~0); 699736#L694-1 assume !(0 == ~T3_E~0); 699733#L699-1 assume !(0 == ~T4_E~0); 699734#L704-1 assume !(0 == ~T5_E~0); 699687#L709-1 assume !(0 == ~T6_E~0); 699615#L714-1 assume !(0 == ~E_M~0); 699616#L719-1 assume !(0 == ~E_1~0); 699886#L724-1 assume !(0 == ~E_2~0); 699357#L729-1 assume !(0 == ~E_3~0); 699358#L734-1 assume !(0 == ~E_4~0); 699976#L739-1 assume !(0 == ~E_5~0); 699570#L744-1 assume !(0 == ~E_6~0); 699571#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 699312#L334 assume !(1 == ~m_pc~0); 699313#L334-2 is_master_triggered_~__retres1~0#1 := 0; 699676#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 699576#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 699538#L849 assume !(0 != activate_threads_~tmp~1#1); 699539#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 699465#L353 assume !(1 == ~t1_pc~0); 699466#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 699790#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 699326#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 699327#L857 assume !(0 != activate_threads_~tmp___0~0#1); 699408#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 699409#L372 assume !(1 == ~t2_pc~0); 699525#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 699524#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 699670#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 699791#L865 assume !(0 != activate_threads_~tmp___1~0#1); 699301#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 699302#L391 assume !(1 == ~t3_pc~0); 699227#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 699228#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 699252#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 699253#L873 assume !(0 != activate_threads_~tmp___2~0#1); 699545#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 699546#L410 assume !(1 == ~t4_pc~0); 699804#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 699805#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 699424#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 699425#L881 assume !(0 != activate_threads_~tmp___3~0#1); 699556#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 699557#L429 assume !(1 == ~t5_pc~0); 699363#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 699364#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 699587#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 699588#L889 assume !(0 != activate_threads_~tmp___4~0#1); 699811#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 699537#L448 assume !(1 == ~t6_pc~0); 699447#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 699448#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 699773#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 699774#L897 assume !(0 != activate_threads_~tmp___5~0#1); 700006#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 700070#L762 assume !(1 == ~M_E~0); 699597#L762-2 assume !(1 == ~T1_E~0); 699598#L767-1 assume !(1 == ~T2_E~0); 700015#L772-1 assume !(1 == ~T3_E~0); 699847#L777-1 assume !(1 == ~T4_E~0); 699717#L782-1 assume !(1 == ~T5_E~0); 699390#L787-1 assume !(1 == ~T6_E~0); 699388#L792-1 assume !(1 == ~E_M~0); 699389#L797-1 assume !(1 == ~E_1~0); 699431#L802-1 assume !(1 == ~E_2~0); 699680#L807-1 assume !(1 == ~E_3~0); 699681#L812-1 assume !(1 == ~E_4~0); 699973#L817-1 assume !(1 == ~E_5~0); 699739#L822-1 assume !(1 == ~E_6~0); 699740#L827-1 assume { :end_inline_reset_delta_events } true; 699983#L1053-2 [2023-11-06 22:33:34,290 INFO L750 eck$LassoCheckResult]: Loop: 699983#L1053-2 assume !false; 729596#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 729310#L659-1 assume !false; 729593#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 729358#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 729351#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 729349#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 729346#L570 assume !(0 != eval_~tmp~0#1); 729347#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 730294#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 730292#L684-3 assume !(0 == ~M_E~0); 730289#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 730287#L689-3 assume !(0 == ~T2_E~0); 730285#L694-3 assume !(0 == ~T3_E~0); 730283#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 730281#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 730279#L709-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 730277#L714-3 assume !(0 == ~E_M~0); 730275#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 730274#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 730273#L729-3 assume !(0 == ~E_3~0); 730271#L734-3 assume !(0 == ~E_4~0); 730270#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 730269#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 730268#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 730266#L334-24 assume !(1 == ~m_pc~0); 730265#L334-26 is_master_triggered_~__retres1~0#1 := 0; 730264#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 730263#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 730262#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 730261#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 730259#L353-24 assume !(1 == ~t1_pc~0); 730257#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 730255#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 730253#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 730251#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 730249#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 730247#L372-24 assume 1 == ~t2_pc~0; 730245#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 730242#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 730240#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 730238#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 730236#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 730234#L391-24 assume !(1 == ~t3_pc~0); 730231#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 730229#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 730227#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 730225#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 730223#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 730220#L410-24 assume !(1 == ~t4_pc~0); 730219#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 730216#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 730214#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 730212#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 730210#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 730208#L429-24 assume 1 == ~t5_pc~0; 730206#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 730207#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 730267#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 730197#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 730195#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 730193#L448-24 assume !(1 == ~t6_pc~0); 730189#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 730187#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 730185#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 730183#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 730180#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 730178#L762-3 assume !(1 == ~M_E~0); 730175#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 730172#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 730170#L772-3 assume !(1 == ~T3_E~0); 730168#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 730166#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 730164#L787-3 assume !(1 == ~T6_E~0); 730163#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 730162#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 730158#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 730156#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 730154#L812-3 assume !(1 == ~E_4~0); 730153#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 730152#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 730151#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 729769#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 729765#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 729764#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 729761#L1072 assume !(0 == start_simulation_~tmp~3#1); 729759#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 729616#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 729609#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 729607#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 729605#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 729603#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 729601#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 729599#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 699983#L1053-2 [2023-11-06 22:33:34,290 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:34,291 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 1 times [2023-11-06 22:33:34,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:34,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390427161] [2023-11-06 22:33:34,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:34,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:34,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:34,304 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:34,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:34,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:34,356 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:34,357 INFO L85 PathProgramCache]: Analyzing trace with hash 255238396, now seen corresponding path program 1 times [2023-11-06 22:33:34,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:34,357 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820208627] [2023-11-06 22:33:34,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:34,357 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:34,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:34,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:34,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:34,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1820208627] [2023-11-06 22:33:34,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1820208627] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:34,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:34,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:34,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2027810129] [2023-11-06 22:33:34,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:34,398 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:34,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:34,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:34,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:34,399 INFO L87 Difference]: Start difference. First operand 42936 states and 60060 transitions. cyclomatic complexity: 17140 Second operand has 3 states, 3 states have (on average 31.333333333333332) internal successors, (94), 3 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:34,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:34,575 INFO L93 Difference]: Finished difference Result 49888 states and 69580 transitions. [2023-11-06 22:33:34,575 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49888 states and 69580 transitions. [2023-11-06 22:33:34,781 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49489 [2023-11-06 22:33:34,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49888 states to 49888 states and 69580 transitions. [2023-11-06 22:33:34,897 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49888 [2023-11-06 22:33:34,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49888 [2023-11-06 22:33:34,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49888 states and 69580 transitions. [2023-11-06 22:33:34,944 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:34,944 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49888 states and 69580 transitions. [2023-11-06 22:33:34,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49888 states and 69580 transitions. [2023-11-06 22:33:35,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49888 to 49888. [2023-11-06 22:33:35,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49888 states, 49888 states have (on average 1.3947241821680565) internal successors, (69580), 49887 states have internal predecessors, (69580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:35,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49888 states to 49888 states and 69580 transitions. [2023-11-06 22:33:35,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 49888 states and 69580 transitions. [2023-11-06 22:33:35,392 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:35,392 INFO L428 stractBuchiCegarLoop]: Abstraction has 49888 states and 69580 transitions. [2023-11-06 22:33:35,393 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-06 22:33:35,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49888 states and 69580 transitions. [2023-11-06 22:33:35,654 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 49489 [2023-11-06 22:33:35,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:35,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:35,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:35,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:35,657 INFO L748 eck$LassoCheckResult]: Stem: 792450#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 792451#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 792597#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 792598#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 792231#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 792232#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 792593#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 792594#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 792512#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 792292#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 792293#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 792214#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 792215#L684 assume !(0 == ~M_E~0); 792731#L684-2 assume !(0 == ~T1_E~0); 792547#L689-1 assume !(0 == ~T2_E~0); 792548#L694-1 assume !(0 == ~T3_E~0); 792545#L699-1 assume !(0 == ~T4_E~0); 792546#L704-1 assume !(0 == ~T5_E~0); 792495#L709-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 792430#L714-1 assume !(0 == ~E_M~0); 792431#L719-1 assume !(0 == ~E_1~0); 792697#L724-1 assume !(0 == ~E_2~0); 792185#L729-1 assume !(0 == ~E_3~0); 792186#L734-1 assume !(0 == ~E_4~0); 792930#L739-1 assume !(0 == ~E_5~0); 792929#L744-1 assume !(0 == ~E_6~0); 792928#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 792142#L334 assume !(1 == ~m_pc~0); 792143#L334-2 is_master_triggered_~__retres1~0#1 := 0; 792486#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 792393#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 792394#L849 assume !(0 != activate_threads_~tmp~1#1); 792924#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 792923#L353 assume !(1 == ~t1_pc~0); 792922#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 792600#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 792156#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 792157#L857 assume !(0 != activate_threads_~tmp___0~0#1); 792920#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 792826#L372 assume !(1 == ~t2_pc~0); 792827#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 792919#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 792601#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 792602#L865 assume !(0 != activate_threads_~tmp___1~0#1); 792762#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 792917#L391 assume !(1 == ~t3_pc~0); 792916#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 792915#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 792914#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 792913#L873 assume !(0 != activate_threads_~tmp___2~0#1); 792368#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 792369#L410 assume !(1 == ~t4_pc~0); 792615#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 792616#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 792250#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 792251#L881 assume !(0 != activate_threads_~tmp___3~0#1); 792375#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 792376#L429 assume !(1 == ~t5_pc~0); 792191#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 792192#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 792931#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 792621#L889 assume !(0 != activate_threads_~tmp___4~0#1); 792622#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 792654#L448 assume !(1 == ~t6_pc~0); 792899#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 792898#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 792584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 792585#L897 assume !(0 != activate_threads_~tmp___5~0#1); 792871#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 792872#L762 assume !(1 == ~M_E~0); 792897#L762-2 assume !(1 == ~T1_E~0); 792896#L767-1 assume !(1 == ~T2_E~0); 792811#L772-1 assume !(1 == ~T3_E~0); 792655#L777-1 assume !(1 == ~T4_E~0); 792528#L782-1 assume !(1 == ~T5_E~0); 792218#L787-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 792216#L792-1 assume !(1 == ~E_M~0); 792217#L797-1 assume !(1 == ~E_1~0); 792257#L802-1 assume !(1 == ~E_2~0); 792490#L807-1 assume !(1 == ~E_3~0); 792491#L812-1 assume !(1 == ~E_4~0); 792771#L817-1 assume !(1 == ~E_5~0); 792549#L822-1 assume !(1 == ~E_6~0); 792550#L827-1 assume { :end_inline_reset_delta_events } true; 792782#L1053-2 [2023-11-06 22:33:35,657 INFO L750 eck$LassoCheckResult]: Loop: 792782#L1053-2 assume !false; 812137#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 811762#L659-1 assume !false; 812136#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 811818#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 811810#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 811808#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 811804#L570 assume !(0 != eval_~tmp~0#1); 811805#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 812440#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 812438#L684-3 assume !(0 == ~M_E~0); 812436#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 812434#L689-3 assume !(0 == ~T2_E~0); 812432#L694-3 assume !(0 == ~T3_E~0); 812430#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 812428#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 812425#L709-3 assume !(0 == ~T6_E~0); 812426#L714-3 assume !(0 == ~E_M~0); 812919#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 812913#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 812906#L729-3 assume !(0 == ~E_3~0); 812900#L734-3 assume !(0 == ~E_4~0); 812894#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 812887#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 812881#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 812876#L334-24 assume !(1 == ~m_pc~0); 812871#L334-26 is_master_triggered_~__retres1~0#1 := 0; 812866#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 812861#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 812856#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 812850#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 812843#L353-24 assume !(1 == ~t1_pc~0); 812835#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 812829#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 812820#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 812807#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 812800#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 812644#L372-24 assume 1 == ~t2_pc~0; 812636#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 812620#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 812610#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 812576#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 812528#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 812520#L391-24 assume !(1 == ~t3_pc~0); 812518#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 812516#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 812513#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 812511#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 812509#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 812507#L410-24 assume !(1 == ~t4_pc~0); 812505#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 812503#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 812501#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 812499#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 812497#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 812494#L429-24 assume 1 == ~t5_pc~0; 812492#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 812493#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 812714#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 812483#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 812481#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 812479#L448-24 assume !(1 == ~t6_pc~0); 812477#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 812475#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 812473#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 812471#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 812469#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 812467#L762-3 assume !(1 == ~M_E~0); 812463#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 812461#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 812459#L772-3 assume !(1 == ~T3_E~0); 812457#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 812455#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 812299#L787-3 assume !(1 == ~T6_E~0); 812297#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 812295#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 812292#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 812290#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 812288#L812-3 assume !(1 == ~E_4~0); 812286#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 812284#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 812282#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 812271#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 812267#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 812265#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 812263#L1072 assume !(0 == start_simulation_~tmp~3#1); 812261#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 812257#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 812247#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 812208#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 812202#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 812197#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 812193#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 812192#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 792782#L1053-2 [2023-11-06 22:33:35,658 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:35,658 INFO L85 PathProgramCache]: Analyzing trace with hash -843787639, now seen corresponding path program 1 times [2023-11-06 22:33:35,658 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:35,658 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1462974261] [2023-11-06 22:33:35,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:35,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:35,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:35,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:35,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:35,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1462974261] [2023-11-06 22:33:35,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1462974261] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:35,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:35,712 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:35,712 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1011376150] [2023-11-06 22:33:35,712 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:35,712 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:35,713 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:35,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1094272058, now seen corresponding path program 1 times [2023-11-06 22:33:35,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:35,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024594038] [2023-11-06 22:33:35,713 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:35,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:35,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:35,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:35,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:35,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024594038] [2023-11-06 22:33:35,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024594038] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:35,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:35,770 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:33:35,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822115364] [2023-11-06 22:33:35,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:35,770 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:35,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:35,771 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-06 22:33:35,771 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-06 22:33:35,771 INFO L87 Difference]: Start difference. First operand 49888 states and 69580 transitions. cyclomatic complexity: 19708 Second operand has 4 states, 4 states have (on average 21.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:36,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:36,027 INFO L93 Difference]: Finished difference Result 62240 states and 86697 transitions. [2023-11-06 22:33:36,027 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62240 states and 86697 transitions. [2023-11-06 22:33:36,248 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 61771 [2023-11-06 22:33:36,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62240 states to 62240 states and 86697 transitions. [2023-11-06 22:33:36,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62240 [2023-11-06 22:33:36,420 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62240 [2023-11-06 22:33:36,420 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62240 states and 86697 transitions. [2023-11-06 22:33:36,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:36,446 INFO L218 hiAutomatonCegarLoop]: Abstraction has 62240 states and 86697 transitions. [2023-11-06 22:33:36,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62240 states and 86697 transitions. [2023-11-06 22:33:37,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62240 to 42936. [2023-11-06 22:33:37,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42936 states, 42936 states have (on average 1.396287497670952) internal successors, (59951), 42935 states have internal predecessors, (59951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:37,387 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42936 states to 42936 states and 59951 transitions. [2023-11-06 22:33:37,387 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42936 states and 59951 transitions. [2023-11-06 22:33:37,387 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-06 22:33:37,387 INFO L428 stractBuchiCegarLoop]: Abstraction has 42936 states and 59951 transitions. [2023-11-06 22:33:37,388 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-06 22:33:37,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42936 states and 59951 transitions. [2023-11-06 22:33:37,492 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42599 [2023-11-06 22:33:37,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:37,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:37,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:37,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:37,494 INFO L748 eck$LassoCheckResult]: Stem: 904595#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 904596#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 904743#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 904744#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 904375#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 904376#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 904741#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 904742#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 904662#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 904437#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 904438#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 904356#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 904357#L684 assume !(0 == ~M_E~0); 904875#L684-2 assume !(0 == ~T1_E~0); 904697#L689-1 assume !(0 == ~T2_E~0); 904698#L694-1 assume !(0 == ~T3_E~0); 904695#L699-1 assume !(0 == ~T4_E~0); 904696#L704-1 assume !(0 == ~T5_E~0); 904647#L709-1 assume !(0 == ~T6_E~0); 904578#L714-1 assume !(0 == ~E_M~0); 904579#L719-1 assume !(0 == ~E_1~0); 904839#L724-1 assume !(0 == ~E_2~0); 904328#L729-1 assume !(0 == ~E_3~0); 904329#L734-1 assume !(0 == ~E_4~0); 904917#L739-1 assume !(0 == ~E_5~0); 904537#L744-1 assume !(0 == ~E_6~0); 904538#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 904283#L334 assume !(1 == ~m_pc~0); 904284#L334-2 is_master_triggered_~__retres1~0#1 := 0; 904638#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 904540#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 904506#L849 assume !(0 != activate_threads_~tmp~1#1); 904507#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 904435#L353 assume !(1 == ~t1_pc~0); 904436#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 904747#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 904297#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 904298#L857 assume !(0 != activate_threads_~tmp___0~0#1); 904380#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 904381#L372 assume !(1 == ~t2_pc~0); 904493#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 904492#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 904630#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 904748#L865 assume !(0 != activate_threads_~tmp___1~0#1); 904272#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 904273#L391 assume !(1 == ~t3_pc~0); 904197#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 904198#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 904222#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 904223#L873 assume !(0 != activate_threads_~tmp___2~0#1); 904513#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 904514#L410 assume !(1 == ~t4_pc~0); 904761#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 904762#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 904395#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 904396#L881 assume !(0 != activate_threads_~tmp___3~0#1); 904519#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 904520#L429 assume !(1 == ~t5_pc~0); 904334#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 904335#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 904552#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 904553#L889 assume !(0 != activate_threads_~tmp___4~0#1); 904767#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 904503#L448 assume !(1 == ~t6_pc~0); 904418#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 904419#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 904731#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 904732#L897 assume !(0 != activate_threads_~tmp___5~0#1); 904949#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 905012#L762 assume !(1 == ~M_E~0); 904558#L762-2 assume !(1 == ~T1_E~0); 904559#L767-1 assume !(1 == ~T2_E~0); 904958#L772-1 assume !(1 == ~T3_E~0); 904798#L777-1 assume !(1 == ~T4_E~0); 904679#L782-1 assume !(1 == ~T5_E~0); 904362#L787-1 assume !(1 == ~T6_E~0); 904360#L792-1 assume !(1 == ~E_M~0); 904361#L797-1 assume !(1 == ~E_1~0); 904401#L802-1 assume !(1 == ~E_2~0); 904642#L807-1 assume !(1 == ~E_3~0); 904643#L812-1 assume !(1 == ~E_4~0); 904912#L817-1 assume !(1 == ~E_5~0); 904699#L822-1 assume !(1 == ~E_6~0); 904700#L827-1 assume { :end_inline_reset_delta_events } true; 904924#L1053-2 [2023-11-06 22:33:37,495 INFO L750 eck$LassoCheckResult]: Loop: 904924#L1053-2 assume !false; 916767#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 916762#L659-1 assume !false; 916761#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 916756#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 916749#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 916747#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 916744#L570 assume !(0 != eval_~tmp~0#1); 916742#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 916740#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 916738#L684-3 assume !(0 == ~M_E~0); 916736#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 916734#L689-3 assume !(0 == ~T2_E~0); 916732#L694-3 assume !(0 == ~T3_E~0); 916730#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 916729#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 916728#L709-3 assume !(0 == ~T6_E~0); 916727#L714-3 assume !(0 == ~E_M~0); 916726#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 916725#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 916717#L729-3 assume !(0 == ~E_3~0); 916715#L734-3 assume !(0 == ~E_4~0); 916713#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 916711#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 916709#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 916707#L334-24 assume !(1 == ~m_pc~0); 916705#L334-26 is_master_triggered_~__retres1~0#1 := 0; 916703#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 916701#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 916699#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 916696#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 916694#L353-24 assume !(1 == ~t1_pc~0); 916692#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 916690#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 916688#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 916686#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 916684#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916682#L372-24 assume 1 == ~t2_pc~0; 916680#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 916677#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916675#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916673#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 916671#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916669#L391-24 assume !(1 == ~t3_pc~0); 916667#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 916665#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 916663#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 916659#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 916657#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 916655#L410-24 assume !(1 == ~t4_pc~0); 916653#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 916650#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 916648#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 916646#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 916645#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916642#L429-24 assume !(1 == ~t5_pc~0); 916638#L429-26 is_transmit5_triggered_~__retres1~5#1 := 0; 916636#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 916634#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 916632#L889-24 assume !(0 != activate_threads_~tmp___4~0#1); 916629#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916628#L448-24 assume !(1 == ~t6_pc~0); 916626#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 916624#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916622#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 916620#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 916618#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 916616#L762-3 assume !(1 == ~M_E~0); 915870#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 916613#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 916611#L772-3 assume !(1 == ~T3_E~0); 916609#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 916607#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 916605#L787-3 assume !(1 == ~T6_E~0); 916603#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 916602#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 916601#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 916600#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 916599#L812-3 assume !(1 == ~E_4~0); 916598#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 916590#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 916588#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 916007#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 916003#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 916001#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 915980#L1072 assume !(0 == start_simulation_~tmp~3#1); 915981#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 916788#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 916780#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 916778#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 916776#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 916774#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 916772#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 916770#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 904924#L1053-2 [2023-11-06 22:33:37,495 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:37,496 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 2 times [2023-11-06 22:33:37,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:37,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [359654335] [2023-11-06 22:33:37,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:37,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:37,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:37,510 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:37,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:37,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:37,543 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:37,544 INFO L85 PathProgramCache]: Analyzing trace with hash -706661827, now seen corresponding path program 1 times [2023-11-06 22:33:37,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:37,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962711889] [2023-11-06 22:33:37,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:37,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:37,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:37,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:37,599 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:37,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962711889] [2023-11-06 22:33:37,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962711889] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:37,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:37,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:33:37,600 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076323927] [2023-11-06 22:33:37,600 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:37,601 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:37,601 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:37,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:33:37,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:33:37,601 INFO L87 Difference]: Start difference. First operand 42936 states and 59951 transitions. cyclomatic complexity: 17031 Second operand has 5 states, 5 states have (on average 18.8) internal successors, (94), 5 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:37,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:37,952 INFO L93 Difference]: Finished difference Result 76193 states and 104781 transitions. [2023-11-06 22:33:37,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76193 states and 104781 transitions. [2023-11-06 22:33:38,257 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 75608 [2023-11-06 22:33:38,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76193 states to 76193 states and 104781 transitions. [2023-11-06 22:33:38,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76193 [2023-11-06 22:33:38,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76193 [2023-11-06 22:33:38,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76193 states and 104781 transitions. [2023-11-06 22:33:38,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:38,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76193 states and 104781 transitions. [2023-11-06 22:33:38,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76193 states and 104781 transitions. [2023-11-06 22:33:39,496 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76193 to 43260. [2023-11-06 22:33:39,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43260 states, 43260 states have (on average 1.3933194637078132) internal successors, (60275), 43259 states have internal predecessors, (60275), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:39,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43260 states to 43260 states and 60275 transitions. [2023-11-06 22:33:39,604 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43260 states and 60275 transitions. [2023-11-06 22:33:39,605 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-06 22:33:39,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 43260 states and 60275 transitions. [2023-11-06 22:33:39,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-06 22:33:39,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43260 states and 60275 transitions. [2023-11-06 22:33:39,722 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 42923 [2023-11-06 22:33:39,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:39,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:39,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:39,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:39,724 INFO L748 eck$LassoCheckResult]: Stem: 1023745#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1023746#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1023893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1023894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1023521#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1023522#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1023891#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1023892#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1023810#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1023583#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1023584#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1023502#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1023503#L684 assume !(0 == ~M_E~0); 1024035#L684-2 assume !(0 == ~T1_E~0); 1023845#L689-1 assume !(0 == ~T2_E~0); 1023846#L694-1 assume !(0 == ~T3_E~0); 1023843#L699-1 assume !(0 == ~T4_E~0); 1023844#L704-1 assume !(0 == ~T5_E~0); 1023795#L709-1 assume !(0 == ~T6_E~0); 1023728#L714-1 assume !(0 == ~E_M~0); 1023729#L719-1 assume !(0 == ~E_1~0); 1023999#L724-1 assume !(0 == ~E_2~0); 1023472#L729-1 assume !(0 == ~E_3~0); 1023473#L734-1 assume !(0 == ~E_4~0); 1024082#L739-1 assume !(0 == ~E_5~0); 1023686#L744-1 assume !(0 == ~E_6~0); 1023687#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1023428#L334 assume !(1 == ~m_pc~0); 1023429#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1023786#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1023688#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1023654#L849 assume !(0 != activate_threads_~tmp~1#1); 1023655#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1023581#L353 assume !(1 == ~t1_pc~0); 1023582#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1023897#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1023442#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1023443#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1023526#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1023527#L372 assume !(1 == ~t2_pc~0); 1023641#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1023640#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1023778#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1023898#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1023417#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1023418#L391 assume !(1 == ~t3_pc~0); 1023343#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1023344#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1023368#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1023369#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1023661#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1023662#L410 assume !(1 == ~t4_pc~0); 1023910#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1023911#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1023540#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1023541#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1023668#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1023669#L429 assume !(1 == ~t5_pc~0); 1023478#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1023479#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1023701#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1023702#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1023916#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1023651#L448 assume !(1 == ~t6_pc~0); 1023564#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1023565#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1023880#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1023881#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1024114#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1024169#L762 assume !(1 == ~M_E~0); 1023709#L762-2 assume !(1 == ~T1_E~0); 1023710#L767-1 assume !(1 == ~T2_E~0); 1024122#L772-1 assume !(1 == ~T3_E~0); 1023950#L777-1 assume !(1 == ~T4_E~0); 1023826#L782-1 assume !(1 == ~T5_E~0); 1023508#L787-1 assume !(1 == ~T6_E~0); 1023506#L792-1 assume !(1 == ~E_M~0); 1023507#L797-1 assume !(1 == ~E_1~0); 1023546#L802-1 assume !(1 == ~E_2~0); 1023790#L807-1 assume !(1 == ~E_3~0); 1023791#L812-1 assume !(1 == ~E_4~0); 1024076#L817-1 assume !(1 == ~E_5~0); 1023847#L822-1 assume !(1 == ~E_6~0); 1023848#L827-1 assume { :end_inline_reset_delta_events } true; 1024090#L1053-2 [2023-11-06 22:33:39,725 INFO L750 eck$LassoCheckResult]: Loop: 1024090#L1053-2 assume !false; 1053141#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1053135#L659-1 assume !false; 1052989#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1052987#L518 assume !(0 == ~m_st~0); 1052988#L522 assume !(0 == ~t1_st~0); 1052983#L526 assume !(0 == ~t2_st~0); 1052984#L530 assume !(0 == ~t3_st~0); 1052986#L534 assume !(0 == ~t4_st~0); 1052981#L538 assume !(0 == ~t5_st~0); 1052982#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1052985#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1045210#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1045211#L570 assume !(0 != eval_~tmp~0#1); 1052978#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1052977#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1052976#L684-3 assume !(0 == ~M_E~0); 1052975#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1052974#L689-3 assume !(0 == ~T2_E~0); 1052973#L694-3 assume !(0 == ~T3_E~0); 1052972#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1052971#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1052970#L709-3 assume !(0 == ~T6_E~0); 1052969#L714-3 assume !(0 == ~E_M~0); 1052968#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1052967#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1052966#L729-3 assume !(0 == ~E_3~0); 1052965#L734-3 assume !(0 == ~E_4~0); 1052964#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1052963#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1052962#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1052961#L334-24 assume !(1 == ~m_pc~0); 1052960#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1052959#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1052958#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1052957#L849-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1052956#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1052955#L353-24 assume !(1 == ~t1_pc~0); 1052954#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1052953#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1052952#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1052951#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1052950#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1052949#L372-24 assume !(1 == ~t2_pc~0); 1052947#L372-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1052946#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1052945#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1052944#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1052943#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1052942#L391-24 assume !(1 == ~t3_pc~0); 1052941#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1052940#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1052939#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1052938#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1052937#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1052936#L410-24 assume !(1 == ~t4_pc~0); 1052935#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1052934#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1052933#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1052932#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1052931#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1052930#L429-24 assume 1 == ~t5_pc~0; 1052928#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1052926#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1052924#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1052922#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1052921#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1052920#L448-24 assume !(1 == ~t6_pc~0); 1052919#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1052918#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1052917#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1052916#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1052915#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1052914#L762-3 assume !(1 == ~M_E~0); 1052703#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1052913#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1052912#L772-3 assume !(1 == ~T3_E~0); 1052911#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052910#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1052909#L787-3 assume !(1 == ~T6_E~0); 1052908#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1052907#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1052906#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1052905#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1052904#L812-3 assume !(1 == ~E_4~0); 1052903#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1052902#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1052901#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1052896#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1052892#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1052890#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1052888#L1072 assume !(0 == start_simulation_~tmp~3#1); 1052889#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1053165#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1053158#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1053154#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1053152#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1053148#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1053147#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1053146#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1024090#L1053-2 [2023-11-06 22:33:39,726 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:39,726 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 3 times [2023-11-06 22:33:39,726 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:39,726 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1145041358] [2023-11-06 22:33:39,726 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:39,727 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:39,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:39,743 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:39,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:39,775 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:39,776 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:39,776 INFO L85 PathProgramCache]: Analyzing trace with hash -933551606, now seen corresponding path program 1 times [2023-11-06 22:33:39,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:39,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857084510] [2023-11-06 22:33:39,777 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:39,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:39,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:39,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:39,869 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:39,869 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857084510] [2023-11-06 22:33:39,869 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857084510] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:39,869 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:39,869 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-06 22:33:39,870 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1774670983] [2023-11-06 22:33:39,870 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:39,870 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:39,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:39,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-06 22:33:39,871 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-06 22:33:39,871 INFO L87 Difference]: Start difference. First operand 43260 states and 60275 transitions. cyclomatic complexity: 17031 Second operand has 5 states, 5 states have (on average 20.0) internal successors, (100), 5 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:40,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:40,303 INFO L93 Difference]: Finished difference Result 66988 states and 92022 transitions. [2023-11-06 22:33:40,303 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66988 states and 92022 transitions. [2023-11-06 22:33:40,592 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 66619 [2023-11-06 22:33:40,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66988 states to 66988 states and 92022 transitions. [2023-11-06 22:33:40,768 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66988 [2023-11-06 22:33:40,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66988 [2023-11-06 22:33:40,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66988 states and 92022 transitions. [2023-11-06 22:33:40,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:40,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66988 states and 92022 transitions. [2023-11-06 22:33:40,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66988 states and 92022 transitions. [2023-11-06 22:33:41,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66988 to 43884. [2023-11-06 22:33:41,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43884 states, 43884 states have (on average 1.3794093519278097) internal successors, (60534), 43883 states have internal predecessors, (60534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:41,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43884 states to 43884 states and 60534 transitions. [2023-11-06 22:33:41,982 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43884 states and 60534 transitions. [2023-11-06 22:33:41,982 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-06 22:33:41,983 INFO L428 stractBuchiCegarLoop]: Abstraction has 43884 states and 60534 transitions. [2023-11-06 22:33:41,983 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-06 22:33:41,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43884 states and 60534 transitions. [2023-11-06 22:33:42,090 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43547 [2023-11-06 22:33:42,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:42,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:42,092 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:42,092 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:42,092 INFO L748 eck$LassoCheckResult]: Stem: 1133996#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1133997#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1134137#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1134138#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1133778#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1133779#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1134135#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1134136#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1134059#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1133841#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1133842#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1133759#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1133760#L684 assume !(0 == ~M_E~0); 1134270#L684-2 assume !(0 == ~T1_E~0); 1134092#L689-1 assume !(0 == ~T2_E~0); 1134093#L694-1 assume !(0 == ~T3_E~0); 1134090#L699-1 assume !(0 == ~T4_E~0); 1134091#L704-1 assume !(0 == ~T5_E~0); 1134045#L709-1 assume !(0 == ~T6_E~0); 1133979#L714-1 assume !(0 == ~E_M~0); 1133980#L719-1 assume !(0 == ~E_1~0); 1134235#L724-1 assume !(0 == ~E_2~0); 1133732#L729-1 assume !(0 == ~E_3~0); 1133733#L734-1 assume !(0 == ~E_4~0); 1134315#L739-1 assume !(0 == ~E_5~0); 1133939#L744-1 assume !(0 == ~E_6~0); 1133940#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1133689#L334 assume !(1 == ~m_pc~0); 1133690#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1134036#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1133942#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1133909#L849 assume !(0 != activate_threads_~tmp~1#1); 1133910#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1133839#L353 assume !(1 == ~t1_pc~0); 1133840#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1134141#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1133704#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1133705#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1133783#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1133784#L372 assume !(1 == ~t2_pc~0); 1133897#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1133896#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1134028#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1134142#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1133678#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1133679#L391 assume !(1 == ~t3_pc~0); 1133603#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1133604#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1133628#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1133629#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1133916#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1133917#L410 assume !(1 == ~t4_pc~0); 1134154#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1134155#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1133798#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1133799#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1133922#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1133923#L429 assume !(1 == ~t5_pc~0); 1133738#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1133739#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1133953#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1133954#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1134162#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1133906#L448 assume !(1 == ~t6_pc~0); 1133821#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1133822#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1134125#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1134126#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1134344#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1134403#L762 assume !(1 == ~M_E~0); 1133959#L762-2 assume !(1 == ~T1_E~0); 1133960#L767-1 assume !(1 == ~T2_E~0); 1134353#L772-1 assume !(1 == ~T3_E~0); 1134194#L777-1 assume !(1 == ~T4_E~0); 1134074#L782-1 assume !(1 == ~T5_E~0); 1133765#L787-1 assume !(1 == ~T6_E~0); 1133763#L792-1 assume !(1 == ~E_M~0); 1133764#L797-1 assume !(1 == ~E_1~0); 1133804#L802-1 assume !(1 == ~E_2~0); 1134040#L807-1 assume !(1 == ~E_3~0); 1134041#L812-1 assume !(1 == ~E_4~0); 1134310#L817-1 assume !(1 == ~E_5~0); 1134094#L822-1 assume !(1 == ~E_6~0); 1134095#L827-1 assume { :end_inline_reset_delta_events } true; 1134321#L1053-2 [2023-11-06 22:33:42,093 INFO L750 eck$LassoCheckResult]: Loop: 1134321#L1053-2 assume !false; 1151825#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1151821#L659-1 assume !false; 1151820#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1151819#L518 assume !(0 == ~m_st~0); 1151818#L522 assume !(0 == ~t1_st~0); 1151817#L526 assume !(0 == ~t2_st~0); 1151816#L530 assume !(0 == ~t3_st~0); 1151815#L534 assume !(0 == ~t4_st~0); 1151814#L538 assume !(0 == ~t5_st~0); 1151812#L542 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 1151811#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1151810#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1151808#L570 assume !(0 != eval_~tmp~0#1); 1151807#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1151806#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1151805#L684-3 assume !(0 == ~M_E~0); 1151804#L684-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1151803#L689-3 assume !(0 == ~T2_E~0); 1151802#L694-3 assume !(0 == ~T3_E~0); 1151801#L699-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1151800#L704-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1151799#L709-3 assume !(0 == ~T6_E~0); 1151798#L714-3 assume !(0 == ~E_M~0); 1151797#L719-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1151796#L724-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1151795#L729-3 assume !(0 == ~E_3~0); 1151794#L734-3 assume !(0 == ~E_4~0); 1151793#L739-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1151792#L744-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1151791#L749-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1151790#L334-24 assume !(1 == ~m_pc~0); 1151789#L334-26 is_master_triggered_~__retres1~0#1 := 0; 1151788#L345-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1151787#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1151786#L849-24 assume !(0 != activate_threads_~tmp~1#1); 1151785#L849-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1151784#L353-24 assume !(1 == ~t1_pc~0); 1151783#L353-26 is_transmit1_triggered_~__retres1~1#1 := 0; 1151782#L364-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1151781#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1151780#L857-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1151779#L857-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1151778#L372-24 assume 1 == ~t2_pc~0; 1151777#L373-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1151775#L383-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1151774#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1151773#L865-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1151772#L865-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1151771#L391-24 assume !(1 == ~t3_pc~0); 1151770#L391-26 is_transmit3_triggered_~__retres1~3#1 := 0; 1151769#L402-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1151768#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1151767#L873-24 assume !(0 != activate_threads_~tmp___2~0#1); 1151766#L873-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1151765#L410-24 assume !(1 == ~t4_pc~0); 1151764#L410-26 is_transmit4_triggered_~__retres1~4#1 := 0; 1151763#L421-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1151762#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1151761#L881-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1151760#L881-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1151759#L429-24 assume 1 == ~t5_pc~0; 1151757#L430-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1151758#L440-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1152130#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1151752#L889-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1151751#L889-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1151750#L448-24 assume !(1 == ~t6_pc~0); 1151749#L448-26 is_transmit6_triggered_~__retres1~6#1 := 0; 1151748#L459-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1151747#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1151746#L897-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1151745#L897-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1151744#L762-3 assume !(1 == ~M_E~0); 1151596#L762-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1151743#L767-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1151742#L772-3 assume !(1 == ~T3_E~0); 1151741#L777-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1151740#L782-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1151739#L787-3 assume !(1 == ~T6_E~0); 1151738#L792-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1151737#L797-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1151736#L802-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1151735#L807-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1151734#L812-3 assume !(1 == ~E_4~0); 1151733#L817-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1151732#L822-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1151731#L827-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1151725#L518-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1151722#L555-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1151721#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1151720#L1072 assume !(0 == start_simulation_~tmp~3#1); 1146050#L1072-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1146051#L518-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1151831#L555-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1151830#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret20#1;havoc stop_simulation_#t~ret20#1; 1151829#L1027 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1151828#L1034 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1151827#stop_simulation_returnLabel#1 start_simulation_#t~ret22#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret20#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1151826#L1085 assume !(0 != start_simulation_~tmp___0~1#1); 1134321#L1053-2 [2023-11-06 22:33:42,093 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:42,094 INFO L85 PathProgramCache]: Analyzing trace with hash -895696695, now seen corresponding path program 4 times [2023-11-06 22:33:42,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:42,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516955791] [2023-11-06 22:33:42,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:42,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:42,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:42,107 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:42,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:42,146 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:42,147 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:42,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1434968523, now seen corresponding path program 1 times [2023-11-06 22:33:42,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:42,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538890128] [2023-11-06 22:33:42,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:42,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:42,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:42,191 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:42,191 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:42,191 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538890128] [2023-11-06 22:33:42,191 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538890128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:42,191 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:42,192 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:42,192 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845466143] [2023-11-06 22:33:42,192 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:42,192 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-06 22:33:42,192 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:42,193 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:42,193 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:42,193 INFO L87 Difference]: Start difference. First operand 43884 states and 60534 transitions. cyclomatic complexity: 16666 Second operand has 3 states, 3 states have (on average 33.333333333333336) internal successors, (100), 3 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:42,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:42,409 INFO L93 Difference]: Finished difference Result 65503 states and 88997 transitions. [2023-11-06 22:33:42,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65503 states and 88997 transitions. [2023-11-06 22:33:42,649 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 65164 [2023-11-06 22:33:42,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65503 states to 65503 states and 88997 transitions. [2023-11-06 22:33:42,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65503 [2023-11-06 22:33:42,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65503 [2023-11-06 22:33:42,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65503 states and 88997 transitions. [2023-11-06 22:33:42,852 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:42,852 INFO L218 hiAutomatonCegarLoop]: Abstraction has 65503 states and 88997 transitions. [2023-11-06 22:33:42,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65503 states and 88997 transitions. [2023-11-06 22:33:43,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65503 to 64063. [2023-11-06 22:33:43,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64063 states, 64063 states have (on average 1.3599893854486989) internal successors, (87125), 64062 states have internal predecessors, (87125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:44,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64063 states to 64063 states and 87125 transitions. [2023-11-06 22:33:44,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 64063 states and 87125 transitions. [2023-11-06 22:33:44,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:44,048 INFO L428 stractBuchiCegarLoop]: Abstraction has 64063 states and 87125 transitions. [2023-11-06 22:33:44,048 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-06 22:33:44,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64063 states and 87125 transitions. [2023-11-06 22:33:44,205 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 63724 [2023-11-06 22:33:44,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:44,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:44,206 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:44,206 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:44,206 INFO L748 eck$LassoCheckResult]: Stem: 1243402#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1243403#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1243555#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1243556#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1243174#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1243175#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1243551#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1243552#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1243469#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1243235#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1243236#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1243154#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1243155#L684 assume !(0 == ~M_E~0); 1243691#L684-2 assume !(0 == ~T1_E~0); 1243504#L689-1 assume !(0 == ~T2_E~0); 1243505#L694-1 assume !(0 == ~T3_E~0); 1243502#L699-1 assume !(0 == ~T4_E~0); 1243503#L704-1 assume !(0 == ~T5_E~0); 1243454#L709-1 assume !(0 == ~T6_E~0); 1243379#L714-1 assume !(0 == ~E_M~0); 1243380#L719-1 assume !(0 == ~E_1~0); 1243655#L724-1 assume !(0 == ~E_2~0); 1243125#L729-1 assume !(0 == ~E_3~0); 1243126#L734-1 assume !(0 == ~E_4~0); 1243734#L739-1 assume !(0 == ~E_5~0); 1243338#L744-1 assume !(0 == ~E_6~0); 1243339#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1243081#L334 assume !(1 == ~m_pc~0); 1243082#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1243443#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1243341#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1243306#L849 assume !(0 != activate_threads_~tmp~1#1); 1243307#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1243231#L353 assume !(1 == ~t1_pc~0); 1243232#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1243559#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1243095#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1243096#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1243176#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1243177#L372 assume !(1 == ~t2_pc~0); 1243292#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1243291#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1243435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1243560#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1243070#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1243071#L391 assume !(1 == ~t3_pc~0); 1242996#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1242997#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1243021#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1243022#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1243313#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1243314#L410 assume !(1 == ~t4_pc~0); 1243574#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1243575#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1243191#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1243192#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1243324#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1243325#L429 assume !(1 == ~t5_pc~0); 1243131#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1243132#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1243351#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1243352#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1243580#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1243305#L448 assume !(1 == ~t6_pc~0); 1243213#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1243214#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1243541#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1243542#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1243768#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1243834#L762 assume !(1 == ~M_E~0); 1243360#L762-2 assume !(1 == ~T1_E~0); 1243361#L767-1 assume !(1 == ~T2_E~0); 1243779#L772-1 assume !(1 == ~T3_E~0); 1243612#L777-1 assume !(1 == ~T4_E~0); 1243487#L782-1 assume !(1 == ~T5_E~0); 1243158#L787-1 assume !(1 == ~T6_E~0); 1243156#L792-1 assume !(1 == ~E_M~0); 1243157#L797-1 assume !(1 == ~E_1~0); 1243198#L802-1 assume !(1 == ~E_2~0); 1243447#L807-1 assume !(1 == ~E_3~0); 1243448#L812-1 assume !(1 == ~E_4~0); 1243730#L817-1 assume !(1 == ~E_5~0); 1243508#L822-1 assume !(1 == ~E_6~0); 1243509#L827-1 assume { :end_inline_reset_delta_events } true; 1243744#L1053-2 assume !false; 1245950#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1245951#L659-1 [2023-11-06 22:33:44,207 INFO L750 eck$LassoCheckResult]: Loop: 1245951#L659-1 assume !false; 1261789#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1245937#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1245844#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1245835#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1245828#L570 assume 0 != eval_~tmp~0#1; 1245820#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1245809#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1245799#L578-2 havoc eval_~tmp_ndt_1~0#1; 1245791#L575-1 assume !(0 == ~t1_st~0); 1245781#L589-1 assume !(0 == ~t2_st~0); 1245768#L603-1 assume !(0 == ~t3_st~0); 1245769#L617-1 assume !(0 == ~t4_st~0); 1261859#L631-1 assume !(0 == ~t5_st~0); 1261846#L645-1 assume !(0 == ~t6_st~0); 1245951#L659-1 [2023-11-06 22:33:44,208 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:44,208 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 1 times [2023-11-06 22:33:44,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:44,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1926970354] [2023-11-06 22:33:44,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:44,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:44,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:44,221 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:44,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:44,259 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:44,259 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:44,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1779949543, now seen corresponding path program 1 times [2023-11-06 22:33:44,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:44,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [426543325] [2023-11-06 22:33:44,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:44,263 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:44,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:44,267 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:44,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:44,271 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:44,272 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:44,272 INFO L85 PathProgramCache]: Analyzing trace with hash 1784869629, now seen corresponding path program 1 times [2023-11-06 22:33:44,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:44,272 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841178673] [2023-11-06 22:33:44,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:44,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:44,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:44,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:44,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:44,326 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841178673] [2023-11-06 22:33:44,326 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841178673] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:44,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:44,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:44,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [955775715] [2023-11-06 22:33:44,327 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:44,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:44,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:44,470 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:44,470 INFO L87 Difference]: Start difference. First operand 64063 states and 87125 transitions. cyclomatic complexity: 23092 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:44,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:44,805 INFO L93 Difference]: Finished difference Result 121242 states and 163123 transitions. [2023-11-06 22:33:44,806 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 121242 states and 163123 transitions. [2023-11-06 22:33:45,932 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 116709 [2023-11-06 22:33:46,200 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 121242 states to 121242 states and 163123 transitions. [2023-11-06 22:33:46,201 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121242 [2023-11-06 22:33:46,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121242 [2023-11-06 22:33:46,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 121242 states and 163123 transitions. [2023-11-06 22:33:46,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:46,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 121242 states and 163123 transitions. [2023-11-06 22:33:46,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121242 states and 163123 transitions. [2023-11-06 22:33:47,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121242 to 118749. [2023-11-06 22:33:47,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118749 states, 118749 states have (on average 1.3469839746018915) internal successors, (159953), 118748 states have internal predecessors, (159953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:48,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118749 states to 118749 states and 159953 transitions. [2023-11-06 22:33:48,047 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118749 states and 159953 transitions. [2023-11-06 22:33:48,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:48,047 INFO L428 stractBuchiCegarLoop]: Abstraction has 118749 states and 159953 transitions. [2023-11-06 22:33:48,047 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-06 22:33:48,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118749 states and 159953 transitions. [2023-11-06 22:33:48,438 INFO L131 ngComponentsAnalysis]: Automaton has 54 accepting balls. 114216 [2023-11-06 22:33:48,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:48,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:48,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:48,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:48,440 INFO L748 eck$LassoCheckResult]: Stem: 1428719#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1428720#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1428877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1428878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1428489#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1428490#L475-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1428873#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1428874#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1428785#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1428786#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1429060#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1429061#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1429131#L684 assume !(0 == ~M_E~0); 1429132#L684-2 assume !(0 == ~T1_E~0); 1428823#L689-1 assume !(0 == ~T2_E~0); 1428824#L694-1 assume !(0 == ~T3_E~0); 1428821#L699-1 assume !(0 == ~T4_E~0); 1428822#L704-1 assume !(0 == ~T5_E~0); 1428770#L709-1 assume !(0 == ~T6_E~0); 1428771#L714-1 assume !(0 == ~E_M~0); 1428989#L719-1 assume !(0 == ~E_1~0); 1428990#L724-1 assume !(0 == ~E_2~0); 1428439#L729-1 assume !(0 == ~E_3~0); 1428440#L734-1 assume !(0 == ~E_4~0); 1429098#L739-1 assume !(0 == ~E_5~0); 1429099#L744-1 assume !(0 == ~E_6~0); 1428992#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1428993#L334 assume !(1 == ~m_pc~0); 1428757#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1428758#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1428658#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1428659#L849 assume !(0 != activate_threads_~tmp~1#1); 1428945#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1428946#L353 assume !(1 == ~t1_pc~0); 1429083#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1429084#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1428407#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1428408#L857 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1428844#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1429163#L372 assume !(1 == ~t2_pc~0); 1429164#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1428749#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1428750#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1429078#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1429079#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1429057#L391 assume !(1 == ~t3_pc~0); 1429058#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1428530#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1428531#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1428979#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1428980#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1429076#L410 assume !(1 == ~t4_pc~0); 1429077#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1428950#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1428951#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1429085#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1429086#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1428811#L429 assume !(1 == ~t5_pc~0); 1428812#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1429230#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1429231#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1428903#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1428904#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1428621#L448 assume !(1 == ~t6_pc~0); 1428622#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1428899#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1428900#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1429137#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1429138#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1429218#L762 assume !(1 == ~M_E~0); 1429219#L762-2 assume !(1 == ~T1_E~0); 1429189#L767-1 assume !(1 == ~T2_E~0); 1429190#L772-1 assume !(1 == ~T3_E~0); 1428943#L777-1 assume !(1 == ~T4_E~0); 1428944#L782-1 assume !(1 == ~T5_E~0); 1428472#L787-1 assume !(1 == ~T6_E~0); 1428473#L792-1 assume !(1 == ~E_M~0); 1428513#L797-1 assume !(1 == ~E_1~0); 1428514#L802-1 assume !(1 == ~E_2~0); 1428763#L807-1 assume !(1 == ~E_3~0); 1428764#L812-1 assume !(1 == ~E_4~0); 1429206#L817-1 assume !(1 == ~E_5~0); 1429207#L822-1 assume !(1 == ~E_6~0); 1429106#L827-1 assume { :end_inline_reset_delta_events } true; 1429107#L1053-2 assume !false; 1433106#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1433107#L659-1 [2023-11-06 22:33:48,440 INFO L750 eck$LassoCheckResult]: Loop: 1433107#L659-1 assume !false; 1506282#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1506279#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1478220#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1478216#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1478217#L570 assume 0 != eval_~tmp~0#1; 1478209#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1478210#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1506515#L578-2 havoc eval_~tmp_ndt_1~0#1; 1478199#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1478198#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1478245#L592-2 havoc eval_~tmp_ndt_2~0#1; 1478243#L589-1 assume !(0 == ~t2_st~0); 1478238#L603-1 assume !(0 == ~t3_st~0); 1478239#L617-1 assume !(0 == ~t4_st~0); 1478232#L631-1 assume !(0 == ~t5_st~0); 1478231#L645-1 assume !(0 == ~t6_st~0); 1433107#L659-1 [2023-11-06 22:33:48,441 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:48,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1481595819, now seen corresponding path program 1 times [2023-11-06 22:33:48,442 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:48,442 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380386207] [2023-11-06 22:33:48,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:48,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:48,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:48,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:48,478 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:48,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380386207] [2023-11-06 22:33:48,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380386207] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:48,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:48,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:48,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1003601530] [2023-11-06 22:33:48,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:48,480 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-06 22:33:48,480 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:48,481 INFO L85 PathProgramCache]: Analyzing trace with hash -1384180882, now seen corresponding path program 1 times [2023-11-06 22:33:48,481 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:48,481 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238028329] [2023-11-06 22:33:48,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:48,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:48,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:48,486 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:48,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:48,491 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:48,596 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:48,598 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:48,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:48,598 INFO L87 Difference]: Start difference. First operand 118749 states and 159953 transitions. cyclomatic complexity: 41258 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:48,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:48,898 INFO L93 Difference]: Finished difference Result 94698 states and 127623 transitions. [2023-11-06 22:33:48,898 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94698 states and 127623 transitions. [2023-11-06 22:33:50,131 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 94193 [2023-11-06 22:33:50,305 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94698 states to 94698 states and 127623 transitions. [2023-11-06 22:33:50,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94698 [2023-11-06 22:33:50,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94698 [2023-11-06 22:33:50,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94698 states and 127623 transitions. [2023-11-06 22:33:50,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:50,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 94698 states and 127623 transitions. [2023-11-06 22:33:50,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94698 states and 127623 transitions. [2023-11-06 22:33:50,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94698 to 94698. [2023-11-06 22:33:50,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94698 states, 94698 states have (on average 1.3476842171957168) internal successors, (127623), 94697 states have internal predecessors, (127623), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:51,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94698 states to 94698 states and 127623 transitions. [2023-11-06 22:33:51,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94698 states and 127623 transitions. [2023-11-06 22:33:51,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:51,880 INFO L428 stractBuchiCegarLoop]: Abstraction has 94698 states and 127623 transitions. [2023-11-06 22:33:51,880 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-06 22:33:51,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94698 states and 127623 transitions. [2023-11-06 22:33:52,084 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 94193 [2023-11-06 22:33:52,084 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-06 22:33:52,084 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-06 22:33:52,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:52,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-06 22:33:52,085 INFO L748 eck$LassoCheckResult]: Stem: 1642165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int(48, 1, 0, 1);call write~init~int(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~token~0 := 0;~local~0 := 0; 1642166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1642323#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret21#1, start_simulation_#t~ret22#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1642324#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1641939#L475 assume 1 == ~m_i~0;~m_st~0 := 0; 1641940#L475-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1642319#L480-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1642320#L485-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1642231#L490-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1642001#L495-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1642002#L500-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1641919#L505-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1641920#L684 assume !(0 == ~M_E~0); 1642453#L684-2 assume !(0 == ~T1_E~0); 1642268#L689-1 assume !(0 == ~T2_E~0); 1642269#L694-1 assume !(0 == ~T3_E~0); 1642266#L699-1 assume !(0 == ~T4_E~0); 1642267#L704-1 assume !(0 == ~T5_E~0); 1642217#L709-1 assume !(0 == ~T6_E~0); 1642142#L714-1 assume !(0 == ~E_M~0); 1642143#L719-1 assume !(0 == ~E_1~0); 1642415#L724-1 assume !(0 == ~E_2~0); 1641890#L729-1 assume !(0 == ~E_3~0); 1641891#L734-1 assume !(0 == ~E_4~0); 1642498#L739-1 assume !(0 == ~E_5~0); 1642102#L744-1 assume !(0 == ~E_6~0); 1642103#L749-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1641846#L334 assume !(1 == ~m_pc~0); 1641847#L334-2 is_master_triggered_~__retres1~0#1 := 0; 1642205#L345 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1642106#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1642072#L849 assume !(0 != activate_threads_~tmp~1#1); 1642073#L849-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1641997#L353 assume !(1 == ~t1_pc~0); 1641998#L353-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1642325#L364 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1641861#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1641862#L857 assume !(0 != activate_threads_~tmp___0~0#1); 1641941#L857-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1641942#L372 assume !(1 == ~t2_pc~0); 1642059#L372-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1642058#L383 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1642197#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1642326#L865 assume !(0 != activate_threads_~tmp___1~0#1); 1641835#L865-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1641836#L391 assume !(1 == ~t3_pc~0); 1641762#L391-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1641763#L402 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1641787#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1641788#L873 assume !(0 != activate_threads_~tmp___2~0#1); 1642079#L873-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1642080#L410 assume !(1 == ~t4_pc~0); 1642338#L410-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1642339#L421 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1641956#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1641957#L881 assume !(0 != activate_threads_~tmp___3~0#1); 1642088#L881-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1642089#L429 assume !(1 == ~t5_pc~0); 1641896#L429-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1641897#L440 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1642116#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1642117#L889 assume !(0 != activate_threads_~tmp___4~0#1); 1642344#L889-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1642071#L448 assume !(1 == ~t6_pc~0); 1641979#L448-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1641980#L459 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1642307#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1642308#L897 assume !(0 != activate_threads_~tmp___5~0#1); 1642532#L897-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1642594#L762 assume !(1 == ~M_E~0); 1642123#L762-2 assume !(1 == ~T1_E~0); 1642124#L767-1 assume !(1 == ~T2_E~0); 1642540#L772-1 assume !(1 == ~T3_E~0); 1642380#L777-1 assume !(1 == ~T4_E~0); 1642248#L782-1 assume !(1 == ~T5_E~0); 1641923#L787-1 assume !(1 == ~T6_E~0); 1641921#L792-1 assume !(1 == ~E_M~0); 1641922#L797-1 assume !(1 == ~E_1~0); 1641963#L802-1 assume !(1 == ~E_2~0); 1642210#L807-1 assume !(1 == ~E_3~0); 1642211#L812-1 assume !(1 == ~E_4~0); 1642494#L817-1 assume !(1 == ~E_5~0); 1642272#L822-1 assume !(1 == ~E_6~0); 1642273#L827-1 assume { :end_inline_reset_delta_events } true; 1642505#L1053-2 assume !false; 1678826#L1054 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1678822#L659-1 [2023-11-06 22:33:52,085 INFO L750 eck$LassoCheckResult]: Loop: 1678822#L659-1 assume !false; 1678820#L566 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1678817#L518 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1678815#L555 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1678813#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1678811#L570 assume 0 != eval_~tmp~0#1; 1678808#L570-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1678806#L578 assume !(0 != eval_~tmp_ndt_1~0#1); 1678804#L578-2 havoc eval_~tmp_ndt_1~0#1; 1678802#L575-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1678799#L592 assume !(0 != eval_~tmp_ndt_2~0#1); 1678800#L592-2 havoc eval_~tmp_ndt_2~0#1; 1678837#L589-1 assume !(0 == ~t2_st~0); 1678833#L603-1 assume !(0 == ~t3_st~0); 1678831#L617-1 assume !(0 == ~t4_st~0); 1678828#L631-1 assume !(0 == ~t5_st~0); 1678824#L645-1 assume !(0 == ~t6_st~0); 1678822#L659-1 [2023-11-06 22:33:52,086 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:52,086 INFO L85 PathProgramCache]: Analyzing trace with hash -1771052117, now seen corresponding path program 2 times [2023-11-06 22:33:52,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:52,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1233888745] [2023-11-06 22:33:52,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:52,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:52,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:52,098 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:52,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:52,125 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:52,126 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:52,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1384180882, now seen corresponding path program 2 times [2023-11-06 22:33:52,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:52,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410473893] [2023-11-06 22:33:52,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:52,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:52,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:52,130 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-06 22:33:52,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-06 22:33:52,135 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-06 22:33:52,135 INFO L145 PredicateUnifier]: Initialized classic predicate unifier [2023-11-06 22:33:52,135 INFO L85 PathProgramCache]: Analyzing trace with hash -950945532, now seen corresponding path program 1 times [2023-11-06 22:33:52,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-06 22:33:52,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2145853971] [2023-11-06 22:33:52,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-06 22:33:52,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-06 22:33:52,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-06 22:33:52,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-06 22:33:52,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-06 22:33:52,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2145853971] [2023-11-06 22:33:52,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2145853971] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-06 22:33:52,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-06 22:33:52,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-06 22:33:52,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1615057969] [2023-11-06 22:33:52,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-06 22:33:52,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-06 22:33:52,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-06 22:33:52,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-06 22:33:52,275 INFO L87 Difference]: Start difference. First operand 94698 states and 127623 transitions. cyclomatic complexity: 32955 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:52,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-06 22:33:52,802 INFO L93 Difference]: Finished difference Result 177213 states and 237365 transitions. [2023-11-06 22:33:52,802 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 177213 states and 237365 transitions. [2023-11-06 22:33:54,212 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 176294 [2023-11-06 22:33:54,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 177213 states to 177213 states and 237365 transitions. [2023-11-06 22:33:54,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 177213 [2023-11-06 22:33:54,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 177213 [2023-11-06 22:33:54,668 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177213 states and 237365 transitions. [2023-11-06 22:33:54,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-06 22:33:54,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 177213 states and 237365 transitions. [2023-11-06 22:33:54,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177213 states and 237365 transitions. [2023-11-06 22:33:56,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177213 to 167783. [2023-11-06 22:33:56,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 167783 states, 167783 states have (on average 1.345124357056436) internal successors, (225689), 167782 states have internal predecessors, (225689), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-06 22:33:56,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167783 states to 167783 states and 225689 transitions. [2023-11-06 22:33:56,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 167783 states and 225689 transitions. [2023-11-06 22:33:56,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-06 22:33:56,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 167783 states and 225689 transitions. [2023-11-06 22:33:56,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-06 22:33:56,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 167783 states and 225689 transitions.